BFMMLA (non-widening)

BFloat16 matrix multiply-accumulate

This instruction multiplies the 2x2 matrix of BFloat16 values in each 64-bit segment of the first source vector by the 2x2 matrix of BFloat16 values in the corresponding 64-bit segment of the second source vector. The intermediate products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the 2x2 BFloat16 matrix held in the corresponding 64-bit segment of the addend and destination vector. This is equivalent to performing a 2-way dot product per destination element. This instruction is unpredicated.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

SVE
(FEAT_SVE_B16MM)

313029282726252423222120191817161514131211109876543210
01100100111Zm111000ZnZda
op

Encoding

BFMMLA <Zda>.H, <Zn>.H, <Zm>.H

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_B16MM) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2025-09_diff_tag 2025-11-28 16:29:05

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