Data synchronization barrier
This instruction is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier.
This instruction is used by the aliases PSSBB, and SSBB.
It has encodings from 2 classes: Memory barrier and Memory nXS barrier
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| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |||
| opc | Rt | ||||||||||||||||||||||||||||||
var nXS : boolean = FALSE; var alias : DSBAlias; case CRm of when '0000' => alias = DSBAlias_SSBB; when '0100' => alias = DSBAlias_PSSBB; otherwise => alias = DSBAlias_DSB; end; var domain : MBReqDomain; case CRm[3:2] of when '00' => domain = MBReqDomain_OuterShareable; when '01' => domain = MBReqDomain_Nonshareable; when '10' => domain = MBReqDomain_InnerShareable; when '11' => domain = MBReqDomain_FullSystem; end; var types : MBReqTypes; case CRm[1:0] of when '00' => types = MBReqTypes_All; domain = MBReqDomain_FullSystem; when '01' => types = MBReqTypes_Reads; when '10' => types = MBReqTypes_Writes; when '11' => types = MBReqTypes_All; end;
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| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | imm2 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | |
| op2 | Rt | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_XS) then EndOfDecode(Decode_UNDEF); end; let types : MBReqTypes = MBReqTypes_All; var nXS : boolean = TRUE; let alias : DSBAlias = DSBAlias_DSB; var domain : MBReqDomain; case imm2 of when '00' => domain = MBReqDomain_OuterShareable; when '01' => domain = MBReqDomain_Nonshareable; when '10' => domain = MBReqDomain_InnerShareable; when '11' => domain = MBReqDomain_FullSystem; end;
| <option> |
For the "Memory barrier" variant: specifies the limitation on the barrier operation. Values are:
All other encodings of "CRm" that are not listed, other than the values 0b0000 and 0b0100, are reserved and can be encoded using the #<imm> syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see Data Memory Barrier (DMB) or see Data Synchronization Barrier (DSB). NoteThe value 0b0000 is used to encode SSBB and the value 0b0100 is used to encode PSSBB.
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For the "Memory nXS barrier" variant: specifies the limitation on the barrier operation. Values are:
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| <imm> |
Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. |
| Alias | Is preferred when |
|---|---|
| PSSBB | CRm == '0100' |
| SSBB | CRm == '0000' |
case alias of when DSBAlias_SSBB => SpeculativeStoreBypassBarrierToVA(); when DSBAlias_PSSBB => SpeculativeStoreBypassBarrierToPA(); when DSBAlias_DSB => if !nXS && IsFeatureImplemented(FEAT_XS) then nXS = PSTATE.EL IN {EL0, EL1} && IsHCRXEL2Enabled() && HCRX_EL2().FnXS == '1'; end; DataSynchronizationBarrier(domain, types, nXS); otherwise => unreachable; end;
2025-09_diff_tag 2025-11-28 16:29:05
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