F1CVTLT, F2CVTLT

8-bit floating-point convert to half-precision (top)

This instruction converts each odd-numbered 8-bit floating-point element of the source vector to half-precision while downscaling the value, and places the results in the overlapping 16-bit elements of the destination vector. F1CVTLT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVTLT scales the values by 2-UInt(FPMR.LSCALE2[3:0]).

The 8-bit floating-point encoding format for F1CVTLT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTLT is selected by FPMR.F8S2.

This instruction is unpredicated.

It has encodings from 2 classes: F1CVTLT and F2CVTLT

F1CVTLT
((FEAT_SVE2 || FEAT_SME2) && FEAT_FP8)

313029282726252423222120191817161514131211109876543210
0110010100001001001100ZnZd
Lopc

Encoding

F1CVTLT <Zd>.H, <Zn>.B

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_FP8)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let n : integer = UInt(Zn); let d : integer = UInt(Zd); let issrc2 : boolean = FALSE;

F2CVTLT
((FEAT_SVE2 || FEAT_SME2) && FEAT_FP8)

313029282726252423222120191817161514131211109876543210
0110010100001001001101ZnZd
Lopc

Encoding

F2CVTLT <Zd>.H, <Zn>.B

Decode for this encoding

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_FP8)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let n : integer = UInt(Zn); let d : integer = UInt(Zd); let issrc2 : boolean = TRUE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.


2025-09_diff_tag 2025-11-28 16:29:05

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