Floating-point narrowing convert to interleaved signed integer, rounding toward zero
This instruction converts each floating-point element of the pair of source vectors to half-width signed integer nearer to zero, and places the two-way interleaved results in the corresponding half-width elements of the destination vector.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | Zn | 0 | Zd | ||||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd); let unsigned : boolean = FALSE; let rounding : FPRounding = FPRounding_ZERO;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(n+0); let operand2 : bits(VL) = Z{}(n+1); var result : bits(VL); for e = 0 to elements-1 do let element1 : bits(esize) = operand1[e*:esize]; let element2 : bits(esize) = operand2[e*:esize]; result[(2*e + 0)*:(esize DIV 2)] = FPToFixed{esize DIV 2, esize}(element1, 0, unsigned, FPCR(), rounding); result[(2*e + 1)*:(esize DIV 2)] = FPToFixed{esize DIV 2, esize}(element2, 0, unsigned, FPCR(), rounding); end; Z{VL}(d) = result;
2025-09_diff_tag 2025-11-28 16:29:05
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