FMLALB (indexed, FP8 to FP16)

8-bit floating-point multiply-add by indexed element to half-precision (bottom)

This instruction widens the even 8-bit elements in the first source vector and the indexed element from the corresponding 128-bit segment in the second source vector to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector. The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

SVE2
((FEAT_SVE2 && FEAT_FP8FMA) || FEAT_SSVE_FP8FMA)

313029282726252423222120191817161514131211109876543210
01100100001i4hZm0101i4lZnZda
T

Encoding

FMLALB <Zda>.H, <Zn>.B, <Zm>.B[<imm>]

Decode for this encoding

if !HaveSVE2FP8FMA() then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let index : integer = UInt(i4h::i4l);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

<imm>

Is the immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2025-09_diff_tag 2025-11-28 16:29:05

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