Half-precision matrix multiply-accumulate to single-precision
This instruction performs two fused sums-of-products within each two pairs of adjacent half-precision elements while multiplying the 2x4 matrix of half-precision values held in the first source vector by the 4x2 matrix of half-precision values in the second source vector. The intermediate sums-of-products are rounded before they are summed, and their intermediate sum is rounded before accumulation into the 2x2 single-precision matrix in the destination vector. This is equivalent to performing a 4-way dot product per destination element.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 1 | 1 | 1 | 0 | 1 | 1 | Rn | Rd | ||||||||||||
| Q | U | size | opcode | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_F16F32MM) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm);
| <Vd> |
Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
AArch64_CheckFPAdvSIMDEnabled(); let op1 : bits(128) = V{}(n); let op2 : bits(128) = V{}(m); let acc : bits(128) = V{}(d); V{128}(d) = FPMatMulAddH{128}(acc, op1, op2, FPCR());
2025-09_diff_tag 2025-11-28 16:29:05
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