FRINTP

Multi-vector single-precision round to integral value, toward plus Infinity

This instruction rounds up each single-precision element of the two or four source vectors to an integral floating-point value, and places the results in the corresponding elements of the two or four destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

It has encodings from 2 classes: Two registers and Four registers

Two registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000110101001111000Zn0Zd0
sizeopc

Encoding

FRINTP { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd::'0'); let nreg : integer{} = 2; let exact : boolean = FALSE; let rounding : FPRounding = FPRounding_POSINF;

Four registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000110111001111000Zn00Zd00
sizeopc

Encoding

FRINTP { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn::'00'); let d : integer = UInt(Zd::'00'); let nreg : integer{} = 4; let exact : boolean = FALSE; let rounding : FPRounding = FPRounding_POSINF;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn1>

For the "Two registers" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.


2025-09_diff_tag 2025-11-28 16:29:05

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.