Load-acquire RCpc pair of registers
This instruction calculates an address from a base register value, loads two 64-bit doublewords from memory, and writes them to two registers. Explicit Memory effects produced by this instruction have AcquirePC semantics, unless both destination registers are XZR. For information about memory ordering semantics, see Load-Acquire, Load-AcquirePC, and Store-Release.
For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | Rt2 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rt | ||||||||||||
| size | L | opc2 | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSCP) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let acquire : boolean = t != 31 && t2 != 31; let tagchecked : boolean = n != 31; let ispair : boolean = TRUE; var rt_unknown : boolean = FALSE; if t == t2 then let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // Result is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDP and LDIAPP, which applies when t==t2.
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
var address : bits(64); var data1 : bits(64); var data2 : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescLDAcqPC(tagchecked, ispair, acquire, t, t2); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let full_data : bits(128) = Mem{128}(address, accdesc); if BigEndian(accdesc.acctype) then data2 = full_data[63:0]; data1 = full_data[127:64]; else data1 = full_data[63:0]; data2 = full_data[127:64]; end; if rt_unknown then data1 = ARBITRARY : bits(64); data2 = ARBITRARY : bits(64); end; X{64}(t) = data1; X{64}(t2) = data2;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2025-09_diff_tag 2025-11-28 16:29:05
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