LUTI6 (table, four registers, 8-bit)

Lookup table read with 6-bit indices (8-bit)

This instruction copies indexed 8-bit elements from ZT0 to four destination vectors using packed 6-bit indices in the three source vectors. This instruction is unpredicated.

It has encodings from 2 classes: Consecutive and Strided

Consecutive
(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
1100000010001010000000Zn00Zd00
sizeopc

Encoding

LUTI6 { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn3> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8; let isize : integer{} = 6; let n : integer = UInt('00'::Zn); let dstride : integer = 1; let d : integer = UInt(Zd::'00');

Strided
(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
1100000010011010000000Zn00D00Zd
sizeopc

Encoding

LUTI6 { <Zd1>.B, <Zd2>.B, <Zd3>.B, <Zd4>.B }, ZT0, { <Zn1>-<Zn3> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8; let isize : integer{} = 6; let n : integer = UInt('00'::Zn); let dstride : integer = 4; let d : integer = UInt(D::'00'::Zd);

Assembler Symbols

<Zd1>

For the "Consecutive" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

For the "Strided" variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd4>

For the "Consecutive" variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

For the "Strided" variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group Z0-Z7, encoded in the "Zn" field.

<Zn3>

Is the name of the third scalable vector register of the source multi-vector group Z2-Z9, encoded as "Zn" plus 2.

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

Operation

CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let indexes : bits(3*VL) = Z{VL}(n+2) :: Z{VL}(n+1) :: Z{VL}(n+0); var dst : integer = d; let table : bits(512) = ZT0{}(); for r = 0 to 3 do let base : integer = r * elements; var result : bits(VL); for e = 0 to elements-1 do let index : integer = UInt(indexes[(base+e)*:isize]); result[e*:esize] = table[index*:esize]; end; Z{VL}(dst) = result; dst = dst + dstride; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-09_diff_tag 2025-11-28 16:29:05

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