Predicate extract from predicate-as-counter
This instruction converts the source predicate-as-counter into a four register wide predicate-as-mask, and copies the portion of the mask value selected by the portion index to the destination predicate register. A portion corresponds to a one predicate register fraction of the wider predicate-as-mask value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | imm2 | PNn | 1 | Pd | |||||||
if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt('1'::PNn); let d : integer = UInt(Pd); let part : integer = UInt(imm2);
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <PNn> |
Is the name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field. |
| <imm> |
Is the portion index, in the range 0 to 3, encoded in the "imm2" field. |
if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let pred : bits(PL) = P{}(n); let mask : bits(PL*4) = CounterToPredicate{}(pred[15:0]); var result : bits(PL); let psize : integer{} = esize DIV 8; for e = 0 to elements-1 do let pbit : bit = PredicateElement{PL*4}(mask, part * elements + e, esize); result[e*:psize] = ZeroExtend{psize}(pbit); end; P{PL}(d) = result;
2025-09_diff_tag 2025-11-28 16:29:05
Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.