PMLAL

Multi-vector polynomial multiply long and accumulate

This instruction performs a polynomial multiplication over [0, 1] of the even-numbered elements of the first source vector by the corresponding elements of the second source vector, and then performs a bitwise exclusive-OR between the result and the overlapping double-width elements of the first destination vector. The same operation is performed with odd-numbered elements of the source vectors, writing to the second destination vector. This instruction is unpredicated.

This instruction is legal when executed in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.

SVE2
(FEAT_SVE_AES2)

313029282726252423222120191817161514131211109876543210
01000101001Zm111111ZnZda0
size

Encoding

PMLAL { <Zda1>.Q-<Zda2>.Q }, <Zn>.D, <Zm>.D

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_AES2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 128; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda::'0');

Assembler Symbols

<Zda1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zda" times 2.

<Zda2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zda" times 2 plus 1.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.


2025-09_diff_tag 2025-11-28 16:29:05

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