SHA512 schedule update 0
This instruction takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||
| opcode | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SHA512) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn);
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); var sig0 : bits(64); var Vtmp : bits(128); let x : bits(128) = V{}(n); let w : bits(128) = V{}(d); sig0 = ROR(w[127:64], 1) XOR ROR(w[127:64], 8) XOR ('0000000'::w[127:71]); Vtmp[63:0] = w[63:0] + sig0; sig0 = ROR(x[63:0], 1) XOR ROR(x[63:0], 8) XOR ('0000000'::x[63:7]); Vtmp[127:64] = w[127:64] + sig0; V{128}(d) = Vtmp;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2025-09_diff_tag 2025-11-28 16:29:05
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