SM3SS1
This instruction rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | Ra | Rn | Rd | ||||||||||||||||
| Op0 | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SM3) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let a : integer{} = UInt(Ra);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Va> |
Is the name of the third SIMD&FP source register, encoded in the "Ra" field. |
AArch64_CheckFPAdvSIMDEnabled(); let Vm : bits(128) = V{}(m); let Vn : bits(128) = V{}(n); let Va : bits(128) = V{}(a); var result : bits(128); result[127:96] = ROL((ROL(Vn[127:96], 12) + Vm[127:96] + Va[127:96]), 7); result[95:0] = Zeros{96}; V{128}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2025-09_diff_tag 2025-11-28 16:29:05
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