ST1H (scalar plus scalar, tile slice) -- A64

This instruction performs a contiguous store of halfwords from a 16-bit element ZA tile slice. The slice number within the tile is selected by the sum of the slice index register and immediate offset, modulo the number of 16-bit elements in a vector. The immediate offset is in the range 0 to 7. The memory address is generated by a 64-bit scalar base and an optional 64-bit scalar offset that is multiplied by 2 and added to the base address. Inactive elements are not written to memory.

SME
(FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt('0'::Pg); let s : integer = UInt('011'::Rs); let t : integer = UInt(ZAt); let offset : integer = UInt(off3); let esize : integer{} = 16; let vertical : boolean = V == '1';

Assembler Symbols

<ZAt>

Is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAt" field.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V	<HV>
0	H
1	V

<Ws>	Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs>

Is the slice index offset, in the range 0 to 7, encoded in the "off3" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>	Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operation

CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let dim : integer = VL DIV esize; var base : bits(64); var addr : bits(64); let mask : bits(PL) = P{}(g); var moffs : bits(64) = X{}(m); let index : bits(32) = X{}(s); let slice : integer = (UInt(index) + offset) MOD dim; var src : bits(VL); let mbytes : integer{} = esize DIV 8; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSME(MemOp_STORE, nontemporal, contiguous, tagchecked); if n == 31 then if (AnyActiveElement{PL}(mask, esize) || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE)) then CheckSPAlignment(); end; base = SP{64}(); else base = X{64}(n); end; src = ZAslice{VL}(t, esize, vertical, slice); for e = 0 to dim-1 do addr = AddressAdd(base, UInt(moffs) * mbytes, accdesc); if ActivePredicateElement{PL}(mask, e, esize) then Mem{esize}(addr, accdesc) = src[e*:esize]; end; moffs = moffs + 1; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2025-09_diff_tag 2025-11-28 16:29:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	0	0	0	0	1	1	Rm					V	Rs		Pg			Rn					0	ZAt	off3
								msz