UQXTNB

Unsigned saturating extract narrow (bottom)

This instruction saturates the unsigned integer value in each source element to half the original source element width, and places the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.

SVE2
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010010ZnZd
UT

Encoding

UQXTNB <Zd>.<T>, <Zn>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(3) = tszh::tszl; if !(tsize IN {'001', '010', '100'}) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16 << HighestSetBitNZ(tsize); let n : integer = UInt(Zn); let d : integer = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in (tszh :: tszl):

tszh tszl <T>
0 00 RESERVED
0 01 B
0 10 H
0 11 RESERVED
1 00 S
1 01 RESERVED
1 1x RESERVED
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in (tszh :: tszl):

tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 10 S
0 11 RESERVED
1 00 D
1 01 RESERVED
1 1x RESERVED

2025-09_diff_tag 2025-11-28 16:29:05

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