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SEL

Multi-vector conditional select

This instruction selects consecutive elements from the two or four first source vectors where vector select predicate elements are true, and places them in the corresponding elements of the two or four destination vectors. WhereThe vector select predicate elements are false, the corresponding consecutive elements are selected from the two or four second source vectors andare placed in the remaining elements of the destination vectors.

It has encodings from 2 classes: Two registers and Four registers

Two registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size1Zm0100PNvPNgZn0Zd0

Encoding

SEL { <Zd1>.<T>-<Zd2>.<T> }, <PNv><PNg>, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'0'); let m : integer = UInt(Zm::'0'); let d : integer = UInt(Zd::'0'); let vg : integer = UInt('1'::PNvPNg); let nreg : integer{} = 2;

Four registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size1Zm01100PNvPNgZn00Zd00

Encoding

SEL { <Zd1>.<T>-<Zd4>.<T> }, <PNv><PNg>, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'00'); let m : integer = UInt(Zm::'00'); let d : integer = UInt(Zd::'00'); let vg : integer = UInt('1'::PNvPNg); let nreg : integer{} = 4;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<PNvPNg>

Is the name of the vectorgoverning selectscalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNvPNg" field.

<Zn1>

For the "Two registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm1>

For the "Two registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.

<Zm2>

Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zm4>

Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-12_rel2025-09_diff_tag 2025-12-102025-11-28 16:4129:4505

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