BFMOPS (non-widening)

BFloat16 outer product, subtracting

This instruction works with a 16-bit element ZA tile.

This instruction generates an outer product of the first source vector and the second source vector. The first source is SVLH×1 vector and the second source is 1×SVLH vector.

Each source vector is independently predicated by a corresponding governing predicate. When either source vector element is Inactive the corresponding destination tile element remains unmodified.

The resulting outer product, SVLH×SVLH, is then destructively subtracted from the destination tile. This is equivalent to performing a single multiply-subtract from each of the destination tile elements.

This instruction follows SME2 ZA-targeting non-widening BFloat16 numerical behaviors.

ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.

SME2
(FEAT_SME_B16B16)

313029282726252423222120191817161514131211109876543210
10000001101ZmPmPnZn1100ZAda
S

Encoding

BFMOPS <ZAda>.H, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_B16B16) then EndOfDecode(Decode_UNDEF); end; let a : integer = UInt(Pn); let b : integer = UInt(Pm); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(ZAda);

Assembler Symbols

<ZAda>

Is the name of the ZA tile ZA0-ZA1, encoded in the "ZAda" field.

<Pn>

Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.

<Pm>

Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.


2025-12_rel 2025-12-10 16:41:45

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