F1CVTL, F2CVTL

Multi-vector 8-bit floating-point convert to deinterleaved half-precision

This instruction converts each 8-bit floating-point element of the source vector to half-precision while downscaling the value, and places the two-way deinterleaved results in the corresponding 16-bit elements of the destination vectors. F1CVTL scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVTL scales the values by 2-UInt(FPMR.LSCALE2[3:0]). The 8-bit floating-point encoding format for F1CVTL is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTL is selected by FPMR.F8S2.

This instruction is unpredicated.

It has encodings from 2 classes: F1CVTL and F2CVTL

F1CVTL
(FEAT_SME2 && FEAT_FP8)

313029282726252423222120191817161514131211109876543210
1100000100100110111000ZnZd1
opcL

Encoding

F1CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let d : integer = UInt(Zd:: '0'); let issrc2 : boolean = FALSE;

F2CVTL
(FEAT_SME2 && FEAT_FP8)

313029282726252423222120191817161514131211109876543210
1100000110100110111000ZnZd1
opcL

Encoding

F2CVTL { <Zd1>.H-<Zd2>.H }, <Zn>.B

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let d : integer = UInt(Zd:: '0'); let issrc2 : boolean = TRUE;

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.


2025-12_rel 2025-12-10 16:41:45

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