FCVTN (half-precision to 8-bit floating-point) -- A64

This instruction converts half-precision elements of the two source vectors to 8-bit floating-point while scaling the values by 2^{SInt(FPMR.NSCALE[4:0])}, and places the in-order results in the 8-bit elements of the destination vector.

Advanced SIMD
(FEAT_FP8)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	1	0	0	1	0	Rm					1	1	1	1	0	1	Rn					Rd
		U						size									opcode

Decode for this encoding

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let datasize : integer{} = if Q == '1' then 128 else 64; let elements : integer = datasize DIV 16;

Assembler Symbols

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in Q:

Q	<Ta>
0	8B
1	16B

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in Q:

Q	<Tb>
0	4H
1	8H

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(datasize) = V{}(m); var result : bits(datasize); for e = 0 to elements-1 do result[(0*elements + e)*:8] = FPConvertFP8{8, 16}(operand1[e*:16], FPCR(), FPMR()); result[(1*elements + e)*:8] = FPConvertFP8{8, 16}(operand2[e*:16], FPCR(), FPMR()); end; V{datasize}(d) = result;

2025-12_rel 2025-12-10 16:41:45