FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)

8-bit floating-point multiply-add to single-precision (vector)

This instruction widens the first (bottom bottom), second (bottom top), third (top bottom), or fourth (top top) 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Advanced SIMD
(FEAT_FP8FMA)

313029282726252423222120191817161514131211109876543210
0Q0011100x0Rm110001RnRd
Usizeopcode

Encoding for the FMLALLBB variant

Applies when (Q == 0 && size == 00)

FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B

Encoding for the FMLALLBT variant

Applies when (Q == 0 && size == 01)

FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.16B

Encoding for the FMLALLTB variant

Applies when (Q == 1 && size == 00)

FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.16B

Encoding for the FMLALLTT variant

Applies when (Q == 1 && size == 01)

FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.16B

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP8FMA) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let elements : integer = 128 DIV 32; let sel : integer = UInt(Q::size[0]);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


2025-12_rel 2025-12-10 16:41:45

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