LUTI6 (vector, 16-bit) -- A64

This instruction copies indexed 16-bit elements from the low 512 bits of the two table vectors to four destination vectors using packed 6-bit indices in the low or high one and a half vector segment of the two source vectors. The source vectors segment consumed in order to fill the destination vectors is selected by the source vector segment index. This instruction is unpredicated. This instruction requires that the Effective SVE vector length is at least 512 bits.

Consecutive
(FEAT_SME2p3)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; if MaxImplementedSVL() < 512 then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let isize : integer{} = 6; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let dstride : integer = 1; let d : integer = UInt(Zd::'00'); let select : integer = UInt(i1);

Strided
(FEAT_SME2p3)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; if MaxImplementedSVL() < 512 then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let isize : integer{} = 6; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let dstride : integer = 4; let d : integer = UInt(D::'00'::Zd); let select : integer = UInt(i1);

Assembler Symbols

<Zd1>	For the "Consecutive" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
	For the "Strided" variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd4>	For the "Consecutive" variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.
	For the "Strided" variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first table vector register, encoded as "Zn".

<Zn2>

Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32.

<Zm1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zm".

<Zm2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zm" plus 1 modulo 32.

<index>

Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); if VL < 512 then EndOfDecode(Decode_UNDEF); end; let elements : integer = VL DIV esize; let operand : bits(2*VL) = Z{VL}((m+1) MOD 32) :: Z{VL}(m+0); let idxsize : integer{} = VL + (VL DIV 2); let idxpos : integer{} = if select == 1 then (VL DIV 2) else 0; let indexes : bits(idxsize) = operand[idxpos+:idxsize]; let table : bits(1024) = Z{VL}((n+1) MOD 32)[511:0] :: Z{VL}(n+0)[511:0]; var dst : integer = d; var result : bits(VL); for r = 0 to 3 do let base : integer = r * elements; for e = 0 to elements-1 do let index : integer = UInt(indexes[(base+e)*:isize]); result[e*:esize] = table[index*:esize]; end; Z{VL}(dst) = result; dst = dst + dstride; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2025-12_rel 2025-12-10 16:41:45