Lookup table read with 6-bit indices (8-bit)
This instruction copies indexed 8-bit elements from the low 256 bits of the two table vectors to the destination vector using packed 6-bit indices from the bottom three quarters of the source vector.
This instruction is unpredicated.
This instruction requires that the Effective SVE vector length is at least 256 bits.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Zm | 1 | 0 | 1 | 0 | 1 | 1 | Zn | Zd | ||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p3) then EndOfDecode(Decode_UNDEF); end; if MaxImplementedAnyVL() < 256 then EndOfDecode(Decode_UNDEF); end; let isize : integer{} = 6; let esize : integer{} = 8; let m : integer = UInt(Zm); let n : integer = UInt(Zn); let d : integer = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first table vector register, encoded as "Zn". |
| <Zn2> |
Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32. |
| <Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); if VL < 256 then EndOfDecode(Decode_UNDEF); end; let elements : integer = VL DIV esize; let indexes : bits(VL) = Z{}(m); // Only bottom 3/4 used let table : bits(512) = Z{VL}((n+1) MOD 32)[255:0] :: Z{VL}(n+0)[255:0]; var result : bits(VL); for e = 0 to elements-1 do let index : integer = UInt(indexes[e*:isize]); let res : bits(esize) = table[index*:esize]; result[e*:esize] = res; end; Z{VL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2025-12_rel 2025-12-10 16:41:45
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