Multiply-add checked pointer vectors
This instruction multiplies, with overflow check, the elements of the first and second source vectors and adds the results of multiplication, with pointer check, to elements of the third source (addend) vector. The final results are destructively placed in the destination and third source (addend) vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | Zm | 1 | 1 | 0 | 1 | 0 | 0 | Zn | Zda | ||||||||||||
| opc | o2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_CPA) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 64; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do let element1 : integer = SInt(operand1[e*:64]); let element2 : integer = SInt(operand2[e*:64]); let product : integer = element1 * element2; let overflow : boolean = (product != SInt(product[63:0])); let addend : bits(64) = operand3[e*:64]; result[e*:64] = PointerMultiplyAddCheck(addend + product, addend, overflow); end; Z{VL}(da) = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2025-12_rel 2025-12-10 16:41:45
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