Bitwise rotate left by 1 and exclusive-OR
This instruction rotates each 64-bit element of the second source vector left by 1 and performs an exclusive-OR with the corresponding elements of the first source vector. The results are placed in the corresponding elements of the destination vector. This instruction is unpredicated.
ID_AA64ZFR0_EL1.SHA3 indicates whether this instruction is implemented.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p1 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Zm | 1 | 1 | 1 | 1 | 0 | 1 | Zn | Zd | ||||||||||||
| size | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE_SHA3) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
if IsFeatureImplemented(FEAT_SME2p1) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 64; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); var result : bits(VL); for e = 0 to elements-1 do let element1 : bits(64) = operand1[e*:64]; let element2 : bits(64) = operand2[e*:64]; result[e*:64] = element1 XOR ROL(element2, 1); end; Z{VL}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2025-12_rel 2025-12-10 16:41:45
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