SQDMULLB (indexed)

Signed saturating doubling multiply by indexed element (bottom)

This instruction multiplies the even-numbered signed elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment, and then doubles and places the results in overlapping double-width elements of the destination vector register. Each result element is saturated to the double-width N-bit element's signed integer range -2(N-1) to (2(N-1))-1.

The elements within the second source vector are specified using an immediate index that selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01000100101i3hZm1110i3l0ZnZd
sizeT

Encoding

SQDMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let index : integer = UInt(i3h::i3l); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let sel : integer = 0;

64-bit
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01000100111i2hZm1110i2l0ZnZd
sizeT

Encoding

SQDMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let index : integer = UInt(i2h::i2l); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let sel : integer = 0;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<imm>

For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.


2025-12_rel 2025-12-10 16:41:45

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