Multi-vector signed 32-bit integer saturating rounding shift right narrow by immediate to unsigned 16-bit integer
This instruction shifts right by an immediate value the signed integer value in each element of the two source vectors, and places the rounded results in the half-width destination elements. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to 16.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | imm4 | 1 | 1 | 0 | 1 | 0 | 1 | Zn | 0 | Zd | ||||||||||
| op | U | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd); let shift : integer = esize - UInt(imm4);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
| <const> |
Is the immediate shift amount, in the range 1 to 16, encoded in the "imm4" field. |
CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV (2 * esize); var result : bits(VL); for r = 0 to 1 do let operand : bits(VL) = Z{}(n+r); for e = 0 to elements-1 do let element : bits(2 * esize) = operand[e*:(2 * esize)]; let res : integer = (SInt(element) + (1 << (shift-1))) >> shift; result[(r*elements + e)*:esize] = UnsignedSat{esize}(res); end; end; Z{VL}(d) = result;
2025-12_rel 2025-12-10 16:41:45
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