ST1W (scalar plus scalar, tile slice)

Contiguous store of words from 32-bit element ZA tile slice

This instruction performs a contiguous store of words from a 32-bit element ZA tile slice. The slice number within the tile is selected by the sum of the slice index register and immediate offset, modulo the number of 32-bit elements in a vector. The immediate offset is in the range 0 to 3. The memory address is generated by a 64-bit scalar base and an optional 64-bit scalar offset that is multiplied by 4 and added to the base address. Inactive elements are not written to memory.

SME
(FEAT_SME)

313029282726252423222120191817161514131211109876543210
11100000101RmVRsPgRn0ZAtoff2
msz

Encoding

ST1W { <ZAt><HV>.S[<Ws>, <offs>] }, <Pg>, [<Xn|SP>{, <Xm>, LSL #2}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let m : integer = UInt(Rm); let g : integer = UInt('0'::Pg); let s : integer = UInt('011'::Rs); let t : integer = UInt(ZAt); let offset : integer = UInt(off2); let esize : integer{} = 32; let vertical : boolean = V == '1';

Assembler Symbols

<ZAt>

Is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAt" field.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V <HV>
0 H
1 V
<Ws>

Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs>

Is the slice index offset, in the range 0 to 3, encoded in the "off2" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-12_rel 2025-12-10 16:41:45

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