UMLSLL (multiple and single vector)

Multi-vector unsigned integer multiply-subtract long long by vector

This instruction multiplies each unsigned 8-bit or 16-bit element in the one, two, or four first source vectors by each unsigned 8-bit or 16-bit element in the second source vector, widens each product to 32 bits or 64 bits, and destructively subtracts these values from the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.

The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

It has encodings from 3 classes: One ZA quad-vector , Two ZA quad-vectors and Four ZA quad-vectors

One ZA quad-vector
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv001Zn110off2
USop

Encoding

UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>], <Zn>.<Tb>, <Zm>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off2::'00'); let nreg : integer{} = 1;

Two ZA quad-vectors
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv000Zn1100o1
USop

Encoding

UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zm>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 2;

Four ZA quad-vectors
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv000Zn1100o1
USop

Encoding

UMLSLL ZA.<T>[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.<Tb>-<Zn4>.<Tb> }, <Zm>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if sz == '1' && !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32 << UInt(sz); let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 4;

Assembler Symbols

<T>

Is the size specifier, encoded in sz:

sz <T>
0 S
1 D
<Wv>

Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1>

For the "One ZA quad-vector" variant: is the first vector select offset, encoded as "off2" field times 4.

For the "Four ZA quad-vectors" and "Two ZA quad-vectors" variants: is the first vector select offset, encoded as "o1" field times 4.

<offs4>

For the "One ZA quad-vector" variant: is the fourth vector select offset, encoded as "off2" field times 4 plus 3.

For the "Four ZA quad-vectors" and "Two ZA quad-vectors" variants: is the fourth vector select offset, encoded as "o1" field times 4 plus 3.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in sz:

sz <Tb>
0 B
1 H
<Zm>

Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<Zn1>

Is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn".

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" plus 1 modulo 32.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" plus 3 modulo 32.

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-12_rel 2025-12-10 16:41:45

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