UMOP4A (2-way)

Unsigned 16-bit integer quarter-tile sum of outer products to 32-bit integer, accumulating

This instruction generates four independent quarter-tile unsigned integer sums of outer products from the sub-matrices in the half-vectors of the one or two first and second source vectors and accumulates the results to the corresponding elements of a 32-bit element ZA tile.

Each of the quarter-tile sums of outer products is generated by multiplying the SVLS÷2 × 2 sub-matrix of 16-bit unsigned values held in the half-vectors of the first source vectors by the 2 × SVLS÷2 sub-matrix of 16-bit unsigned values held in the half-vectors of the second source vectors. Each 32-bit container of the half-vectors in the first source vectors holds 2 elements of each row of a SVLS÷2 × 2 sub-matrix. Similarly, each 32-bit container of the half-vectors in the second source vector holds 2 elements of each column of a 2 × SVLS÷2 sub-matrix. The resulting quarter-tile SVLS÷2 × SVLS÷2 widened 32-bit integer sums of outer products are then destructively added to the 32-bit integer destination tile.

This is equivalent to performing a 2-way dot product and accumulate to each of the destination tile elements.

This instruction is unpredicated.

It has encodings from 4 classes: Single and multiple vectors , Single vectors , Multiple and single vectors and Multiple vectors

Single and multiple vectors
(FEAT_SME_MOP4)

313029282726252423222120191817161514131211109876543210
100000010001Zm01000000Zn0010ZAda
u0MNS

Encoding

UMOP4A <ZAda>.S, <Zn>.H, { <Zm1>.H-<Zm2>.H }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = FALSE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = TRUE;

Single vectors
(FEAT_SME_MOP4)

313029282726252423222120191817161514131211109876543210
100000010000Zm01000000Zn0010ZAda
u0MNS

Encoding

UMOP4A <ZAda>.S, <Zn>.H, <Zm>.H

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = FALSE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = TRUE;

Multiple and single vectors
(FEAT_SME_MOP4)

313029282726252423222120191817161514131211109876543210
100000010000Zm01000001Zn0010ZAda
u0MNS

Encoding

UMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, <Zm>.H

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = FALSE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = TRUE;

Multiple vectors
(FEAT_SME_MOP4)

313029282726252423222120191817161514131211109876543210
100000010001Zm01000001Zn0010ZAda
u0MNS

Encoding

UMOP4A <ZAda>.S, { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = FALSE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = TRUE;

Assembler Symbols

<ZAda>

Is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.

<Zn>

Is the name of the first source scalable vector register, registers in the range Z0-Z15, encoded as "Zn" times 2.

<Zm1>

Is the name of the first scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 16.

<Zm2>

Is the name of the second scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 17.

<Zm>

Is the name of the second source scalable vector register, registers in the range Z16-Z31, encoded as "Zm" times 2 plus 16.

<Zn1>

Is the name of the first scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2 plus 1.

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-12_rel 2025-12-10 16:41:45

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