AARCHMRS Schema 2.7.4

2.7

Highlights

AARCHMRS-5447: Improve the Registers schema (2.7.4)

The Registers schema has been improved to include information about the schema.

AARCHMRS-5366: Disallow additional properties for ConditionalField.fields and Resets (2.7.3)

The schema has been improved to use the correct additionalProperties for the following schemas:

AARCHMRS-5420: Add Registers schema to support an array of Register, RegisterArray, or RegisterBlock (2.7.3)

A Registers schema has been added to represent an array that can contain the following objects:

AARCHMRS-5239: Support for additional combinations of read/write accesses and side effects

Support has been added for the following shorthand read/write accesses:

  1. RC/WS (W: sets all bits, R: clears all bits)
  2. RS/WC (W: clears all bits, R: sets all bits)
  3. RC/W1S (W: 1/0 sets/no effect on matching bit, R: clears all bits)
  4. RS/W1C (W: 1/0 clears/no effect on matching bit, R: sets all bits)
  5. RC/W0S (W: 1/0 no effect on/sets matching bit, R: clears all bits)
  6. RS/W0C (W: 1/0 no effect on/clears matching bit, R: sets all bits)
  7. ERROR/W (W: as-is, R: error)
  8. ERROR/W0C (W: clears all bits, R: error)
  9. ERROR/W0S (W: sets all bits, R: error)

AARCHMRS-5227: Update ASL1 implication and logical equivalence syntax

The syntax of the implication and logical equivalence has been updated in the BinaryOp schema to align with the latest ASL reference documentation as the following:

For more details refer to Chapter 3 of ASLRef BET0.

AARCHMRS-5226: Change AST.Concat into an AST.BinaryOp operator (::)

In order to align more closely with the ASL Reference manual we have updated bit concatenation to an AST.BinaryOp operator.

AST.Concat will remain in use when specifying mulit-bit field accesses of the form REG.[F1,F2] and is planned for deprecation in a future version when a better model is made available.