GICM_SETSPI_SR, Set Secure SPI Pending Register

The GICM_SETSPI_SR characteristics are:

Purpose

Adds the pending state to a valid SPI.

A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.

Configuration

This register is present only when GICM_TYPER.SR == 1. Otherwise, direct accesses to GICM_SETSPI_SR are RES0.

When GICD_CTLR.DS==1, this register is WI.

Attributes

GICM_SETSPI_SR is a 32-bit register.

Field descriptions

The GICM_SETSPI_SR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0INTID

Bits [31:13]

Reserved, RES0.

INTID, bits [12:0]

This field is an alias of GICD_SETSPI_SR.

Accessing the GICM_SETSPI_SR

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

GICM_SETSPI_SR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorMSI_base0x0050GICM_SETSPI_SR

This interface is accessible as follows:


30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.