GICC_IIDR, CPU Interface Identification Register

The GICC_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the CPU interface.

Configuration

Attributes

GICC_IIDR is a 32-bit register.

Field descriptions

The GICC_IIDR bit assignments are:

313029282726252423222120191817161514131211109876543210
ProductIDArchitecture_versionRevisionImplementer

ProductID, bits [31:20]

Product Identifier.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Architecture_version, bits [19:16]

The version of the GIC architecture that is implemented.

Architecture_versionMeaning
0b0001

GICv1.

0b0010

GICv2.

0b0011

FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

0b0100

FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

Other values are reserved.

Revision, bits [15:12]

Revision number for the CPU interface.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Implementer, bits [11:0]

Contains the JEP106 code of the company that implemented the CPU interface.

Accessing the GICC_IIDR

GICC_IIDR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC CPU interface0x00FCGICC_IIDR

This interface is accessible as follows:


30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e

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