The GICM_SETSPI_SR characteristics are:
Adds the pending state to a valid SPI.
A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.
This register is present only when GICM_TYPER.SR == 1. Otherwise, direct accesses to GICM_SETSPI_SR are RES0.
When GICD_CTLR.DS==1, this register is WI.
GICM_SETSPI_SR is a 32-bit register.
The GICM_SETSPI_SR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | INTID |
Reserved, RES0.
This field is an alias of GICD_SETSPI_SR.
Writes to this register have no effect if:
16-bit accesses to bits [15:0] of this register must be supported.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | MSI_base | 0x0050 | GICM_SETSPI_SR |
This interface is accessible as follows:
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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