The TRCLAR characteristics are:
Used to lock and unlock the Software Lock.
Note that ETE does not implement the Software Lock.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCLAR are RES0.
TRCLAR is a 32-bit register.
The TRCLAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY |
Software Lock Key.
A value of 0xC5ACCE55 unlocks the Software Lock.
Any other value locks the Software Lock.
Reserved, RES0.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFB0 | TRCLAR |
This interface is accessible as follows:
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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