The PMCR_EL0 characteristics are:
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
AArch64 System register PMCR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCR[31:0].
AArch64 System register PMCR_EL0 bits [7:0] are architecturally mapped to External register PMCR_EL0[7:0].
This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCR_EL0 are UNDEFINED.
PMCR_EL0 is a 64-bit register.
The PMCR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FZS | ||||||||||||||||||||||||||||||
IMP | IDCODE | N | RES0 | FZO | RES0 | LP | LC | DP | X | D | C | P | E |
Reserved, RES0.
Freeze-on-SPE event. Stop counters when PMBLIMITR_EL1.{PMFZ,E} == {1,1} and PMBSR_EL1.S == 1.
FZS | Meaning |
---|---|
0b0 |
Do not freeze on Statistical Profiling Buffer Management event. |
0b1 |
Event counters do not count following a Statistical Profiling Buffer Management event. |
If EL2 is implemented, then:
This field does not affect the operation of PMCCNTR_EL0.
On a Warm reset, when AArch32 is supported at any Exception level, this field resets to 0.
On a Warm reset, when the implementation only supports execution in AArch64 state, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Implementer code.
If this field is zero, then PMCR_EL0.IDCODE is RES0 and software must use MIDR_EL1 to identify the PE.
Otherwise, this field and PMCR_EL0.IDCODE identify the PMU implementation to software. The implementer codes are allocated by Arm. A non-zero value has the same interpretation as MIDR_EL1.Implementer.
Use of this field is deprecated.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RAZ.
Identification code. Use of this field is deprecated. This field has an IMPLEMENTATION DEFINED value.
Each implementer must maintain a list of identification codes that are specific to the implementer. A specific implementation is identified by the combination of the implementer code and the identification code.
Access to this field is RO.
Reserved, RES0.
Indicates the number of event counters implemented. This value is in the range of 0b00000-0b11111. If the value is 0b00000 then only PMCCNTR_EL0 is implemented. If the value is 0b11111 PMCCNTR_EL0 and 31 event counters are implemented.
When EL2 is implemented and enabled for the current Security state, reads of this field from EL1 and EL0 return the value of MDCR_EL2.HPMN.
Access to this field is RO.
Reserved, RES0.
Freeze-on-overflow. Stop event counters on overflow.
FZO | Meaning |
---|---|
0b0 |
Do not freeze on overflow. |
0b1 |
Event counters do not count when PMOVSCLR_EL0[(N-1):0] is nonzero, where N is the value of MDCR_EL2.HPMN if EL2 is implemented, and PMCR_EL0.N otherwise. |
If EL2 is implemented, then:
This field does not affect the operation of PMCCNTR_EL0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
LP | Meaning |
---|---|
0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. |
0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. |
If EL2 is implemented and MDCR_EL2.HPMN or HDCR.HPMN is less than PMCR_EL0.N, this bit does not affect the operation of event counters in the range [HDCR.HPMN..(PMCR_EL0.N-1)] or [MDCR_EL2.HPMN..(PMCR_EL0.N-1)].
The effect of MDCR_EL2.HPMN or HDCR.HPMN on the operation of this bit always applies if EL2 is implemented, at all Exception levels including EL2 and EL3, and regardless of whether EL2 is enabled in the current Security state. For more information, see the description of MDCR_EL2.HPMN or HDCR.HPMN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.
LC | Meaning |
---|---|
0b0 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. |
0b1 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. |
Arm deprecates use of PMCR_EL0.LC = 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Disable cycle counter when event counting is prohibited.
DP | Meaning |
---|---|
0b0 |
Cycle counting by PMCCNTR_EL0 is not affected by this bit. |
0b1 |
When event counting for counters in the range [0..(MDCR_EL2.HPMN-1)] is prohibited, cycle counting by PMCCNTR_EL0 is disabled. |
For more information see 'Prohibiting event counting'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.
X | Meaning |
---|---|
0b0 |
Do not export events. |
0b1 |
Export events where not prohibited. |
This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL PE trace unit.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Clock divider.
D | Meaning |
---|---|
0b0 |
When enabled, PMCCNTR_EL0 counts every clock cycle. |
0b1 |
When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. |
If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
Arm deprecates use of PMCR_EL0.D = 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Cycle counter reset. The effects of writing to this bit are:
C | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Reset PMCCNTR_EL0 to zero. |
Resetting PMCCNTR_EL0 does not change the cycle counter overflow bit. If FEAT_PMUv3p5 is implemented, the value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset.
Access to this field is WO/RAZ.
Event counter reset. The effects of writing to this bit are:
P | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Reset all event counters accessible in the current Exception level, not including PMCCNTR_EL0, to zero. |
In EL0 and EL1:
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not change the event counter overflow bits. If FEAT_PMUv3p5 is implemented, the values of MDCR_EL2.HLP and PMCR_EL0.LP are ignored, and bits [63:0] of all affected event counters are reset.
Access to this field is WO/RAZ.
Enable.
E | Meaning |
---|---|
0b0 |
All event counters in the range [0..(PMN-1)] and PMCCNTR_EL0, are disabled. |
0b1 |
All event counters in the range [0..(PMN-1)] and PMCCNTR_EL0, are enabled by PMCNTENSET_EL0. |
If EL2 is implemented, then:
If EL2 is not implemented, PMN is PMCR_EL0.N.
The effect of MDCR_EL2.HPMN or HDCR.HPMN on the operation of this bit always applies if EL2 is implemented, at all Exception levels including EL2 and EL3, and regardless of whether EL2 is enabled in the current Security state. For more information, see the description of MDCR_EL2.HPMN or HDCR.HPMN.
On a Warm reset, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1100 | 0b000 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMCR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMCR_EL0; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMCR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMCR_EL0; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMCR_EL0; elsif PSTATE.EL == EL3 then return PMCR_EL0;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1100 | 0b000 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMCR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMCR_EL0 = X[t]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMCR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMCR_EL0 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMCR_EL0 = X[t]; elsif PSTATE.EL == EL3 then PMCR_EL0 = X[t];
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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