The CNTP_CTL characteristics are:
Control register for the EL1 physical timer.
The power domain of CNTP_CTL is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTP_CTL is a 32-bit register.
The CNTP_CTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ISTATUS | IMASK | ENABLE |
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
ISTATUS | Meaning |
---|---|
0b0 |
Timer condition is not met. |
0b1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
On a Timer reset, this field resets to an architecturally UNKNOWN value.
Access to this field is RO.
Timer interrupt mask bit. Permitted values are:
IMASK | Meaning |
---|---|
0b0 |
Timer interrupt is not masked by the IMASK bit. |
0b1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
On a Timer reset, this field resets to an architecturally UNKNOWN value.
Enables the timer. Permitted values are:
ENABLE | Meaning |
---|---|
0b0 |
Timer disabled. |
0b1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTP_TVAL continues to count down.
Disabling the output signal might be a power-saving option.
On a Timer reset, this field resets to an architecturally UNKNOWN value.
CNTP_CTL can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.
'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:
For an implemented CNTBaseN frame:
For an implemented CNTEL0BaseN frame:
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTBaseN | 0x02C | CNTP_CTL |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTEL0BaseN | 0x02C | CNTP_CTL |
Accesses on this interface are RW.
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.