TRCDEVAFF, Device Affinity Register

The TRCDEVAFF characteristics are:

Purpose

For additional information, see the CoreSight Architecture Specification.

Reads the same value as the MPIDR_EL1 register for the PE that this trace unit has affinity with.

Configuration

This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCDEVAFF are RES0.

Attributes

TRCDEVAFF is a 64-bit register.

Field descriptions

The TRCDEVAFF bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
MPIDR_EL1
MPIDR_EL1

MPIDR_EL1, bits [63:0]

Read-only copy of MPIDR_EL1, as seen from the highest implemented Exception level.

Accessing the TRCDEVAFF

External debugger accesses to this register are unaffected by the OS Lock.

TRCDEVAFF can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0xFA8TRCDEVAFF

This interface is accessible as follows:


30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e

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