The CNTPCT characteristics are:
Holds the 64-bit physical count value.
The power domain of CNTPCT is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTPCT is a 64-bit register.
The CNTPCT bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Physical count value | |||||||||||||||||||||||||||||||
Physical count value |
Physical count value.
On a Timer reset, this field resets to an architecturally UNKNOWN value.
CNTPCT can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame, as a RO register.
'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:
For an implemented CNTBaseN frame:
For an implemented CNTEL0BaseN frame:
If the implementation supports 64-bit atomic accesses, then the CNTPCT register must be accessible as an atomic 64-bit value.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTBaseN | 0x000 | CNTPCT | 31:0 |
Accesses on this interface are RO.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTBaseN | 0x004 | CNTPCT | 63:32 |
Accesses on this interface are RO.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTEL0BaseN | 0x000 | CNTPCT | 31:0 |
Accesses on this interface are RO.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTEL0BaseN | 0x004 | CNTPCT | 63:32 |
Accesses on this interface are RO.
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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