The AMCIDR3 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Component identification scheme'.
The power domain of AMCIDR3 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMCIDR3 is a 32-bit register.
The AMCIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_3 |
Reserved, RES0.
Preamble.
Reads as 0xB1.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xFFC | AMCIDR3 |
Accesses on this interface are RO.
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.