The TRCEXTINSELR<n> characteristics are:
Use this to set, or read, which External Inputs are resources to the trace unit.
The name TRCEXTINSELR is an alias of TRCEXTINSELR0.
External register TRCEXTINSELR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCEXTINSELR<n>[31:0].
This register is present only when FEAT_ETE is implemented and TRCIDR5.NUMEXTINSEL > n. Otherwise, direct accesses to TRCEXTINSELR<n> are RES0.
TRCEXTINSELR<n> is a 32-bit register.
The TRCEXTINSELR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | evtCount |
Reserved, RES0.
PMU event to select.
The event number as defined by the Arm ARM.
Software must program this field with a PMU event that is supported by the PE being programmed.
There are three ranges of PMU event numbers:
If evtCount is programmed to a PMU event that is reserved or not supported by the PE, the behavior depends on the PMU event type:
UNPREDICTABLE means the PMU event must not expose privileged information.
Arm recommends that the behavior across a family of implementations is defined such that if a given implementation does not include a PMU event from a set of common IMPLEMENTATION DEFINED PMU events, then no PMU event is counted and the value read back on evtCount is the value written.
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Must be programmed if any of the following is true: TRCRSCTLR<a>.GROUP == 0b0000 and TRCRSCTLR<a>.EXTIN[n] == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Component | Offset | Instance |
---|---|---|
ETE | 0x120 + (4 * n) | TRCEXTINSELR<n> |
This interface is accessible as follows:
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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