The BRBINFINJ_EL1 characteristics are:
The information of a Branch record for injection.
This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBINFINJ_EL1 are UNDEFINED.
BRBINFINJ_EL1 is a 64-bit register.
The BRBINFINJ_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CCU | CC | |||||||||||||||||||||||||||||
RES0 | LASTFAILED | T | RES0 | TYPE | EL | MPRED | RES0 | VALID |
Reserved, RES0.
The number of PE clock cycles since the last Branch record entry is UNKNOWN.
CCU | Meaning |
---|---|
0b0 |
Indicates that the number of PE clock cycles since the last Branch record is indicated by BRBINFINJ_EL1.CC. |
0b1 |
Indicates that the number of PE clock cycles since the last Branch record is UNKNOWN. |
The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
The number of PE clock cycles since the last Branch record entry.
The format of this field uses a mantissa and exponent to express the cycle count value, as follows:
The cycle count is expressed using the following function:
if IsZero(E) then UInt(M) else UInt('1':M:Zeros(UInt(E)-1))
If required, the cycle count is rounded to a multiple of 2(E-1) towards zero before being encoded.
A value of all ones in both the mantissa and exponent indicates the cycle count value exceeded the size of the cycle counter.
The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Reserved, RES0.
Indicates transaction failure or cancellation.
LASTFAILED | Meaning |
---|---|
0b0 |
Indicates that no transactions in a non-prohibited region have failed or been canceled between the previous Branch record and this Branch record. |
0b1 |
Indicates that at least one transaction in a non-prohibited region has failed or been canceled between the previous Branch record and this Branch record. |
The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Reserved, RES0.
Transactional state.
T | Meaning |
---|---|
0b0 |
The branch or exception was not executed in Transactional state. |
0b1 |
The branch or exception was executed in Transactional state. |
The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b10 or BRBINFINJ_EL1.VALID == 0b11.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Reserved, RES0.
Reserved, RES0.
Branch type.
TYPE | Meaning |
---|---|
0b000000 |
Direct branch, excluding Branch with link. |
0b000001 |
Indirect branch, excluding Branch with link, Return from subroutine, and Exception return. |
0b000010 |
Direct Branch with link. |
0b000011 |
Indirect Branch with link. |
0b000101 |
Return from subroutine. |
0b000111 |
Exception return. |
0b100001 |
Debug halt. |
0b100010 |
Call. |
0b100011 |
Trap. |
0b100100 |
SError. |
0b100110 |
Instruction debug. |
0b100111 |
Data debug. |
0b101010 |
Alignment. |
0b101011 |
Inst Fault. |
0b101100 |
Data Fault. |
0b101110 |
IRQ. |
0b101111 |
FIQ. |
0b111001 |
Debug State Exit. |
All other values are reserved.
The value in this field is only valid when BRBINFINJ_EL1.VALID != 0b00.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
The Exception Level at the target address.
EL | Meaning |
---|---|
0b00 |
EL0. |
0b01 |
EL1. |
0b10 |
EL2. |
All other values are reserved.
The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b11 or BRBINFINJ_EL1.VALID == 0b01.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Branch mispredict.
MPRED | Meaning |
---|---|
0b0 |
Branch was correctly predicted or the result of the prediction was not captured. |
0b1 |
Branch was incorrectly predicted. |
The value in this field is only valid when BRBINFINJ_EL1.VALID == 0b11 or BRBINFINJ_EL1.VALID == 0b10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Reserved, RES0.
The Branch record is valid.
VALID | Meaning |
---|---|
0b00 | This Branch record is not valid. The values of following fields are not valid:
|
0b01 | This Branch record is valid. The values of following fields are not valid:
|
0b10 | This Branch record is valid. The values of following fields are not valid:
|
0b11 |
This Branch record is valid. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b1001 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.nBRBDATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return BRBINFINJ_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return BRBINFINJ_EL1; elsif PSTATE.EL == EL3 then return BRBINFINJ_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b1001 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.nBRBDATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else BRBINFINJ_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else BRBINFINJ_EL1 = X[t]; elsif PSTATE.EL == EL3 then BRBINFINJ_EL1 = X[t];
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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