The MPAMF_ERR_MSI_ATTR characteristics are:
MPAMF_ERR_MSI_ATTR is a 32-bit read/write register that controls MPAM error MSI write attributes for MPAM errors in this MSC.
The power domain of MPAMF_ERR_MSI_ATTR is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_ERR_MSI == 1. Otherwise, direct accesses to MPAMF_ERR_MSI_ATTR are RES0.
The power and reset domain of each MSC component is specific to that component.
MPAMF_ERR_MSI_ATTR is a 32-bit register.
The MPAMF_ERR_MSI_ATTR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | MSI_SH | MSI_MEMATTR | RES0 | MSIEN |
Reserved, RES0.
Sharability attribute of MSI writes.
MSI_SH | Meaning |
---|---|
0b00 |
Non-shareable. |
0b01 |
Reserved, CONSTRAINED UNPREDICTABLE. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
When MPAMF_ERR_MSI_ATTR.MSI_MEMATTR specifies a Device memory type, the contents of this field are IGNORED and Shareability is effectively Outer Shareable.
Memory attributes of MSI writes.
Note: This encoding matches the VMSAv8-64 stage 2 MemAttr[3:0] field as described in the Arm ARM, except that the following encodings are Reserved (not UNPREDICTABLE) and behave as DEvice-nGnRnE: 0b0100, 0b1000, and 0b1100.
MSI_MEMATTR | Meaning |
---|---|
0b0000 |
Device-nGnRnE. |
0b0001 |
Device-nGnRE. |
0b0010 |
Device-nGRE. |
0b0011 |
Device-GRE. |
0b0100 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b0101 |
Normal Inner Non-cacheable, Outer Non-cacheable. |
0b0110 |
Normal Inner Write-Through Cacheable, Outer Non-cacheable. |
0b0111 |
Normal Inner Write-Back Cacheable, Outer Non-cacheable. |
0b1000 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b1001 |
Normal Inner Non-Cachable, Outer Write-Through Cacheable. |
0b1010 |
Normal Inner Write-Through Cacheable, Outer Write-Through Cacheable. |
0b1011 |
Normal Inner Write-Back Cacheable, Outer Write-Through Cacheable. |
0b1100 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b1101 |
Normal Inner Non-cacheable, Outer Write-Back Cacheable. |
0b1110 |
Normal Inner Write-Through Cacheable, Outer Write-Back Cacheable. |
0b1111 |
Normal Inner Write-Back Cacheable, Outer Write-Back Cacheable. |
When this field specifies a Device memory type, the contents of MPAMF_ERR_MSI_ATTR.MSI_SH are IGNORED and Shareability is effectively Outer Shareable.
Device types may be implemented as any Device type with more than 'n' characters. For example, if this field is set to 0b0010, an implementation may treat the MSI write as the specified type, Device-nGRE, or as Device-nGnRE or as Device-nGnRnE.
Reserved encodings 0b0100, 0b1000, and 0b1100 must be implemented to behave the same as the 0b0000 encoding.
Reserved, RES0.
Error interrupt MSI Enable.
MSIEN | Meaning |
---|---|
0b0 |
MPAM error MSI writes are not generated to signal enabled MPAM error interrupts. When error MSI writesare disabled, hardwired error interrupts could be generated. |
0b1 |
MPAM error MSI writes are generated to signal enabled MPAM error interrupts. When error MSI writes are enabled, hardwired error interrupts are not generated. |
The value of this field affects whether hardwired error interrupts are generated.
On a MSC reset, this field resets to 0.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.
MPAMF_ERR_MSI_ATTR_s, MPAMF_ERR_MSI_ATTR_ns, MPAMF_ERR_MSI_ATTR_rt, and MPAMF_ERR_MSI_ATTR_rl must be separate registers.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x00EC | MPAMF_ERR_MSI_ATTR_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x00EC | MPAMF_ERR_MSI_ATTR_ns |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x00EC | MPAMF_ERR_MSI_ATTR_rt |
When FEAT_RME is implemented access on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x00EC | MPAMF_ERR_MSI_ATTR_rl |
When FEAT_RME is implemented access on this interface are RW.
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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