The DIT characteristics are:
Allows access to the Data Independent Timing bit.
This register is present only when FEAT_DIT is implemented. Otherwise, direct accesses to DIT are UNDEFINED.
DIT is a 64-bit register.
The DIT bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | DIT | RES0 |
Reserved, RES0.
Data Independent Timing.
DIT | Meaning |
---|---|
0b0 |
The architecture makes no statement about the timing properties of any instructions. |
0b1 | The architecture requires that:
|
The data processing instructions affected by this bit are:
All cryptographic instructions. These instructions are:
A subset of those instructions which use the general-purpose register file. These instructions are:
A subset of those instructions which use the SIMD&FP register file. These instructions are:
ABS, ADD, ADDHN, ADDHN2, ADDP, ADDV, AND, BIC, BIF, BIT, BSL, CLS, CLZ, CMEQ, CMGE, CMGT, CMHI, CMHS, CMLE, CMLT, CMTST, CNT, DUP, EOR, EXT, FCSEL, INS, MLA, MLS, MOV, MOVI, MUL, MVN, MVNI, NEG, NOT, ORN, ORR, PMUL, PMULL, PMULL2, RADDHN, RADDHN2, RBIT, REV16, REV32, RSHRN, RSHRN2, RSUBHN, RSUBHN2, SABA, SABD, SABAL, SABAL2, SABDL, SABDL2, SADALP, SADDL, SADDL2, SADDLP, SADDLV, SADDW, SADDW2, SHADD, SHL, SHLL, SHLL2, SHRN, SHRN2, SHSUB, SLI, SMAX, SMAXP, SMAXV, SMIN, SMINP, SMINV, SMLAL, SMLAL2, SMLSL, SMLSL2, SMOV, SMULL, SMULL2, SRI, SSHL, SSHLL, SSHLL2, SSHR, SSRA, SSUBL, SSUBL2, SSUBW, SSUBW2, SUB, SUBHN, SUBHN2, SXTL, SXTL2, TBL, TBX, TRN1, TRN2, UABA, UABAL, UABAL2, UABD, UABDL, UABDL2, UADALP, UADDL, UADDL2, UADDLP, UADDLV, UADDW, UADDW2, UHADD, UHSUB, UMAX, UMAXP, UMAXV, UMIN, UMINP, UMINV, UMLAL, UMLAL2, UMLSL, UMOV, UMLSL2, UMULL, UMULL2, USHL, USHLL, USHLL2, USHR, USRA, USUBL, USUBL2, USUBW, USUBW2, UXTL, UXTL2, UZP1, UZP2, XTN, XTN2, ZIP1, and ZIP2.
If FEAT_CRC32 is implemented, CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and CRC32CX.
The architecture makes no statement about the timing properties when the PSTATE.DIT bit is not set. However, it is likely that many of these instructions have timing that is invariant of the data in many situations.
In particular, Arm strongly recommends that the Armv8.3 pointer authentication instructions do not have their timing dependent on the key value used in the pointer authentication in all cases, regardless of the PSTATE.DIT bit.
On a Warm reset, this field resets to 0.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then return Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL1 then return Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL2 then return Zeros(39):PSTATE.DIT:Zeros(24); elsif PSTATE.EL == EL3 then return Zeros(39):PSTATE.DIT:Zeros(24);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then PSTATE.DIT = X[t]<24>; elsif PSTATE.EL == EL1 then PSTATE.DIT = X[t]<24>; elsif PSTATE.EL == EL2 then PSTATE.DIT = X[t]<24>; elsif PSTATE.EL == EL3 then PSTATE.DIT = X[t]<24>;
op0 | op1 | CRn | op2 |
---|---|---|---|
0b00 | 0b011 | 0b0100 | 0b010 |
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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