The CNTVCT characteristics are:
Holds the 64-bit virtual count value. The virtual count value is equal to the physical count value minus the virtual offset visible in CNTVOFF.
AArch32 System register CNTVCT bits [63:0] are architecturally mapped to AArch64 System register CNTVCT_EL0[63:0].
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to CNTVCT are UNDEFINED.
The value of this register is the same as the value of CNTPCT in the following conditions:
All reads to the CNTVCT occur in program order relative to reads to CNTVCTSS or CNTVCT.
CNTVCT is a 64-bit register.
The CNTVCT bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual count value | |||||||||||||||||||||||||||||||
Virtual count value |
Virtual count value.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | CRm | opc1 |
---|---|---|
0b1111 | 0b1110 | 0b0001 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0VCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVCT == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else if HaveEL(EL2) && !ELUsingAArch32(EL2) && (!EL2Enabled() || HCR_EL2.<E2H,TGE> != '11') then return PhysicalCountInt() - CNTVOFF_EL2; elsif HaveEL(EL2) && ELUsingAArch32(EL2) then return PhysicalCountInt() - CNTVOFF; else return PhysicalCountInt(); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && CNTHCTL_EL2.EL1TVCT == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else if HaveEL(EL2) && !ELUsingAArch32(EL2) then return PhysicalCountInt() - CNTVOFF_EL2; elsif HaveEL(EL2) && ELUsingAArch32(EL2) then return PhysicalCountInt() - CNTVOFF; else return PhysicalCountInt(); elsif PSTATE.EL == EL2 then return PhysicalCountInt() - CNTVOFF; elsif PSTATE.EL == EL3 then if HaveEL(EL2) then return PhysicalCountInt() - CNTVOFF; else return PhysicalCountInt();
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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