The TRCSEQSTR characteristics are:
Use this to set, or read, the Sequencer state.
External register TRCSEQSTR bits [31:0] are architecturally mapped to AArch64 System register TRCSEQSTR[31:0].
This register is present only when FEAT_ETE is implemented and TRCIDR5.NUMSEQSTATE != 0b000. Otherwise, direct accesses to TRCSEQSTR are RES0.
TRCSEQSTR is a 32-bit register.
The TRCSEQSTR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | STATE |
Reserved, RES0.
Set or returns the state of the Sequencer.
STATE | Meaning |
---|---|
0b00 |
State 0. |
0b01 |
State 1. |
0b10 |
State 2. |
0b11 |
State 3. |
On a Trace unit reset, this field resets to an architecturally UNKNOWN value.
Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.SEQUENCER != 0b0000.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
Component | Offset | Instance |
---|---|---|
ETE | 0x11C | TRCSEQSTR |
This interface is accessible as follows:
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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