TPIDR_EL3, EL3 Software Thread ID Register

The TPIDR_EL3 characteristics are:

Purpose

Provides a location where software executing at EL3 can store thread identifying information, for OS management purposes.

The PE makes no use of this register.

Configuration

This register is present only when EL3 is implemented. Otherwise, direct accesses to TPIDR_EL3 are UNDEFINED.

Attributes

TPIDR_EL3 is a 64-bit register.

Field descriptions

The TPIDR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Thread ID
Thread ID

Bits [63:0]

Thread ID. Thread identifying information stored by software running at this Exception level.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the TPIDR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, TPIDR_EL3

op0op1CRnCRmop2
0b110b1100b11010b00000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return TPIDR_EL3;

MSR TPIDR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b11010b00000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then TPIDR_EL3 = X[t];


30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.