The AMPIDR4 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Peripheral identification scheme'.
The power domain of AMPIDR4 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMPIDR4 is a 32-bit register.
The AMPIDR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
Size of the component. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.
This field reads as 0b0000.
Designer. JEP106 continuation code, least significant nibble.
For Arm Limited, this field is 0b0100.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xFD0 | AMPIDR4 |
Accesses on this interface are RO.
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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