The FPCR characteristics are:
Controls floating-point behavior.
AArch64 System register FPCR bits [26:15] are architecturally mapped to AArch32 System register FPSCR[26:15].
AArch64 System register FPCR bits [12:8] are architecturally mapped to AArch32 System register FPSCR[12:8].
It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to non-zero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ.
FPCR is a 64-bit register.
The FPCR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | AHP | DN | FZ | RMode | Stride | FZ16 | Len | IDE | RES0 | IXE | UFE | OFE | DZE | IOE | RES0 | NEP | AH | FIZ |
Reserved, RES0.
Alternative half-precision control bit.
AHP | Meaning |
---|---|
0b0 |
IEEE half-precision format selected. |
0b1 |
Alternative half-precision format selected. |
This bit is used only for conversions between half-precision floating-point and other floating-point formats.
The data-processing instructions added as part of the FEAT_FP16 extension always use the IEEE half-precision format, and ignore the value of this bit.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Default NaN use for NaN propagation.
DN | Meaning |
---|---|
0b0 |
NaN operands propagate through to the output of a floating-point operation. |
0b1 | Any operation involving one or more NaNs returns the Default NaN. This bit has no effect on the output of FABS, FMAX*, FMIN*, and FNEG instructions, and a default NaN is never returned as a result of these instructions. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Flushing denormalized numbers to zero control bit.
FZ | Meaning |
---|---|
0b0 | If FPCR.AH is 0, disables flushing to zero of inputs and outputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. If FPCR.AH is 1, disables flushing to zero of outputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. |
0b1 | Flushing denormalized numbers to zero enabled. If FPCR.AH is 0, enables flushing to zero of inputs and outputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. If FPCR.AH is 1, enables flushing to zero of outputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Rounding Mode control field.
RMode | Meaning |
---|---|
0b00 |
Round to Nearest (RN) mode. |
0b01 |
Round towards Plus Infinity (RP) mode. |
0b10 |
Round towards Minus Infinity (RM) mode. |
0b11 |
Round towards Zero (RZ) mode. |
The specified rounding mode is used by both scalar and Advanced SIMD floating-point instructions.
If FPCR.AH is 1, then the following instructions use Round to Nearest mode regardless of the value of this bit:
The FRECPE, FRECPS, FRECPX, FRSQRTE, and FRSQRTS instructions.
The BFCVT, BFCVTN, BFCVTN2, BFCVTNT, BFMLALB, and BFMLALT instructions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state.
This field is included only for context saving and restoration of the AArch32 FPSCR.Stride field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Flushing denormalized numbers to zero control bit on half-precision data-processing instructions.
FZ16 | Meaning |
---|---|
0b0 |
For some instructions, this bit disables flushing to zero of inputs and outputs that are half-precision denormalized numbers. For more information, see 'Flushing denormalized numbers to zero'. |
0b1 | Flushing denormalized numbers to zero enabled. For some instructions that do not convert a half-precision input to a higher precision output, this bit enables flushing to zero of inputs and outputs that are half-precision denormalized numbers. For more information, see 'Flushing denormalized numbers to zero'. |
The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state.
This field is included only for context saving and restoration of the AArch32 FPSCR.Len field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Input Denormal floating-point exception trap enable.
IDE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IDC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Inexact floating-point exception trap enable.
IXE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IXC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Underflow floating-point exception trap enable.
UFE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.UFC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs and Flush-to-zero is not enabled, the PE does not update the FPSR.UFC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Overflow floating-point exception trap enable.
OFE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.OFC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Divide by Zero floating-point exception trap enable.
DZE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.DZC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Invalid Operation floating-point exception trap enable.
IOE | Meaning |
---|---|
0b0 |
Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IOC bit is set to 1. |
0b1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions.
NEP | Meaning |
---|---|
0b0 |
Does not affect how the output elements other than the lowest are determined for Advanced SIMD scalar instructions. |
0b1 | The output elements other than the lowest are taken from the following registers:
|
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Alternate Handling. Controls alternate handling of denormalized floating-point numbers.
AH | Meaning |
---|---|
0b0 |
FPCR.FZ controls flushing to zero of inputs and outputs that are single-precision, double-precision, and BF16 denormalized numbers. FPCR.FIZ is RES0. For half-precision, single-precision, and double-precision numbers, the test for a denormalized number for the purpose of flushing the output to zero occurs before rounding. For more information, see 'Flushing denormalized numbers to zero'. |
0b1 |
FPCR.FZ controls flushing to zero of outputs that are single-precision, double-precision, and BF16 denormalized numbers. For all precisions, the test for a denormalized number for the purpose of flushing the output to zero occurs after rounding with an unbounded exponent. FPCR.FIZ controls flushing to zero of inputs that are single-precision, double-precision, and BF16 denormalized numbers. Some instructions unconditionally flush to zero. For more information, see 'Flushing denormalized numbers to zero'. |
The AH bit affects the generation and operation of floating-point exceptions. For more information, see 'Floating-point exceptions and exception traps'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Flush Inputs to Zero. Controls whether single-precision, double-precision, and BFloat16 input operands that are denormalized numbers are flushed to zero.
FIZ | Meaning |
---|---|
0b0 | If FPCR.AH is 0, this bit is RES0. If FPCR.AH is 1, disables flushing to zero of inputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. |
0b1 | If FPCR.AH is 0, this bit is RES0. If FPCR.AH is 1, enables flushing to zero of inputs that are single-precision, double-precision, and BF16 denormalized numbers, other than for some instructions. For more information, see 'Flushing denormalized numbers to zero'. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0100 | 0b000 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0100 | 0b000 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t];
30/03/2021 20:51; e3551d56dc294a4d55296a6c10544191ada08a8e
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