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Store Allocation Tags stores an Allocation Tag to two Tag granules of memory. The address used for the store is calculated from the basesource register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register.
This instruction generates an Unchecked access.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | imm9 | 0 | 1 | Xn | |||||||||||||||||
integer n = UInt(Xn);
integer t =bits(64) offset = UInt(Xt);
bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE);
boolean writeback = TRUE;
boolean postindex = TRUE;
boolean zero_data = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | imm9 | 1 | 1 | Xn | |||||||||||||||||
integer n = UInt(Xn);
integer t =bits(64) offset = UInt(Xt);
bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE);
boolean writeback = TRUE;
boolean postindex = FALSE;
boolean zero_data = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | imm9 | 1 | 0 | Xn | |||||||||||||||||
integer n = UInt(Xn);
integer t =bits(64) offset = UInt(Xt);
bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE);
boolean writeback = FALSE;
boolean postindex = FALSE;
boolean zero_data = FALSE;
<Xt | Is the 64-bit name of the general-purpose |
<simm> | Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field. |
bits(64) address;
bits(64) data = if t == 31 thenbits(4) tag;
SetNotTagCheckedInstruction(TRUE);
if n == 31 then SP[] else X[t];
bits(4) tag = AArch64.AllocationTagFromAddress(data);
SetNotTagCheckedInstruction(TRUE);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
if !postindex then
address = address + offset;
if zero_data then
Mem[address, TAG_GRANULE, AccType_NORMAL] = Zeros(8*TAG_GRANULE);
Mem[address+TAG_GRANULE, TAG_GRANULE, AccType_NORMAL] = Zeros(8*TAG_GRANULE);(8*TAG_GRANULE);
tag =
AArch64.MemTagAllocationTagFromAddress[address] = tag;(address);
[address] = tag;
MemTagAArch64.MemTagMemTag[address+TAG_GRANULE] = tag;
if writeback then
if postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X[n] = address;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
Copyright © 2010-20192010-2018 Arm Limited or its affiliates. All rights reserved.
This document is Non-Confidential.
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