(old) | htmldiff from- | (new) |
Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.
The destination vector elements are twice as long as the elements that are multiplied.
The SMULL instruction extracts each source vector from the lower half of each source register, while the SMULL2 instruction extracts each source vector from the upper half of each source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | |||||||||||||
U |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean unsigned = (U == '1');
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Ta> |
Is an arrangement specifier,
encoded in
size:
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Tb> |
Is an arrangement specifier,
encoded in
size:Q:
|
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
for e = 0 to elements-1
element1 = Int(Elem[operand1, e, esize], unsigned);
element2 = Int(Elem[operand2, e, esize], unsigned);
Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;[result, e, 2*esize] = (element1 * element2)<2*esize-1:0>;
V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |