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SHA256 schedule update 1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 1 | 1 | 0 | 0 | 0 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !HaveSHA256Ext() then UNDEFINED;
<Vd> | Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
<Vn> | Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled();
bits(128) operand1 = V[d];
bits(128) operand2 = V[n];
bits(128) operand3 = V[m];
bits(128) result;
bits(128) T0 = operand3<31:0>:operand2<127:32>;
bits(128) T0 = operand3<31:0> : operand2<127:32>;
bits(64) T1;
bits(32) elt;
T1 = operand3<127:64>;
for e = 0 to 1
elt = Elem[T1, e, 32];
elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
Elem[result, e, 32] = elt;
T1 = result<63:0>;
for e = 2 to 3
elt = Elem[T1, e-2, 32];
[T1, e - 2, 32];
elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
Elem[result, e, 32] = elt;
V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
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