LDAR

Load-Acquire Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

For this instruction, if the destination is WZR/ZXR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.

313029282726252423222120191817161514131211109876543210
1x001000110(1)(1)(1)(1)(1)1(1)(1)(1)(1)(1)RnRt
sizeLRso0Rt2

32-bit (size == 10)

LDAR <Wt>, [<Xn|SP>{,#0}]

64-bit (size == 11)

LDAR <Xt>, [<Xn|SP>{,#0}]

integer n = UInt(Rn); integer t = UInt(Rt); integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; boolean tag_checked = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(elsize) data; constant integer dbytes = elsize DIV 8; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, dbytes, AccType_ORDERED]; X[t] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T07:14

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