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Floating-point Move register without conversion. This instruction copies the floating-point value in the SIMD&FP source register to the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | |||||||||
opc |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer datasize;
case ftype of
case type of
when '00' datasize = 32;
when '01' datasize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
datasize = 16;
else
UNDEFINED;
FPUnaryOp fpop;
case opc of
when '00' fpop = FPUnaryOp_MOV;
when '01' fpop = FPUnaryOp_ABS;
when '10' fpop = FPUnaryOp_NEG;
when '11' fpop = FPUnaryOp_SQRT;
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Dn> | Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> | Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) result; bits(datasize) operand = V[n]; case fpop of when FPUnaryOp_MOV result = operand; when FPUnaryOp_ABS result = FPAbs(operand); when FPUnaryOp_NEG result = FPNeg(operand); when FPUnaryOp_SQRT result = FPSqrt(operand, FPCR); V[d] = result;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
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