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FCMLA (by element)

Floating-point Complex Multiply Accumulate (by element).

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register:

The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Vector
(Armv8.3)

313029282726252423222120191817161514131211109876543210
0Q101111sizeLMRm0rot1H0RnRd

(size == 01)

FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>

(size == 10)

FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>

if !HaveFCADDExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(M:Rm); if size == '00' || size == '11' then UNDEFINED; if size == '01' then index = UInt(H:L); if size == '10' then index = UInt(H); integer esize = 8 << UInt(size); if !HaveFP16Ext() && esize == 16 then UNDEFINED; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; if size == '10' && (L == '1' || Q == '0') then UNDEFINED; if size == '01' && H == '1' && Q == '0' then UNDEFINED;if size == '10' && (L == '1' || Q == '0') then UNDEFINED; if size == '01' && H == '1' && Q=='0' then UNDEFINED;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
100RESERVED
1014S
11xRESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.

<Ts> Is an element size specifier, encoded in size:
size<Ts>
00RESERVED
01H
10S
11RESERVED
<index> Is the element index, encoded in size:H:L:
size<index>
00RESERVED
01H:L
10H
11RESERVED
<rotate> Is the rotation, encoded in rot:
rot<rotate>
000
0190
10180
11270

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; for e = 0 to (elements DIV 2)-1 case rot of for e = 0 to (elements DIV 2) -1 case rot of when '00' element1 = Elem[operand2, index*2, esize]; element2 = Elem[operand1, e*2, esize]; element3 = Elem[operand2, index*2+1, esize]; element4 = Elem[operand1, e*2, esize]; when '01' element1 = FPNeg(Elem[operand2, index*2+1, esize]); element2 = Elem[operand1, e*2+1, esize]; element3 = Elem[operand2, index*2, esize]; element4 = Elem[operand1, e*2+1, esize]; when '10' element1 = FPNeg(Elem[operand2, index*2, esize]); [operand2, index*2,esize]); element2 = Elem[operand1, e*2, esize]; element3 = FPNeg(Elem[operand2, index*2+1, esize]); element4 = Elem[operand1, e*2, esize]; when '11' element1 = Elem[operand2, index*2+1, esize]; element2 = Elem[operand1, e*2+1, esize]; element3 = FPNeg(Elem[operand2, index*2, esize]); element4 = Elem[operand1, e*2+1, esize]; Elem[result, e*2, esize] = FPMulAdd(Elem[operand3, e*2, esize], element2, element1, FPCR); Elem[result, e*2+1, esize] = FPMulAdd(Elem[operand3, e*2+1, esize], element4, element3, FPCR); V[d] = result;


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T072019-03-28T06:1434

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