Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |||
opc |
MemBarrierOp op; MBReqDomain domain; MBReqTypes types; case opc of when '00' op = MemBarrierOp_DSB; when '01' op = MemBarrierOp_DMB; when '10' op = MemBarrierOp_ISB; otherwise if HaveSBExt() && CRm<3:0> == '0000' then op = MemBarrierOp_SB; else UNDEFINED; case CRm<3:2> of when '00' domain = MBReqDomain_OuterShareable; when '01' domain = MBReqDomain_Nonshareable; when '10' domain = MBReqDomain_InnerShareable; when '11' domain = MBReqDomain_FullSystem; case CRm<1:0> of when '01' types = MBReqTypes_Reads; when '10' types = MBReqTypes_Writes; when '11' types = MBReqTypes_All; otherwise if CRm<3:2> == '01' then op = MemBarrierOp_PSSBB; elsif CRm<3:2> == '00' && opc == '00' then op = MemBarrierOp_SSBB; elsif HaveSBExt() && CRm<3:2> == '00' && opc == '11' then op = MemBarrierOp_SB; else types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
<imm> |
Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field. |
case op of when MemBarrierOp_DSB DataSynchronizationBarrier(domain, types); when MemBarrierOp_DMB DataMemoryBarrier(domain, types); when MemBarrierOp_ISB InstructionSynchronizationBarrier(); when MemBarrierOp_SSBB SpeculativeStoreBypassBarrierToVA(); when MemBarrierOp_PSSBB SpeculativeStoreBypassBarrierToPA(); when MemBarrierOp_SB SpeculationBarrier();
Internal version only: isa v30.3, AdvSIMD v27.04, pseudocode v85-xml-00bet9_rc1_1, sve v8.5-00bet9_rc1 ; Build timestamp: 2018-12-12T11:50
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