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ORN (vector)

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001110111Rm000111RnRd
size

Three registers of the same type

ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if Q == '1' then 128 else 64;integer esize = 8; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean invert = (size<0> == '1');LogicalOp op = if size<1> == '1' then LogicalOp_ORR else LogicalOp_AND;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in Q:
Q<T>
08B
116B
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; operand2 = NOT(operand2); if invert then operand2 = NOT(operand2); result = operand1 OR operand2;case op of when LogicalOp_AND result = operand1 AND operand2; when LogicalOp_ORR result = operand1 OR operand2; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T072019-03-28T06:1434

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