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Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.
The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:
This difference in memory ordering is not described in the pseudocode.
For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | (1) | (1) | (1) | (1) | (1) | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||
size | Rs |
integer n = UInt(Rn);
integer t = UInt(Rt);
integer elsize = 8 <<integer s = UInt(size);
integer regsize = if elsize == 64 then 64 else 32;
boolean tag_checked = n != 31;(Rs); // ignored by all loads and store-releaseAccType acctype = AccType_ORDERED;
integer elsize = 8 << UInt(size);
integer regsize = if elsize == 64 then 64 else 32;
integer datasize = elsize;
boolean tag_checked = n != 31;
<Wt> | Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;
if HaveMTEExt() then
SetNotTagCheckedInstruction(!tag_checked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
data = Mem[address, dbytes,[address, dbytes, acctype]; AccType_ORDERED];
X[t] = ZeroExtend(data, regsize);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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