Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is used by the alias TST (shifted register).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 1 | 1 | 0 | 1 | 0 | 1 | 0 | shift | 0 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
opc | N |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if sf == '1' then 64 else 32; if sf == '0' && imm6<5> == '1' then UNDEFINED; ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> |
Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Wm> |
Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> |
Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Xm> |
Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<shift> |
Is the optional shift to be applied to the final source, defaulting to LSL and
encoded in
shift:
|
Alias | Is preferred when |
---|---|
TST (shifted register) | Rd == '11111' |
bits(datasize) operand1 = X[n]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); result = operand1 AND operand2; PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00'; X[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T07:14
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.