LDGM

Load Tag Multiple reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.

Integer
(Armv8.5)

313029282726252423222120191817161514131211109876543210
1101100111100000000000XnXt

Integer

LDGM <Xt>, [<Xn|SP>]

integer t = UInt(Xt); integer n = UInt(Xn);

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.

Operation

if PSTATE.EL == EL0 then UndefinedFault(); bits(64) data = Zeros(64); bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; integer size = 4*(2^(UInt(GMID_EL1.BS))); address = Align(address,size); integer count = size >> LOG2_TAG_GRANULE; integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>); for i = 0 to count-1 bits(4) tag = AArch64.MemTag[address]; data<(index*4)+3:index*4> = tag; address = address + TAG_GRANULE; index = index + 1; X[t] = data;


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T06:34

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