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Load Allocation Tag loads an Allocation Tag from a memory address, generates aan address with the Logical Address Tag generated from the loaded Allocation Tag, and mergeswrites itthe intoresult to the destination register. The address used for the load is calculated from the basesource register and an immediate signed offset scaled by the Tag granule.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | imm9 | 0 | 0 | Xn | Xt |
integer t = UInt(Xt); integer n = UInt(Xn); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE);
<Xt> | Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field. |
<simm> | Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field. |
bits(64) address;
bits(4) tag;
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
address = address + offset;
address = Align(address, TAG_GRANULE);
tag = AArch64.MemTagMemTag[address];[address];
address =
XAddressWithAllocationTag[t] = AArch64.AddressWithAllocationTag((address, tag);X[t], tag);[t] = address;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
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This document is Non-Confidential.
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