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STLLRH

Store LORelease Register Halfword stores a halfword from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about memory accesses, see Load/Store addressing modes.

No offset
(Armv8.1)

313029282726252423222120191817161514131211109876543210
01001000100(1)(1)(1)(1)(1)0(1)(1)(1)(1)(1)RnRt
sizeLRso0Rt2

No offset

STLLRH <Wt>, [<Xn|SP>{,#0}]

integer n = UInt(Rn); integer t = UInt(Rt); boolean tag_checked = n != 31;integer t2 =UInt(Rt2); // ignored by load/store single register integer s = UInt(Rs); // ignored by all loads and store-release AccType acctype = if o0 == '0' then AccType_LIMITEDORDERED else AccType_ORDERED; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize; boolean tag_checked = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(16) data; bits(datasize) data; constant integer dbytes = datasize DIV 8; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data =case memop of when MemOp_STORE data = X[t]; Mem[address, 2,[address, dbytes, acctype] = data; when data = Mem[address, dbytes, acctype]; X[t] = ZeroExtendAccType_LIMITEDORDEREDMemOp_LOAD] = data;(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T072019-03-28T06:1434

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