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SHA256 hash update (part 2).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 1 | 0 | 1 | 0 | 0 | Rn | Rd | ||||||||||||
P |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
if !HaveSHA256Ext() then UNDEFINED;() then UNDEFINED;
boolean part1 = (P == '0');
<Qd> | Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field. |
<Qn> | Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled();
bits(128) result;
result =if part1 then
result = SHA256hash(V[n],[d], V[d],[n], V[m], FALSE);[m], TRUE);
else
result =
SHA256hash(V[n], V[d], V[m], FALSE);
V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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