SHA1H

SHA1 fixed rotate.

313029282726252423222120191817161514131211109876543210
0101111000101000000010RnRd

Advanced SIMD

SHA1H <Sd>, <Sn>

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;

Assembler Symbols

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(32) operand = V[n]; // read element [0] only, [1-3] zeroed V[d] = ROL(operand, 30);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T06:34

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.