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Prefetch Memory (literal) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.
The effect of an PRFM instruction is implementation defined. For more information, see Prefetch memory.
For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | imm19 | Rt | ||||||||||||||||||||||
opc |
integer t = UInt(Rt);
bits(64) offset;
offset =(Rt); MemOp memop = MemOp_LOAD;
boolean signed = FALSE;
integer size;
bits(64) offset;
case opc of
when '00'
size = 4;
when '01'
size = 8;
when '10'
size = 4;
signed = TRUE;
when '11'
memop = MemOp_PREFETCH;
offset = SignExtend(imm19:'00', 64);(imm19:'00', 64);
boolean tag_checked = FALSE;
<prfop> | Is the prefetch operation, defined as <type><target><policy>. <type> is one of:
<target> is one of:
<policy> is one of:
For more information on these prefetch operations, see Prefetch memory. For other encodings of the "Rt" field, use <imm5>. |
<imm5> | Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field. This syntax is only for encodings that are not accessible using <prfop>. |
<label> | Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4. |
bits(64) address = PC[] + offset;
bits(size*8) data;
if HaveMTEExt() then
SetNotTagCheckedInstruction(TRUE); SetNotTagCheckedInstruction(!tag_checked);
case memop of
when
MemOp_LOAD
data = Mem[address, size, AccType_NORMAL];
if signed then
X[t] = SignExtend(data, 64);
else
X[t] = data;
when MemOp_PREFETCHPrefetch(address, t<4:0>);
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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