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Programmable table lookup in single vector table.
Reads each element of the second source (index) vector and uses its value to select an indexed element from the first source (table) vector, and places the indexed table element in the destination vector element corresponding to the index vector element. If an index value is greater than or equal to the number of vector elements then it places zero in the corresponding destination vector element.
Since the index values can select any element in a vector this operation is not naturally vector length agnostic.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 0 | 1 | 1 | 0 | 0 | Zn | Zd |
if !HaveSVE() then UNDEFINED;
integer esize = 8 << UInt(size);
integer n = UInt(Zn);
integer m = UInt(Zm);
integer d = UInt(Zd);(Zd);
boolean double_table = FALSE;
<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 =bits(VL) indexes = Z[n];
bits(VL) operand2 =[m];
bits( VL) result;
integer table_size = if double_table then VL*2 else VL;
integer table_elems = table_size DIV esize;
bits(table_size) table;
if double_table then
bits(VL) top = Z[m];
bits([(n + 1) MOD 32];
bits(VL) bottom =[n];
table = (top:bottom)<table_size-1:0>;
else
table = ZVLZ) result;
[n];
for e = 0 to elements-1
integer idx = UInt(Elem[operand2, e, esize]);[indexes, e, esize]);
Elem[result, e, esize] = if idx < elements then[result, e, esize] = if idx < table_elems then Elem[operand1, idx, esize] else[table, idx, esize] else Zeros();
Z[d] = result;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
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