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Add (shifted register) adds a register value and an optionally-shifted register value, and writes the result to the destination register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 0 | 0 | 1 | 0 | 1 | 1 | shift | 0 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
op | S |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer datasize = if sf == '1' then 64 else 32;
boolean sub_op = (op == '1');
boolean setflags = (S == '1');
if shift == '11' then UNDEFINED;
if sf == '0' && imm6<5> == '1' then UNDEFINED;
ShiftType shift_type = DecodeShift(shift);
integer shift_amount = UInt(imm6);
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> | Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Wm> | Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> | Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Xm> | Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<shift> |
Is the optional shift type to be applied to the second source operand, defaulting to LSL and
encoded in
shift:
|
bits(datasize) result;
bits(datasize) operand1 = X[n];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount);
bits(4) nzcv;
bit carry_in;
(result, -) =if sub_op then
operand2 = NOT(operand2);
carry_in = '1';
else
carry_in = '0';
(result, nzcv) = AddWithCarry(operand1, operand2, '0');(operand1, operand2, carry_in);
if setflags then
PSTATE.<N,Z,C,V> = nzcv;
X[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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