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SHA1 hash update (parity).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 0 | 1 | 0 | 0 | Rn | Rd |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !HaveSHA1Ext() then UNDEFINED;
<Qd> | Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled();
bits(128) X = V[d];
bits(32) Y = V[n]; // Note: 32 not 128 bits wide
bits(128) W = V[m];
bits(32) t;
for e = 0 to 3
t = SHAparity(X<63:32>, X<95:64>, X<127:96>);
Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
X<63:32> = ROL(X<63:32>, 30);
<Y, X> = ROL(Y:X, 32);(Y : X, 32);
V[d] = X;
If PSTATE.DIT is 1:
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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