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PRFM (register)

Prefetch Memory (register) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.

The effect of an PRFM instruction is implementation defined. For more information, see Prefetch memory.

For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
11111000101RmoptionS10RnRt
sizeopc

Integer

PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]

if option<1> == '0' then UNDEFINED; // sub-word indexboolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(size); if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option); integer shift = if S == '1' then 3 else 0;integer shift = if S == '1' then scale else 0;

Assembler Symbols

<prfop>

Is the prefetch operation, defined as <type><target><policy>.

<type> is one of:

PLD
Prefetch for load, encoded in the "Rt<4:3>" field as 0b00.
PLI
Preload instructions, encoded in the "Rt<4:3>" field as 0b01.
PST
Prefetch for store, encoded in the "Rt<4:3>" field as 0b10.

<target> is one of:

L1
Level 1 cache, encoded in the "Rt<2:1>" field as 0b00.
L2
Level 2 cache, encoded in the "Rt<2:1>" field as 0b01.
L3
Level 3 cache, encoded in the "Rt<2:1>" field as 0b10.

<policy> is one of:

KEEP
Retained or temporal prefetch, allocated in the cache normally. Encoded in the "Rt<0>" field as 0.
STRM
Streaming or non-temporal prefetch, for data that is used only once. Encoded in the "Rt<0>" field as 1.

For more information on these prefetch operations, see Prefetch memory.

For other encodings of the "Rt" field, use <imm5>.

<imm5>

Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.

This syntax is only for encodings that are not accessible using <prfop>.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm>

When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>

When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

<extend> Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted. encoded in option:
option<extend>
010UXTW
011LSL
110SXTW
111SXTX
<amount> Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is encoded in S:
S<amount>
0#0
1#3

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm);AccType acctype = AccType_NORMAL; MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = if size == '11' then 64 else 32; signed = FALSE; else if size == '11' then memop = MemOp_PREFETCH; if opc<0> == '1' then UNDEFINED; else // sign-extending load memop = MemOp_LOAD; if size == '10' && opc<0> == '1' then UNDEFINED; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; integer datasize = 8 << scale; boolean tag_checked = memop != MemOp_PREFETCH;

Operation

bits(64) offset = ExtendReg(m, extend_type, shift); if HaveMTEExt() then SetNotTagCheckedInstruction(TRUE); SetNotTagCheckedInstruction(!tag_checked); bits(64) address; bits(datasize) data; if n == 31 then address =boolean wb_unknown = FALSE; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if memop == MemOp_STORE && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if n == 31 then if memop != MemOp_PREFETCH then CheckSPAlignment(); address = SP[]; else address = X[n]; address = address + offset;if ! postindex then address = address + offset; case memop of when MemOp_STORE if rt_unknown then data = bits(datasize) UNKNOWN; else data = X[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD data = Mem[address, datasize DIV 8, acctype]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCHPrefetch(address, t<4:0>); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = address + offset; if n == 31 then SP[] = address; else X(address, t<4:0>);[n] = address;


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T072019-03-28T06:1434

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