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FCADD

Floating-point Complex Add.

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers:

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Three registers of the same type
(Armv8.3)

313029282726252423222120191817161514131211109876543210
0Q101110size0Rm111rot01RnRd

Three registers of the same type

FCADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate>

if !HaveFCADDExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '00' then UNDEFINED; if Q == '0' && size == '11' then UNDEFINED; integer esize = 8 << UInt(size); if !HaveFP16Ext() && esize == 16 then UNDEFINED; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
110RESERVED
1112D
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

<rotate> Is the rotation, encoded in rot:
rot<rotate>
090
1270

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element3; for e = 0 to (elements DIV 2)-1 case rot of for e = 0 to (elements DIV 2) -1 case rot of when '0' element1 = FPNeg(Elem[operand2, e*2+1, esize]); element3 = Elem[operand2, e*2, esize]; when '1' element1 = Elem[operand2, e*2+1, esize]; element3 = FPNeg(Elem[operand2, e*2, esize]); Elem[result, e*2, esize] = FPAdd(Elem[operand1, e*2, esize], element1, FPCR); Elem[result, e*2+1, esize] = FPAdd(Elem[operand1, e*2+1, esize], element3, FPCR); V[d] = result;


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T072019-03-28T06:1434

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