SWP, SWPA, SWPAL, SWPL

Swap word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

Integer
(Armv8.1)

313029282726252423222120191817161514131211109876543210
1x111000AR1Rs100000RnRt
size

32-bit SWP (size == 10 && A == 0 && R == 0)

SWP <Ws>, <Wt>, [<Xn|SP>]

32-bit SWPA (size == 10 && A == 1 && R == 0)

SWPA <Ws>, <Wt>, [<Xn|SP>]

32-bit SWPAL (size == 10 && A == 1 && R == 1)

SWPAL <Ws>, <Wt>, [<Xn|SP>]

32-bit SWPL (size == 10 && A == 0 && R == 1)

SWPL <Ws>, <Wt>, [<Xn|SP>]

64-bit SWP (size == 11 && A == 0 && R == 0)

SWP <Xs>, <Xt>, [<Xn|SP>]

64-bit SWPA (size == 11 && A == 1 && R == 0)

SWPA <Xs>, <Xt>, [<Xn|SP>]

64-bit SWPAL (size == 11 && A == 1 && R == 1)

SWPAL <Xs>, <Xt>, [<Xn|SP>]

64-bit SWPL (size == 11 && A == 0 && R == 1)

SWPL <Xs>, <Xt>, [<Xn|SP>]

if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; boolean tag_checked = n != 31;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xs>

Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(datasize) data; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = Mem[address, datasize DIV 8, ldacctype]; Mem[address, datasize DIV 8, stacctype] = X[s]; X[t] = ZeroExtend(data, regsize);


Internal version only: isa v30.3, AdvSIMD v27.04, pseudocode v85-xml-00bet9_rc1_1, sve v8.5-00bet9_rc1 ; Build timestamp: 2018-12-12T11:50

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