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Contiguous store doublewords from vector (scalar index).
Contiguous store of doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 8 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | Rm | 0 | 1 | 0 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED;
if Rm == '11111' then UNDEFINED;
integer t =if size == '0x' then SEE(sve_mem_spill);
if size == '10' then UNDEFINED;
if Rm == '11111' then UNDEFINED;
integer t = UInt(Zt);
integer n = UInt(Zt);
integer n =(Rn);
integer m = UInt(Rn);
integer m =(Rm);
integer g = UInt(Rm);
integer g =(Pg);
integer esize = 8 << UInt(Pg);
integer esize = 64;
(size);
integer msize = 64;
<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Xm> | Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; bits(64) offset = X[m]; bits(VL) src = Z[t]; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetNotTagCheckedInstruction(FALSE); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; for e = 0 to elements-1 addr = base + UInt(offset) * mbytes; if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>; offset = offset + 1;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
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