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Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 0 | 1 | 1 | 0 | 0 | 0 | scale | Rn | Rd | ||||||||||||||
rmode | opcode |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer intsize = if sf == '1' then 64 else 32;
integer fltsize;
case ftype of
when '00' fltsize = 32;
when '01' fltsize = 64;
when '10' UNDEFINED;
when '11'
ifinteger fltsize; FPConvOp op;
FPRounding rounding;
boolean unsigned;
case ftype of
when '00' fltsize = 32;
when '01' fltsize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
fltsize = 16;
else
UNDEFINED;
if sf == '0' && scale<5> == '0' then UNDEFINED;
integer fracbits = 64 - UInt(scale);
case opcode<2:1>:rmode of
when '00 11' // FCVTZ
rounding = FPRounding_ZERO;
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_FtoI;
when '01 00' // [US]CVTF
rounding = FPRoundingMode(FPCR);
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_ItoF(scale);;
otherwise
UNDEFINED;
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Hn> | Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Dn> | Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64();
bits(fltsize) fltval;
bits(intsize) intval;
fltval =case op of
when FPConvOp_CVT_FtoI
fltval = V[n];
intval = FPToFixed(fltval, fracbits, FALSE, FPCR,(fltval, fracbits, unsigned, FPCR, rounding); FPRounding_ZEROX);[d] = intval;
when
FPConvOp_CVT_ItoF
intval = X[n];
fltval = FixedToFP(intval, fracbits, unsigned, FPCR, rounding);
V[d] = intval;[d] = fltval;
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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