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Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it, and writes it to a register. For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | x | 1 | Rm | option | S | 1 | 0 | Rn | Rt | ||||||||||||||
size | opc |
if option<1> == '0' then UNDEFINED; // sub-word indexboolean wback = FALSE;
boolean postindex = FALSE;
integer scale =
UInt(size);
if option<1> == '0' then UNDEFINED; // sub-word index
ExtendType extend_type = DecodeRegExtend(option);
integer shift = if S == '1' then 1 else 0;integer shift = if S == '1' then scale else 0;
<Wt> | Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Wm> | When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field. |
<Xm> | When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field. |
<extend> |
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
encoded in
option:
|
<amount> |
Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S:
|
integer n = UInt(Rn);
integer t = UInt(Rt);
integer m = UInt(Rm);
AccType acctype = AccType_NORMAL;
MemOp memop;
boolean signed;
integer regsize;
if opc<1> == '0' then
// store or zero-extending load
memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
regsize = if size == '11' then 64 else 32;
signed = FALSE;
else
if size == '11' then
memop = MemOp_PREFETCH;
regsize = 32;
signed = FALSE;
else
// sign-extending load
memop = if opc<0> == '1' then UNDEFINED;
else
// sign-extending load
memop = MemOp_LOAD;
regsize = if opc<0> == '1' then 32 else 64;
signed = TRUE;
if size == '10' && opc<0> == '1' then UNDEFINED;
regsize = if opc<0> == '1' then 32 else 64;
signed = TRUE;
integer datasize = 8 << scale;
boolean tag_checked = memop != MemOp_PREFETCH;
bits(64) offset = ExtendReg(m, extend_type, shift);
if HaveMTEExt() then
SetNotTagCheckedInstruction(!tag_checked);
bits(64) address;
bits(16) data;
bits(datasize) data;
if n == 31 then
if memop !=boolean wb_unknown = FALSE;
boolean rt_unknown = FALSE;
if memop == MemOp_LOAD && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed
when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if memop == MemOp_STORE && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST);
assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_NONE rt_unknown = FALSE; // value stored is original value
when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if n == 31 then
if memop != MemOp_PREFETCH then CheckSPAlignment();
address = SP[];
else
address = X[n];
address = address + offset;
if ! postindex then
address = address + offset;
case memop of
when MemOp_STORE
data =if rt_unknown then
data = bits(datasize) UNKNOWN;
else
data = X[t];
Mem[address, 2,[address, datasize DIV 8, acctype] = data;
when AccType_NORMAL] = data;
when MemOp_LOAD
data = Mem[address, 2,[address, datasize DIV 8, acctype];
if signed then AccType_NORMAL];
if signed then
X[t] = SignExtend(data, regsize);
else
X[t] = ZeroExtend(data, regsize);
when MemOp_PREFETCHPrefetch(address, t<4:0>);
if wback then
if wb_unknown then
address = bits(64) UNKNOWN;
elsif postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X(address, t<4:0>);[n] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5
; Build timestamp: 2019-03-28T072019-03-28T06:1434
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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