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LDEORH, LDEORAH, LDEORALH, LDEORLH

Atomic exclusive OR on halfword in memory atomically loads a 16-bit halfword from memory, performs an exclusive OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

This instruction is used by the alias STEORH, STEORLH.

Integer
(Armv8.1)

313029282726252423222120191817161514131211109876543210
01111000AR1Rs001000RnRt
sizeopc

LDEORAH (A == 1 && R == 0)

LDEORAH <Ws>, <Wt>, [<Xn|SP>]

LDEORALH (A == 1 && R == 1)

LDEORALH <Ws>, <Wt>, [<Xn|SP>]

LDEORH (A == 0 && R == 0)

LDEORH <Ws>, <Wt>, [<Xn|SP>]

LDEORLH (A == 0 && R == 1)

LDEORLH <Ws>, <Wt>, [<Xn|SP>]

if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; MemAtomicOp op; case opc of when '000' op = MemAtomicOp_ADD; when '001' op = MemAtomicOp_BIC; when '010' op = MemAtomicOp_EOR; when '011' op = MemAtomicOp_ORR; when '100' op = MemAtomicOp_SMAX; when '101' op = MemAtomicOp_SMIN; when '110' op = MemAtomicOp_UMAX; when '111' op = MemAtomicOp_UMIN; boolean tag_checked = n != 31;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

AliasIs preferred when
STEORH, STEORLHA == '0' && Rt == '11111'

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = [address, datasize DIV 8, ldacctype]; case op of when MemAtomicOp_ADD result = data + value; when MemAtomicOp_BIC result = data AND NOT(value); when MemAtomicOp_EOR result = data EOR value; when MemAtomicOp_ORR result = data OR value; when MemAtomicOp_SMAX result = if SInt(data) > SInt(value) then data else value; when MemAtomicOp_SMIN result = if SInt(data) > SInt(value) then value else data; when MemAtomicOp_UMAX result = if UInt(data) > UInt(value) then data else value; when MemAtomicOp_UMIN result = if UInt(data) > UInt(value) then value else data; MemMemAtomicMem(address, op, value, ldacctype, stacctype); [address, datasize DIV 8, stacctype] = result; if t != 31 then X[t] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1 ; Build timestamp: 2019-03-28T062018-12-12T11:3450

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