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Insert Random Tag inserts a random Logical Address Tag into the address in the first source register, and writes the result to the destination register. Any tags specified in the optional second source register or in GCR_EL1.Exclude are excluded from the selection of the random Logical Address Tag.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | Xm | 0 | 0 | 0 | 1 | 0 | 0 | Xn | Xd |
integer d = UInt(Xd); integer n = UInt(Xn); integer m = UInt(Xm);
<Xd|SP> | Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Xd" field. |
<Xn|SP> | Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Xn" field. |
<Xm> | Is the 64-bit name of the second general-purpose source register, encoded in the "Xm" field. Defaults to XZR if absent. |
bits(64) operand = if n == 31 then SP[] else X[n];
bits(64) exclude_reg =bits(64) xm = X[m];
bits(16) exclude = exclude_reg<15:0> OR GCR_EL1.Exclude;
bits(16) exclude = xm<15:0> OR GCR_EL1.Exclude;
if AArch64.AllocationTagAccessIsEnabledAllocationTagAccessIsEnabled() then
if GCR_EL1.RRND == '1' then
RGSR_EL1 = bits(32) UNKNOWN;
rtag = _ChooseRandomNonExcludedTag(exclude);
else
bits(4) start = RGSR_EL1.TAG;
bits(4) offset = AArch64.RandomTagRandomTag();
rtag = AArch64.ChooseNonExcludedTagChooseNonExcludedTag(start, offset, exclude);
RGSR_EL1.TAG = rtag;
else
rtag = '0000';
bits(64) result = AArch64.AddressWithAllocationTagAddressWithAllocationTag(operand, rtag);
if d == 31 then
SP[] = result;
else
X[d] = result;
Internal version only: isa v30.41v30.3, AdvSIMD v27.08v27.04, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1, sve v8.5-00bet10_rc5v8.5-00bet9_rc1
; Build timestamp: 2019-03-28T062018-12-12T11:3450
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This document is Non-Confidential.
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