FJCVTZS

Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be accommodated as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Double-precision to 32-bit
(Armv8.3)

313029282726252423222120191817161514131211109876543210
0001111001111110000000RnRd
sfftypermodeopcode

Double-precision to 32-bit

FJCVTZS <Wd>, <Dn>

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveFJCVTZSExt() then UNDEFINED;

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(64) fltval; bits(32) intval; fltval = V[n]; intval = FPToFixedJS(fltval, FPCR, TRUE); X[d] = ZeroExtend(intval<31:0>, 64);


Internal version only: isa v30.41, AdvSIMD v27.08, pseudocode r8p5_00bet2_rc5, sve v8.5-00bet10_rc5 ; Build timestamp: 2019-03-28T07:14

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.