SSBB

Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions.

The semantics of the Speculative Store Bypass Barrier are:

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)01000000

A1

SSBB{<q>}

// No additional decoding required

T1

15141312111098765432101514131211109876543210
111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)01000000

T1

SSBB{<q>}

if InITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); SpeculativeStoreBypassBarrierToVA();


Internal version only: isa v00_98, pseudocode v8.5-2019-06_rc2-5-g22901f2 ; Build timestamp: 2019-06-27T01:26

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