1. Introduction

This is the 2019-06 release of the AArch32 ISA XML for ARMv8.5.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

If you have comments on the content of this package, please send them by e-mail to support-aarchv8@arm.com. Give:

• The title, "AArch32 ISA XML for ARMv8.5".
• The version, "2019-06".
• A concise explanation of your comments.

2. Contents

3. Release Notes

Change history

No updates are made to the AArch32 ISA.

The following changes are made to the instruction definitions:

• The CONSTRAINED UNPREDICTABLE behaviors described for the A1 and A2 encodings of STRT, STRBT and STRHT have been corrected.
• VST4 instruction decode in the post-index form corrected to give proper decode of size field.

The following changes are made to the Shared Pseudocode:

• The FPToFixedJS() pseudocode function is corrected to describe the effect when FPSCR.FZ == '1' with a positive denormal number as the input. This affects the behavior of the VJCVT instruction.
• The Watchpoint and Breakpoint Debug pseudocode is updated to reflect the behavior expected for Secure EL2.
• Added CheckValidStateMatch() as a refactor to StateMatch() as part of Secure EL2 corrections to Debug behavior.
• The function AArch32.TranslationTableWalkLD() is corrected to remove a reference to Secure EL2 controls.
• The function CollectRecord() is corrected for behavior expected for ARMv8.3-SPE.
• Added IsCorePowered() to describe when the Core power domain is powered on.
• The ARMv8.3-DoDP feature has now been implemented.
• Added HaveELUsingSecurityState() to identify if a given EL+Security state is supported.
• The AArch32.ExclusiveMonitorsPass() and AArch64.ExclusiveMonitorsPass() pseudocode functions incorrectly showed that the exclusive monitor reset only applies if the address passed is not held in the monitor. This is corrected.

Known issues

• The table for the "Advanced SIMD two registers and shift amount" class within the A32 and T32 encoding index page includes a column "imm3H:L" with the value "!= 0000" for all rows. This condition applies to all instructions in this table, and so is removed.
• The encoding diagram for the "Advanced SIMD and floating-point 32-bit move" class within the A32 and T32 encoding index page shows bits[3:0] as "1111". This is incorrect, as the next level of decode shows these bits as "(0)(0)(0)(0)".
• There is an apparent clash in the following instruction encoding tables for A32 and T32:
  • System register access, Advanced SIMD, and floating-point
  • System register access, Advanced SIMD, floating-point, and Supervisor call

  There are no overlapping encodings in this part of the instruction set. The "Advanced SIMD two registers and a scalar extension" are split as follows:

  • All encodings with op3 = '0' will be moved to their own table, "Multiply with Accumulate" under the "Floating-point data-processing" group.
  • All encodings with op3 = '1' will be moved to their own table, "Advanced SIMD dot product".
• In the VQDMLAL and VQDMLSL T1 instruction encodings, the position of the 'op' fields is incorrectly pointing at bit 8, and this is corrected to be bit 9.
• The DCPSInstruction() needs to be updated to set PSTATE.TCO to '1'.