VSELEQ, VSELGE, VSELGT, VSELVS
Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the APSR.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm |
| | | | | | size | | | | | |
VSELEQ,doubleprec (cc == 00 && size == 11)
VSELEQ.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
VSELEQ,halfprec (cc == 00 && size == 01)
(Armv8.2)
VSELEQ.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELEQ,singleprec (cc == 00 && size == 10)
VSELEQ.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELGE,doubleprec (cc == 10 && size == 11)
VSELGE.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
VSELGE,halfprec (cc == 10 && size == 01)
(Armv8.2)
VSELGE.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELGE,singleprec (cc == 10 && size == 10)
VSELGE.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELGT,doubleprec (cc == 11 && size == 11)
VSELGT.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
VSELGT,halfprec (cc == 11 && size == 01)
(Armv8.2)
VSELGT.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELGT,singleprec (cc == 11 && size == 10)
VSELGT.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELVS,doubleprec (cc == 01 && size == 11)
VSELVS.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
VSELVS,halfprec (cc == 01 && size == 01)
(Armv8.2)
VSELVS.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
VSELVS,singleprec (cc == 01 && size == 10)
VSELVS.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
cond = cc:(cc<1> EOR cc<0>):'0';
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm |
| | | | | | size | | | | | |
VSELEQ,doubleprec (cc == 00 && size == 11)
VSELEQ.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
VSELEQ,halfprec (cc == 00 && size == 01)
(Armv8.2)
VSELEQ.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELEQ,singleprec (cc == 00 && size == 10)
VSELEQ.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELGE,doubleprec (cc == 10 && size == 11)
VSELGE.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
VSELGE,halfprec (cc == 10 && size == 01)
(Armv8.2)
VSELGE.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELGE,singleprec (cc == 10 && size == 10)
VSELGE.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELGT,doubleprec (cc == 11 && size == 11)
VSELGT.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
VSELGT,halfprec (cc == 11 && size == 01)
(Armv8.2)
VSELGT.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELGT,singleprec (cc == 11 && size == 10)
VSELGT.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELVS,doubleprec (cc == 01 && size == 11)
VSELVS.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
VSELVS,halfprec (cc == 01 && size == 01)
(Armv8.2)
VSELVS.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
VSELVS,singleprec (cc == 01 && size == 10)
VSELVS.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
if InITBlock() then UNPREDICTABLE;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
cond = cc:(cc<1> EOR cc<0>):'0';
CONSTRAINED UNPREDICTABLE behavior
If InITBlock(), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
Assembler Symbols
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
|
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
|
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
|
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
|
<Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
|
<Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.
|
Operational information
If CPSR.DIT is 1 and this instruction passes its condition execution check:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
Internal version only: isa v00_98, pseudocode v8.5-2019-06_rc2-5-g22901f2
; Build timestamp: 2019-06-27T01:26
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