Copy a vector element to a general-purpose register with sign or zero extension copies a byte, halfword, or word from an Advanced SIMD scalar to a general-purpose register. Bytes and halfwords can be either zero-extended or sign-extended.
On a Floating-point-only system, this instruction transfers one word from the upper or lower half of a double-precision floating-point register to a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.
For more information about scalars see Advanced SIMD scalars.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | U | opc1 | 1 | Vn | Rt | 1 | 0 | 1 | 1 | N | opc2 | 1 | (0) | (0) | (0) | (0) | |||||||||||
cond |
case U:opc1:opc2 of when 'x1xxx' advsimd = TRUE; esize = 8; index = UInt(opc1<0>:opc2); when 'x0xx1' advsimd = TRUE; esize = 16; index = UInt(opc1<0>:opc2<1>); when '00x00' advsimd = FALSE; esize = 32; index = UInt(opc1<0>); when '10x00' UNDEFINED; when 'x0x10' UNDEFINED; t = UInt(Rt); n = UInt(N:Vn); unsigned = (U == '1'); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | U | opc1 | 1 | Vn | Rt | 1 | 0 | 1 | 1 | N | opc2 | 1 | (0) | (0) | (0) | (0) |
case U:opc1:opc2 of when 'x1xxx' advsimd = TRUE; esize = 8; index = UInt(opc1<0>:opc2); when 'x0xx1' advsimd = TRUE; esize = 16; index = UInt(opc1<0>:opc2<1>); when '00x00' advsimd = FALSE; esize = 32; index = UInt(opc1<0>); when '10x00' UNDEFINED; when 'x0x10' UNDEFINED; t = UInt(Rt); n = UInt(N:Vn); unsigned = (U == '1'); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Rt> |
The destination general-purpose register. |
<Dn[x]> |
The scalar. For details of how [x] is encoded see the description of <dt>. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if unsigned then R[t] = ZeroExtend(Elem[D[n],index,esize], 32); else R[t] = SignExtend(Elem[D[n],index,esize], 32);
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v00_98, pseudocode v8.5-2019-06_rc2-5-g22901f2 ; Build timestamp: 2019-06-27T01:26
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