Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register. This instruction transfers the value held in the bottom 16 bits of a 32-bit SIMD&FP register to the bottom 16 bits of a general-purpose register, or the value held in the bottom 16 bits of a general-purpose register to the bottom 16 bits of a 32-bit SIMD&FP register.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | op | Vn | Rt | 1 | 0 | 0 | 1 | N | (0) | (0) | 1 | (0) | (0) | (0) | (0) | |||||||||
cond |
if !HaveFP16Ext() then UNDEFINED; if cond != '1110' then UNPREDICTABLE; to_arm_register = (op == '1'); t = UInt(Rt); n = UInt(Vn:N); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
If cond != '1110', then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | op | Vn | Rt | 1 | 0 | 0 | 1 | N | (0) | (0) | 1 | (0) | (0) | (0) | (0) |
if !HaveFP16Ext() then UNDEFINED; if InITBlock() then UNPREDICTABLE; to_arm_register = (op == '1'); t = UInt(Rt); n = UInt(Vn:N); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
If InITBlock(), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<Rt> |
Is the general-purpose register that <Sn> will be transferred to or from, encoded in the "Rt" field. |
<Sn> |
Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Vn:N" field. |
<c> |
<q> |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_arm_register then R[t] = Zeros(16) : S[n]<15:0>; else S[n] = Zeros(16) : R[t]<15:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v00_98, pseudocode v8.5-2019-06_rc2-5-g22901f2 ; Build timestamp: 2019-06-27T01:26
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