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Vector Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 0 | D | 0 | 1 | Vn | Vd | 1 | 0 | size | N | 0 | M | 0 | Vm | |||||||||||||
cond | op |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && cond != '1110' then UNPREDICTABLE;
vtype = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
If size == '01' && cond != '1110', then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | D | 0 | 1 | Vn | Vd | 1 | 0 | size | N | 0 | M | 0 | Vm | ||||||||||
op |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
if size == '01' && InITBlock() then UNPREDICTABLE;
vtype = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
If size == '01' && InITBlock(), then one of the following behaviors must occur:
<c> |
<q> |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sn> | Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
<Sm> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. |
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> | Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL};
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
when 16
product16 = FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR);
case vtype of
case type of
when VFPNegMul_VNMLA S[d] = Zeros(16) : FPAdd(FPNeg(S[d]<15:0>), FPNeg(product16), FPSCR);
when VFPNegMul_VNMLS S[d] = Zeros(16) : FPAdd(FPNeg(S[d]<15:0>), product16, FPSCR);
when VFPNegMul_VNMUL S[d] = Zeros(16) : FPNeg(product16);
when 32
product32 = FPMul(S[n], S[m], FPSCR);
case vtype of
case type of
when VFPNegMul_VNMLA S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR);
when VFPNegMul_VNMLS S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR);
when VFPNegMul_VNMUL S[d] = FPNeg(product32);
when 64
product64 = FPMul(D[n], D[m], FPSCR);
case vtype of
case type of
when VFPNegMul_VNMLA D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR);
when VFPNegMul_VNMLS D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR);
when VFPNegMul_VNMUL D[d] = FPNeg(product64);
Internal version only: isa v00_96v00_88, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1
; Build timestamp: 2019-03-28T072018-12-12T12:5933
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