MVN, MVNS (register-shifted register)
Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result.
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | S | (0) | (0) | (0) | (0) | Rd | Rs | 0 | stypetype | 1 | Rm |
cond | | | | | | | | | | |
d = UInt(Rd); m = UInt(Rm); s = UInt(Rs);
setflags = (S == '1'); shift_t = DecodeRegShift(stype);
(type);
if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<Rd> | Is the general-purpose destination register, encoded in the "Rd" field. |
<Rm> | Is the general-purpose source register, encoded in the "Rm" field. |
<shifttype> |
Is the type of shift to be applied to the second source register,
encoded in
stypetype :
stypetype | <shifttype> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
<Rs> | Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. |
Operation
if ConditionPassed() then
EncodingSpecificOperations();
shift_n = UInt(R[s]<7:0>);
(shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
result = NOT(shifted);
R[d] = result;
if setflags then
PSTATE.N = result<31>;
PSTATE.Z = IsZeroBit(result);
PSTATE.C = carry;
// PSTATE.V unchanged
Internal version only: isa v00_96v00_88, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1
; Build timestamp: 2019-03-28T072018-12-12T12:5933
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