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CMP (register-shifted register)

Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.

A1

313029282726252423222120191817161514131211109876543210
!= 111100010101Rn(0)(0)(0)(0)Rs0stypetype1Rm
cond

A1

CMP{<c>}{<q>} <Rn>, <Rm>, <type> <Rs>

n = UInt(Rn); m = UInt(Rm); s = UInt(Rs); shift_t = DecodeRegShift(stype); (type); if n == 15 || m == 15 || s == 15 then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field.

<type> Is the type of shift to be applied to the second source register, encoded in stypetype:
stypetype<type>
00LSL
01LSR
10ASR
11ROR
<Rs>

Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); shifted = Shift(R[m], shift_t, shift_n, PSTATE.C); (result, nzcv) = AddWithCarry(R[n], NOT(shifted), '1'); PSTATE.<N,Z,C,V> = nzcv;

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:


Internal version only: isa v00_96v00_88, pseudocode r8p5_00bet2_rc5v85-xml-00bet9_rc1_1 ; Build timestamp: 2019-03-28T072018-12-12T12:5933

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