The GICC_IIDR characteristics are:
Provides information about the implementer and revision of the CPU interface.
GICC_IIDR is a 32-bit register.
The GICC_IIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Architecture_version | Revision | Implementer |
An IMPLEMENTATION DEFINED product identifier.
The version of the GIC architecture that is implemented.
Architecture_version | Meaning |
---|---|
0b0001 |
GICv1. |
0b0010 |
GICv2. |
0b0011 |
GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
0b0100 |
GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
Other values are reserved.
An IMPLEMENTATION DEFINED revision number for the CPU interface.
Contains the JEP106 code of the company that implemented the CPU interface.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x00FC | GICC_IIDR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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