DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way

The DC CISW characteristics are:

Purpose

Clean and Invalidate data cache by set/way.

When ARMv8.5-MemTag is implemented, this instruction might clean and invalidate Allocation Tags from caches.

Configuration

AArch64 System instruction DC CISW performs the same function as AArch32 System instruction DCCISW.

Attributes

DC CISW is a 64-bit System instruction.

Field descriptions

The DC CISW input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
SetWayLevelRES0
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

SetWay, bits [31:4]

Contains two fields:

Bits[L-1:4] are RES0.

A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).

ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.

Level, bits [3:1]

Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.

Bit [0]

Reserved, RES0.

Executing the DC CISW instruction

If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:

Accesses to this instruction use the following encodings:

DC CISW, <Xt>

op0op1CRnCRmop2
0b010b0000b01110b11100b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TSW == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else DC_CISW(X[t]); elsif PSTATE.EL == EL2 then DC_CISW(X[t]); elsif PSTATE.EL == EL3 then DC_CISW(X[t]);




27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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