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The DTLBIMVA characteristics are:
Invalidate all cached copies of translation table entries from data TLBs that meet the following requirements:
From the entries that match these requirement, the entries that are invalidated are required for the following translation regime:
The invalidation only applies to the PE that executes this System instruction.
Arm deprecates the use of this System instruction. It is only provided for backwards compatibility with earlier versions of the Arm architecture.
DTLBIMVA is a 32-bit System instruction.
The DTLBIMVA input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA | ASID |
Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.operation.
Reserved, RES0.
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.operation.
Global TLB entries that match the VA value will be affected by this System instructionoperation, regardless of the value of the ASID field.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1000 | 0b0110 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TTLB == '1' then AArch32.TakeHypTrapException(0x03); else DTLBIMVA(R[t]); elsif PSTATE.EL == EL2 then DTLBIMVA(R[t]); elsif PSTATE.EL == EL3 then DTLBIMVA(R[t]);
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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