The PMPIDR2 characteristics are:
Provides information to identify a Performance Monitor component.
For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
It is IMPLEMENTATION DEFINED whether PMPIDR2 is implemented in the Core power domain or in the Debug power domain.
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR2 is a 32-bit register.
The PMPIDR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
Part major revision. Parts can also use this field to extend Part number to 16-bits.
RAO. Indicates a JEP106 identity code is used.
Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.
Component | Offset | Instance |
---|---|---|
PMU | 0xFE8 | PMPIDR2 |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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