The CNTCV characteristics are:
Indicates the current count value.
The power domain of CNTCV is IMPLEMENTATION DEFINED.
On a reset of the reset domain in which an RW instance of this register is implemented, RW fields in the register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
CNTCV is a 64-bit register.
The CNTCV bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CountValue | |||||||||||||||||||||||||||||||
CountValue | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Indicates the counter value.
This field resets to an architecturally UNKNOWN value.
Frame | Accessibility |
---|---|
CNTControlBase | RW |
CNTReadBase | RO |
A write to CNTCV must be visible in the CNTPCT register of each running processor in a finite time.
For the instance of the register in the CNTControlBase frame:
In an implementation that supports 64-bit atomic memory accesses, this register must be accessible using a 64-bit atomic access.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTControlBase | 0x008 | CNTCV | 63:0 |
Access on this interface is RW.
Component | Frame | Offset | Instance | Range |
---|---|---|---|---|
Timer | CNTReadBase | 0x000 | CNTCV | 63:0 |
Access on this interface is RO.
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