The HTCR characteristics are:
The control register for stage 1 of the EL2 translation regime.
This stage of translation always uses the Long-descriptor translation table format.
AArch32 System register HTCR bits [31:0] are architecturally mapped to AArch64 System register TCR_EL2[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
HTCR is a 32-bit register.
The HTCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | IMPLEMENTATION DEFINED | 0 | HWU62 | HWU61 | HWU60 | HWU59 | HPD | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SH0 | ORGN0 | IRGN0 | 0 | 0 | 0 | 0 | 0 | T0SZ |
Reserved, RES1.
IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry.
HWU62 | Meaning |
---|---|
0b0 |
Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
Bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry.
HWU61 | Meaning |
---|---|
0b0 |
Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
Bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry.
HWU60 | Meaning |
---|---|
0b0 |
Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
Bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry.
HWU59 | Meaning |
---|---|
0b0 |
Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
0b1 |
Bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the PL2 translation regime.
HPD | Meaning |
---|---|
0b0 |
Hierarchical permissions are enabled. |
0b1 |
Hierarchical permissions are disabled. |
When disabled, the permissions are treated as if the bits are zero.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Shareability attribute for memory associated with translation table walks using HTTBR.
SH0 | Meaning |
---|---|
0b00 |
Non-shareable. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11.
This field resets to an architecturally UNKNOWN value.
Outer cacheability attribute for memory associated with translation table walks using HTTBR.
ORGN0 | Meaning |
---|---|
0b00 |
Normal memory, Outer Non-cacheable. |
0b01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
Inner cacheability attribute for memory associated with translation table walks using HTTBR.
IRGN0 | Meaning |
---|---|
0b00 |
Normal memory, Inner Non-cacheable. |
0b01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The size offset of the memory region addressed by HTTBR. The region size is 2(32-T0SZ) bytes.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b100 | 0b010 | 0b0010 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then return HTCR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else return HTCR;
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b100 | 0b010 | 0b0010 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then HTCR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else HTCR = R[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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