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The PMBPTR_EL1 characteristics are:
Defines the current write pointer for the profiling buffer.
This register is present only when SPE is implemented. Otherwise, direct accesses to PMBPTR_EL1 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
PMBPTR_EL1 is a 64-bit register.
The PMBPTR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
PTR | |||||||||||||||||||||||||||||||
PTR | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Current write address. Defines the virtual address of the next entry to be written to the buffer.
The architecture places restrictions on the values software can write to the pointer. For more information see 'Restrictions on the current write pointer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D6.3.5.
As a result, an implementation might treat some of bits[M:0], where M is defined by PMBIDR_EL1.Align, as RES0.
On a management interrupt, PMBPTR_EL1 is frozen.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2PB == 'x0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
return NVMem[0x810];
else
return PMBPTR_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMBPTR_EL1;
elsif PSTATE.EL == EL3 then
return PMBPTR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2PB == 'x0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
NVMem[0x810] = X[t];
else
PMBPTR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMBPTR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
PMBPTR_EL1 = X[t];
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-20192010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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