The AMCFGR characteristics are:
Global configuration register for the activity monitors.
Provides information on supported features, the number of counter groups implemented, the total number of activity monitor event counters implemented, and the size of the counters. AMCFGR is applicable to both the architected and the auxiliary counter groups.
AArch32 System register AMCFGR bits [31:0] are architecturally mapped to AArch64 System register AMCFGR_EL0[31:0] .
AArch32 System register AMCFGR bits [31:0] are architecturally mapped to External register AMCFGR[31:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCFGR are UNDEFINED.
AMCFGR is a 32-bit register.
The AMCFGR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCG | 0 | 0 | 0 | HDBG | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SIZE | N |
Defines the number of counter groups.
The number of implemented counter groups is defined as [AMCFGR.NCG + 1].
If the number of implemented auxiliary activity monitor event counters is zero, this field has a value of 0b0000. Otherwise, this field has a value of 0b0001.
Reserved, RES0.
Halt-on-debug supported.
In Armv8, this feature must be supported, and so this bit is 0b1.
HDBG | Meaning |
---|---|
0b0 |
AMCR.HDBG is RES0. |
0b1 |
AMCR.HDBG is read/write. |
Reserved, RAZ.
Defines the size of activity monitor event counters.
The size of the activity monitor event counters implemented by the Activity Monitors Extension is defined as [AMCFGR.SIZE + 1].
In Armv8, the counters are 64-bit, and so this field is 0b111111.
Software also uses this field to determine the spacing of counters in the memory-map. In Armv8, the counters are at doubleword-aligned addresses.
Defines the number of activity monitor event counters.
The total number of counters implemented in all groups by the Activity Monitors Extension is defined as [AMCFGR.N + 1].
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b001 | 0b1101 | 0b1111 | 0b0010 |
if PSTATE.EL == EL0 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return AMCFGR; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return AMCFGR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return AMCFGR; elsif PSTATE.EL == EL3 then return AMCFGR;
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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