ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1

The ID_AA64DFR1_EL1 characteristics are:

Purpose

Reserved for future expansion of top level information about the debug system in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

Configuration

Attributes

ID_AA64DFR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64DFR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
00000000000000000000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Reserved, RES0.

Accessing the ID_AA64DFR1_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64DFR1_EL1

op0CRnop1op2CRm
0b110b00000b0000b0010b0101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64DFR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64DFR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64DFR1_EL1;




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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