The TTBCR characteristics are:
The control register for stage 1 of the PL1&0 translation regime. Its controls include:
In Armv8.2, when the value of TTBCR.{EAE, T2E} is {1, 1}, TTBCR is used with TTBCR2.
AArch32 System register TTBCR bits [31:0] are architecturally mapped to AArch64 System register TCR_EL1[31:0] .
The current translation table format determines which format of the register is used.
When EL3 is using AArch32, write access to TTBCR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
Some RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32 then:
TTBCR is a 32-bit register.
The TTBCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EAE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PD1 | PD0 | 0 | N |
Extended Address Enable. The meanings of the possible values of this bit are:
EAE | Meaning |
---|---|
0b0 |
Use the VMSAv8-32 translation system with the Short-descriptor translation table format. |
This field resets to 0.
Reserved, RES0.
Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. The encoding of this bit is:
PD1 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR1. |
0b1 |
A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed. |
This field resets to 0.
Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR0. The encoding of this bit is:
PD0 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR0. |
0b1 |
A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed. |
This field resets to 0.
Reserved, RES0.
Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is bits[31:14-N]. The value of N also determines:
N can take any value from 0 to 7, that is, from 0b000 to 0b111.
When N has its reset value of 0, the translation table base is compatible with Armv5 and Armv6.
This field resets to 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EAE | IMPLEMENTATION DEFINED | SH1 | ORGN1 | IRGN1 | EPD1 | A1 | 0 | 0 | 0 | T1SZ | 0 | 0 | SH0 | ORGN0 | IRGN0 | EPD0 | T2E | 0 | 0 | 0 | T0SZ |
Extended Address Enable. The meanings of the possible values of this bit are:
EAE | Meaning |
---|---|
0b1 |
Use the VMSAv8-32 translation system with the Long-descriptor translation table format. |
This field resets to 0.
IMPLEMENTATION DEFINED.
This field resets to 0.
Shareability attribute for memory associated with translation table walks using TTBR1. Defined values are:
SH1 | Meaning |
---|---|
0b00 |
Non-shareable. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11.
This field resets to 0.
Outer cacheability attribute for memory associated with translation table walks using TTBR1.
ORGN1 | Meaning |
---|---|
0b00 |
Normal memory, Outer Non-cacheable. |
0b01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to 0.
Inner cacheability attribute for memory associated with translation table walks using TTBR1.
IRGN1 | Meaning |
---|---|
0b00 |
Normal memory, Inner Non-cacheable. |
0b01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to 0.
Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. The encoding of this bit is:
EPD1 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR1. |
0b1 |
A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed. |
This field resets to 0.
Selects whether TTBR0 or TTBR1 defines the ASID. The encoding of this bit is:
A1 | Meaning |
---|---|
0b0 |
TTBR0.ASID defines the ASID. |
0b1 |
TTBR1.ASID defines the ASID. |
This field resets to 0.
Reserved, RES0.
See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1.
This field resets to 0.
Reserved, RES0.
Shareability attribute for memory associated with translation table walks using TTBR0.
SH0 | Meaning |
---|---|
0b00 |
Non-shareable |
0b10 |
Outer Shareable |
0b11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11.
This field resets to 0.
Outer cacheability attribute for memory associated with translation table walks using TTBR0.
ORGN0 | Meaning |
---|---|
0b00 |
Normal memory, Outer Non-cacheable. |
0b01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to 0.
Inner cacheability attribute for memory associated with translation table walks using TTBR0.
IRGN0 | Meaning |
---|---|
0b00 |
Normal memory, Inner Non-cacheable. |
0b01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. |
0b10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable. |
0b11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. |
This field resets to 0.
Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0. The encoding of this bit is:
EPD0 | Meaning |
---|---|
0b0 |
Perform translation table walks using TTBR0. |
0b1 |
A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed. |
This field resets to 0.
TTBCR2 Enable.
T2E | Meaning |
---|---|
0b0 |
TTBCR2 is disabled. The contents of TTBCR2 are treated as 0 for all purposes other than reading or writing the register. |
0b1 |
TTBCR2 is enabled. |
If TTBCR.EAE==0, then the behavior is as if the bit is 0.
Reserved, RES0.
Reserved, RES0.
See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1.
This field resets to 0.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b010 | 0b0010 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '0' then return TTBCR_S; else return TTBCR_NS; else return TTBCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then return TTBCR_NS; else return TTBCR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then return TTBCR_S; else return TTBCR_NS;
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b010 | 0b0010 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T2 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T2 == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '0' then TTBCR_S = R[t]; else TTBCR_NS = R[t]; else TTBCR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then TTBCR_NS = R[t]; else TTBCR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; else if SCR.NS == '0' then TTBCR_S = R[t]; else TTBCR_NS = R[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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