The GICD_IGROUPR<n>E characteristics are:
Controls whether the corresponding SPI in the extended SPI range is in Group 0 or Group 1.
GICD_IGROUPR<n>E resets to 0x00000000.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1:
GICD_IGROUPR<n>E is a 32-bit register.
The GICD_IGROUPR<n>E bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Group_status_bit<x>, bit [x], for x = 0 to 31 |
Group status bit.
Group_status_bit<x> | Meaning |
---|---|
0b0 |
When GICD_CTLR.DS==1, the corresponding interrupt is Group 0. When GICD_CTLR.DS==0, the corresponding interrupt is Secure. |
0b1 |
When GICD_CTLR.DS==1, the corresponding interrupt is Group 1. When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1. |
If affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGRPMODR<n>E to form a 2-bit field that defines an interrupt group. The encoding of this field is described in GICD_IGRPMODR<n>E.
If affinity routing is disabled for the Security state of an interrupt, the bit is RES0:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x1000 + 4n | GICD_IGROUPR<n>E |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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