The FCSEIDR characteristics are:
Identifies whether the Fast Context Switch Extension (FCSE) is implemented.
In Armv8, the FCSE is not implemented, so this register is RAZ/WI. Software can access this register to determine that the implementation does not include the FCSE.
FCSEIDR is a 32-bit register.
The FCSEIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RAZ/WI.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b000 | 0b1101 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); else return FCSEIDR; elsif PSTATE.EL == EL2 then return FCSEIDR; elsif PSTATE.EL == EL3 then return FCSEIDR;
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b000 | 0b1101 | 0b1111 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); else FCSEIDR = R[t]; elsif PSTATE.EL == EL2 then FCSEIDR = R[t]; elsif PSTATE.EL == EL3 then FCSEIDR = R[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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