The CNTTIDR characteristics are:
Indicates the implemented timers in the memory map, and their features. For each value of N from 0 to 7 it indicates whether:
The power domain of CNTTIDR is IMPLEMENTATION DEFINED.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
CNTTIDR is a 32-bit register.
The CNTTIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Frame7 | Frame6 | Frame5 | Frame4 | Frame3 | Frame2 | Frame1 | Frame0 |
A 4-bit field indicating the features of frame CNTBase<n>.
Bit[3] of the field is RES0.
Bit[2], the FEL0 subfield, indicates whether frame CNTBase<n> has a second view, CNTEL0Base<n>. The possible values of this bit are:
Bit[2] | Meaning |
---|---|
0b0 | Frame<n> does not have a second view. The CNTEL0ACR register in the first view of the frame is RES0 |
0b1 | Frame<n> has a second view, CNTEL0Base<n>. |
If bit[0] is 0, bit[2] is RES0.
Bit[1], the FVI subfield, indicates whether both:
The possible values of bit[1] are:
Bit[1] | Meaning |
---|---|
0b0 | Frame<n> does not have virtual capability. The virtual time and offset registers are RES0. |
0b1 | Frame<n> has virtual capability. The virtual time and offset registers are implemented |
If bit[0] is 0, bit[1] is RES0.
Bit[0], the FI subfield, indicates whether frame CNTBase<n> is implemented. The possible values of this bit are:
Bit[0] | Meaning |
---|---|
0b0 | Frame<n> is not implemented. All registers associated with the frame are RES0. |
0b1 | Frame<n> is implemented |
In a system that recognizes two Security states this register is accessible by both Secure and Non-secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTCTLBase | 0x008 | CNTTIDR |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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