The ERRCIDR3 characteristics are:
Provides discovery information for the component.
Implementation of this register is OPTIONAL.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRCIDR3 are RES0.
ERRCIDR3 is a 32-bit register.
The ERRCIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_3 |
Reserved, RES0.
Component identification preamble, segment 3. This field reads as 0xB1.
Component | Offset | Instance |
---|---|---|
RAS | 0xFFC | ERRCIDR3 |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.