The ERRPIDR0 characteristics are:
Provides discovery information about the component.
For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
Implementation of this register is OPTIONAL.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR0 are RES0.
ERRPIDR0 is a 32-bit register.
The ERRPIDR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_0 |
Reserved, RES0.
Part number, bits [7:0].
The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number, and:
If a 12-bit part number is used, it is stored in ERRPIDR1.PART_1 and this field.
If a 16-bit part number is used, it is stored in ERRPIDR2.PART_2, ERRPIDR1.PART_1 and this field.
This field reads as an IMPLEMENTATION DEFINED value.
Component | Offset | Instance |
---|---|---|
RAS | 0xFE0 | ERRPIDR0 |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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