The TLBI VMALLS12E1IS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 0 and ARMv8.4-SecEL2 is not implemented, then the instruction invalidates any entry that would be required to translate an address using the Secure EL1&0 translation regime.
If SCR_EL3.NS is 1, then:
The entry would be required to translate an address using the Non-secure EL1&0 translation regime.
If EL2 is implemented, the entry would be used with the current VMID.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
From Armv8.4, when a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
TLBI VMALLS12E1IS is a 64-bit System instruction.
TLBI VMALLS12E1IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
Rt | op0 | op1 | op2 | CRn | CRm |
---|---|---|---|---|---|
0b11111 | 0b01 | 0b100 | 0b110 | 0b1000 | 0b0011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12E1IS(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALLE1IS(); else TLBI_VMALLS12E1IS();
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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