The EDVIDSR characteristics are:
Contains sampled values captured on reading EDPCSR[31:0].
EDVIDSR is in the Core power domain.
Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.
When the PC Sample-based Profiling Extension is implemented in the external debug registers space, if EL2 is not implemented and EL3 is not implemented, it is IMPLEMENTATION DEFINED whether EDVIDSR is implemented.
ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.
If ARMv8.1-VHE is implemented, the format of this register differs depending on the value of EDSCR.SC2.
The EDVIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS | E2 | E3 | HV | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VMID |
Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.
If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.
If EL2 is not implemented, this bit is RES0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.
If EDVIDSR.NS == 1 or the PE was in AArch32 state when EDPCSRlo (EDPCSR[31:0]) was read, this bit is 0.
If EL3 is not implemented, this bit is RES0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:
HV | Meaning |
---|---|
0b0 |
Bits[63:32] of the most recent EDPCSR sample are zero. |
0b1 |
Bits[63:32] of the most recent EDPCSR sample might be nonzero. |
An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample.
If EL2 is using AArch64 and the value of EDVIDSR.NS is 0 or the value of EDVIDSR.E2 is 1 this field is RES0.
If EL2 is not implemented, then this field is RES0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS | E2 | E3 | HV | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VMID |
This format applies in all Armv8.0 implementations.
Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample.
If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2.
If EL2 is not implemented, this bit is RES0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64.
If EDVIDSR.NS == 1 or the PE was in AArch32 state when EDPCSRlo (EDPCSR[31:0]) was read, this bit is 0.
If EL3 is not implemented, this bit is RES0.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero:
HV | Meaning |
---|---|
0b0 |
Bits[63:32] of the most recent EDPCSR sample are zero. |
0b1 |
Bits[63:32] of the most recent EDPCSR sample might be nonzero. |
An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero. An EDVIDSR.HV value of 0 is a hint that EDPCSRhi (EDPCSR[63:32]) does not need to be read.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL2 |
Context ID.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile
Component | Offset | Instance |
---|---|---|
Debug | 0x0A8 | EDVIDSR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.