The GICC_APR<n> characteristics are:
Provides information about interrupt active priorities.
Some or all RW fields of this register have defined reset values.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
When GICD_CTLR.DS == 0, these registers are Banked, and Non-secure accesses do not affect Secure operation. The Secure copies of these registers hold active priorities for Group 0 interrupts, and the Non-secure copies provide a Non-secure view of the active priorities for Group 1 interrupts.
GICC_APR1 is only implemented in implementations that support 6 or more bits of priority. GICC_APR2 and GICC_APR3 are only implemented in implementations that support 7 bits of priority.
When GICD_CTLR.DS==1, these registers hold the active priorities for Group 0 interrupts, and the active priorities for Group 1 interrupts are held by the GICC_NSAPR<n> registers.
GICC_APR<n> is a 32-bit register.
The GICC_APR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This field resets to 0.
These registers are used only when System register access is not enabled. When System register access is enabled the following registers provide equivalent functionality:
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x00D0 + 4n | GICC_APR<n> |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.