The EDPRCR characteristics are:
Controls the PE functionality related to powerup, reset, and powerdown.
EDPRCR contains fields that are in the Core power domain and fields that are in the Debug power domain.
For RW fields see the field description for a description of the behavior of the field on a reset that applies to its power domain. However:
If ARMv8.3-DoPD is implemented then all fields in this register are in the Core power domain.
CORENPDRQ is the only field that is mapped between the EDPRCR and DBGPRCR and DBGPRCR_EL1.
EDPRCR is a 32-bit register.
The EDPRCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CWRR | CORENPDRQ |
Reserved, RES0.
Reserved, RES0.
Core powerup request. Allows a debugger to request that the power controller power up the core, enabling access to the debug register in the Core power domain, and that the power controller emulates powerdown.
This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1.
COREPURQ | Meaning |
---|---|
0b0 |
Do not request power up of the Core power domain. |
0b1 |
Request power up of the Core power domain, and emulation of powerdown. |
In an implementation that includes the recommended external debug interface, this bit drives the DBGPWRUPREQ signal.
This field is in the Debug power domain and can be read and written when the Core power domain is powered off.
Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted.
On a External debug reset, this field resets to 0.
Accessing this field has the following behavior:
Reserved, RES0.
Warm reset request. Write-only bit that reads as zero.
The extent of the reset is IMPLEMENTATION DEFINED, but must be one of:
Arm deprecates use of this bit, and recommends that implementations ignore the request.
CWRR | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Request Warm reset. |
This field is in the Core power domain
The PE ignores writes to this bit if any of the following are true:
In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal.
On a Warm reset, this field resets to 0.
Accessing this field has the following behavior:
Core no powerdown request. Requests emulation of powerdown.
This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1.
CORENPDRQ | Meaning |
---|---|
0b0 |
If the system responds to a powerdown request, it powers down Core power domain. |
0b1 |
If the system responds to a powerdown request, it does not powerdown the Core power domain, but instead emulates a powerdown of that domain. |
When this bit reads as UNKNOWN, the PE ignores writes to this bit.
This field is in the Core power domain, and permitted accesses to this field map to the DBGPRCR.CORENPDRQ and DBGPRCR_EL1.CORENPDRQ fields.
In an implementation that includes the recommended external debug interface, this bit drives the DBGNOPWRDWN signal.
It is IMPLEMENTATION DEFINED whether this bit is reset to the value of EDPRCR.COREPURQ on exit from an IMPLEMENTATION DEFINED software-visible retention state. For more information about retention states see Core power domain power states.
Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted.
On a Cold reset, this field resets to the value in EDPRCR.COREPURQ.
Accessing this field has the following behavior:
On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.
Component | Offset | Instance |
---|---|---|
Debug | 0x310 | EDPRCR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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