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GCR_EL1, Tag Control Register.

The GCR_EL1 characteristics are:

Purpose

Tag Control Register.

Configuration

This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to GCR_EL1 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

GCR_EL1 is a 64-bit register.

Field descriptions

The GCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES0RRNDExclude
313029282726252423222120191817161514131211109876543210

Bits [63:17]

Reserved, RES0.

RRND, bit [16]

Controls whether RandomTag() generates a deterministic value solely based on the contents of RGSR_EL1, or a non-deterministic value.

RRNDMeaning
0b0

Generate a deterministic value based on RGSR_EL1.

0b1

Generate an IMPLEMENTATION DEFINED non-deterministic value.

Note

When the value of GCR_EL1.RRND is 1, the value generated does not need to be cryptographically random.

A similar algorithm to that used when RRND=0 but with free running clock is sufficient.

This field resets to an architecturally UNKNOWN value.

Exclude, bits [15:0]

Allocation Tag values excluded from selection by ChooseNonExcludedTag().

This field resets to an architecturally UNKNOWN value.

Accessing the GCR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, GCR_EL1

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b00010b00000b110
0b110b00010b0000b1100b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.ATA == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return GCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.ATA == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return GCR_EL1; elsif PSTATE.EL == EL3 then return GCR_EL1;

MSR GCR_EL1, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b00010b00000b110
0b110b00010b0000b1100b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.ATA == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else GCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.ATA == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else GCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then GCR_EL1 = X[t];




2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-20192010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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