The EDECR characteristics are:
Controls Halting debug events.
It is IMPLEMENTATION DEFINED whether EDECR is implemented in the Core power domain or in the Debug power domain. Some or all RW fields of this register have defined reset values, and:
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
EDECR is a 32-bit register.
The EDECR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SS | RES0 | RES0 |
Reserved, RES0.
Halting step enable. Possible values of this field are:
SS | Meaning |
---|---|
0b0 |
Halting step debug event disabled. |
0b1 |
Halting step debug event enabled. |
If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The following resets apply:
On a Cold reset, this field resets to :
On a Debug reset, this field resets to :
Reserved, RES0.
Reset Catch Enable.
RCE | Meaning |
---|---|
0b0 |
Reset Catch debug event disabled. |
0b1 |
Reset Catch debug event enabled. |
On a External debug reset, this field resets to 0.
Reserved, RES0.
OS Unlock Catch Enable.
OSUCE | Meaning |
---|---|
0b0 |
OS Unlock Catch debug event disabled. |
0b1 |
OS Unlock Catch debug event enabled. |
On a External debug reset, this field resets to 0.
Component | Offset | Instance |
---|---|---|
Debug | 0x024 | EDECR |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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