GICD_IGRPMODR<n>E, Interrupt Group Modifier Registers (extended SPI range), n = 1 - 2

The GICD_IGRPMODR<n>E characteristics are:

Purpose

When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:

Configuration

Some or all RW fields of this register have defined reset values.

GICD_IGRPMODR<n>E resets to 0x00000000.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1:

Attributes

GICD_IGRPMODR<n>E is a 32-bit register.

Field descriptions

The GICD_IGRPMODR<n>E bit assignments are:

313029282726252423222120191817161514131211109876543210
Group_modifier_bit<x>, bit [x], for x = 0 to 31

Group_modifier_bit<x>, bit [x], for x = 0 to 31

Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:

Group modifier bitGroup status bitDefinitionShort name
0b00b0Secure Group 0G0S
0b00b1Non-secure Group 1G1NS
0b10b0Secure Group 1G1S
0b10b1Reserved, treated as Non-secure Group 1-

This field resets to 0.

For INTID m, when DIV and MOD are the integer division and modulo operations:

Accessing the GICD_IGRPMODR<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_IGRPMODR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICD_IGRPMODR<n>E can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
GIC Distributor0x3000 + 4nGICD_IGRPMODR<n>E

This interface is accessible as follows:




27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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