The CTICIDR1 characteristics are:
Provides information to identify a CTI component.
For more information see 'About the Component identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
CTICIDR1 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTICIDR1 is a 32-bit register.
The CTICIDR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class. Reads as 0x9, debug component.
Preamble. RAZ.
Component | Offset | Instance |
---|---|---|
CTI | 0xFF4 | CTICIDR1 |
Access on this interface is RO.
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