The UAO characteristics are:
Allows access to the User Access Override bit.
This register is present only when ARMv8.2-UAO is implemented. Otherwise, direct accesses to UAO are UNDEFINED.
UAO is a 64-bit register.
The UAO bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | UAO | RES0 | |||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
User Access Override.
UAO | Meaning |
---|---|
0b0 |
The behavior of LDTR* and STTR* instructions is as defined in the base Armv8 architecture. |
0b1 |
When executed at EL1, or at EL2 with HCR_EL2.{E2H, TGE} == {1, 1}, LDTR* and STTR* instructions behave as the equivalent LDR* and STR* instructions. |
When executed at EL3, or at EL2 with HCR_EL2.E2H == 0 or HCR_EL2.TGE == 0, the LDTR* and STTR* instructions behave as the equivalent LDR* and STR* instructions, regardless of the setting of the PSTATE.UAO bit.
Reserved, RES0.
For details on the operation of the MSR (immediate) accessor, see MSR (immediate)in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0100 | 0b0010 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return Zeros(40):PSTATE.UAO:Zeros(23); elsif PSTATE.EL == EL2 then return Zeros(40):PSTATE.UAO:Zeros(23); elsif PSTATE.EL == EL3 then return Zeros(40):PSTATE.UAO:Zeros(23);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0100 | 0b0010 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.UAO = X[t]<23>; elsif PSTATE.EL == EL2 then PSTATE.UAO = X[t]<23>; elsif PSTATE.EL == EL3 then PSTATE.UAO = X[t]<23>;
op0 | op1 | CRn | op2 |
---|---|---|---|
0b00 | 0b000 | 0b0100 | 0b011 |
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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