The PMUSERENR characteristics are:
Enables or disables User mode access to the Performance Monitors.
AArch32 System register PMUSERENR bits [31:0] are architecturally mapped to AArch64 System register PMUSERENR_EL0[31:0] .
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMUSERENR is a 32-bit register.
The PMUSERENR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ER | CR | SW | EN |
Reserved, RES0.
Event counter read trap control:
ER | Meaning |
---|---|
0b0 |
EL0 reads of the PMXEVCNTR and PMEVCNTR<n>, and EL0 RW access to the PMSELR, are trapped to Undefined mode if PMUSERENR.EN is also 0. |
0b1 |
Overrides PMUSERENR.EN and enables RO access to PMXEVCNTR and PMEVCNTR<n>, and RW access to PMSELR. |
On a Warm reset, this field resets to 0.
Cycle counter read trap control:
CR | Meaning |
---|---|
0b0 |
EL0 reads of the PMCCNTR are trapped to Undefined mode if PMUSERENR.EN is also 0. |
0b1 |
Overrides PMUSERENR.EN and enables access to PMCCNTR. |
On a Warm reset, this field resets to 0.
Software increment write trap control:
SW | Meaning |
---|---|
0b0 |
EL0 writes to the PMSWINC are trapped to Undefined mode if PMUSERENR.EN is also 0. |
0b1 |
Overrides PMUSERENR.EN and enables access to PMSWINC. |
On a Warm reset, this field resets to 0.
Traps EL0 accesses to the Performance Monitors registers to Undefined mode:
EN | Meaning |
---|---|
0b0 |
While at EL0, PMUSERENR is always RO. Accesses to the other Performance Monitors registers are trapped to Undefined mode, unless enabled by one of PMUSERENR.{ER, CR, SW}. |
0b1 |
While at EL0, software can access all PMU registers except PMINTENSET and PMINTENCLR. |
On a Warm reset, this field resets to 0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b000 |
if PSTATE.EL == EL0 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMUSERENR; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMUSERENR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMUSERENR; elsif PSTATE.EL == EL3 then return PMUSERENR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMUSERENR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMUSERENR = R[t]; elsif PSTATE.EL == EL3 then PMUSERENR = R[t];
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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