LORC_EL1, LORegion Control (EL1)

The LORC_EL1 characteristics are:

Purpose

Enables and disables LORegions, and selects the current LORegion descriptor.

Configuration

This register is present only from Armv8.1. Otherwise, direct accesses to LORC_EL1 are UNDEFINED.

If no LORegion descriptors are supported by the PE, then this register is RES0.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

LORC_EL1 is a 64-bit register.

Field descriptions

The LORC_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000000000000000000000DS0EN
313029282726252423222120191817161514131211109876543210

Bits [63:10]

Reserved, RES0.

DS, bits [9:2]

From Armv8.1:

Descriptor Select. Selects the current LORegion descriptor accessed by LORSA_EL1, LOREA_EL1, and LORN_EL1.

The number of LORegion descriptors in IMPLEMENTATION DEFINED. The maximum number of LORegion descriptors supported is 256. If the number is less than 256, then bits[63:M+2] are RES0, where M is Log2(Number of LORegion descriptors supported by the implementation).

If this field points to an LORegion descriptor that is not supported by an implementation, then the registers LORN_EL1, LOREA_EL1, and LORSA_EL1 are RES0.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bit [1]

Reserved, RES0.

EN, bit [0]

From Armv8.1:

Enable. Indicates whether LORegions are enabled.

ENMeaning
0b0

Disabled. Memory accesses do not match any LORegions.

0b1

Enabled. Memory accesses may match a LORegion.

This bit is permitted to be cached in a TLB.

This field resets to 0.


Otherwise:

Reserved, RES0.

Accessing the LORC_EL1

Accesses to this register use the following encodings:

MRS <Xt>, LORC_EL1

CRnop0op1op2CRm
0b10100b110b0000b0110b0100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORC_EL1; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORC_EL1; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else return LORC_EL1;

MSR LORC_EL1, <Xt>

CRnop0op1op2CRm
0b10100b110b0000b0110b0100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORC_EL1 = X[t]; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORC_EL1 = X[t]; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else LORC_EL1 = X[t];




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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