The MPAMF_ECR characteristics are:
MPAMF_ECR is a 32-bit read-write register that controls MPAM error interrupts for this MSC.
The power domain of MPAMF_ECR is IMPLEMENTATION DEFINED.
If a MSC cannot encounter any of the error conditions listed in section 15.1, both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.
MPAMF_ECR is a 32-bit register.
The MPAMF_ECR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTEN |
Reserved, RES0.
Interrupt Enable.
INTEN | Meaning |
---|---|
0b0 |
MPAM error interrupts are not generated. |
0b1 |
MPAM error interrupts are generated. |
This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.
MPAMF_ECR must be accessible from the Non-secure and Secure address maps.
MPAMF_ECR must be banked for the Secure and Non-secure address maps. The Secure instance accesses the error interrupt controls used for Secure PARTIDs, and the Non-secure instance accesses the error interrupt controls used for Non-secure PARTIDs.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_s | 0x00F0 | MPAMF_ECR_s |
Access on this interface is RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_ns | 0x00F0 | MPAMF_ECR_ns |
Access on this interface is RW.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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