The DBGDTRRXext characteristics are:
Used for save/restore of DBGDTRRXint. It is a component of the Debug Communications Channel.
AArch32 System register DBGDTRRXext bits [31:0] are architecturally mapped to AArch64 System register OSDTRRX_EL1[31:0] .
RW fields in this register reset to architecturally UNKNOWN values.
DBGDTRRXext is a 32-bit register.
The DBGDTRRXext bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Update DTRRX without side-effect |
Update DTRRX without side-effect.
Writes to this register update the value in DTRRX and do not change RXfull.
Reads of this register return the last value written to DTRRX and do not change RXfull.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, chapter H4.
This field resets to an architecturally UNKNOWN value.
Arm deprecates reads and writes of DBGDTRRXext through the System register interface when the OS Lock is unlocked, DBGOSLSR.OSLK == 0.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b010 | 0b0000 | 0b1110 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDTRRXext; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDTRRXext; elsif PSTATE.EL == EL3 then return DBGDTRRXext;
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b010 | 0b0000 | 0b1110 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGDTRRXext = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGDTRRXext = R[t]; elsif PSTATE.EL == EL3 then DBGDTRRXext = R[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.