The MPAMF_IDR characteristics are:
The MPAMF_IDR is a 32-bit read-only register that indicates which memory partitioning and monitoring features are present on this MSC.
The power domain of MPAMF_IDR is IMPLEMENTATION DEFINED.
MPAMF_IDR is a 32-bit register.
The MPAMF_IDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HAS_PARTID_NRW | HAS_MSMON | HAS_IMPL_IDR | 0 | HAS_PRI_PART | HAS_MBW_PART | HAS_CPOR_PART | HAS_CCAP_PART | PMG_MAX | PARTID_MAX |
Has PARTID narrowing.
HAS_PARTID_NRW | Meaning |
---|---|
0b0 |
Does not have MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID or intPARTID mapping support. |
0b1 |
Supports the MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID registers. |
Has resource monitors. Indicates whether this MSC has MPAM resource monitors.
HAS_MSMON | Meaning |
---|---|
0b0 |
Does not support MPAM resource monitoring by groups or MPAMF_MSMON_IDR. |
0b1 |
Supports resource monitoring by matching a combination of PARTID and PMG. See MPAMF_MSMON_IDR. |
Has MPAMF_IMPL_IDR. Indicates whether this MSC has the implementation-specific MPAM features register, MPAMF_IMPL_IDR.
HAS_IMPL_IDR | Meaning |
---|---|
0b0 |
Does not have MPAMF_IMPL_IDR. |
0b1 |
Has MPAMF_IMPL_IDR. |
Reserved, RES0.
Has priority partitioning. Indicates whether this MSC implements MPAM priority partitioning and MPAMF_PRI_IDR.
HAS_PRI_PART | Meaning |
---|---|
0b0 |
Does not support priority partitioning or have MPAMF_PRI_IDR. |
0b1 |
Has MPAMF_PRI_IDR. |
Has memory bandwidth partitioning. Indicates whether this MSC implements MPAM memory bandwdith partitioning and MPAMF_MBW_IDR.
HAS_MBW_PART | Meaning |
---|---|
0b0 |
Does not support memory bandwidth partitioning or have MPAMF_MBW_IDR register. |
0b1 |
Has MPAMF_MBW_IDR register. |
Has cache portion partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and MPAMF_CPOR_IDR.
HAS_CPOR_PART | Meaning |
---|---|
0b0 |
Does not support cache portion partitioning or have MPAMF_CPOR_IDR or MPAMCFG_CPBM registers. |
0b1 |
Has MPAMF_CPOR_IDR and MPAMCFG_CPBM registers. |
Has cache capacity partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.
HAS_CCAP_PART | Meaning |
---|---|
0b0 |
Does not support cache capacity partitioning or have MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. |
0b1 |
Has MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. |
Maximum value of Non-secure PMG supported by this component.
Maximum value of Non-secure PARTID supported by this component.
This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.
MPAMF_IDR must be accessible from the Non-secure and Secure address maps.
MPAMF_IDR is permitted to be shared between the Secure and Non-secure address maps unless the register contents is different for Secure and Non-secure partitions, when the register must be banked.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_s | 0x0000 | MPAMF_IDR_s |
Access on this interface is RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_ns | 0x0000 | MPAMF_IDR_ns |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.