(old) htmldiff from-(new)

System Register index by functional group

Below are indexes for registers with the following main functional groups:

In the ID functional group:

Exec stateNameDescription
AArch32CCSIDRCurrent Cache Size ID Register
AArch32CCSIDR2Current Cache Size ID Register 2
AArch32CLIDRCache Level ID Register
AArch32CSSELRCache Size Selection Register
AArch32CTRCache Type Register
AArch32ID_AFR0Auxiliary Feature Register 0
AArch32ID_DFR0Debug Feature Register 0
AArch32ID_ISAR0Instruction Set Attribute Register 0
AArch32ID_ISAR1Instruction Set Attribute Register 1
AArch32ID_ISAR2Instruction Set Attribute Register 2
AArch32ID_ISAR3Instruction Set Attribute Register 3
AArch32ID_ISAR4Instruction Set Attribute Register 4
AArch32ID_ISAR5Instruction Set Attribute Register 5
AArch32ID_ISAR6Instruction Set Attribute Register 6
AArch32ID_MMFR0Memory Model Feature Register 0
AArch32ID_MMFR1Memory Model Feature Register 1
AArch32ID_MMFR2Memory Model Feature Register 2
AArch32ID_MMFR3Memory Model Feature Register 3
AArch32ID_MMFR4Memory Model Feature Register 4
AArch32ID_PFR0Processor Feature Register 0
AArch32ID_PFR1Processor Feature Register 1
AArch32ID_PFR2Processor Feature Register 2
AArch32MIDRMain ID Register
AArch32MPIDRMultiprocessor Affinity Register
AArch32REVIDRRevision ID Register
AArch32TCMTRTCM Type Register
AArch32TLBTRTLB Type Register
AArch64CCSIDR2_EL1Current Cache Size ID Register 2
AArch64CCSIDR_EL1Current Cache Size ID Register
AArch64CLIDR_EL1Cache Level ID Register
AArch64CSSELR_EL1Cache Size Selection Register
AArch64CTR_EL0Cache Type Register
AArch64DCZID_EL0Data Cache Zero ID register
AArch64GMID_EL1 Multiple tag transfer ID register
AArch64ID_AA64AFR0_EL1AArch64 Auxiliary Feature Register 0
AArch64ID_AA64AFR1_EL1AArch64 Auxiliary Feature Register 1
AArch64ID_AA64DFR0_EL1AArch64 Debug Feature Register 0
AArch64ID_AA64DFR1_EL1AArch64 Debug Feature Register 1
AArch64ID_AA64ISAR0_EL1AArch64 Instruction Set Attribute Register 0
AArch64ID_AA64ISAR1_EL1AArch64 Instruction Set Attribute Register 1
AArch64ID_AA64MMFR0_EL1AArch64 Memory Model Feature Register 0
AArch64ID_AA64MMFR1_EL1AArch64 Memory Model Feature Register 1
AArch64ID_AA64MMFR2_EL1AArch64 Memory Model Feature Register 2
AArch64ID_AA64PFR0_EL1AArch64 Processor Feature Register 0
AArch64ID_AA64PFR1_EL1AArch64 Processor Feature Register 1
AArch64ID_AFR0_EL1AArch32 Auxiliary Feature Register 0
AArch64ID_DFR0_EL1AArch32 Debug Feature Register 0
AArch64ID_ISAR0_EL1AArch32 Instruction Set Attribute Register 0
AArch64ID_ISAR1_EL1AArch32 Instruction Set Attribute Register 1
AArch64ID_ISAR2_EL1AArch32 Instruction Set Attribute Register 2
AArch64ID_ISAR3_EL1AArch32 Instruction Set Attribute Register 3
AArch64ID_ISAR4_EL1AArch32 Instruction Set Attribute Register 4
AArch64ID_ISAR5_EL1AArch32 Instruction Set Attribute Register 5
AArch64ID_ISAR6_EL1AArch32 Instruction Set Attribute Register 6
AArch64ID_MMFR0_EL1AArch32 Memory Model Feature Register 0
AArch64ID_MMFR1_EL1AArch32 Memory Model Feature Register 1
AArch64ID_MMFR2_EL1AArch32 Memory Model Feature Register 2
AArch64ID_MMFR3_EL1AArch32 Memory Model Feature Register 3
AArch64ID_MMFR4_EL1AArch32 Memory Model Feature Register 4
AArch64ID_PFR0_EL1AArch32 Processor Feature Register 0
AArch64ID_PFR1_EL1AArch32 Processor Feature Register 1
AArch64ID_PFR2_EL1AArch32 Processor Feature Register 2
AArch64MIDR_EL1Main ID Register
AArch64MPIDR_EL1Multiprocessor Affinity Register
AArch64REVIDR_EL1Revision ID Register
ExternalEDAA32PFRExternal Debug AArch32 Processor Feature Register
ExternalEDDFRExternal Debug Feature Register
ExternalEDPFRExternal Debug Processor Feature Register
ExternalMIDR_EL1Main ID Register

In the Memory functional group:

Exec stateNameDescription
AArch32AMAIR0Auxiliary Memory Attribute Indirection Register 0
AArch32AMAIR1Auxiliary Memory Attribute Indirection Register 1
AArch32CONTEXTIDRContext ID Register
AArch32DACRDomain Access Control Register
AArch32HAMAIR0Hyp Auxiliary Memory Attribute Indirection Register 0
AArch32HAMAIR1Hyp Auxiliary Memory Attribute Indirection Register 1
AArch32HMAIR0Hyp Memory Attribute Indirection Register 0
AArch32HMAIR1Hyp Memory Attribute Indirection Register 1
AArch32HTCRHyp Translation Control Register
AArch32HTTBRHyp Translation Table Base Register
AArch32MAIR0Memory Attribute Indirection Register 0
AArch32MAIR1Memory Attribute Indirection Register 1
AArch32NMRRNormal Memory Remap Register
AArch32PRRRPrimary Region Remap Register
AArch32TTBCRTranslation Table Base Control Register
AArch32TTBCR2Translation Table Base Control Register 2
AArch32TTBR0Translation Table Base Register 0
AArch32TTBR1Translation Table Base Register 1
AArch32VTCRVirtualization Translation Control Register
AArch32VTTBRVirtualization Translation Table Base Register
AArch64AMAIR_EL1Auxiliary Memory Attribute Indirection Register (EL1)
AArch64AMAIR_EL2Auxiliary Memory Attribute Indirection Register (EL2)
AArch64AMAIR_EL3Auxiliary Memory Attribute Indirection Register (EL3)
AArch64CONTEXTIDR_EL1Context ID Register (EL1)
AArch64CONTEXTIDR_EL2Context ID Register (EL2)
AArch64DACR32_EL2Domain Access Control Register
AArch64LORC_EL1LORegion Control (EL1)
AArch64LOREA_EL1LORegion End Address (EL1)
AArch64LORID_EL1LORegionID (EL1)
AArch64LORN_EL1LORegion Number (EL1)
AArch64LORSA_EL1LORegion Start Address (EL1)
AArch64MAIR_EL1Memory Attribute Indirection Register (EL1)
AArch64MAIR_EL2Memory Attribute Indirection Register (EL2)
AArch64MAIR_EL3Memory Attribute Indirection Register (EL3)
AArch64TCR_EL1Translation Control Register (EL1)
AArch64TCR_EL2Translation Control Register (EL2)
AArch64TCR_EL3Translation Control Register (EL3)
AArch64TTBR0_EL1Translation Table Base Register 0 (EL1)
AArch64TTBR0_EL2Translation Table Base Register 0 (EL2)
AArch64TTBR0_EL3Translation Table Base Register 0 (EL3)
AArch64TTBR1_EL1Translation Table Base Register 1 (EL1)
AArch64TTBR1_EL2Translation Table Base Register 1 (EL2)
AArch64VTCR_EL2Virtualization Translation Control Register
AArch64VTTBR_EL2Virtualization Translation Table Base Register

In the Other functional group:

Exec stateNameDescription
AArch32CPACRArchitectural Feature Access Control Register
AArch32SCTLRSystem Control Register
AArch64CPACR_EL1Architectural Feature Access Control Register
AArch64SCTLR_EL1System Control Register (EL1)
AArch64SCTLR_EL3System Control Register (EL3)
AArch64ZCR_EL1SVE Control Register for EL1
AArch64ZCR_EL2SVE Control Register for EL2
AArch64ZCR_EL3SVE Control Register for EL3

In the Exception functional group:

Exec stateNameDescription
AArch32ADFSRAuxiliary Data Fault Status Register
AArch32AIFSRAuxiliary Instruction Fault Status Register
AArch32DFARData Fault Address Register
AArch32DFSRData Fault Status Register
AArch32HADFSRHyp Auxiliary Data Fault Status Register
AArch32HAIFSRHyp Auxiliary Instruction Fault Status Register
AArch32HDFARHyp Data Fault Address Register
AArch32HIFARHyp Instruction Fault Address Register
AArch32HPFARHyp IPA Fault Address Register
AArch32HSRHyp Syndrome Register
AArch32HVBARHyp Vector Base Address Register
AArch32IFARInstruction Fault Address Register
AArch32IFSRInstruction Fault Status Register
AArch32ISRInterrupt Status Register
AArch32MVBARMonitor Vector Base Address Register
AArch32VBARVector Base Address Register
AArch64AFSR0_EL1Auxiliary Fault Status Register 0 (EL1)
AArch64AFSR0_EL2Auxiliary Fault Status Register 0 (EL2)
AArch64AFSR0_EL3Auxiliary Fault Status Register 0 (EL3)
AArch64AFSR1_EL1Auxiliary Fault Status Register 1 (EL1)
AArch64AFSR1_EL2Auxiliary Fault Status Register 1 (EL2)
AArch64AFSR1_EL3Auxiliary Fault Status Register 1 (EL3)
AArch64ESR_EL1Exception Syndrome Register (EL1)
AArch64ESR_EL2Exception Syndrome Register (EL2)
AArch64ESR_EL3Exception Syndrome Register (EL3)
AArch64FAR_EL1Fault Address Register (EL1)
AArch64FAR_EL2Fault Address Register (EL2)
AArch64FAR_EL3Fault Address Register (EL3)
AArch64HPFAR_EL2Hypervisor IPA Fault Address Register
AArch64IFSR32_EL2Instruction Fault Status Register (EL2)
AArch64ISR_EL1Interrupt Status Register
AArch64VBAR_EL1Vector Base Address Register (EL1)
AArch64VBAR_EL2Vector Base Address Register (EL2)
AArch64VBAR_EL3Vector Base Address Register (EL3)

In the Special functional group:

Exec stateNameDescription
AArch32DLRDebug Link Register
AArch32DSPSRDebug Saved Program Status Register
AArch32ELR_hypException Link Register (Hyp mode)
AArch32SPSRSaved Program Status Register
AArch32SPSR_abtSaved Program Status Register (Abort mode)
AArch32SPSR_fiqSaved Program Status Register (FIQ mode)
AArch32SPSR_hypSaved Program Status Register (Hyp mode)
AArch32SPSR_irqSaved Program Status Register (IRQ mode)
AArch32SPSR_monSaved Program Status Register (Monitor mode)
AArch32SPSR_svcSaved Program Status Register (Supervisor mode)
AArch32SPSR_undSaved Program Status Register (Undefined mode)
AArch64ELR_EL1Exception Link Register (EL1)
AArch64ELR_EL2Exception Link Register (EL2)
AArch64ELR_EL3Exception Link Register (EL3)
AArch64SPSR_EL1Saved Program Status Register (EL1)
AArch64SPSR_EL2Saved Program Status Register (EL2)
AArch64SPSR_EL3Saved Program Status Register (EL3)
AArch64SPSR_abtSaved Program Status Register (Abort mode)
AArch64SPSR_fiqSaved Program Status Register (FIQ mode)
AArch64SPSR_irqSaved Program Status Register (IRQ mode)
AArch64SPSR_undSaved Program Status Register (Undefined mode)
AArch64SP_EL0Stack Pointer (EL0)
AArch64SP_EL1Stack Pointer (EL1)
AArch64SP_EL2Stack Pointer (EL2)
AArch64SP_EL3Stack Pointer (EL3)

In the PSTATE functional group:

Exec stateNameDescription
AArch32APSRApplication Program Status Register
AArch32CPSRCurrent Program Status Register
AArch64CurrentELCurrent Exception Level
AArch64DAIFInterrupt Mask Bits
AArch64DITData Independent Timing
AArch64NZCVCondition Flags
AArch64PANPrivileged Access Never
AArch64SPSelStack Pointer Select
AArch64SSBSSpeculative Store Bypass Safe
AArch64TCOTag Check Override
AArch64UAOUser Access Override

In the Cache functional group:

Exec stateNameDescription
AArch32BPIALLBranch Predictor Invalidate All
AArch32BPIALLISBranch Predictor Invalidate All, Inner Shareable
AArch32BPIMVABranch Predictor Invalidate by VA
AArch32DCCIMVACData Cache line Clean and Invalidate by VA to PoC
AArch32DCCISWData Cache line Clean and Invalidate by Set/Way
AArch32DCCMVACData Cache line Clean by VA to PoC
AArch32DCCMVAUData Cache line Clean by VA to PoU
AArch32DCCSWData Cache line Clean by Set/Way
AArch32DCIMVACData Cache line Invalidate by VA to PoC
AArch32DCISWData Cache line Invalidate by Set/Way
AArch32ICIALLUInstruction Cache Invalidate All to PoU
AArch32ICIALLUISInstruction Cache Invalidate All to PoU, Inner Shareable
AArch32ICIMVAUInstruction Cache line Invalidate by VA to PoU
AArch64DC CGDSWData, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way
AArch64DC CGDVACData, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC
AArch64DC CGDVADPData, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP
AArch64DC CGDVAPData, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP
AArch64DC CGSWData, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way
AArch64DC CGVACData, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC
AArch64DC CGVADPData, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoDP
AArch64DC CGVAPData, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP
AArch64DC CIGDSWData, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way
AArch64DC CIGDVACData, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC
AArch64DC CIGSWData, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way
AArch64DC CIGVACData, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC
AArch64DC CISWData or unified Cache line Clean and Invalidate by Set/Way
AArch64DC CIVACData or unified Cache line Clean and Invalidate by VA to PoC
AArch64DC CSWData or unified Cache line Clean by Set/Way
AArch64DC CVACData or unified Cache line Clean by VA to PoC
AArch64DC CVADPData or unified Cache line Clean by VA to PoDP
AArch64DC CVAPData or unified Cache line Clean by VA to PoP
AArch64DC CVAUData or unified Cache line Clean by VA to PoU
AArch64DC GVAData Cache set Allocation Tag by VA
AArch64DC GZVAData Cache set Allocation Tags and Zero by VA
AArch64DC IGDSWData, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way
AArch64DC IGDVACData, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC
AArch64DC IGSWData, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way
AArch64DC IGVACData, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC
AArch64DC ISWData or unified Cache line Invalidate by Set/Way
AArch64DC IVACData or unified Cache line Invalidate by VA to PoC
AArch64DC ZVAData Cache Zero by VA
AArch64IC IALLUInstruction Cache Invalidate All to PoU
AArch64IC IALLUISInstruction Cache Invalidate All to PoU, Inner Shareable
AArch64IC IVAUInstruction Cache line Invalidate by VA to PoU

In the Address functional group:

Exec stateNameDescription
AArch32ATS12NSOPRAddress Translate Stages 1 and 2 Non-secure Only PL1 Read
AArch32ATS12NSOPWAddress Translate Stages 1 and 2 Non-secure Only PL1 Write
AArch32ATS12NSOURAddress Translate Stages 1 and 2 Non-secure Only Unprivileged Read
AArch32ATS12NSOUWAddress Translate Stages 1 and 2 Non-secure Only Unprivileged Write
AArch32ATS1CPRAddress Translate Stage 1 Current state PL1 Read
AArch32ATS1CPRPAddress Translate Stage 1 Current state PL1 Read PAN
AArch32ATS1CPWAddress Translate Stage 1 Current state PL1 Write
AArch32ATS1CPWPAddress Translate Stage 1 Current state PL1 Write PAN
AArch32ATS1CURAddress Translate Stage 1 Current state Unprivileged Read
AArch32ATS1CUWAddress Translate Stage 1 Current state Unprivileged Write
AArch32ATS1HRAddress Translate Stage 1 Hyp mode Read
AArch32ATS1HWAddress Translate Stage 1 Hyp mode Write
AArch32PARPhysical Address Register
AArch64AT S12E0RAddress Translate Stages 1 and 2 EL0 Read
AArch64AT S12E0WAddress Translate Stages 1 and 2 EL0 Write
AArch64AT S12E1RAddress Translate Stages 1 and 2 EL1 Read
AArch64AT S12E1WAddress Translate Stages 1 and 2 EL1 Write
AArch64AT S1E0RAddress Translate Stage 1 EL0 Read
AArch64AT S1E0WAddress Translate Stage 1 EL0 Write
AArch64AT S1E1RAddress Translate Stage 1 EL1 Read
AArch64AT S1E1RPAddress Translate Stage 1 EL1 Read PAN
AArch64AT S1E1WAddress Translate Stage 1 EL1 Write
AArch64AT S1E1WPAddress Translate Stage 1 EL1 Write PAN
AArch64AT S1E2RAddress Translate Stage 1 EL2 Read
AArch64AT S1E2WAddress Translate Stage 1 EL2 Write
AArch64AT S1E3RAddress Translate Stage 1 EL3 Read
AArch64AT S1E3WAddress Translate Stage 1 EL3 Write
AArch64PAR_EL1Physical Address Register

In the TLB functional group:

Exec stateNameDescription
AArch32CFPRCTXControl Flow Prediction Restriction by Context
AArch32CPPRCTXCache Prefetch Prediction Restriction by Context
AArch32DTLBIALLData TLB Invalidate All
AArch32DTLBIASIDData TLB Invalidate by ASID match
AArch32DTLBIMVAData TLB Invalidate by VA
AArch32DVPRCTXData Value Prediction Restriction by Context
AArch32ITLBIALLInstruction TLB Invalidate All
AArch32ITLBIASIDInstruction TLB Invalidate by ASID match
AArch32ITLBIMVAInstruction TLB Invalidate by VA
AArch32TLBIALLTLB Invalidate All
AArch32TLBIALLHTLB Invalidate All, Hyp mode
AArch32TLBIALLHISTLB Invalidate All, Hyp mode, Inner Shareable
AArch32TLBIALLISTLB Invalidate All, Inner Shareable
AArch32TLBIALLNSNHTLB Invalidate All, Non-Secure Non-Hyp
AArch32TLBIALLNSNHISTLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
AArch32TLBIASIDTLB Invalidate by ASID match
AArch32TLBIASIDISTLB Invalidate by ASID match, Inner Shareable
AArch32TLBIIPAS2TLB Invalidate by Intermediate Physical Address, Stage 2
AArch32TLBIIPAS2ISTLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
AArch32TLBIIPAS2LTLB Invalidate by Intermediate Physical Address, Stage 2, Last level
AArch32TLBIIPAS2LISTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
AArch32TLBIMVATLB Invalidate by VA
AArch32TLBIMVAATLB Invalidate by VA, All ASID
AArch32TLBIMVAAISTLB Invalidate by VA, All ASID, Inner Shareable
AArch32TLBIMVAALTLB Invalidate by VA, All ASID, Last level
AArch32TLBIMVAALISTLB Invalidate by VA, All ASID, Last level, Inner Shareable
AArch32TLBIMVAHTLB Invalidate by VA, Hyp mode
AArch32TLBIMVAHISTLB Invalidate by VA, Hyp mode, Inner Shareable
AArch32TLBIMVAISTLB Invalidate by VA, Inner Shareable
AArch32TLBIMVALTLB Invalidate by VA, Last level
AArch32TLBIMVALHTLB Invalidate by VA, Last level, Hyp mode
AArch32TLBIMVALHISTLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
AArch32TLBIMVALISTLB Invalidate by VA, Last level, Inner Shareable
AArch64TLBI ALLE1TLB Invalidate All, EL1
AArch64TLBI ALLE1ISTLB Invalidate All, EL1, Inner Shareable
AArch64TLBI ALLE1OSTLB Invalidate All, EL1, Outer Shareable
AArch64TLBI ALLE2TLB Invalidate All, EL2
AArch64TLBI ALLE2ISTLB Invalidate All, EL2, Inner Shareable
AArch64TLBI ALLE2OSTLB Invalidate All, EL2, Outer Shareable
AArch64TLBI ALLE3TLB Invalidate All, EL3
AArch64TLBI ALLE3ISTLB Invalidate All, EL3, Inner Shareable
AArch64TLBI ALLE3OSTLB Invalidate All, EL3, Outer Shareable
AArch64TLBI ASIDE1TLB Invalidate by ASID, EL1
AArch64TLBI ASIDE1ISTLB Invalidate by ASID, EL1, Inner Shareable
AArch64TLBI ASIDE1OSTLB Invalidate by ASID, EL1, Outer Shareable
AArch64TLBI IPAS2E1TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
AArch64TLBI IPAS2E1ISTLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
AArch64TLBI IPAS2E1OSTLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
AArch64TLBI IPAS2LE1TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
AArch64TLBI IPAS2LE1ISTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
AArch64TLBI IPAS2LE1OSTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
AArch64TLBI RIPAS2E1TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1
AArch64TLBI RIPAS2E1ISTLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
AArch64TLBI RIPAS2E1OSTLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
AArch64TLBI RIPAS2LE1TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
AArch64TLBI RIPAS2LE1ISTLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
AArch64TLBI RIPAS2LE1OSTLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
AArch64TLBI RVAAE1TLB Range Invalidate by VA, All ASID, EL1
AArch64TLBI RVAAE1ISTLB Range Invalidate by VA, All ASID, EL1, Inner Shareable
AArch64TLBI RVAAE1OSTLB Range Invalidate by VA, All ASID, EL1, Outer Shareable
AArch64TLBI RVAALE1TLB Range Invalidate by VA, All ASID, Last level, EL1
AArch64TLBI RVAALE1ISTLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
AArch64TLBI RVAALE1OSTLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable
AArch64TLBI RVAE1TLB Range Invalidate by VA, EL1
AArch64TLBI RVAE1ISTLB Range Invalidate by VA, EL1, Inner Shareable
AArch64TLBI RVAE1OSTLB Range Invalidate by VA, EL1, Outer Shareable
AArch64TLBI RVAE2TLB Range Invalidate by VA, EL2
AArch64TLBI RVAE2ISTLB Range Invalidate by VA, EL2, Inner Shareable
AArch64TLBI RVAE2OSTLB Range Invalidate by VA, EL2, Outer Shareable
AArch64TLBI RVAE3TLB Range Invalidate by VA, EL3
AArch64TLBI RVAE3ISTLB Range Invalidate by VA, EL3, Inner Shareable
AArch64TLBI RVAE3OSTLB Range Invalidate by VA, EL3, Outer Shareable
AArch64TLBI RVALE1TLB Range Invalidate by VA, Last level, EL1
AArch64TLBI RVALE1ISTLB Range Invalidate by VA, Last level, EL1, Inner Shareable
AArch64TLBI RVALE1OSTLB Range Invalidate by VA, Last level, EL1, Outer Shareable
AArch64TLBI RVALE2TLB Range Invalidate by VA, Last level, EL2
AArch64TLBI RVALE2ISTLB Range Invalidate by VA, Last level, EL2, Inner Shareable
AArch64TLBI RVALE2OSTLB Range Invalidate by VA, Last level, EL2, Outer Shareable
AArch64TLBI RVALE3TLB Range Invalidate by VA, Last level, EL3
AArch64TLBI RVALE3ISTLB Range Invalidate by VA, Last level, EL3, Inner Shareable
AArch64TLBI RVALE3OSTLB Range Invalidate by VA, Last level, EL3, Outer Shareable
AArch64TLBI VAAE1TLB Invalidate by VA, All ASID, EL1
AArch64TLBI VAAE1ISTLB Invalidate by VA, All ASID, EL1, Inner Shareable
AArch64TLBI VAAE1OSTLB Invalidate by VA, All ASID, EL1, Outer Shareable
AArch64TLBI VAALE1TLB Invalidate by VA, All ASID, Last level, EL1
AArch64TLBI VAALE1ISTLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
AArch64TLBI VAALE1OSTLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable
AArch64TLBI VAE1TLB Invalidate by VA, EL1
AArch64TLBI VAE1ISTLB Invalidate by VA, EL1, Inner Shareable
AArch64TLBI VAE1OSTLB Invalidate by VA, EL1, Outer Shareable
AArch64TLBI VAE2TLB Invalidate by VA, EL2
AArch64TLBI VAE2ISTLB Invalidate by VA, EL2, Inner Shareable
AArch64TLBI VAE2OSTLB Invalidate by VA, EL2, Outer Shareable
AArch64TLBI VAE3TLB Invalidate by VA, EL3
AArch64TLBI VAE3ISTLB Invalidate by VA, EL3, Inner Shareable
AArch64TLBI VAE3OSTLB Invalidate by VA, EL3, Outer Shareable
AArch64TLBI VALE1TLB Invalidate by VA, Last level, EL1
AArch64TLBI VALE1ISTLB Invalidate by VA, Last level, EL1, Inner Shareable
AArch64TLBI VALE1OSTLB Invalidate by VA, Last level, EL1, Outer Shareable
AArch64TLBI VALE2TLB Invalidate by VA, Last level, EL2
AArch64TLBI VALE2ISTLB Invalidate by VA, Last level, EL2, Inner Shareable
AArch64TLBI VALE2OSTLB Invalidate by VA, Last level, EL2, Outer Shareable
AArch64TLBI VALE3TLB Invalidate by VA, Last level, EL3
AArch64TLBI VALE3ISTLB Invalidate by VA, Last level, EL3, Inner Shareable
AArch64TLBI VALE3OSTLB Invalidate by VA, Last level, EL3, Outer Shareable
AArch64TLBI VMALLE1TLB Invalidate by VMID, All at stage 1, EL1
AArch64TLBI VMALLE1ISTLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
AArch64TLBI VMALLE1OSTLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable
AArch64TLBI VMALLS12E1TLB Invalidate by VMID, All at Stage 1 and 2, EL1
AArch64TLBI VMALLS12E1ISTLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
AArch64TLBI VMALLS12E1OSTLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable

In the PMU functional group:

Exec stateNameDescription
AArch32PMCCFILTRPerformance Monitors Cycle Count Filter Register
AArch32PMCCNTRPerformance Monitors Cycle Count Register
AArch32PMCEID0Performance Monitors Common Event Identification register 0
AArch32PMCEID1Performance Monitors Common Event Identification register 1
AArch32PMCEID2Performance Monitors Common Event Identification register 2
AArch32PMCEID3Performance Monitors Common Event Identification register 3
AArch32PMCNTENCLRPerformance Monitors Count Enable Clear register
AArch32PMCNTENSETPerformance Monitors Count Enable Set register
AArch32PMCRPerformance Monitors Control Register
AArch32PMEVCNTR<n>Performance Monitors Event Count Registers
AArch32PMEVTYPER<n>Performance Monitors Event Type Registers
AArch32PMINTENCLRPerformance Monitors Interrupt Enable Clear register
AArch32PMINTENSETPerformance Monitors Interrupt Enable Set register
AArch32PMMIRPerformance Monitors Machine Identification Register
AArch32PMOVSRPerformance Monitors Overflow Flag Status Register
AArch32PMOVSSETPerformance Monitors Overflow Flag Status Set register
AArch32PMSELRPerformance Monitors Event Counter Selection Register
AArch32PMSWINCPerformance Monitors Software Increment register
AArch32PMUSERENRPerformance Monitors User Enable Register
AArch32PMXEVCNTRPerformance Monitors Selected Event Count Register
AArch32PMXEVTYPERPerformance Monitors Selected Event Type Register
AArch64PMCCFILTR_EL0Performance Monitors Cycle Count Filter Register
AArch64PMCCNTR_EL0Performance Monitors Cycle Count Register
AArch64PMCEID0_EL0Performance Monitors Common Event Identification register 0
AArch64PMCEID1_EL0Performance Monitors Common Event Identification register 1
AArch64PMCNTENCLR_EL0Performance Monitors Count Enable Clear register
AArch64PMCNTENSET_EL0Performance Monitors Count Enable Set register
AArch64PMCR_EL0Performance Monitors Control Register
AArch64PMEVCNTR<n>_EL0Performance Monitors Event Count Registers
AArch64PMEVTYPER<n>_EL0Performance Monitors Event Type Registers
AArch64PMINTENCLR_EL1Performance Monitors Interrupt Enable Clear register
AArch64PMINTENSET_EL1Performance Monitors Interrupt Enable Set register
AArch64PMMIR_EL1Performance Monitors Machine Identification Register
AArch64PMOVSCLR_EL0Performance Monitors Overflow Flag Status Clear Register
AArch64PMOVSSET_EL0Performance Monitors Overflow Flag Status Set register
AArch64PMSELR_EL0Performance Monitors Event Counter Selection Register
AArch64PMSWINC_EL0Performance Monitors Software Increment register
AArch64PMUSERENR_EL0Performance Monitors User Enable Register
AArch64PMXEVCNTR_EL0Performance Monitors Selected Event Count Register
AArch64PMXEVTYPER_EL0Performance Monitors Selected Event Type Register
ExternalPMAUTHSTATUSPerformance Monitors Authentication Status register
ExternalPMCCFILTR_EL0Performance Monitors Cycle Counter Filter Register
ExternalPMCCNTR_EL0Performance Monitors Cycle Counter
ExternalPMCEID0Performance Monitors Common Event Identification register 0
ExternalPMCEID1Performance Monitors Common Event Identification register 1
ExternalPMCEID2Performance Monitors Common Event Identification register 2
ExternalPMCEID3Performance Monitors Common Event Identification register 3
ExternalPMCFGRPerformance Monitors Configuration Register
ExternalPMCID1SRCONTEXTIDR_EL1 Sample Register
ExternalPMCID2SRCONTEXTIDR_EL2 Sample Register
ExternalPMCIDR0Performance Monitors Component Identification Register 0
ExternalPMCIDR1Performance Monitors Component Identification Register 1
ExternalPMCIDR2Performance Monitors Component Identification Register 2
ExternalPMCIDR3Performance Monitors Component Identification Register 3
ExternalPMCNTENCLR_EL0Performance Monitors Count Enable Clear register
ExternalPMCNTENSET_EL0Performance Monitors Count Enable Set register
ExternalPMCR_EL0Performance Monitors Control Register
ExternalPMDEVAFF0Performance Monitors Device Affinity register 0
ExternalPMDEVAFF1Performance Monitors Device Affinity register 1
ExternalPMDEVARCHPerformance Monitors Device Architecture register
ExternalPMDEVIDPerformance Monitors Device ID register
ExternalPMDEVTYPEPerformance Monitors Device Type register
ExternalPMEVCNTR<n>_EL0Performance Monitors Event Count Registers
ExternalPMEVTYPER<n>_EL0Performance Monitors Event Type Registers
ExternalPMINTENCLR_EL1Performance Monitors Interrupt Enable Clear register
ExternalPMINTENSET_EL1Performance Monitors Interrupt Enable Set register
ExternalPMITCTRLPerformance Monitors Integration mode Control register
ExternalPMLARPerformance Monitors Lock Access Register
ExternalPMLSRPerformance Monitors Lock Status Register
ExternalPMOVSCLR_EL0Performance Monitors Overflow Flag Status Clear register
ExternalPMOVSSET_EL0Performance Monitors Overflow Flag Status Set register
ExternalPMPCSRProgram Counter Sample Register
ExternalPMPIDR0Performance Monitors Peripheral Identification Register 0
ExternalPMPIDR1Performance Monitors Peripheral Identification Register 1
ExternalPMPIDR2Performance Monitors Peripheral Identification Register 2
ExternalPMPIDR3Performance Monitors Peripheral Identification Register 3
ExternalPMPIDR4Performance Monitors Peripheral Identification Register 4
ExternalPMSWINC_EL0Performance Monitors Software Increment register
ExternalPMVIDSRVMID Sample Register

In the Reset functional group:

Exec stateNameDescription
AArch32HRMRHyp Reset Management Register
AArch32RMRReset Management Register
AArch32RVBARReset Vector Base Address Register
AArch64RMR_EL1Reset Management Register (EL1)
AArch64RMR_EL2Reset Management Register (EL2)
AArch64RMR_EL3Reset Management Register (EL3)
AArch64RVBAR_EL1Reset Vector Base Address Register (if EL2 and EL3 not implemented)
AArch64RVBAR_EL2Reset Vector Base Address Register (if EL3 not implemented)
AArch64RVBAR_EL3Reset Vector Base Address Register (if EL3 implemented)

In the Thread functional group:

Exec stateNameDescription
AArch32HTPIDRHyp Software Thread ID Register
AArch32TPIDRPRWPL1 Software Thread ID Register
AArch32TPIDRUROPL0 Read-Only Software Thread ID Register
AArch32TPIDRURWPL0 Read/Write Software Thread ID Register
AArch64SCXTNUM_EL0EL0 Read/Write Software Context Number
AArch64SCXTNUM_EL1EL1 Read/Write Software Context Number
AArch64SCXTNUM_EL2EL2 Read/Write Software Context Number
AArch64SCXTNUM_EL3EL3 Read/Write Software Context Number
AArch64TPIDRRO_EL0EL0 Read-Only Software Thread ID Register
AArch64TPIDR_EL0EL0 Read/Write Software Thread ID Register
AArch64TPIDR_EL1EL1 Software Thread ID Register
AArch64TPIDR_EL2EL2 Software Thread ID Register
AArch64TPIDR_EL3EL3 Software Thread ID Register

In the IMP DEF functional group:

Exec stateNameDescription
AArch32ACTLRAuxiliary Control Register
AArch32ACTLR2Auxiliary Control Register 2
AArch32ADFSRAuxiliary Data Fault Status Register
AArch32AIDRAuxiliary ID Register
AArch32AIFSRAuxiliary Instruction Fault Status Register
AArch32AMAIR0Auxiliary Memory Attribute Indirection Register 0
AArch32AMAIR1Auxiliary Memory Attribute Indirection Register 1
AArch32HACTLRHyp Auxiliary Control Register
AArch32HACTLR2Hyp Auxiliary Control Register 2
AArch32HADFSRHyp Auxiliary Data Fault Status Register
AArch32HAIFSRHyp Auxiliary Instruction Fault Status Register
AArch32HAMAIR0Hyp Auxiliary Memory Attribute Indirection Register 0
AArch32HAMAIR1Hyp Auxiliary Memory Attribute Indirection Register 1
AArch64ACTLR_EL1Auxiliary Control Register (EL1)
AArch64ACTLR_EL2Auxiliary Control Register (EL2)
AArch64ACTLR_EL3Auxiliary Control Register (EL3)
AArch64AFSR0_EL1Auxiliary Fault Status Register 0 (EL1)
AArch64AFSR0_EL2Auxiliary Fault Status Register 0 (EL2)
AArch64AFSR0_EL3Auxiliary Fault Status Register 0 (EL3)
AArch64AFSR1_EL1Auxiliary Fault Status Register 1 (EL1)
AArch64AFSR1_EL2Auxiliary Fault Status Register 1 (EL2)
AArch64AFSR1_EL3Auxiliary Fault Status Register 1 (EL3)
AArch64AIDR_EL1Auxiliary ID Register
AArch64AMAIR_EL1Auxiliary Memory Attribute Indirection Register (EL1)
AArch64AMAIR_EL2Auxiliary Memory Attribute Indirection Register (EL2)
AArch64AMAIR_EL3Auxiliary Memory Attribute Indirection Register (EL3)
AArch64HACR_EL2Hypervisor Auxiliary Control Register
AArch64S1_<op1>_<Cn>_<Cm>_<op2>IMPLEMENTATION DEFINED maintenance instructions
AArch64S3_<op1>_<Cn>_<Cm>_<op2>IMPLEMENTATION DEFINED registers

In the Timer functional group:

Exec stateNameDescription
AArch32CNTFRQCounter-timer Frequency register
AArch32CNTHPS_CTLCounter-timer Secure Physical Timer Control Register (EL2)
AArch32CNTHPS_CVALCounter-timer Secure Physical Timer CompareValue Register (EL2)
AArch32CNTHPS_TVALCounter-timer Secure Physical Timer TimerValue Register (EL2)
AArch32CNTHP_CTLCounter-timer Hyp Physical Timer Control register
AArch32CNTHVS_CTLCounter-timer Secure Virtual Timer Control Register (EL2)
AArch32CNTHVS_CVALCounter-timer Secure Virtual Timer CompareValue Register (EL2)
AArch32CNTHVS_TVALCounter-timer Secure Virtual Timer TimerValue Register (EL2)
AArch32CNTHV_CTLCounter-timer Virtual Timer Control register (EL2)
AArch32CNTHV_CVALCounter-timer Virtual Timer CompareValue register (EL2)
AArch32CNTHV_TVALCounter-timer Virtual Timer TimerValue register (EL2)
AArch32CNTKCTLCounter-timer Kernel Control register
AArch32CNTPCTCounter-timer Physical Count register
AArch32CNTP_CTLCounter-timer Physical Timer Control register
AArch32CNTP_CVALCounter-timer Physical Timer CompareValue register
AArch32CNTP_TVALCounter-timer Physical Timer TimerValue register
AArch32CNTVCTCounter-timer Virtual Count register
AArch32CNTV_CTLCounter-timer Virtual Timer Control register
AArch32CNTV_CVALCounter-timer Virtual Timer CompareValue register
AArch32CNTV_TVALCounter-timer Virtual Timer TimerValue register
AArch64CNTFRQ_EL0Counter-timer Frequency register
AArch64CNTHVS_CTL_EL2Counter-timer Secure Virtual Timer Control register (EL2)
AArch64CNTHVS_CVAL_EL2Counter-timer Secure Virtual Timer CompareValue register (EL2)
AArch64CNTHVS_TVAL_EL2Counter-timer Secure Virtual Timer TimerValue register (EL2)
AArch64CNTHV_CTL_EL2Counter-timer Virtual Timer Control register (EL2)
AArch64CNTHV_CVAL_EL2Counter-timer Virtual Timer CompareValue register (EL2)
AArch64CNTHV_TVAL_EL2Counter-timer Virtual Timer TimerValue Register (EL2)
AArch64CNTKCTL_EL1Counter-timer Kernel Control register
AArch64CNTPCT_EL0Counter-timer Physical Count register
AArch64CNTPS_CTL_EL1Counter-timer Physical Secure Timer Control register
AArch64CNTPS_CVAL_EL1Counter-timer Physical Secure Timer CompareValue register
AArch64CNTPS_TVAL_EL1Counter-timer Physical Secure Timer TimerValue register
AArch64CNTP_CTL_EL0Counter-timer Physical Timer Control register
AArch64CNTP_CVAL_EL0Counter-timer Physical Timer CompareValue register
AArch64CNTP_TVAL_EL0Counter-timer Physical Timer TimerValue register
AArch64CNTVCT_EL0Counter-timer Virtual Count register
AArch64CNTV_CTL_EL0Counter-timer Virtual Timer Control register
AArch64CNTV_CVAL_EL0Counter-timer Virtual Timer CompareValue register
AArch64CNTV_TVAL_EL0Counter-timer Virtual Timer TimerValue register
ExternalCNTACR<n>Counter-timer Access Control Registers
ExternalCNTCRCounter Control Register
ExternalCNTCVCounter Count Value register
ExternalCNTEL0ACRCounter-timer EL0 Access Control Register
ExternalCNTFID0Counter Frequency ID
ExternalCNTFID<n>Counter Frequency IDs, n > 0
ExternalCNTFRQCounter-timer Frequency
ExternalCNTIDCounter Identification Register
ExternalCNTNSARCounter-timer Non-secure Access Register
ExternalCNTPCTCounter-timer Physical Count
ExternalCNTP_CTLCounter-timer Physical Timer Control
ExternalCNTP_CVALCounter-timer Physical Timer CompareValue
ExternalCNTP_TVALCounter-timer Physical Timer TimerValue
ExternalCNTSCRCounter Scale Register
ExternalCNTSRCounter Status Register
ExternalCNTTIDRCounter-timer Timer ID Register
ExternalCNTVCTCounter-timer Virtual Count
ExternalCNTVOFFCounter-timer Virtual Offset
ExternalCNTVOFF<n>Counter-timer Virtual Offsets
ExternalCNTV_CTLCounter-timer Virtual Timer Control
ExternalCNTV_CVALCounter-timer Virtual Timer CompareValue
ExternalCNTV_TVALCounter-timer Virtual Timer TimerValue
ExternalCounterID<n>Counter ID registers

In the Debug functional group:

Exec stateNameDescription
AArch32DBGAUTHSTATUSDebug Authentication Status register
AArch32DBGBCR<n>Debug Breakpoint Control Registers
AArch32DBGBVR<n>Debug Breakpoint Value Registers
AArch32DBGBXVR<n>Debug Breakpoint Extended Value Registers
AArch32DBGCLAIMCLRDebug Claim Tag Clear register
AArch32DBGCLAIMSETDebug Claim Tag Set register
AArch32DBGDCCINTDCC Interrupt Enable Register
AArch32DBGDEVIDDebug Device ID register 0
AArch32DBGDEVID1Debug Device ID register 1
AArch32DBGDEVID2Debug Device ID register 2
AArch32DBGDIDRDebug ID Register
AArch32DBGDRARDebug ROM Address Register
AArch32DBGDSARDebug Self Address Register
AArch32DBGDSCRextDebug Status and Control Register, External View
AArch32DBGDSCRintDebug Status and Control Register, Internal View
AArch32DBGDTRRXextDebug OS Lock Data Transfer Register, Receive, External View
AArch32DBGDTRRXintDebug Data Transfer Register, Receive
AArch32DBGDTRTXextDebug OS Lock Data Transfer Register, Transmit
AArch32DBGDTRTXintDebug Data Transfer Register, Transmit
AArch32DBGOSDLRDebug OS Double Lock Register
AArch32DBGOSECCRDebug OS Lock Exception Catch Control Register
AArch32DBGOSLARDebug OS Lock Access Register
AArch32DBGOSLSRDebug OS Lock Status Register
AArch32DBGPRCRDebug Power Control Register
AArch32DBGVCRDebug Vector Catch Register
AArch32DBGWCR<n>Debug Watchpoint Control Registers
AArch32DBGWFARDebug Watchpoint Fault Address Register
AArch32DBGWVR<n>Debug Watchpoint Value Registers
AArch32TRFCRTrace Filter Control Register
AArch64DBGAUTHSTATUS_EL1Debug Authentication Status register
AArch64DBGBCR<n>_EL1Debug Breakpoint Control Registers
AArch64DBGBVR<n>_EL1Debug Breakpoint Value Registers
AArch64DBGCLAIMCLR_EL1Debug Claim Tag Clear register
AArch64DBGCLAIMSET_EL1Debug Claim Tag Set register
AArch64DBGDTRRX_EL0Debug Data Transfer Register, Receive
AArch64DBGDTRTX_EL0Debug Data Transfer Register, Transmit
AArch64DBGDTR_EL0Debug Data Transfer Register, half-duplex
AArch64DBGPRCR_EL1Debug Power Control Register
AArch64DBGVCR32_EL2Debug Vector Catch Register
AArch64DBGWCR<n>_EL1Debug Watchpoint Control Registers
AArch64DBGWVR<n>_EL1Debug Watchpoint Value Registers
AArch64DLR_EL0Debug Link Register
AArch64DSPSR_EL0Debug Saved Program Status Register
AArch64MDCCINT_EL1Monitor DCC Interrupt Enable Register
AArch64MDCCSR_EL0Monitor DCC Status Register
AArch64MDRAR_EL1Monitor Debug ROM Address Register
AArch64MDSCR_EL1Monitor Debug System Control Register
AArch64OSDLR_EL1OS Double Lock Register
AArch64OSDTRRX_EL1OS Lock Data Transfer Register, Receive
AArch64OSDTRTX_EL1OS Lock Data Transfer Register, Transmit
AArch64OSECCR_EL1OS Lock Exception Catch Control Register
AArch64OSLAR_EL1OS Lock Access Register
AArch64OSLSR_EL1OS Lock Status Register
AArch64TRFCR_EL1Trace Filter Control Register (EL1)
AArch64TRFCR_EL2Trace Filter Control Register (EL2)
ExternalDBGAUTHSTATUS_EL1Debug Authentication Status register
ExternalDBGBCR<n>_EL1Debug Breakpoint Control Registers
ExternalDBGBVR<n>_EL1Debug Breakpoint Value Registers
ExternalDBGCLAIMCLR_EL1Debug Claim Tag Clear register
ExternalDBGCLAIMSET_EL1Debug Claim Tag Set register
ExternalDBGDTRRX_EL0Debug Data Transfer Register, Receive
ExternalDBGDTRTX_EL0Debug Data Transfer Register, Transmit
ExternalDBGWCR<n>_EL1Debug Watchpoint Control Registers
ExternalDBGWVR<n>_EL1Debug Watchpoint Value Registers
ExternalEDACRExternal Debug Auxiliary Control Register
ExternalEDCIDR0External Debug Component Identification Register 0
ExternalEDCIDR1External Debug Component Identification Register 1
ExternalEDCIDR2External Debug Component Identification Register 2
ExternalEDCIDR3External Debug Component Identification Register 3
ExternalEDCIDSRExternal Debug Context ID Sample Register
ExternalEDDEVAFF0External Debug Device Affinity register 0
ExternalEDDEVAFF1External Debug Device Affinity register 1
ExternalEDDEVARCHExternal Debug Device Architecture register
ExternalEDDEVIDExternal Debug Device ID register 0
ExternalEDDEVID1External Debug Device ID register 1
ExternalEDDEVID2External Debug Device ID register 2
ExternalEDDEVTYPEExternal Debug Device Type register
ExternalEDECCRExternal Debug Exception Catch Control Register
ExternalEDECRExternal Debug Execution Control Register
ExternalEDESRExternal Debug Event Status Register
ExternalEDITCTRLExternal Debug Integration mode Control register
ExternalEDITRExternal Debug Instruction Transfer Register
ExternalEDLARExternal Debug Lock Access Register
ExternalEDLSRExternal Debug Lock Status Register
ExternalEDPCSRExternal Debug Program Counter Sample Register
ExternalEDPIDR0External Debug Peripheral Identification Register 0
ExternalEDPIDR1External Debug Peripheral Identification Register 1
ExternalEDPIDR2External Debug Peripheral Identification Register 2
ExternalEDPIDR3External Debug Peripheral Identification Register 3
ExternalEDPIDR4External Debug Peripheral Identification Register 4
ExternalEDPRCRExternal Debug Power/Reset Control Register
ExternalEDPRSRExternal Debug Processor Status Register
ExternalEDRCRExternal Debug Reserve Control Register
ExternalEDSCRExternal Debug Status and Control Register
ExternalEDVIDSRExternal Debug Virtual Context Sample Register
ExternalEDWARExternal Debug Watchpoint Address Register
ExternalOSLAR_EL1OS Lock Access Register

In the CTI functional group:

Exec stateNameDescription
ExternalASICCTLCTI External Multiplexer Control register
ExternalCTIAPPCLEARCTI Application Trigger Clear register
ExternalCTIAPPPULSECTI Application Pulse register
ExternalCTIAPPSETCTI Application Trigger Set register
ExternalCTIAUTHSTATUSCTI Authentication Status register
ExternalCTICHINSTATUSCTI Channel In Status register
ExternalCTICHOUTSTATUSCTI Channel Out Status register
ExternalCTICIDR0CTI Component Identification Register 0
ExternalCTICIDR1CTI Component Identification Register 1
ExternalCTICIDR2CTI Component Identification Register 2
ExternalCTICIDR3CTI Component Identification Register 3
ExternalCTICLAIMCLRCTI Claim Tag Clear register
ExternalCTICLAIMSETCTI Claim Tag Set register
ExternalCTICONTROLCTI Control register
ExternalCTIDEVAFF0CTI Device Affinity register 0
ExternalCTIDEVAFF1CTI Device Affinity register 1
ExternalCTIDEVARCHCTI Device Architecture register
ExternalCTIDEVCTLCTI Device Control register
ExternalCTIDEVIDCTI Device ID register 0
ExternalCTIDEVID1CTI Device ID register 1
ExternalCTIDEVID2CTI Device ID register 2
ExternalCTIDEVTYPECTI Device Type register
ExternalCTIGATECTI Channel Gate Enable register
ExternalCTIINEN<n>CTI Input Trigger to Output Channel Enable registers
ExternalCTIINTACKCTI Output Trigger Acknowledge register
ExternalCTIITCTRLCTI Integration mode Control register
ExternalCTILARCTI Lock Access Register
ExternalCTILSRCTI Lock Status Register
ExternalCTIOUTEN<n>CTI Input Channel to Output Trigger Enable registers
ExternalCTIPIDR0CTI Peripheral Identification Register 0
ExternalCTIPIDR1CTI Peripheral Identification Register 1
ExternalCTIPIDR2CTI Peripheral Identification Register 2
ExternalCTIPIDR3CTI Peripheral Identification Register 3
ExternalCTIPIDR4CTI Peripheral Identification Register 4
ExternalCTITRIGINSTATUSCTI Trigger In Status register
ExternalCTITRIGOUTSTATUSCTI Trigger Out Status register

In the Virt functional group:

Exec stateNameDescription
AArch32ATS1HRAddress Translate Stage 1 Hyp mode Read
AArch32ATS1HWAddress Translate Stage 1 Hyp mode Write
AArch32CNTHCTLCounter-timer Hyp Control register
AArch32CNTHP_CVALCounter-timer Hyp Physical CompareValue register
AArch32CNTHP_TVALCounter-timer Hyp Physical Timer TimerValue register
AArch32CNTVOFFCounter-timer Virtual Offset register
AArch32HACRHyp Auxiliary Configuration Register
AArch32HACTLRHyp Auxiliary Control Register
AArch32HACTLR2Hyp Auxiliary Control Register 2
AArch32HADFSRHyp Auxiliary Data Fault Status Register
AArch32HAIFSRHyp Auxiliary Instruction Fault Status Register
AArch32HAMAIR0Hyp Auxiliary Memory Attribute Indirection Register 0
AArch32HAMAIR1Hyp Auxiliary Memory Attribute Indirection Register 1
AArch32HCPTRHyp Architectural Feature Trap Register
AArch32HCRHyp Configuration Register
AArch32HCR2Hyp Configuration Register 2
AArch32HDCRHyp Debug Control Register
AArch32HDFARHyp Data Fault Address Register
AArch32HIFARHyp Instruction Fault Address Register
AArch32HMAIR0Hyp Memory Attribute Indirection Register 0
AArch32HMAIR1Hyp Memory Attribute Indirection Register 1
AArch32HPFARHyp IPA Fault Address Register
AArch32HRMRHyp Reset Management Register
AArch32HSCTLRHyp System Control Register
AArch32HSRHyp Syndrome Register
AArch32HSTRHyp System Trap Register
AArch32HTCRHyp Translation Control Register
AArch32HTPIDRHyp Software Thread ID Register
AArch32HTRFCRHyp Trace Filter Control Register
AArch32HTTBRHyp Translation Table Base Register
AArch32HVBARHyp Vector Base Address Register
AArch32ICC_HSREInterrupt Controller Hyp System Register Enable register
AArch32ICH_AP0R<n>Interrupt Controller Hyp Active Priorities Group 0 Registers
AArch32ICH_AP1R<n>Interrupt Controller Hyp Active Priorities Group 1 Registers
AArch32ICH_EISRInterrupt Controller End of Interrupt Status Register
AArch32ICH_ELRSRInterrupt Controller Empty List Register Status Register
AArch32ICH_HCRInterrupt Controller Hyp Control Register
AArch32ICH_LR<n>Interrupt Controller List Registers
AArch32ICH_LRC<n>Interrupt Controller List Registers
AArch32ICH_MISRInterrupt Controller Maintenance Interrupt State Register
AArch32ICH_VMCRInterrupt Controller Virtual Machine Control Register
AArch32ICH_VTRInterrupt Controller VGIC Type Register
AArch32TLBIALLHTLB Invalidate All, Hyp mode
AArch32TLBIALLHISTLB Invalidate All, Hyp mode, Inner Shareable
AArch32TLBIIPAS2TLB Invalidate by Intermediate Physical Address, Stage 2
AArch32TLBIIPAS2ISTLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
AArch32TLBIIPAS2LTLB Invalidate by Intermediate Physical Address, Stage 2, Last level
AArch32TLBIIPAS2LISTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
AArch32TLBIMVAHTLB Invalidate by VA, Hyp mode
AArch32TLBIMVAHISTLB Invalidate by VA, Hyp mode, Inner Shareable
AArch32TLBIMVALHTLB Invalidate by VA, Last level, Hyp mode
AArch32TLBIMVALHISTLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
AArch32VMPIDRVirtualization Multiprocessor ID Register
AArch32VPIDRVirtualization Processor ID Register
AArch32VTCRVirtualization Translation Control Register
AArch32VTTBRVirtualization Translation Table Base Register
AArch64ACTLR_EL2Auxiliary Control Register (EL2)
AArch64AFSR0_EL2Auxiliary Fault Status Register 0 (EL2)
AArch64AFSR1_EL2Auxiliary Fault Status Register 1 (EL2)
AArch64AMAIR_EL2Auxiliary Memory Attribute Indirection Register (EL2)
AArch64CNTHCTL_EL2Counter-timer Hypervisor Control register
AArch64CNTHPS_CTL_EL2Counter-timer Secure Physical Timer Control register (EL2)
AArch64CNTHPS_CVAL_EL2Counter-timer Secure Physical Timer CompareValue register (EL2)
AArch64CNTHPS_TVAL_EL2Counter-timer Secure Physical Timer TimerValue register (EL2)
AArch64CNTHP_CTL_EL2Counter-timer Hypervisor Physical Timer Control register
AArch64CNTHP_CVAL_EL2Counter-timer Physical Timer CompareValue register (EL2)
AArch64CNTHP_TVAL_EL2Counter-timer Physical Timer TimerValue register (EL2)
AArch64CNTVOFF_EL2Counter-timer Virtual Offset register
AArch64CPTR_EL2Architectural Feature Trap Register (EL2)
AArch64ESR_EL2Exception Syndrome Register (EL2)
AArch64FAR_EL2Fault Address Register (EL2)
AArch64HACR_EL2Hypervisor Auxiliary Control Register
AArch64HCR_EL2Hypervisor Configuration Register
AArch64HPFAR_EL2Hypervisor IPA Fault Address Register
AArch64HSTR_EL2Hypervisor System Trap Register
AArch64ICC_SRE_EL2Interrupt Controller System Register Enable register (EL2)
AArch64ICH_AP0R<n>_EL2Interrupt Controller Hyp Active Priorities Group 0 Registers
AArch64ICH_AP1R<n>_EL2Interrupt Controller Hyp Active Priorities Group 1 Registers
AArch64ICH_EISR_EL2Interrupt Controller End of Interrupt Status Register
AArch64ICH_ELRSR_EL2Interrupt Controller Empty List Register Status Register
AArch64ICH_HCR_EL2Interrupt Controller Hyp Control Register
AArch64ICH_LR<n>_EL2Interrupt Controller List Registers
AArch64ICH_MISR_EL2Interrupt Controller Maintenance Interrupt State Register
AArch64ICH_VMCR_EL2Interrupt Controller Virtual Machine Control Register
AArch64ICH_VTR_EL2Interrupt Controller VGIC Type Register
AArch64MAIR_EL2Memory Attribute Indirection Register (EL2)
AArch64MDCR_EL2Monitor Debug Configuration Register (EL2)
AArch64MPAMHCR_EL2MPAM Hypervisor Control Register (EL2)
AArch64MPAMVPM0_EL2MPAM Virtual PARTID Mapping Register 0
AArch64MPAMVPM1_EL2MPAM Virtual PARTID Mapping Register 1
AArch64MPAMVPM2_EL2MPAM Virtual PARTID Mapping Register 2
AArch64MPAMVPM3_EL2MPAM Virtual PARTID Mapping Register 3
AArch64MPAMVPM4_EL2MPAM Virtual PARTID Mapping Register 4
AArch64MPAMVPM5_EL2MPAM Virtual PARTID Mapping Register 5
AArch64MPAMVPM6_EL2MPAM Virtual PARTID Mapping Register 6
AArch64MPAMVPM7_EL2MPAM Virtual PARTID Mapping Register 7
AArch64MPAMVPMV_EL2MPAM Virtual Partition Mapping Valid Register
AArch64RMR_EL2Reset Management Register (EL2)
AArch64SCTLR_EL2System Control Register (EL2)
AArch64TCR_EL2Translation Control Register (EL2)
AArch64TLBI IPAS2E1TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
AArch64TLBI IPAS2E1ISTLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
AArch64TLBI IPAS2E1OSTLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
AArch64TLBI IPAS2LE1TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
AArch64TLBI IPAS2LE1ISTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
AArch64TLBI IPAS2LE1OSTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
AArch64TLBI RIPAS2E1TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1
AArch64TLBI RIPAS2E1ISTLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
AArch64TLBI RIPAS2E1OSTLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
AArch64TLBI RIPAS2LE1TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
AArch64TLBI RIPAS2LE1ISTLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
AArch64TLBI RIPAS2LE1OSTLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
AArch64TPIDR_EL2EL2 Software Thread ID Register
AArch64TTBR0_EL2Translation Table Base Register 0 (EL2)
AArch64TTBR1_EL2Translation Table Base Register 1 (EL2)
AArch64VBAR_EL2Vector Base Address Register (EL2)
AArch64VMPIDR_EL2Virtualization Multiprocessor ID Register
AArch64VPIDR_EL2Virtualization Processor ID Register
AArch64VTCR_EL2Virtualization Translation Control Register
AArch64VTTBR_EL2Virtualization Translation Table Base Register

In the Secure functional group:

Exec stateNameDescription
AArch32ICC_MCTLRInterrupt Controller Monitor Control Register
AArch32ICC_MSREInterrupt Controller Monitor System Register Enable register
AArch32MVBARMonitor Vector Base Address Register
AArch32NSACRNon-Secure Access Control Register
AArch32SCRSecure Configuration Register
AArch32SDCRSecure Debug Control Register
AArch32SDERSecure Debug Enable Register
AArch64ACTLR_EL3Auxiliary Control Register (EL3)
AArch64AFSR0_EL3Auxiliary Fault Status Register 0 (EL3)
AArch64AFSR1_EL3Auxiliary Fault Status Register 1 (EL3)
AArch64AMAIR_EL3Auxiliary Memory Attribute Indirection Register (EL3)
AArch64CPTR_EL3Architectural Feature Trap Register (EL3)
AArch64ICC_CTLR_EL3Interrupt Controller Control Register (EL3)
AArch64ICC_SRE_EL3Interrupt Controller System Register Enable register (EL3)
AArch64MDCR_EL3Monitor Debug Configuration Register (EL3)
AArch64SCR_EL3Secure Configuration Register
AArch64SDER32_EL3AArch32 Secure Debug Enable Register
AArch64VBAR_EL3Vector Base Address Register (EL3)

In the Float functional group:

Exec stateNameDescription
AArch32FPEXCFloating-Point Exception Control register
AArch32FPSCRFloating-Point Status and Control Register
AArch32FPSIDFloating-Point System ID register
AArch32MVFR0Media and VFP Feature Register 0
AArch32MVFR1Media and VFP Feature Register 1
AArch32MVFR2Media and VFP Feature Register 2
AArch64FPCRFloating-point Control Register
AArch64FPEXC32_EL2Floating-Point Exception Control register
AArch64FPSRFloating-point Status Register
AArch64MVFR0_EL1AArch32 Media and VFP Feature Register 0
AArch64MVFR1_EL1AArch32 Media and VFP Feature Register 1
AArch64MVFR2_EL1AArch32 Media and VFP Feature Register 2

In the Legacy functional group:

Exec stateNameDescription
AArch32CP15DMBData Memory Barrier System instruction
AArch32CP15DSBData Synchronization Barrier System instruction
AArch32CP15ISBInstruction Synchronization Barrier System instruction
AArch32FCSEIDRFCSE Process ID register
AArch32JIDRJazelle ID Register
AArch32JMCRJazelle Main Configuration Register
AArch32JOSCRJazelle OS Control Register

In the GIC functional group:

Exec stateNameDescription
AArch32ICC_AP0R<n>Interrupt Controller Active Priorities Group 0 Registers
AArch32ICC_AP1R<n>Interrupt Controller Active Priorities Group 1 Registers
AArch32ICC_ASGI1RInterrupt Controller Alias Software Generated Interrupt Group 1 Register
AArch32ICC_BPR0Interrupt Controller Binary Point Register 0
AArch32ICC_BPR1Interrupt Controller Binary Point Register 1
AArch32ICC_CTLRInterrupt Controller Control Register
AArch32ICC_DIRInterrupt Controller Deactivate Interrupt Register
AArch32ICC_EOIR0Interrupt Controller End Of Interrupt Register 0
AArch32ICC_EOIR1Interrupt Controller End Of Interrupt Register 1
AArch32ICC_HPPIR0Interrupt Controller Highest Priority Pending Interrupt Register 0
AArch32ICC_HPPIR1Interrupt Controller Highest Priority Pending Interrupt Register 1
AArch32ICC_HSREInterrupt Controller Hyp System Register Enable register
AArch32ICC_IAR0Interrupt Controller Interrupt Acknowledge Register 0
AArch32ICC_IAR1Interrupt Controller Interrupt Acknowledge Register 1
AArch32ICC_IGRPEN0Interrupt Controller Interrupt Group 0 Enable register
AArch32ICC_IGRPEN1Interrupt Controller Interrupt Group 1 Enable register
AArch32ICC_MCTLRInterrupt Controller Monitor Control Register
AArch32ICC_MGRPEN1Interrupt Controller Monitor Interrupt Group 1 Enable register
AArch32ICC_MSREInterrupt Controller Monitor System Register Enable register
AArch32ICC_PMRInterrupt Controller Interrupt Priority Mask Register
AArch32ICC_RPRInterrupt Controller Running Priority Register
AArch32ICC_SGI0RInterrupt Controller Software Generated Interrupt Group 0 Register
AArch32ICC_SGI1RInterrupt Controller Software Generated Interrupt Group 1 Register
AArch32ICC_SREInterrupt Controller System Register Enable register
AArch32ICH_AP0R<n>Interrupt Controller Hyp Active Priorities Group 0 Registers
AArch32ICH_AP1R<n>Interrupt Controller Hyp Active Priorities Group 1 Registers
AArch32ICH_EISRInterrupt Controller End of Interrupt Status Register
AArch32ICH_ELRSRInterrupt Controller Empty List Register Status Register
AArch32ICH_HCRInterrupt Controller Hyp Control Register
AArch32ICH_LR<n>Interrupt Controller List Registers
AArch32ICH_LRC<n>Interrupt Controller List Registers
AArch32ICH_MISRInterrupt Controller Maintenance Interrupt State Register
AArch32ICH_VMCRInterrupt Controller Virtual Machine Control Register
AArch32ICH_VTRInterrupt Controller VGIC Type Register
AArch32ICV_AP0R<n>Interrupt Controller Virtual Active Priorities Group 0 Registers
AArch32ICV_AP1R<n>Interrupt Controller Virtual Active Priorities Group 1 Registers
AArch32ICV_BPR0Interrupt Controller Virtual Binary Point Register 0
AArch32ICV_BPR1Interrupt Controller Virtual Binary Point Register 1
AArch32ICV_CTLRInterrupt Controller Virtual Control Register
AArch32ICV_DIRInterrupt Controller Deactivate Virtual Interrupt Register
AArch32ICV_EOIR0Interrupt Controller Virtual End Of Interrupt Register 0
AArch32ICV_EOIR1Interrupt Controller Virtual End Of Interrupt Register 1
AArch32ICV_HPPIR0Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
AArch32ICV_HPPIR1Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
AArch32ICV_IAR0Interrupt Controller Virtual Interrupt Acknowledge Register 0
AArch32ICV_IAR1Interrupt Controller Virtual Interrupt Acknowledge Register 1
AArch32ICV_IGRPEN0Interrupt Controller Virtual Interrupt Group 0 Enable register
AArch32ICV_IGRPEN1Interrupt Controller Virtual Interrupt Group 1 Enable register
AArch32ICV_PMRInterrupt Controller Virtual Interrupt Priority Mask Register
AArch32ICV_RPRInterrupt Controller Virtual Running Priority Register
AArch64ICC_AP0R<n>_EL1Interrupt Controller Active Priorities Group 0 Registers
AArch64ICC_AP1R<n>_EL1Interrupt Controller Active Priorities Group 1 Registers
AArch64ICC_ASGI1R_EL1Interrupt Controller Alias Software Generated Interrupt Group 1 Register
AArch64ICC_BPR0_EL1Interrupt Controller Binary Point Register 0
AArch64ICC_BPR1_EL1Interrupt Controller Binary Point Register 1
AArch64ICC_CTLR_EL1Interrupt Controller Control Register (EL1)
AArch64ICC_CTLR_EL3Interrupt Controller Control Register (EL3)
AArch64ICC_DIR_EL1Interrupt Controller Deactivate Interrupt Register
AArch64ICC_EOIR0_EL1Interrupt Controller End Of Interrupt Register 0
AArch64ICC_EOIR1_EL1Interrupt Controller End Of Interrupt Register 1
AArch64ICC_HPPIR0_EL1Interrupt Controller Highest Priority Pending Interrupt Register 0
AArch64ICC_HPPIR1_EL1Interrupt Controller Highest Priority Pending Interrupt Register 1
AArch64ICC_IAR0_EL1Interrupt Controller Interrupt Acknowledge Register 0
AArch64ICC_IAR1_EL1Interrupt Controller Interrupt Acknowledge Register 1
AArch64ICC_IGRPEN0_EL1Interrupt Controller Interrupt Group 0 Enable register
AArch64ICC_IGRPEN1_EL1Interrupt Controller Interrupt Group 1 Enable register
AArch64ICC_IGRPEN1_EL3Interrupt Controller Interrupt Group 1 Enable register (EL3)
AArch64ICC_PMR_EL1Interrupt Controller Interrupt Priority Mask Register
AArch64ICC_RPR_EL1Interrupt Controller Running Priority Register
AArch64ICC_SGI0R_EL1Interrupt Controller Software Generated Interrupt Group 0 Register
AArch64ICC_SGI1R_EL1Interrupt Controller Software Generated Interrupt Group 1 Register
AArch64ICC_SRE_EL1Interrupt Controller System Register Enable register (EL1)
AArch64ICC_SRE_EL2Interrupt Controller System Register Enable register (EL2)
AArch64ICC_SRE_EL3Interrupt Controller System Register Enable register (EL3)
AArch64ICH_AP0R<n>_EL2Interrupt Controller Hyp Active Priorities Group 0 Registers
AArch64ICH_AP1R<n>_EL2Interrupt Controller Hyp Active Priorities Group 1 Registers
AArch64ICH_EISR_EL2Interrupt Controller End of Interrupt Status Register
AArch64ICH_ELRSR_EL2Interrupt Controller Empty List Register Status Register
AArch64ICH_HCR_EL2Interrupt Controller Hyp Control Register
AArch64ICH_LR<n>_EL2Interrupt Controller List Registers
AArch64ICH_MISR_EL2Interrupt Controller Maintenance Interrupt State Register
AArch64ICH_VMCR_EL2Interrupt Controller Virtual Machine Control Register
AArch64ICH_VTR_EL2Interrupt Controller VGIC Type Register
AArch64ICV_AP0R<n>_EL1Interrupt Controller Virtual Active Priorities Group 0 Registers
AArch64ICV_AP1R<n>_EL1Interrupt Controller Virtual Active Priorities Group 1 Registers
AArch64ICV_BPR0_EL1Interrupt Controller Virtual Binary Point Register 0
AArch64ICV_BPR1_EL1Interrupt Controller Virtual Binary Point Register 1
AArch64ICV_CTLR_EL1Interrupt Controller Virtual Control Register
AArch64ICV_DIR_EL1Interrupt Controller Deactivate Virtual Interrupt Register
AArch64ICV_EOIR0_EL1Interrupt Controller Virtual End Of Interrupt Register 0
AArch64ICV_EOIR1_EL1Interrupt Controller Virtual End Of Interrupt Register 1
AArch64ICV_HPPIR0_EL1Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
AArch64ICV_HPPIR1_EL1Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
AArch64ICV_IAR0_EL1Interrupt Controller Virtual Interrupt Acknowledge Register 0
AArch64ICV_IAR1_EL1Interrupt Controller Virtual Interrupt Acknowledge Register 1
AArch64ICV_IGRPEN0_EL1Interrupt Controller Virtual Interrupt Group 0 Enable register
AArch64ICV_IGRPEN1_EL1Interrupt Controller Virtual Interrupt Group 1 Enable register
AArch64ICV_PMR_EL1Interrupt Controller Virtual Interrupt Priority Mask Register
AArch64ICV_RPR_EL1Interrupt Controller Virtual Running Priority Register

In the GICD functional group:

Exec stateNameDescription
ExternalGICD_CLRSPI_NSRClear Non-secure SPI Pending Register
ExternalGICD_CLRSPI_SRClear Secure SPI Pending Register
ExternalGICD_CPENDSGIR<n>SGI Clear-Pending Registers
ExternalGICD_CTLRDistributor Control Register
ExternalGICD_ICACTIVER<n>Interrupt Clear-Active Registers
ExternalGICD_ICACTIVER<n>EInterrupt Clear-Active Registers (extended SPI range)
ExternalGICD_ICENABLER<n>Interrupt Clear-Enable Registers
ExternalGICD_ICENABLER<n>EInterrupt Clear-Enable Registers
ExternalGICD_ICFGR<n>Interrupt Configuration Registers
ExternalGICD_ICFGR<n>EInterrupt Configuration Registers (Extended SPI Range)
ExternalGICD_ICPENDR<n>Interrupt Clear-Pending Registers
ExternalGICD_ICPENDR<n>EInterrupt Clear-Pending Registers (extended SPI range)
ExternalGICD_IGROUPR<n>Interrupt Group Registers
ExternalGICD_IGROUPR<n>EInterrupt Group Registers (extended SPI range)
ExternalGICD_IGRPMODR<n>Interrupt Group Modifier Registers
ExternalGICD_IGRPMODR<n>EInterrupt Group Modifier Registers (extended SPI range)
ExternalGICD_IIDRDistributor Implementer Identification Register
ExternalGICD_IPRIORITYR<n>Interrupt Priority Registers
ExternalGICD_IPRIORITYR<n>EHolds the priority of the corresponding interrupt for each extended SPI supported by the GIC.
ExternalGICD_IROUTER<n>Interrupt Routing Registers
ExternalGICD_IROUTER<n>EInterrupt Routing Registers (Extended SPI Range)
ExternalGICD_ISACTIVER<n>Interrupt Set-Active Registers
ExternalGICD_ISACTIVER<n>EInterrupt Set-Active Registers (extended SPI range)
ExternalGICD_ISENABLER<n>Interrupt Set-Enable Registers
ExternalGICD_ISENABLER<n>EInterrupt Set-Enable Registers
ExternalGICD_ISPENDR<n>Interrupt Set-Pending Registers
ExternalGICD_ISPENDR<n>EInterrupt Set-Pending Registers (extended SPI range)
ExternalGICD_ITARGETSR<n>Interrupt Processor Targets Registers
ExternalGICD_NSACR<n>Non-secure Access Control Registers
ExternalGICD_NSACR<n>ENon-secure Access Control Registers
ExternalGICD_SETSPI_NSRSet Non-secure SPI Pending Register
ExternalGICD_SETSPI_SRSet Secure SPI Pending Register
ExternalGICD_SGIRSoftware Generated Interrupt Register
ExternalGICD_SPENDSGIR<n>SGI Set-Pending Registers
ExternalGICD_STATUSRError Reporting Status Register
ExternalGICD_TYPERInterrupt Controller Type Register

In the GICR functional group:

Exec stateNameDescription
ExternalGICR_CLRLPIRClear LPI Pending Register
ExternalGICR_CTLRRedistributor Control Register
ExternalGICR_ICACTIVER0Interrupt Clear-Active Register 0
ExternalGICR_ICACTIVER<n>EInterrupt Clear-Active Registers
ExternalGICR_ICENABLER0Interrupt Clear-Enable Register 0
ExternalGICR_ICENABLER<n>EInterrupt Clear-Enable Registers
ExternalGICR_ICFGR0Interrupt Configuration Register 0
ExternalGICR_ICFGR1Interrupt Configuration Register 1
ExternalGICR_ICFGR<n>EInterrupt configuration registers
ExternalGICR_ICPENDR0Interrupt Clear-Pending Register 0
ExternalGICR_ICPENDR<n>EInterrupt Clear-Pending Registers
ExternalGICR_IGROUPR0Interrupt Group Register 0
ExternalGICR_IGROUPR<n>EInterrupt Group Registers
ExternalGICR_IGRPMODR0Interrupt Group Modifier Register 0
ExternalGICR_IGRPMODR<n>EInterrupt Group Modifier Registers
ExternalGICR_IIDRRedistributor Implementer Identification Register
ExternalGICR_INVALLRRedistributor Invalidate All Register
ExternalGICR_INVLPIRRedistributor Invalidate LPI Register
ExternalGICR_IPRIORITYR<n>Interrupt Priority Registers
ExternalGICR_IPRIORITYR<n>EInterrupt Priority Registers (extended PPI range)
ExternalGICR_ISACTIVER0Interrupt Set-Active Register 0
ExternalGICR_ISACTIVER<n>EInterrupt Set-Active Registers
ExternalGICR_ISENABLER0Interrupt Set-Enable Register 0
ExternalGICR_ISENABLER<n>EInterrupt Set-Enable Registers
ExternalGICR_ISPENDR0Interrupt Set-Pending Register 0
ExternalGICR_ISPENDR<n>EInterrupt Set-Pending Registers
ExternalGICR_MPAMIDRReport maximum PARTID and PMG Register
ExternalGICR_NSACRNon-secure Access Control Register
ExternalGICR_PARTIDRSet PARTID and PMG Register
ExternalGICR_PENDBASERRedistributor LPI Pending Table Base Address Register
ExternalGICR_PROPBASERRedistributor Properties Base Address Register
ExternalGICR_SETLPIRSet LPI Pending Register
ExternalGICR_STATUSRError Reporting Status Register
ExternalGICR_SYNCRRedistributor Synchronize Register
ExternalGICR_TYPERRedistributor Type Register
ExternalGICR_VPENDBASERVirtual Redistributor LPI Pending Table Base Address Register
ExternalGICR_VPROPBASERVirtual Redistributor Properties Base Address Register
ExternalGICR_WAKERRedistributor Wake Register

In the GICC functional group:

Exec stateNameDescription
ExternalGICC_ABPRCPU Interface Aliased Binary Point Register
ExternalGICC_AEOIRCPU Interface Aliased End Of Interrupt Register
ExternalGICC_AHPPIRCPU Interface Aliased Highest Priority Pending Interrupt Register
ExternalGICC_AIARCPU Interface Aliased Interrupt Acknowledge Register
ExternalGICC_APR<n>CPU Interface Active Priorities Registers
ExternalGICC_BPRCPU Interface Binary Point Register
ExternalGICC_CTLRCPU Interface Control Register
ExternalGICC_DIRCPU Interface Deactivate Interrupt Register
ExternalGICC_EOIRCPU Interface End Of Interrupt Register
ExternalGICC_HPPIRCPU Interface Highest Priority Pending Interrupt Register
ExternalGICC_IARCPU Interface Interrupt Acknowledge Register
ExternalGICC_IIDRCPU Interface Identification Register
ExternalGICC_NSAPR<n>CPU Interface Non-secure Active Priorities Registers
ExternalGICC_PMRCPU Interface Priority Mask Register
ExternalGICC_RPRCPU Interface Running Priority Register
ExternalGICC_STATUSRCPU Interface Status Register

In the GICV functional group:

Exec stateNameDescription
ExternalGICV_ABPRVirtual Machine Aliased Binary Point Register
ExternalGICV_AEOIRVirtual Machine Aliased End Of Interrupt Register
ExternalGICV_AHPPIRVirtual Machine Aliased Highest Priority Pending Interrupt Register
ExternalGICV_AIARVirtual Machine Aliased Interrupt Acknowledge Register
ExternalGICV_APR<n>Virtual Machine Active Priorities Registers
ExternalGICV_BPRVirtual Machine Binary Point Register
ExternalGICV_CTLRVirtual Machine Control Register
ExternalGICV_DIRVirtual Machine Deactivate Interrupt Register
ExternalGICV_EOIRVirtual Machine End Of Interrupt Register
ExternalGICV_HPPIRVirtual Machine Highest Priority Pending Interrupt Register
ExternalGICV_IARVirtual Machine Interrupt Acknowledge Register
ExternalGICV_IIDRVirtual Machine CPU Interface Identification Register
ExternalGICV_PMRVirtual Machine Priority Mask Register
ExternalGICV_RPRVirtual Machine Running Priority Register
ExternalGICV_STATUSRVirtual Machine Error Reporting Status Register

In the GICH functional group:

Exec stateNameDescription
ExternalGICH_APR<n>Active Priorities Registers
ExternalGICH_EISREnd Interrupt Status Register
ExternalGICH_ELRSREmpty List Register Status Register
ExternalGICH_HCRHypervisor Control Register
ExternalGICH_LR<n>List Registers
ExternalGICH_MISRMaintenance Interrupt Status Register
ExternalGICH_VMCRVirtual Machine Control Register
ExternalGICH_VTRVirtual Type Register

In the GITS functional group:

Exec stateNameDescription
ExternalGITS_BASER<n>ITS Translation Table Descriptors
ExternalGITS_CBASERITS Command Queue Descriptor
ExternalGITS_CREADRITS Read Register
ExternalGITS_CTLRITS Control Register
ExternalGITS_CWRITERITS Write Register
ExternalGITS_IIDRITS Identification Register
ExternalGITS_MPAMIDRReport maximum PARTID and PMG Register
ExternalGITS_PARTIDRSet PARTID and PMG Register
ExternalGITS_TRANSLATERITS Translation Register
ExternalGITS_TYPERITS Type Register

In the RAS functional group:

Exec stateNameDescription
AArch32DISRDeferred Interrupt Status Register
AArch32ERRIDRError Record ID Register
AArch32ERRSELRError Record Select Register
AArch32ERXADDRSelected Error Record Address Register
AArch32ERXADDR2Selected Error Record Address Register 2
AArch32ERXCTLRSelected Error Record Control Register
AArch32ERXCTLR2Selected Error Record Control Register 2
AArch32ERXFRSelected Error Record Feature Register
AArch32ERXFR2Selected Error Record Feature Register 2
AArch32ERXMISC0 Selected Error Record Miscellaneous Register 0
AArch32ERXMISC1 Selected Error Record Miscellaneous Register 1
AArch32ERXMISC2 Selected Error Record Miscellaneous Register 2
AArch32ERXMISC3 Selected Error Record Miscellaneous Register 3
AArch32ERXMISC4 Selected Error Record Miscellaneous Register 4
AArch32ERXMISC5 Selected Error Record Miscellaneous Register 5
AArch32ERXMISC6 Selected Error Record Miscellaneous Register 6
AArch32ERXMISC7 Selected Error Record Miscellaneous Register 7
AArch32ERXSTATUSSelected Error Record Primary Status Register
AArch32VDFSRVirtual SError Exception Syndrome Register
AArch32VDISRVirtual Deferred Interrupt Status Register
AArch64DISR_EL1Deferred Interrupt Status Register
AArch64ERRIDR_EL1Error Record ID Register
AArch64ERRSELR_EL1Error Record Select Register
AArch64ERXADDR_EL1Selected Error Record Address Register
AArch64ERXCTLR_EL1Selected Error Record Control Register
AArch64ERXFR_EL1Selected Error Record Feature Register
AArch64ERXMISC0_EL1Selected Error Record Miscellaneous Register 0
AArch64ERXMISC1_EL1Selected Error Record Miscellaneous Register 1
AArch64ERXMISC2_EL1Selected Error Record Miscellaneous Register 2
AArch64ERXMISC3_EL1Selected Error Record Miscellaneous Register 3
AArch64ERXPFGCDN_EL1Selected Pseudo-fault Generation Countdown Register
AArch64ERXPFGCTL_EL1Selected Pseudo-fault Generation Control Register
AArch64ERXPFGF_EL1Selected Pseudo-fault Generation Feature Register
AArch64ERXSTATUS_EL1Selected Error Record Primary Status Register
AArch64VDISR_EL2Virtual Deferred Interrupt Status Register
AArch64VSESR_EL2Virtual SErrorDeferred ExceptionInterrupt SyndromeStatus Register
ExternalERR<n>ADDRError Record Address Register
ExternalERR<n>CTLRError Record Control Register
ExternalERR<n>FRError Record Feature Register
ExternalERR<n>MISC0Error Record Miscellaneous Register 0
ExternalERR<n>MISC1Error Record Miscellaneous Register 1
ExternalERR<n>MISC2Error Record Miscellaneous Register 2
ExternalERR<n>MISC3Error Record Miscellaneous Register 3
ExternalERR<n>PFGCDNPseudo-fault Generation Countdown Register
ExternalERR<n>PFGCTLPseudo-fault Generation Control Register
ExternalERR<n>PFGFPseudo-fault Generation Feature Register
ExternalERR<n>STATUSError Record Primary Status Register
ExternalERRCIDR0Component Identification Register 0
ExternalERRCIDR1Component Identification Register 1
ExternalERRCIDR2Component Identification Register 2
ExternalERRCIDR3Component Identification Register 3
ExternalERRCRICR0Critical Error Interrupt Configuration Register 0
ExternalERRCRICR1Critical Error Interrupt Configuration Register 1
ExternalERRCRICR2Critical Error Interrupt Configuration Register 2
ExternalERRDEVAFFDevice Affinity Register
ExternalERRDEVARCHDevice Architecture Register
ExternalERRDEVIDDevice Configuration Register
ExternalERRERICR0Error Recovery Interrupt Configuration Register 0
ExternalERRERICR1Error Recovery Interrupt Configuration Register 1
ExternalERRERICR2Error Recovery Interrupt Configuration Register 2
ExternalERRFHICR0Fault-Handling Interrupt Configuration Register 0
ExternalERRFHICR1Fault-Handling Interrupt Configuration Register 1
ExternalERRFHICR2Fault-Handling Interrupt Configuration Register 2
ExternalERRGSRError Group Status Register
ExternalERRIIDRImplementation Identification Register
ExternalERRIRQCR<n>Generic Error Interrupt Configuration Register
ExternalERRIRQSRError Interrupt Status Register
ExternalERRPIDR0Peripheral Identification Register 0
ExternalERRPIDR1Peripheral Identification Register 1
ExternalERRPIDR2Peripheral Identification Register 2
ExternalERRPIDR3Peripheral Identification Register 3
ExternalERRPIDR4Peripheral Identification Register 4

In the Ptr Auth functional group:

Exec stateNameDescription
AArch64APDAKeyHi_EL1Pointer Authentication Key A for Data (bits[127:64])
AArch64APDAKeyLo_EL1Pointer Authentication Key A for Data (bits[63:0])
AArch64APDBKeyHi_EL1Pointer Authentication Key B for Data (bits[127:64])
AArch64APDBKeyLo_EL1Pointer Authentication Key B for Data (bits[63:0])
AArch64APGAKeyHi_EL1Pointer Authentication Key A for Code (bits[127:64])
AArch64APGAKeyLo_EL1Pointer Authentication Key A for Code (bits[63:0])
AArch64APIAKeyHi_EL1Pointer Authentication Key A for Instruction (bits[127:64])
AArch64APIAKeyLo_EL1Pointer Authentication Key A for Instruction (bits[63:0])
AArch64APIBKeyHi_EL1Pointer Authentication Key B for Instruction (bits[127:64])
AArch64APIBKeyLo_EL1Pointer Authentication Key B for Instruction (bits[63:0])

In the Resource monitoring configuration functional group:

Exec stateNameDescription
ExternalMSMON_CAPT_EVNTMPAM Capture Event Generation Register
ExternalMSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register
ExternalMSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register
ExternalMSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
ExternalMSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register
ExternalMSMON_CFG_MON_SELMPAM Partion Configuration Selection Register
ExternalMSMON_CSUMPAM Cache Storage Usage Monitor Register
ExternalMSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture Register
ExternalMSMON_MBWUMPAM Memory Bandwdith Usage Monitor Register
ExternalMSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture Register

2713/0312/20192018 2116:5943

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