The TLBIALLNSNHIS characteristics are:
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk that would be required for stage 1 or stage 2 of the Non-secure PL1&0 translation regime, regardless of the associated VMID.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
TLBIALLNSNHIS is a 32-bit System instruction.
TLBIALLNSNHIS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
Accesses to this instruction use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b100 | 0b100 | 0b1000 | 0b1111 | 0b0011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBIALLNSNHIS(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then UNDEFINED; else TLBIALLNSNHIS();
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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