The GICH_APR<n> characteristics are:
These registers track which preemption levels are active in the virtual CPU interface, and indicate the current active priority. Corresponding bits are set to 1 in this register when an interrupt is acknowledged, based on GICH_LR<n>.Priority, and the least significant bit set is cleared on EOI.
Some or all RW fields of this register have defined reset values.
This register is available when the GIC implementation supports interrupt virtualization.
The number of registers required depends on how many bits are implemented in GICH_LR<n>.Priority:
Unimplemented registers are RAZ/WI.
GICH_APR<n> is a 32-bit register.
The GICH_APR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Active priorities. Possible values of each bit are:
P<x> | Meaning |
---|---|
0b0 |
There is no interrupt active at the priority corresponding to that bit. |
0b1 |
There is an interrupt active at the priority corresponding to that bit. |
The correspondence between priorities and bits depends on the number of bits of priority that are implemented.
If 5 bits of priority are implemented (bits [7:3] of priority), then there are 32 priority groups, and the active state of these priorities are held in GICH_APR0 in the bits corresponding to Priority[7:3].
If 6 bits of priority are implemented (bits [7:2] of priority), then there are 64 priority groups, and:
If 7 bits of priority are implemented (bits [7:1] of priority), then there are 128 priority groups, and:
This field resets to 0.
These registers are used only when System register access is not enabled. When System register access is enabled the following registers provide equivalent functionality:
Component | Offset | Instance |
---|---|---|
GIC Virtual interface control | 0x00F0 + 4n | GICH_APR<n> |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.