The ERRIIDR characteristics are:
Defines the implementer of the component.
Implementation of this register is OPTIONAL.
This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERRIIDR are RES0.
ERRIIDR is a 32-bit register.
The ERRIIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Variant | Revision | Implementer |
IMPLEMENTATION DEFINED.
Part number, bits [11:0]. The part number is selected by the designer of the component.
If ERRPIDR0 and ERRPIDR1 are implemented, ERRPIDR0.PART_0 matches bits [7:0] of ERRIIDR.ProductID and ERRPIDR1.PART_1 matches bits [11:8] of ERRIIDR.ProductID.
IMPLEMENTATION DEFINED.
Component major revision.
This field distinguishes product variants or major revisions of the product.
If ERRPIDR2 is implemented, ERRPIDR2.REVISION matches ERRIIDR.Variant.
IMPLEMENTATION DEFINED.
Component minor revision.
This field distinguishes minor revisions of the product.
If ERRPIDR3 is implemented, ERRPIDR3.REVAND matches ERRIIDR.Revision.
IMPLEMENTATION DEFINED.
Contains the JEP106 code of the company that implemented the RAS component. For an Arm implementation, this field has the value 0x43B.
Bits [11:8] contain the JEP106 continuation code of the implementer, and bits [6:0] contain the JEP106 identity code of the implementer. Bit 7 is RES0.
If ERRPIDR4 is implemented, ERRPIDR2 is implemented, and ERRPIDR1 is implemented, ERRPIDR4.DES_2 matches bits [11:8] of ERRIIDR.Implementer, ERRPIDR2.DES_1 matches bits [6:4] of ERRIIDR.Implementer, and ERRPIDR1.DES_0 matches bits [3:0] of ERRIIDR.Implementer.
Component | Offset |
---|---|
RAS | 0xE10 |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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