The CTIDEVCTL characteristics are:
Provides target-specific device controls
CTIDEVCTL is in the Debug power domain. Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
This register is present only when ARMv8.3-DoPD is implemented. Otherwise, direct accesses to CTIDEVCTL are RES0.
CTIDEVCTL is a 32-bit register.
The CTIDEVCTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RCE | OSUCE |
Reserved, RES0.
Reset Catch Enable.
RCE | Meaning |
---|---|
0b0 |
Reset Catch debug event disabled. |
0b1 |
Reset Catch debug event enabled. |
On a External debug reset, this field resets to 0.
OS Unlock Catch Enable
OSUCE | Meaning |
---|---|
0b0 |
OS Unlock Catch debug event disabled. |
0b1 |
OS Unlock Catch debug event enabled. |
On a External debug reset, this field resets to 0.
Component | Offset | Instance |
---|---|---|
CTI | 0x150 | CTIDEVCTL |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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