The MPAMF_AIDR characteristics are:
The MPAMF_AIDR is a 32-bit read-only register that identifies the version of the MPAM architecture that this MSC implements.
Note: The following values are defined for bits [7:0]:
The power domain of MPAMF_AIDR is IMPLEMENTATION DEFINED.
MPAMF_AIDR is a 32-bit register.
The MPAMF_AIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ArchMajorRev | ArchMinorRev |
Reserved, RES0.
Major revision of the MPAM architecture implemented by the MSC.
Minor revision of the MPAM architecture implemented by the MSC.
This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.
MPAMF_AIDR must be accessible from the Non-secure and Secure address maps.
MPAMF_AIDR must be shared between the Secure and Non-secure address maps.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_s | 0x0020 | MPAMF_AIDR_s |
Access on this interface is RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_ns | 0x0020 | MPAMF_AIDR_ns |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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