TLBI ASIDE1IS, TLB Invalidate by ASID, EL1, Inner Shareable

The TLBI ASIDE1IS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.

Configuration

Attributes

TLBI ASIDE1IS is a 64-bit System instruction.

Field descriptions

The TLBI ASIDE1IS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDRES0
RES0
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.

If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0.

Bits [47:0]

Reserved, RES0.

Executing the TLBI ASIDE1IS instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1IS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00110b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1IS(X[t]);




27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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