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VBAR_EL1, Vector Base Address Register (EL1)

The VBAR_EL1 characteristics are:

Purpose

Holds the vector base address for any exception that is taken to EL1.

Configuration

AArch64 System register VBAR_EL1 bits [31:0] are architecturally mapped to AArch32 System register VBAR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VBAR_EL1 is a 64-bit register.

Field descriptions

The VBAR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Vector Base Address
Vector Base Address0 0 0 0 0 0 0 0 0 0 0 RES0
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL1.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

This field resets to an architecturally UNKNOWN value.

Bits [10:0]

Reserved, RES0.

Accessing the VBAR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic VBAR_EL1 or VBAR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, VBAR_EL1

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b11000b00000b000
0b110b11000b0000b0000b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x250]; else return VBAR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return VBAR_EL2; else return VBAR_EL1; elsif PSTATE.EL == EL3 then return VBAR_EL1;

MSR VBAR_EL1, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b11000b00000b000
0b110b11000b0000b0000b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x250] = X[t]; else VBAR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then VBAR_EL2 = X[t]; else VBAR_EL1 = X[t]; elsif PSTATE.EL == EL3 then VBAR_EL1 = X[t];

MRS <Xt>, VBAR_EL12

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b1010b11000b00000b000
0b110b11000b1010b0000b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x250]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then return VBAR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then return VBAR_EL1; else else UNDEFINED;

MSR VBAR_EL12, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b1010b11000b00000b000
0b110b11000b1010b0000b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x250] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then VBAR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then VBAR_EL1 = X[t]; else else UNDEFINED;




2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009

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