The DBGWCR<n>_EL1 characteristics are:
Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>_EL1.
AArch64 System register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGWCR<n>[31:0] .
AArch64 System register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to External register DBGWCR<n>_EL1[31:0] .
If breakpoint n is not implemented then this register is unallocated.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
DBGWCR<n>_EL1 is a 64-bit register.
The DBGWCR<n>_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E | |||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Address mask. Only objects up to 2GB can be watched using a single mask.
MASK | Meaning |
---|---|
0b00000 |
No mask. |
0b00001 |
Reserved. |
0b00010 |
Reserved. |
If programmed with a reserved value, a watchpoint must behave as if either:
Software must not rely on this property because the behavior of reserved values might change in a future revision of the architecture.
Other values mask the corresponding number of address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Watchpoint type. Possible values are:
WT | Meaning |
---|---|
0b0 |
Unlinked data address match. |
0b1 |
Linked data address match. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.
For more information, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug), and 'Reserved DBGBCR<n>_EL1.{SSC, HMC, PMC} values' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched.
BAS | Description |
---|---|
xxxxxxx1 | Match byte at DBGWVR<n>_EL1 |
xxxxxx1x | Match byte at DBGWVR<n>_EL1 + 1 |
xxxxx1xx | Match byte at DBGWVR<n>_EL1 + 2 |
xxxx1xxx | Match byte at DBGWVR<n>_EL1 + 3 |
In cases where DBGWVR<n>_EL1 addresses a double-word:
BAS | Description, if DBGWVR<n>_EL1[2] == 0 |
---|---|
xxx1xxxx | Match byte at DBGWVR<n>_EL1 + 4 |
xx1xxxxx | Match byte at DBGWVR<n>_EL1 + 5 |
x1xxxxxx | Match byte at DBGWVR<n>_EL1 + 6 |
1xxxxxxx | Match byte at DBGWVR<n>_EL1 + 7 |
If DBGWVR<n>_EL1[2] == 1, only BAS[3:0] are used and BAS[7:4] are ignored. Arm deprecates setting DBGWVR<n>_EL1[2] == 1.
The valid values for BAS are non-zero binary numbers all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>_EL1.BAS values' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:
LSC | Meaning |
---|---|
0b01 |
Match instructions that load from a watchpointed address. |
0b10 |
Match instructions that store to a watchpointed address. |
0b11 |
Match instructions that load from or store to a watchpointed address. |
All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug).
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Enable watchpoint n. Possible values are:
E | Meaning |
---|---|
0b0 |
Watchpoint disabled. |
0b1 |
Watchpoint enabled. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL3 then if !ELUsingAArch32(EL1) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t];
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.