The GICV_BPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.
This register corresponds to GICC_BPR in the physical CPU interface.
GICH_LR<n>.Group determines whether a virtual interrupt is Group 0 or Group 1.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when the GIC implementation supports interrupt virtualization.
When GICV_CTLR.CBPR == 1, this register determines interrupt preemption for both Group 0 and Group 1 interrupts.
GICV_BPR is a 32-bit register.
The GICV_BPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Binary_Point |
Reserved, RES0.
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field.
For information about how this field determines the interrupt priority bits assigned to the group priority field, see Priority grouping for Group 0 interrupts, or Group 1 interrupts when CBPR==1
This field resets to an architecturally UNKNOWN value.
The Binary_Point field of this register is aliased to GICH_VMCR.VBPR0.
This register is used only when System register access is not enabled. When System register access is enabled:
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x0008 | GICV_BPR |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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