The TLBI VMALLS12E1OS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 0, then
The entry would be required to translate an address using the Secure EL1&0 translation regime.
If ARMv8.4-SecEL2 is implemented and enabled, the entry would be used with the current VMID.
If SCR_EL3.NS is 1, then:
The entry would be required to translate an address using the Non-secure EL1&0 translation regime.
If Non-secure EL2 is implemented, the entry would be used with the current VMID.
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
When a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI VMALLS12E1OS are UNDEFINED.
TLBI VMALLS12E1OS is a 64-bit System instruction.
TLBI VMALLS12E1OS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0001 | 0b110 | 0b11111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12E1OS(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALLE1OS(); else TLBI_VMALLS12E1OS();
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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