The VBAR_EL2 characteristics are:
Holds the vector base address for any exception that is taken to EL2.
AArch64 System register VBAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HVBAR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
VBAR_EL2 is a 64-bit register.
The VBAR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Vector Base Address | |||||||||||||||||||||||||||||||
Vector Base Address | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Vector Base Address. Base address of the exception vectors for exceptions taken to EL2.
If the implementation does not support ARMv8.2-LVA, then:
If the implementation supports ARMv8.2-LVA, then:
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic VBAR_EL2 or VBAR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b100 | 0b000 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return VBAR_EL2; elsif PSTATE.EL == EL3 then return VBAR_EL2;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b100 | 0b000 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VBAR_EL2 = X[t]; elsif PSTATE.EL == EL3 then VBAR_EL2 = X[t];
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b000 | 0b000 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x250]; else return VBAR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return VBAR_EL2; else return VBAR_EL1; elsif PSTATE.EL == EL3 then return VBAR_EL1;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b000 | 0b000 | 0b0000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x250] = X[t]; else VBAR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then VBAR_EL2 = X[t]; else VBAR_EL1 = X[t]; elsif PSTATE.EL == EL3 then VBAR_EL1 = X[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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