The GICC_ABPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.
RW fields in this register reset to architecturally UNKNOWN values.
In systems that support two Security states:
The reset value of this register is defined as (minimum GICC_BPR.Binary_Point + 1), resulting in a permitted range of 0x1-0x4.
The GICC_ABPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Binary_Point |
Reserved, RES0.
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:
This field resets to an architecturally UNKNOWN value.
This register is used only when System register access is not enabled. When System register access is enabled, the System registers ICC_BPR0_EL1 and ICC_BPR1_EL1 provide equivalent functionality.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x001C | GICC_ABPR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.