TFSRE0_EL1, Tag Fail Status Register (EL0).

The TFSRE0_EL1 characteristics are:

Purpose

Holds accumulated Tag Check Fails occurring in EL0 which are not taken precisely.

Configuration

This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to TFSRE0_EL1 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TFSRE0_EL1 is a 64-bit register.

Field descriptions

The TFSRE0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000000000000000000000000000TF1TF0
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

TF1, bit [1]

Tag Check Fail. Asynchronously set to 1 when a Tag Check fail using a virtual address with bit<55>==0b1 occurs.

This field resets to an architecturally UNKNOWN value.

TF0, bit [0]

Tag Check Fail. Asynchronously set to 1 when a Tag Check fail using a virtual address with bit<55>==0b0 occurs.

This field resets to an architecturally UNKNOWN value.

Accessing the TFSRE0_EL1

Accesses to this register use the following encodings:

MRS <Xt>, TFSRE0_EL1

op0CRnop1op2CRm
0b110b01100b0000b0010b0110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return TFSRE0_EL1; elsif PSTATE.EL == EL2 then return TFSRE0_EL1; elsif PSTATE.EL == EL3 then return TFSRE0_EL1;

MSR TFSRE0_EL1, <Xt>

op0CRnop1op2CRm
0b110b01100b0000b0010b0110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then TFSRE0_EL1 = X[t]; elsif PSTATE.EL == EL2 then TFSRE0_EL1 = X[t]; elsif PSTATE.EL == EL3 then TFSRE0_EL1 = X[t];




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.