The TCO characteristics are:
When ARMv8.5-MemTag is implemented, this register allows tag checks to be disabled globally.
This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to TCO are UNDEFINED.
TCO is a 64-bit register.
The TCO bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | TCO | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Allows memory tag checks to be globally disabled.
TCO | Meaning |
---|---|
0b0 |
Loads and Stores are not affected by this control. |
0b1 |
Loads and Stores are unchecked. |
Reserved, RES0.
Reserved, RES0.
For details on the operation of the MSR (immediate) accessor, see MSR (immediate).
Accesses to this register use the following encodings:
CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|
0b0100 | 0b11 | 0b011 | 0b111 | 0b0010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return Zeros(38):PSTATE.TCO:Zeros(25); elsif PSTATE.EL == EL2 then return Zeros(38):PSTATE.TCO:Zeros(25); elsif PSTATE.EL == EL3 then return Zeros(38):PSTATE.TCO:Zeros(25);
CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|
0b0100 | 0b11 | 0b011 | 0b111 | 0b0010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.TCO = X[t]<25>; elsif PSTATE.EL == EL2 then PSTATE.TCO = X[t]<25>; elsif PSTATE.EL == EL3 then PSTATE.TCO = X[t]<25>;
CRn | op0 | op1 | op2 |
---|---|---|---|
0b0100 | 0b00 | 0b011 | 0b100 |
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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