AT S1E0R, Address Translate Stage 1 EL0 Read

The AT S1E0R characteristics are:

Purpose

Performs stage 1 address translation from EL0, with permissions as if reading from the given virtual address from EL0, using the following translation regime:

Configuration

Attributes

AT S1E0R is a 64-bit System instruction.

Field descriptions

The AT S1E0R input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Input address for translation
Input address for translation
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing the AT S1E0R instruction

Accesses to this instruction use the following encodings:

AT S1E0R, <Xt>

op0CRnop1op2CRm
0b010b01110b0000b0100b1000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AT_S1E0R(X[t]); elsif PSTATE.EL == EL2 then AT_S1E0R(X[t]); elsif PSTATE.EL == EL3 then AT_S1E0R(X[t]);




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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