The VTTBR_EL2 characteristics are:
Holds the base address of the translation table for the initial lookup for stage 2 of an address translation in the EL1&0 translation regime, and other information for this translation regime.
AArch64 System register VTTBR_EL2 bits [63:0] are architecturally mapped to AArch32 System register VTTBR[63:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
VTTBR_EL2 is a 64-bit register.
The VTTBR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
VMID[15:8] | VMID[7:0] | BADDR | |||||||||||||||||||||||||||||
BADDR | CnP | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Extension to VMID[7:0]. See VMID[7:0] for more details.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The VMID for the translation table.
It is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.
If the implementation has an 8-bit VMID, then VMID[15:8] are RES0.
If the implementation has a 16-bit VMID, then:
This field resets to an architecturally UNKNOWN value.
Translation table base address, A[47:x] or A[51:x], bits[47:1].
In an implementation that includes ARMv8.2-LPA, if the value of VTCR_EL2.PS is 0b110, then:
If the Effective value of VTCR_EL2.PS is not 0b110 then:
This definition applies:
If any VTTBR_EL2[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using VTTBR_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of VTCR_EL2.T0SZ, the stage of translation, and the translation granule size.
This field resets to an architecturally UNKNOWN value.
Common not Private. This bit indicates whether each entry that is pointed to by VTTBR_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of VTTBR_EL2.CnP is 1.
CnP | Meaning |
---|---|
0b0 |
The translation table entries pointed to by VTTBR_EL2 are permitted to differ from the entries for VTTBR_EL2 for other PEs in the Inner Shareable domain. This is not affected by the value of the current VMID. |
0b1 |
The translation table entries pointed to by VTTBR_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of VTTBR_EL2.CnP is 1 and the VMID is the same as the current VMID. |
This field is permitted to be cached in a TLB.
If the value of VTTBR_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those VTTBR_EL2s do not point to the same translation table entries when using the current VMID then the results of translations using VTTBR_EL2 are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b0010 | 0b100 | 0b000 | 0b0001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x020]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return VTTBR_EL2; elsif PSTATE.EL == EL3 then return VTTBR_EL2;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b0010 | 0b100 | 0b000 | 0b0001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x020] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VTTBR_EL2 = X[t]; elsif PSTATE.EL == EL3 then VTTBR_EL2 = X[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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