The CPSR characteristics are:
Holds PE status and control information.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
CPSR is a 32-bit register.
The CPSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | Q | RES0 | SSBS | PAN | DIT | RES0 | GE | RES0 | E | A | I | F | RES0 | RES1 | M |
Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and N is set to 0 if the result was positive or zero.
Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison.
Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition.
Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition.
Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.
Reserved, RES0.
Speculative Store Bypass Safe.
Prohibits speculative loads or stores which might practically allow a cache timing side channel.
A cache timing side channel might be exploited where a load or store uses an address that is derived from a register that is being loaded from memory using a load instruction speculatively read from a memory location. If PSTATE.SSBS is enabled, the address derived from the load instruction might be from earlier in the coherence order than the lastest store to that memory location with the same virtual address.
SSBS | Meaning |
---|---|
0b0 |
Hardware is not permitted to load or store speculatively in the manner described. |
0b1 |
Hardware is permitted to load or store speculatively in the manner described. |
The value of this bit is usually set to the value described by the SCTLR.DSSBS bit on exceptions to any mode except Hyp mode, and the value described by HSCTLR.DSSBS on exceptions to Hyp mode.
This field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Privileged Access Never.
PAN | Meaning |
---|---|
0b0 |
The translation system is the same as Armv8.0. |
0b1 |
Disables privileged read and write accesses to addresses accessible at EL0. |
The value of this bit is usually preserved on taking an exception, except in the following situations:
Reserved, RES0.
Data Independent Timing.
DIT | Meaning |
---|---|
0b0 |
The architecture makes no statement about the timing properties of any instructions. |
0b1 |
The architecture requires that:
|
The data processing instructions affected by this bit are:
All cryptographic instructions. These instructions are:
A subset of those instructions which use the general-purpose register file. For these instructions, the effects of CPSR.DIT apply only if they do not use R15 as either their source or destination and pass their condition execution check. The instructions are:
A subset of those instructions which use the general-purpose register file. For these instructions, the effects of CPSR.DIT apply only if they do not use R15 as either their source or destination. The effects of CPSR.DIT do not depend on these instructions passing their condition execution check. These instructions are:
A subset of those instructions which use the SIMD&FP register file. For these instructions, the effects of CPSR.DIT apply only if they pass their condition execution check. These instructions are:
This field resets to 0.
Reserved, RES0.
Reserved, RES0.
Greater than or Equal flags, for parallel addition and subtraction.
Reserved, RES0.
Endianness state bit. Controls the load and store endianness for data accesses:
E | Meaning |
---|---|
0b0 |
Little-endian operation |
0b1 |
Big-endian operation. |
Instruction fetches ignore this bit.
If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.
If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.
Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.
When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.
SError interrupt mask bit. The possible values of this bit are:
A | Meaning |
---|---|
0b0 |
Exception not masked. |
0b1 |
Exception masked. |
IRQ mask bit. The possible values of this bit are:
I | Meaning |
---|---|
0b0 |
Exception not masked. |
0b1 |
Exception masked. |
FIQ mask bit. The possible values of this bit are:
F | Meaning |
---|---|
0b0 |
Exception not masked. |
0b1 |
Exception masked. |
Reserved, RES0.
Reserved, RES1.
Current PE mode. Possible values are:
M | Meaning |
---|---|
0b0000 |
User. |
0b0001 |
FIQ. |
0b0010 |
IRQ. |
0b0011 |
Supervisor. |
0b0110 |
Monitor. |
0b0111 |
Abort. |
0b1010 |
Hyp. |
0b1011 |
Undefined. |
0b1111 |
System. |
CPSR can be read using the MRS instruction and written using the MSR (register) or MSR (immediate) instructions. For more details, see MRS, MSR (register), and MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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