The GICD_STATUSR characteristics are:
Provides software with a mechanism to detect:
If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.
GICD_STATUSR is a 32-bit register.
The GICD_STATUSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | WROD | RWOD | WRD | RRD |
Reserved, RES0.
Write to an RO location.
WROD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to an RO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Read of a WO location.
RWOD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a WO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Write to a reserved location.
WRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Read of a reserved location.
RRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
This is an optional register. If the register is not implemented, the location is RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x0010 | GICD_STATUSR (S) |
This interface is accessible as follows:
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x0010 | GICD_STATUSR (NS) |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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