The PMOVSSET_EL0 characteristics are:
Sets the state of the overflow bit for the Cycle Count Register, PMCCNTR_EL0, and each of the implemented event counters PMEVCNTR<n>.
External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMOVSSET_EL0[31:0] .
External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0] .
PMOVSSET_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMOVSSET_EL0 is a 32-bit register.
The PMOVSSET_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P<n>, bit [n] |
Cycle counter overflow set bit.
C | Meaning |
---|---|
0b0 |
When read, means the cycle counter has not overflowed since this bit was last cleared. When written, has no effect. |
0b1 |
When read, means the cycle counter has overflowed since this bit was last cleared. When written, sets the cycle counter overflow bit to 1. |
PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0[63:0].
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Event counter overflow set bit for PMEVCNTR<n>_EL0.
If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.
P<n> | Meaning |
---|---|
0b0 |
When read, means that PMEVCNTR<n>_EL0 has not overflowed since this bit was last cleared. When written, has no effect. |
0b1 |
When read, means that PMEVCNTR<n>_EL0 has overflowed since this bit was last cleared. When written, sets the PMEVCNTR<n>_EL0 overflow bit to 1. |
If ARMv8.5-PMU is implemented, MDCR_EL2.HLP and PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMEVCNTR<n>_EL0[63:0].
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0xCC0 | PMOVSSET_EL0 |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.