The CTIPIDR3 characteristics are:
Provides information to identify a CTI component.
For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
CTIPIDR3 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR3 is a 32-bit register.
The CTIPIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVAND | CMOD |
Reserved, RES0.
Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.
Customer modified. Indicates someone other than the Designer has modified the component.
Component | Offset | Instance |
---|---|---|
CTI | 0xFEC | CTIPIDR3 |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.