TLBI ASIDE1OS, TLB Invalidate by ASID, EL1, Outer Shareable

The TLBI ASIDE1OS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this instructions.

Configuration

This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI ASIDE1OS are UNDEFINED.

Attributes

TLBI ASIDE1OS is a 64-bit System instruction.

Field descriptions

The TLBI ASIDE1OS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASID0000000000000000
00000000000000000000000000000000
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this operation.

If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0.

Bits [47:0]

Reserved, RES0.

Executing the TLBI ASIDE1OS instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1OS{, <Xt>}

op0CRnop1op2CRm
0b010b10000b0000b0100b0001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLBOS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASIDE1OS(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1OS(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1OS(X[t]);




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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