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TLBI ASIDE1, TLB Invalidate by ASID, EL1

The TLBI ASIDE1 characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation only applies to the PE that executes this System instruction.

Configuration

Attributes

TLBI ASIDE1 is a 64-bit System instruction.

Field descriptions

The TLBI ASIDE1 input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES0
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.operation.

If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0.

Bits [47:0]

Reserved, RES0.

Executing the TLBI ASIDE1 instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1{, <Xt>}

op0op1CRnCRmop2
op0CRnop1op2CRm
0b010b0000b10000b01110b010
0b010b10000b0000b0100b0111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FB == '1' then TLBI_ASIDE1IS(X[t]); else TLBI_ASIDE1(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1(X[t]);




2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-20192010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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