The DBGDTRTX_EL0 characteristics are:
Transfers data from the PE to an external debugger. For example, it is used by a debug target to transfer data to the debugger. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communication Channel.
External register DBGDTRTX_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRXint[31:0] .
External register DBGDTRTX_EL0 bits [31:0] are architecturally mapped to External register DBGDTRTXint[31:0] .
External register DBGDTRTX_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRTXint[31:0] when written.
External register DBGDTRTX_EL0 bits [31:0] (read) are architecturally mapped to External register DBGDTRRXint[31:0] .
DBGDTRTX_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
DBGDTRTX_EL0 is a 32-bit register.
The DBGDTRTX_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Return DTRTX |
Return DTRTX.
Reads of this register:
If TXfull is set to 1, return the last value written to DTRTX.
If TXfull is set to 0, return an UNKNOWN value.
After the read, TXfull is cleared to 0.
Writes to this register:
If TXfull is set to 1, set DTRTX to UNKNOWN.
If TXfull is set to 0, update the value in DTRTX.
After the write, TXfull remains unchanged.
For the full behavior of the Debug Communications Channel, see The Debug Communication Channel and Instruction Transfer Register.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
Component | Offset | Instance |
---|---|---|
Debug | 0x08C | DBGDTRTX_EL0 |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.