The GICR_ISENABLER<n>E characteristics are:
Enables forwarding of the corresponding PPI to the CPU interfaces.
Some or all RW fields of this register have defined reset values.
This register is present only when GIC, >=3.1 is implemented. Otherwise, direct accesses to GICR_ISENABLER<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ISENABLER<n>E is a 32-bit register.
The GICR_ISENABLER<n>E bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Set_enable_bit<x>, bit [x], for x = 0 to 31 |
For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
Set_enable_bit<x> | Meaning |
---|---|
0b0 |
If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
0b1 |
If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1. |
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0100 + 4n | GICR_ISENABLER<n>E |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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