The ISR_EL1 characteristics are:
Shows the pending status of the IRQ, FIQ, or SError interrupt.
When executing at EL2, EL3 or Secure EL1 when SCR_EL3.EEL2 == 0b0, this shows the pending status of the physical IRQ, FIQ, or SError interrupts.
When executing at either Non-secure EL1 or at Secure EL1 when SCR_EL3.EEL2 == 0b1:
AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ISR[31:0] .
ISR_EL1 is a 64-bit register.
The ISR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | A | I | F | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
SError interrupt pending bit.
A | Meaning |
---|---|
0b0 |
No pending SError. |
0b1 |
An SError interrupt is pending. |
If the SError interrupt is edge-triggered, this field is cleared to zero when the physical SError interrupt is taken.
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
I | Meaning |
---|---|
0b0 |
No pending IRQ. |
0b1 |
An IRQ interrupt is pending. |
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
F | Meaning |
---|---|
0b0 |
No pending FIQ. |
0b1 |
An FIQ interrupt is pending. |
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b000 | 0b000 | 0b0001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return ISR_EL1; elsif PSTATE.EL == EL2 then return ISR_EL1; elsif PSTATE.EL == EL3 then return ISR_EL1;
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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