The ICH_EISR characteristics are:
Indicates which List registers have outstanding EOI maintenance interrupts.
AArch32 System register ICH_EISR bits [31:0] are architecturally mapped to AArch64 System register ICH_EISR_EL2[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
ICH_EISR is a 32-bit register.
The ICH_EISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Status<n>, bit [n], for n = 0 to 15 |
Reserved, RES0.
EOI maintenance interrupt status bit for List register <n>:
Status<n> | Meaning |
---|---|
0b0 |
List register <n>, ICH_LR<n>, does not have an EOI maintenance interrupt. |
0b1 |
List register <n>, ICH_LR<n>, has an EOI maintenance interrupt that has not been handled. |
For any ICH_LR<n>, the corresponding status bit is set to 1 if all of the following are true:
This field resets to 0.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b100 | 0b011 | 0b1100 | 0b1111 | 0b1011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_EISR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_EISR;
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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