The TLBI RVAAE1 characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry, from any level of the translation table walk.
When EL2 is implemented and enabled in the Security state described by the current value of SCR_EL3.NS:
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2^(5*SCALE +1) * Translation_Granule_Size)].
The invalidation applies to the PE that executes this System instruction.
For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both:
The range of addresses invalidated is UNPREDICTABLE when:
For the 4K translation granule:
If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.
If TTL==10 and BaseADDR[20:12] is not equal to 000000000.
For the 16K translation granule:
For the 64K translation granule:
If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.
If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.
This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI RVAAE1 are UNDEFINED.
TLBI RVAAE1 is a 64-bit System instruction.
The TLBI RVAAE1 input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | TG | SCALE | NUM | TTL | BaseADDR | ||||||||||||||||||||||||||
BaseADDR | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Translation granule size.
TG | Meaning |
---|---|
0b00 |
Reserved. |
0b01 |
4K translation granule. |
0b10 |
16K translation granule. |
0b11 |
64K translation granule. |
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
The exponent element of the calculation that is used to produce the upper range.
The base element of the calculation that is used to produce the upper range.
TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.
TTL | Meaning |
---|---|
0b00 |
The entries in the range can be using any level for the translation table entries. |
0b01 |
When using a 4KB or 64KB translation granule, all entries to invalidate are Level 1 translation table entries. When using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00. |
0b10 |
All entries to invalidate are Level 2 translation table entries. |
0b11 |
All entries to invalidate are Level 3 translation table entries. |
The starting address for the range of the maintenance instruction.
When using a 4KB translation granule, this field is BaseADDR[48:12].
When using a 16KB translation granule, this field is BaseADDR[50:14].
When using a 64KB translation granule, this field is BaseADDR[52:16].
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b1000 | 0b0110 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FB == '1' then TLBI_RVAAE1IS(X[t]); else TLBI_RVAAE1(X[t]); elsif PSTATE.EL == EL2 then TLBI_RVAAE1(X[t]); elsif PSTATE.EL == EL3 then TLBI_RVAAE1(X[t]);
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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