The ISR characteristics are:
Shows the pending status of the IRQ, FIQ, or SError.
When executing at EL2, EL3, or Secure EL1, when SCR_EL3.EEL2 == 0b0, this shows the pending status of the physical interrupts.
When executing at Non-secure EL1, or at Secure EL1, when SCR_EL3.EEL2 == 0b01:
AArch32 System register ISR bits [31:0] are architecturally mapped to AArch64 System register ISR_EL1[31:0] .
ISR is a 32-bit register.
The ISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | A | I | F | RES0 |
Reserved, RES0.
SError interrupt pending bit:
A | Meaning |
---|---|
0b0 |
No pending SError interrupt. |
0b1 |
An SError interrupt is pending. |
If the SError interrupt is edge-triggered, this field is cleared to zero when the physical SError interrupt is taken.
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
I | Meaning |
---|---|
0b0 |
No pending IRQ. |
0b1 |
An IRQ interrupt is pending. |
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
F | Meaning |
---|---|
0b0 |
No pending FIQ. |
0b1 |
An FIQ interrupt is pending. |
Reserved, RES0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1100 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else return ISR; elsif PSTATE.EL == EL2 then return ISR; elsif PSTATE.EL == EL3 then return ISR;
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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