ERXPFGF_EL1, Selected Pseudo-fault Generation Feature Register

The ERXPFGF_EL1 characteristics are:

Purpose

Accesses the ERR<n>PFGF register for the error record selected by ERRSELR_EL1.SEL.

Configuration

This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERXPFGF_EL1 are UNDEFINED.

Attributes

ERXPFGF_EL1 is a 64-bit register.

Field descriptions

The ERXPFGF_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ERR<n>PFGF
ERR<n>PFGF
313029282726252423222120191817161514131211109876543210

Bits [63:0]

ERXPFGF_EL1 accesses ERR<n>PFGF, where n is the value in ERRSELR_EL1.SEL.

Accessing the ERXPFGF_EL1

If ERRIDR_EL1.NUM == 0 or ERRSELR_EL1.SEL is set to a value greater than or equal to ERRIDR_EL1.NUM, then one of the following occurs:

If ERRSELR_EL1.SEL selects an error record that does not implement the RAS Common Fault Injection Model Extension, then one of the following occurs:

Note

An error record does not implement the RAS Common Fault Injection Model Extension when ERR<n>FR.INJ == 0b00.

Accesses to this register use the following encodings:

MRS <Xt>, ERXPFGF_EL1

op0op1CRnCRmop2
0b110b0000b01010b01000b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FIEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIEN == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return ERXPFGF_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIEN == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return ERXPFGF_EL1; elsif PSTATE.EL == EL3 then return ERXPFGF_EL1;




27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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