DC CGSW, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way

The DC CGSW characteristics are:

Purpose

Clean Allocation Tags in data cache by set/way.

Configuration

This instruction is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to DC CGSW are UNDEFINED.

Attributes

DC CGSW is a 64-bit System instruction.

Field descriptions

The DC CGSW input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
SetWayLevel0
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

SetWay, bits [31:4]

Contains two fields:

Bits[L-1:4] are RES0.

A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).

ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.

Level, bits [3:1]

Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.

Bit [0]

Reserved, RES0.

Executing the DC CGSW instruction

If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:

Accesses to this instruction use the following encodings:

DC CGSW, <Xt>

op0CRnop1op2CRm
0b010b01110b0000b1000b1010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TSW == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else DC_CISW(X[t]); elsif PSTATE.EL == EL2 then DC_CISW(X[t]); elsif PSTATE.EL == EL3 then DC_CISW(X[t]);




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.