The DCIMVAC characteristics are:
Invalidate data or unified cache line by virtual address to PoC.
AArch32 System instruction DCIMVAC performs the same function as AArch64 System instruction DC IVAC.
DCIMVAC is a 32-bit System instruction.
The DCIMVAC input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use |
Virtual address to use. No alignment restrictions apply to this VA.
It is IMPLEMENTATION DEFINED whether, when this instruction is executed, it can generate a watchpoint. If this instruction can generate a watchpoint this is prioritized in the same way as other watchpoints.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'AArch32 data cache maintenance instruction (DC*)' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
Accesses to this instruction use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b001 | 0b0111 | 0b1111 | 0b0110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPCP == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TPC == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<DC,VM> != '00' then DCCIMVAC(R[t]); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.<DC,VM> != '00' then DCCIMVAC(R[t]); else DCIMVAC(R[t]); elsif PSTATE.EL == EL2 then DCIMVAC(R[t]); elsif PSTATE.EL == EL3 then DCIMVAC(R[t]);
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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