The MPAMF_IIDR characteristics are:
The MPAMF_IIDR is a 32-bit read-only register that gives identification information to uniquely define the MSC.
The power domain of MPAMF_IIDR is IMPLEMENTATION DEFINED.
MPAMF_IIDR is a 32-bit register.
The MPAMF_IIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Variant | Revision | Implementer |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED value identifying the MPAM MSC.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED value used to distinguish product variants, or major revisions of the product.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED value used to distinguish minor revisions of the product.
Contains the JEP106 code of the company that implemented the MPAM MSC.
[11:8] must contain the JEP106 continuation code of the implementer.
[7] must always be 0.
[6:0] must contain the JEP106 identity code of the implementer.
For an Arm implementation, bits[11:0] are 0x43B.
This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.
MPAMF_IIDR must be accessible from the Non-secure and Secure address maps.
MPAMF_IIDR must be shared between the Secure and Non-secure address maps.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_s | 0x0018 | MPAMF_IIDR_s |
Access on this interface is RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_ns | 0x0018 | MPAMF_IIDR_ns |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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