The GICV_PMR characteristics are:
This register provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE.
Higher interrupt priority corresponds to a lower value of the Priority field.
This register corresponds to the physical CPU interface register GICC_PMR.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when the GIC implementation supports interrupt virtualization.
The Priority field of this register is aliased to GICH_VMCR.VMPR, to enable state to be switched easily between virtual machines during context-switching.
GICV_PMR is a 32-bit register.
The GICV_PMR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The priority mask level for the virtual CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows:
See Interrupt prioritization, section 4.8 of the GICv3 Architecture Specification for more information.
This field resets to an architecturally UNKNOWN value.
This register is used only when System register access is not enabled. When System register access is enabled:
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x0004 | GICV_PMR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.