The ITLBIALL characteristics are:
Invalidate all cached copies of translation table entries from instruction TLBs that are from any level of the translation table walk. The entries that are invalidated are as follows:
The invalidation only applies to the PE that executes this instruction.
Arm deprecates the use of this instruction. It is only provided for backwards compatibility with earlier versions of the Arm architecture.
ITLBIALL is a 32-bit System instruction.
ITLBIALL ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b000 | 0b1000 | 0b1111 | 0b0101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TTLB == '1' then AArch32.TakeHypTrapException(0x03); else ITLBIALL(); elsif PSTATE.EL == EL2 then ITLBIALL(); elsif PSTATE.EL == EL3 then ITLBIALL();
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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