The DLR_EL0 characteristics are:
In Debug state, holds the address to restart from.
AArch64 System register DLR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DLR[31:0] .
DLR_EL0 is a 64-bit register.
The DLR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Restart address | |||||||||||||||||||||||||||||||
Restart address | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Restart address.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b0100 | 0b011 | 0b001 | 0b0101 |
if !Halted() then UNDEFINED; else return DLR_EL0;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b0100 | 0b011 | 0b001 | 0b0101 |
if !Halted() then UNDEFINED; else DLR_EL0 = X[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.