The ICC_EOIR0_EL1 characteristics are:
A PE writes to this register to inform the CPU interface that it has completed the processing of the specified Group 0 interrupt.
AArch64 System register ICC_EOIR0_EL1 performs the same function as AArch32 System register ICC_EOIR0.
ICC_EOIR0_EL1 is a 64-bit register.
The ICC_EOIR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID | |||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
The INTID from the corresponding ICC_IAR0_EL1 access.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
If the EOImode bit for the current Exception level and Security state is 0, a write to this register drops the priority for the interrupt, and also deactivates the interrupt.
If the EOImode bit for the current Exception level and Security state is 1, a write to this register only drops the priority for the interrupt. Software must write to ICC_DIR_EL1 to deactivate the interrupt.
The EOImode bit for the current Exception level and Security state is determined as follows:
A write to this register must correspond to the most recent valid read by this PE from an Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICC_IAR0_EL1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID.
A write of a Special INTID is ignored. See Special INTIDs, for more information.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1100 | 0b000 | 0b001 | 0b1000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then ICV_EOIR0_EL1 = X[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else ICC_EOIR0_EL1 = X[t]; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else ICC_EOIR0_EL1 = X[t]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else ICC_EOIR0_EL1 = X[t];
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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