TLBI VMALLS12E1, TLB Invalidate by VMID, All at Stage 1 and 2, EL1

The TLBI VMALLS12E1 characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation only applies to the PE that executes this instruction.

Note

For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.

Configuration

Attributes

TLBI VMALLS12E1 is a 64-bit System instruction.

Field descriptions

TLBI VMALLS12E1 ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

Executing the TLBI VMALLS12E1 instruction

Accesses to this instruction use the following encodings:

TLBI VMALLS12E1{, <Xt>}

Rtop0op1op2CRnCRm
0b111110b010b1000b1100b10000b0111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12E1(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALLE1(); else TLBI_VMALLS12E1();




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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