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The AMAIR_EL1 characteristics are:
Provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR_EL1.
AArch64 System register AMAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register AMAIR0[31:0] .
AArch64 System register AMAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register AMAIR1[31:0] .
RW fields in this register reset to architecturally UNKNOWN values.
AMAIR_EL1 is a 64-bit register.
The AMAIR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AMAIR_EL1 is permitted to be cached in a TLB.
IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
AMAIR_EL1 is permitted to be cached in a TLB.
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic AMAIR_EL1 or AMAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1010 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x148]; else return AMAIR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return AMAIR_EL2; else return AMAIR_EL1; elsif PSTATE.EL == EL3 then return AMAIR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1010 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x148] = X[t]; else AMAIR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then AMAIR_EL2 = X[t]; else AMAIR_EL1 = X[t]; elsif PSTATE.EL == EL3 then AMAIR_EL1 = X[t];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b1010 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
return NVMem[0x148];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
if PSTATE.EL == EL2 then
return AMAIR_EL1;
else
UNDEFINED;
elsif PSTATE.EL == EL3 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
return AMAIR_EL1;
else
else
UNDEFINED;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b1010 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
NVMem[0x148] = X[t];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
if PSTATE.EL == EL2 then
AMAIR_EL1 = X[t];
else
UNDEFINED;
elsif PSTATE.EL == EL3 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
AMAIR_EL1 = X[t];
else
else
UNDEFINED;
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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