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The TLBI ALLE2IS characteristics are:
If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL2 or Non-secure EL2&0 translation regime.
If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL2 or Secure EL2&0 translation regime.
The invalidation only applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
TLBI ALLE2IS is a 64-bit System instruction.
TLBI ALLE2IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0011 | 0b000 | 0b11111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_ALLE2IS(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; else TLBI_ALLE2IS();
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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