AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

The AFSR1_EL2 characteristics are:

Purpose

Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL2.

Configuration

AArch64 System register AFSR1_EL2 bits [31:0] are architecturally mapped to AArch32 System register HAIFSR[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

AFSR1_EL2 is a 64-bit register.

Field descriptions

The AFSR1_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

This field resets to an architecturally UNKNOWN value.

Accessing the AFSR1_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AFSR1_EL2 or AFSR1_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, AFSR1_EL2

op0CRnop1op2CRm
0b110b01010b1000b0010b0001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return AFSR1_EL2; elsif PSTATE.EL == EL3 then return AFSR1_EL2;

MSR AFSR1_EL2, <Xt>

op0CRnop1op2CRm
0b110b01010b1000b0010b0001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then AFSR1_EL2 = X[t]; elsif PSTATE.EL == EL3 then AFSR1_EL2 = X[t];

MRS <Xt>, AFSR1_EL1

op0CRnop1op2CRm
0b110b01010b0000b0010b0001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x130]; else return AFSR1_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return AFSR1_EL2; else return AFSR1_EL1; elsif PSTATE.EL == EL3 then return AFSR1_EL1;

MSR AFSR1_EL1, <Xt>

op0CRnop1op2CRm
0b110b01010b0000b0010b0001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x130] = X[t]; else AFSR1_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then AFSR1_EL2 = X[t]; else AFSR1_EL1 = X[t]; elsif PSTATE.EL == EL3 then AFSR1_EL1 = X[t];




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.