The ERR<n>CTLR characteristics are:
The error control register contains enable bits for the node that writes to this record, which:
Enable error detection and correction.
Enable an error recovery interrupt.
Enable a fault handling interrupt.
Enable error recovery reporting as a read or write error response.
When ARMv.4-RAS is implemented, enable a critical error interrupt.
For each bit, if the selected node does not support the feature, then the bit is RES0. The definition of each record is IMPLEMENTATION DEFINED.
Some or all RW fields of this register have defined reset values.
The number of error records that are implemented is IMPLEMENTATION DEFINED.
If error record <n> is not implemented, or error record <n> is not the first error record owned by the node, ERR<n>CTLR is RES0.
ERR<n>FR describes the features implemented by the node.
ERR<n>CTLR is a 64-bit register.
The ERR<n>CTLR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
RES0 | CI | RES0 | WDUI | DUI | WCFI | CFI | WUE | WFI | WUI | UE | FI | UI | IMPLEMENTATION DEFINED | ED | |||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.
This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.
Reserved, RES0.
Critical error interrupt enable.
When enabled, the critical error interrupt is generated for a critical error condition.
CI | Meaning |
---|---|
0b0 |
Critical error interrupt not generated for critical errors. Critical errors are treated as Uncontained errors. |
0b1 |
Critical error interrupt generated for critical errors. |
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Error recovery interrupt for deferred errors on writes enable.
When enabled, the error recovery interrupt is generated for all detected Deferred errors on writes.
WDUI | Meaning |
---|---|
0b0 |
Error recovery interrupt not generated for deferred errors on writes. |
0b1 |
Error recovery interrupt generated for deferred errors on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Error recovery interrupt for deferred errors enable. This control applies to errors arising from both reads and writes.
When enabled, an error recovery interrupt is generated for all detected Deferred errors.
DUI | Meaning |
---|---|
0b0 |
Error recovery interrupt not generated for deferred errors. |
0b1 |
Error recovery interrupt generated for deferred errors. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.DUI == 0b11, this field is named RDUI.
Error recovery interrupt for deferred errors on reads enable.
When enabled, the error recovery interrupt is generated for all detected Deferred errors on reads.
RDUI | Meaning |
---|---|
0b0 |
Error recovery interrupt not generated for deferred errors on reads. |
0b1 |
Error recovery interrupt generated for deferred errors on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault handling interrupt for Corrected errors on writes enable.
When enabled:
WCFI | Meaning |
---|---|
0b0 |
Fault handling interrupt not generated for Corrected errors on writes. |
0b1 |
Fault handling interrupt generated for Corrected errors on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault handling interrupt for Corrected errors enable. This control applies to errors arising from both reads and writes.
When enabled:
CFI | Meaning |
---|---|
0b0 |
Fault handling interrupt not generated for Corrected errors. |
0b1 |
Fault handling interrupt generated for Corrected errors. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.CFI == 0b11, this field is named RCFI.
Fault handling interrupt for Corrected errors on reads enable.
When enabled:
RCFI | Meaning |
---|---|
0b0 |
Fault handling interrupt not generated for Corrected errors on reads. |
0b1 |
Fault handling interrupt generated for Corrected errors on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
In-band Uncorrected error reporting on writes enable.
When enabled, responses to writes that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).
WUE | Meaning |
---|---|
0b0 |
External abort response for Uncorrected errors disabled for writes. |
0b1 |
External abort response for Uncorrected errors enabled for writes. |
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault handling interrupt on writes enable.
When enabled:
WFI | Meaning |
---|---|
0b0 |
Fault handling interrupt disabled on writes. |
0b1 |
Fault handling interrupt enabled on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Uncorrected error recovery interrupt on writes enable.
When enabled, the error recovery interrupt is generated for all detected Uncorrected errors on writes that are not deferred.
WUI | Meaning |
---|---|
0b0 |
Error recovery interrupt disabled on writes. |
0b1 |
Error recovery interrupt enabled on writes. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
In-band Uncorrected error reporting enable.
When enabled, responses to transactions that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).
UE | Meaning |
---|---|
0b0 |
External abort response for Uncorrected errors disabled. |
0b1 |
External abort response for Uncorrected errors enabled. |
This control applies to errors arising from both reads and writes.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.UE == 0b11, this field is named RUE.
In-band Uncorrected error reporting on reads enable.
When enabled, responses to reads that detect an Uncorrected error that cannot be deferred are signaled in-band as a detected Uncorrected error (External abort).
RUE | Meaning |
---|---|
0b0 |
External abort response for Uncorrected errors disabled for reads. |
0b1 |
External abort response for Uncorrected errors enabled for reads. |
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault handling interrupt enable. This control applies to errors arising from both reads and writes.
When enabled:
FI | Meaning |
---|---|
0b0 |
Fault handling interrupt disabled. |
0b1 |
Fault handling interrupt enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.FI == 0b11, this field is named RFI.
Fault handling interrupt on reads enable.
When enabled:
RFI | Meaning |
---|---|
0b0 |
Fault handling interrupt disabled on reads. |
0b1 |
Fault handling interrupt enabled on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Uncorrected error recovery interrupt enable. This control applies to errors arising from both reads and writes.
When enabled, the error recovery interrupt is generated for all detected Uncorrected errors that are not deferred.
UI | Meaning |
---|---|
0b0 |
Error recovery interrupt disabled. |
0b1 |
Error recovery interrupt enabled. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
When ERR<n>FR.UI == 0b11, this field is named RUI.
Uncorrected error recovery interrupt on reads enable.
When enabled, the error recovery interrupt is generated for all detected Uncorrected errors on reads that are not deferred.
RUI | Meaning |
---|---|
0b0 |
Error recovery interrupt disabled on reads. |
0b1 |
Error recovery interrupt enabled on reads. |
The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
IMPLEMENTATION DEFINED.
Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.
This bit reads as an IMPLEMENTATION DEFINED value and writes to this bit have IMPLEMENTATION DEFINED behavior.
Error reporting and logging enable.
When disabled, the node behaves as if error detection and correction are disabled, and no errors are recorded or signaled by the node. Arm recommends that, when disabled, correct error detection and correction codes are written for writes, unless disabled by an IMPLEMENTATION DEFINED control for error injection.
ED | Meaning |
---|---|
0b0 |
Error reporting disabled. |
0b1 |
Error reporting enabled. |
It is IMPLEMENTATION DEFINED whether the node fully disables error detection and correction when reporting is disabled. That is, even with error reporting disabled, the node might continue to silently correct errors. Uncorrectable errors might result in corrupt data being silently propagated by the node.
If this node requires initialization after Cold reset to prevent signaling false errors, then Arm recommends this bit is set to 0 on Cold reset. This allows boot software to initialize a node without signaling errors. Software can enable error reporting after the node is initialized. If the Cold reset value is 1, the reset values of other controls in this register are IMPLEMENTATION DEFINED and should not be UNKNOWN.
The following resets apply:
This bit is preserved on an Error Recovery reset.
On a Cold reset, this field resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
RAS | 0x008 + 64n | ERR<n>CTLR |
Access on this interface is RW.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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