The EDPRSR characteristics are:
Holds information about the reset and powerdown state of the PE.
EDPRSR contains fields that are in the Core power domain and fields that are in the Debug power domain.
Some of the fields in the Core power domain are in the Cold reset domain and others are in the Warm reset domain. See the field descriptions for more information. However:
Fields that are in the Cold reset domain are not affected by a warm reset and are not affected by an External debug reset.
Fields in the Warm reset domain are also reset by a Cold reset but are not affected by an External debug reset.
Fields in the Debug power domain are not affected by a Warm reset and are not affected by a Cold reset.
If ARMv8.3-DoPD is implemented then all fields in this register are in the Core power domain.
EDPRSR is a 32-bit register.
The EDPRSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SDR | SPMAD | EPMAD | SDAD | EDAD | DLK | OSLK | HALTED | SR | R | SPD | PU |
Reserved, RES0.
Sticky debug restart. Set to 1 when the PE exits Debug state.
Permitted values are:
SDR | Meaning |
---|---|
0b0 |
The PE has not restarted since EDPRSR was last read. |
0b1 |
The PE has restarted since EDPRSR was last read. |
If a reset occurs when the PE is in Debug state, the PE exits Debug state. SDR is UNKNOWN on Warm reset, meaning a debugger must also use the SR bit to determine whether the PE has left Debug state.
If The Core power domain is powered up, then following a read of EDPRSR:
This field is in the Core power domain and the Warm reset domain.
This field resets to an architecturally UNKNOWN value.
Accessing this field has the following behavior:
Sticky EPMAD error. Set to 1 if an external debug interface access to a Performance Monitors register returns an error because AllowExternalPMUAccess() == FALSE.
Permitted values are:
SPMAD | Meaning |
---|---|
0b0 |
No Non-secure external debug interface accesses to the external Performance Monitors registers have failed because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read.. |
0b1 |
At least one Non-secure external debug interface access to the external Performance Monitors register have failed because AllowExternalPMUAccess() == FALSE for the access since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
This field is in the Core power domain.
On a Cold reset, this field resets to 0.
Accessing this field has the following behavior:
Sticky EPMAD error.
SPMAD | Meaning |
---|---|
0b0 |
No accesses to the external Performance Monitors registers have failed with an AllowExternalPMUAccess() == FALSE error since EDPRSR was last read. |
0b1 |
At least one access to the external Performance Monitors registers returned an AllowExternalPMUAccess() == FALSE error since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
This field is in the Core power domain.
On a Cold reset, this field resets to 0.
Accessing this field has the following behavior:
External Performance Monitors access disable status.
EPMAD | Meaning |
---|---|
0b0 |
External Non-secure Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE. |
0b1 |
External Non-secure Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE. |
This field is in the Core power domain.
Accessing this field has the following behavior:
External Performance Monitors access disable status.
EPMAD | Meaning |
---|---|
0b0 |
External Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE. |
0b1 |
External Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE. |
This field is in the Core power domain.
Accessing this field has the following behavior:
Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.
SDAD | Meaning |
---|---|
0b0 |
No Non-secure accesses to the external debug registers have failed with AllowExternalDebugAccess() == FALSE since EDPRSR was last read. |
0b1 |
At least one Non-secure access to the external debug registers has failed with AllowExternalDebugAccess() == FALSE since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
This field is in the Core power domain.
On a Cold reset, this field resets to 0.
Accessing this field has the following behavior:
Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.
SDAD | Meaning |
---|---|
0b0 |
No accesses to the external debug registers have failed with AllowExternalDebugAccess() == FALSE since EDPRSR was last read. |
0b1 |
At least one access to the external debug registers has failed with AllowExternalDebugAccess() == FALSE since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
This bit is UNKNOWN on reads if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.
This field is in the Core power domain.
On a Cold reset, this field resets to 0.
Accessing this field has the following behavior:
External debug access disable status.
EDAD | Meaning |
---|---|
0b0 |
External Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 is enabled. |
0b1 |
Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 from an external debugger is not permitted. |
This field is in the Core power domain.
Accessing this field has the following behavior:
External debug access disable status.
EDAD | Meaning |
---|---|
0b0 |
Access from an external debugger to breakpoint registers, watchpoint registers, and OSLAR_EL1 is enabled. |
0b1 |
Access from an external debugger to breakpoint registers, watchpoint registers, and OSLAR_EL1 is not permitted. |
This bit is not valid and reads UNKNOWN if OSLockStatus() == TRUE and external debug writes to OSLAR_EL1 do not return an error when AllowExternalDebugAccess() == FALSE.
This field is in the Core power domain.
Accessing this field has the following behavior:
External debug access disable status.
EDAD | Meaning |
---|---|
0b0 |
Access from an external debugger to breakpoint registers, watchpoint registers is enabled. |
0b1 |
Access from an external debugger to breakpoint registers, watchpoint registers is not permitted and it is IMPLEMENTATAION DEFINED whether accesses to OSLAR_EL1 are permitted. |
This field is in the Core power domain.
Accessing this field has the following behavior:
This field is RES0.
From Armv8.2, this field is deprecated.
This field is in the Core power domain.
Accessing this field has the following behavior:
This field returns the result of the pseudocode function DoubleLockStatus().
If the Core power domain is powered up and the OS Double Lock is implemented and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether:
This field is in the Core power domain.
DLK | Meaning |
---|---|
0b0 |
DoubleLockStatus() returns FALSE. |
0b1 |
DoubleLockStatus() returns TRUE and the Core power domain is powered up. |
Accessing this field has the following behavior:
OS lock status bit.
A read of this bit returns the value of OSLSR_EL1.OSLK.
This field is in the Core power domain.
Accessing this field has the following behavior:
Halted status bit.
This bit is UNKNOWN on reads if EDPRSR.PU is 0.
Otherwise permitted values are:
HALTED | Meaning |
---|---|
0b0 |
PE is in Non-debug state. |
0b1 |
PE is in Debug state. |
Because the OS Double Lock is never set when the PE is in Debug state, this bit is always RAZ when DoubleLockStatus() == TRUE.
This field is in the Core power domain.
Accessing this field has the following behavior:
Sticky core reset status bit.
Permitted values are:
SR | Meaning |
---|---|
0b0 |
The non-debug logic of the PE is not in reset state and has not been reset since the last time EDPRSR was read. |
0b1 |
The non-debug logic of the PE is in reset state or has been reset since the last time EDPRSR was read. |
If EDPRSR.PU reads as 1 and EDPRSR.R reads as 0, which means that the Core power domain is in a powerup state and that the non-debug logic of the PE is not in reset state, then following a read of EDPRSR:
This field is in the Core power domain and the Warm reset domain.
This field resets to 1.
Accessing this field has the following behavior:
PE reset status bit.
Permitted values are:
R | Meaning |
---|---|
0b0 |
The non-debug logic of the PE is not in reset state. |
0b1 |
The non-debug logic of the PE is in reset state. |
If the OS Double Lock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)
This field is in the Core power domain.
Accessing this field has the following behavior:
Sticky Core powerdown status bit.
This bit is UNKNOWN on reads if EDPRSR.PU is 1, the OS Double Lock is implemented and DoubleLockStatus() == TRUE .
Otherwise, permitted values are:
SPD | Meaning |
---|---|
0b0 |
If EDPRSR.PU is 0, it is not known whether the state of the debug registers in the Core power domain is lost. If EDPRSR.PU is 1, the state of the debug registers in the Core power domain has not been lost. |
0b1 |
The state of the debug registers in the Core power domain has been lost. |
If the Core power domain is powered up, then, following a read of EDPRSR:
When the value of EDPRSR.PU is 0 indicating that the Core power domain is in either retention or powerdown state, EDPRSR.SPD reads as 0. For more information, see 'EDPRSR.SPD when the Core domain is in either retention or powerdown state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support).
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support).
This field is in the Core power domain and the Cold reset domain.
On a Cold reset, this field resets to 1.
Accessing this field has the following behavior:
Core powerup status bit.
Access to this field is RAO.
Core powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.
PU | Meaning |
---|---|
0b0 |
Either the Core power domain is in a low-power or powerdown state, or the OS Double Lock is implemented and DoubleLockStatus() == TRUE, meaning the debug registers in the Core power domain cannot be accessed. |
0b1 |
The Core power domain is in a powerup state, and either the OS Double Lock is not implemented or DoubleLockStatus() == FALSE, meaning the debug registers in the Core power domain can be accessed. |
If the OS Double Lock is implemented, the PE is in reset state, and the PE entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)
Access to this field is RO.
Core powerup status bit. Indicates whether the debug registers in the Core power domain can be accessed.
When the Core power domain is powered-up and DoubleLockStatus() == TRUE, then the value of EDPRSR.PU is IMPLEMENTATION DEFINED. See the description of the DLK bit for more information.
Otherwise, permitted values are:
PU | Meaning |
---|---|
0b0 |
Core power domain is in a low-power or powerdown state where the debug registers in the Core power domain cannot be accessed. |
0b1 |
Core power domain is in a powerup state where the debug registers in the Core power domain can be accessed. |
If the Core power domain is powered up and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether this bit reads as 0 or 1.
If the PE is in reset state and entered reset state with the OS Double Lock locked this bit has a CONSTRAINED UNPREDICTABLE value. For more information see 'EDPRSR.{DLK, R} and reset state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H6 (Debug Reset and Powerdown Support)
Access to this field is RO.
On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.
If the Core power domain is powered up (EDPRSR.PU == 1), then following a read of EDPRSR:
If the Core power domain is powered down (EDPRSR.PU == 0), then:
The clearing of bits is an indirect write to EDPRSR.
Component | Offset | Instance |
---|---|---|
Debug | 0x314 | EDPRSR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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