The AMEVTYPER0<n> characteristics are:
Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n> counts.
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch64 System register AMEVTYPER0<n>_EL0[31:0] .
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER0<n>[31:0] .
The power domain of AMEVTYPER0<n> is IMPLEMENTATION DEFINED.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n> are RES0.
AMEVTYPER0<n> is a 32-bit register.
The AMEVTYPER0<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | evtCount |
Reserved, RAZ.
Reserved, RES0.
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
evtCount | Meaning | Applies when |
---|---|---|
0x0011 |
Processor frequency cycles | When n == 0 |
0x4004 |
Constant frequency cycles | When n == 1 |
0x0008 |
Instructions retired | When n == 2 |
0x4004 |
Memory stall cycles | When n == 3 |
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVTYPER0<n> are CONSTRAINED UNPREDICTABLE, and accesses to the register behave as RAZ/WI.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
Component | Offset | Instance |
---|---|---|
AMU | 0x400 + 4n | AMEVTYPER0<n> |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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