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The TLBI ALLE3IS characteristics are:
If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry, from any level of the translation table walk.
The entry would be required to translate an address using the EL3 translation regime.
The invalidation only applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
TLBI ALLE3IS is a 64-bit System instruction.
TLBI ALLE3IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|
0b01 | 0b110 | 0b1000 | 0b0011 | 0b000 | 0b11111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then TLBI_ALLE3IS();
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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