The GICR_SYNCR characteristics are:
Indicates completion of physical Redistributor operations.
A copy of this register is provided for each Redistributor.
GICR_SYNCR is a 32-bit register.
The GICR_SYNCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Busy |
Reserved, RES0.
Indicates completion of any Redistributor operations as follows:
Busy | Meaning |
---|---|
0b0 |
No operations are in progress. |
0b1 |
A write is in progress to one or more of the following registers: |
This field also indicates completion of any operations initiated by writes to GICR_PENDBASER or GICR_PROPBASER.
Optionally, when this register is accessed, an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x00C0 | GICR_SYNCR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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