The RVBAR characteristics are:
If EL3 is not implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch32 state.
This register is only implemented if the highest Exception level implemented is capable of using AArch32, and is not EL3.
RVBAR is a 32-bit register.
The RVBAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset Address[31:1] | 1 |
Reset Address[31:1]. Bits [31:1] of the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 32-bit state.
Reserved, RES1.
Accesses to this register use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b001 | 0b1100 | 0b1111 | 0b0000 |
if PSTATE.EL IN {EL2, EL1} && IsHighestEL(PSTATE.EL) then return RVBAR; else UNDEFINED;
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.