The GICD_IPRIORITYR<n>E characteristics are:
Holds the priority of the corresponding interrupt for each extended SPI supported by the GIC.
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when GIC, >=3.1 is implemented. Otherwise, direct accesses to GICD_IPRIORITYR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_IPRIORITYR<n>E registers is ((GICD_TYPER.ESPI_range+1)*8). Registers are numbered from 0.
GICD_IPRIORITYR<n>E is a 32-bit register.
The GICD_IPRIORITYR<n>E bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Priority_offset_3B | Priority_offset_2B | Priority_offset_1B | Priority_offset_0B |
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 3. Lower priority values correspond to greater priority of the interrupt.
This field resets to an architecturally UNKNOWN value.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 2. Lower priority values correspond to greater priority of the interrupt.
This field resets to an architecturally UNKNOWN value.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 1. Lower priority values correspond to greater priority of the interrupt.
This field resets to an architecturally UNKNOWN value.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 0. Lower priority values correspond to greater priority of the interrupt.
This field resets to an architecturally UNKNOWN value.
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_ISACTIVER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0:
Bits corresponding to unimplemented interrupts are RAZ/WI.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than once. The effect of the change must be visible in finite time.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x2000 + 4n | GICD_IPRIORITYR<n>E |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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