JMCR, Jazelle Main Configuration Register

The JMCR characteristics are:

Purpose

A Jazelle register, which provides control of the Jazelle extension.

Configuration

Attributes

JMCR is a 32-bit register.

Field descriptions

The JMCR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000000

Bits [31:0]

RAZ/WI at EL1, EL2, and EL3. It is IMPLEMENTATION DEFINED whether this field is RAZ/WI or UNDEFINED at EL0.

Accessing the JMCR

For accesses from EL0 it is IMPLEMENTATION DEFINED whether the register is RW or UNDEFINED.

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

opc1opc2CRncoprocCRm
0b1110b0000b00100b11100b0000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else return JMCR; elsif PSTATE.EL == EL1 then return JMCR; elsif PSTATE.EL == EL2 then return JMCR; elsif PSTATE.EL == EL3 then return JMCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

opc1opc2CRncoprocCRm
0b1110b0000b00100b11100b0000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else //no operation elsif PSTATE.EL == EL1 then //no operation elsif PSTATE.EL == EL2 then //no operation elsif PSTATE.EL == EL3 then //no operation




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.