TLBI VAALE1, TLB Invalidate by VA, All ASID, Last level, EL1

The TLBI VAALE1 characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation only applies to the PE that executes this instruction.

Note

For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.

Configuration

Attributes

TLBI VAALE1 is a 64-bit System instruction.

Field descriptions

The TLBI VAALE1 input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000TTLVA[55:12]
VA[55:12]
313029282726252423222120191817161514131211109876543210

Bits [63:48]

Reserved, RES0.

TTL, bits [47:44]

When ARMv8.4-TTL is implemented:

Translation Table Level. Indicates the level of the page table walk that holds the leaf entry for the address being invalidated.

TTLMeaning
0b00xx

No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0.

0b01xx

The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

0b10xx

The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Reserved. Treat as if TTL<3:2> is 0b00.

0b10 : Level 2.

0b11 : Level 3.

0b11xx

The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB.


Otherwise:

Reserved, RES0.

VA[55:12], bits [43:0]

Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the VA will be affected by this operation, regardless of the ASID.

If the TLB maintenance instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then the software must treat bits[55:32] as RES0.

The treatment of the low-order bits of this field depends on the translation granule size, as follows:

Executing the TLBI VAALE1 instruction

Accesses to this instruction use the following encodings:

TLBI VAALE1{, <Xt>}

op0CRnop1op2CRm
0b010b10000b0000b1110b0111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FB == '1' then TLBI_VAALE1IS(X[t]); else TLBI_VAALE1(X[t]); elsif PSTATE.EL == EL2 then TLBI_VAALE1(X[t]); elsif PSTATE.EL == EL3 then TLBI_VAALE1(X[t]);




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

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