The PMLSR characteristics are:
Indicates the current status of the software lock for Performance Monitors registers.
It is IMPLEMENTATION DEFINED whether PMLSR is implemented in the Core power domain or in the Debug power domain. Some or all RW fields of this register have defined reset values, and:
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
PMLSR is RAZ if the Software Lock is not implemented and is RAZ for other accesses to the external debug interface.
The Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage.
Software uses PMLAR to set or clear the lock, and PMLSR to check the current status of the lock.
PMLSR is a 32-bit register.
The PMLSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | nTT | SLK | SLI |
Reserved, RES0.
Not thirty-two bit access required. RAZ.
Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when the Software Lock is not implemented, this field is RES0.
For memory-mapped accesses when the software lock is implemented, possible values of this field are:
SLK | Meaning |
---|---|
0b0 |
Lock clear. Writes are permitted to this component's registers. |
0b1 |
Lock set. Writes to this component's registers are ignored, and reads have no side effects. |
The following resets apply:
If Armv8.3-DoPD is implemented, this register is reset by Cold reset and not affected by External debug reset. If Armv8.3-DoPD is not implemented, this register is reset by External debug reset and not affected by Cold reset.
On a reset, this field resets to 1.
Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is IMPLEMENTATION DEFINED. Permitted values are:
SLI | Meaning |
---|---|
0b0 |
Software Lock not implemented or not memory-mapped access. |
0b1 |
Software Lock implemented and memory-mapped access. |
Component | Offset | Instance |
---|---|---|
PMU | 0xFB4 | PMLSR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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