The ERRCRICR0 characteristics are:
Interrupt configuration register.
External register ERRCRICR0 is architecturally mapped to External register ERRIRQCR4.
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERRCRICR0 are RES0.
Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.
ERRCRICR0 is a 64-bit register.
The ERRCRICR0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | ADDR | ||||||||||||||||||||||||||||||
ADDR | RES0 | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Message Signaled Interrupt address.
Specifies the address that the component writes to when signaling an interrupt.
The size of a physical address is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.
The following resets apply:
On a Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
RAS | 0xEA0 | ERRCRICR0 |
Access on this interface is RW.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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