The TLBI ALLE1IS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL1&0 translation regime.
If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL1&0 translation regime.
The invalidation applies to entries with any VMID.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
TLBI ALLE1IS is a 64-bit System instruction.
TLBI ALLE1IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
Rt | op0 | op1 | op2 | CRn | CRm |
---|---|---|---|---|---|
0b11111 | 0b01 | 0b100 | 0b100 | 0b1000 | 0b0011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_ALLE1IS(); elsif PSTATE.EL == EL3 then TLBI_ALLE1IS();
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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