The AMCNTENCLR0 characteristics are:
Disable control bits for the architected s event counters, AMEVCNTR0<n>.
External register AMCNTENCLR0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR0_EL0[31:0] .
External register AMCNTENCLR0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR0[31:0] .
The power domain of AMCNTENCLR0 is IMPLEMENTATION DEFINED. Some or all RW fields of this register have defined reset values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCNTENCLR0 are RES0.
AMCNTENCLR0 is a 32-bit register.
The AMCNTENCLR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P<n>, bit [n] |
Activity monitor event counter disable bit for AMEVCNTR0<n>.
Bits [31:N] are RAZ/WI. N is the value in AMCGCR.CG0NC.
Possible values of each bit are:
P<n> | Meaning |
---|---|
0b0 |
When read, means that AMEVCNTR0<n> is disabled. When written, has no effect. |
0b1 |
When read, means that AMEVCNTR0<n> is enabled. When written, disables AMEVCNTR0<n>. |
On a Cold reset, this field resets to 0.
Component | Offset | Instance |
---|---|---|
AMU | 0xC20 | AMCNTENSET0 |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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