(old) htmldiff from-(new)

AT S1E1RP, Address Translate Stage 1 EL1 Read PAN

The AT S1E1RP characteristics are:

Purpose

Performs a stage 1 address translation, where the value of PSTATE.PAN determines if a read from a location will generate a permission fault for a privileged access, using the following translation regime:

Configuration

This instruction is present only when ARMv8.2-ATS1E1 is implemented. Otherwise, direct accesses to AT S1E1RP are UNDEFINED.

Attributes

AT S1E1RP is a 64-bit System instruction.

Field descriptions

The AT S1E1RP input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Input address for translation
Input address for translation
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing the AT S1E1RP instruction

Accesses to this instruction use the following encodings:

AT S1E1RP, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b010b0000b01110b10010b000
0b010b01110b0000b0000b1001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AT_S1E1RP(X[t]); elsif PSTATE.EL == EL2 then AT_S1E1RP(X[t]); elsif PSTATE.EL == EL3 then AT_S1E1RP(X[t]);




2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-20192010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)