The GICC_HPPIR characteristics are:
Provides the INTID of the highest priority pending interrupt on the CPU interface.
If GICD_CTLR.DS==0:
GICC_HPPIR is a 32-bit register.
The GICC_HPPIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
This register is used only when System register access is not enabled. When System register access is enabled:
If the highest priority pending interrupt is in Group 0, a Non-secure read of this register returns the special INTID 1023.
For Secure reads when GICD_CTLR.DS==0, or for Secure and Non-secure reads when GICD_CTLR.DS==1, returns the special INTID 1022 if the highest priority pending interrupt is in Group 1.
If no interrupts are in the pending state, a read of this register returns the special INTID 1023.
Interrupt identifiers corresponding to an interrupt group that is not enabled are ignored.
If the highest priority pending interrupt is a direct interrupt that is both individually enabled in the Distributor and part of an interrupt group that is enabled in the Distributor, and the interrupt group is disabled in the CPU interface for this PE, this register returns the special INTID 1023.
See Preemption for more information about pending interrupts that are not considered when determining the highest priority pending interrupt.
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x0018 | GICC_HPPIR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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