The ERRGSR characteristics are:
ERRGSR shows the status for the records in the group.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRGSR are UNDEFINED.
This manual describes the memory-mapped view of a group with up to 56 records, the most that can be contained in a 4KB component. Extra records might be added by increasing the page size and extending ERRGSR into multiple registers.
ERRGSR is a 64-bit register.
The ERRGSR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | S<m>, bit [m] | ||||||||||||||||||||||||||||||
S<m>, bit [m] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
The status for Error Record <m>. A read-only copy of ERR<m>STATUS.V.
S<m> | Meaning |
---|---|
0b0 |
No error. |
0b1 |
One or more errors. |
If the corresponding record is not implemented, or the corresponding record does not support this type of reporting, this bit is RES0.
Component | Offset | Instance |
---|---|---|
RAS | 0xE00 | ERRGSR |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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