The PMSCR_EL1 characteristics are:
Provides EL1 controls for Statistical Profiling
This register is present only when SPE is implemented. Otherwise, direct accesses to PMSCR_EL1 are UNDEFINED.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMSCR_EL1 is a 64-bit register.
The PMSCR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PCT | TS | PA | CX | 0 | E1SPE | E0SPE |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Physical Timestamp.
If timestamp sampling is enabled, determines which counter is collected.
PCT | Meaning |
---|---|
0b0 |
Virtual counter, CNTVCT_EL0, is collected. |
0b1 |
Physical counter, CNTPCT_EL0, is collected. |
If EL2 is implemented and enabled in the current Security state:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Timestamp Enable.
TS | Meaning |
---|---|
0b0 |
Timestamp sampling disabled. |
0b1 |
Timestamp sampling enabled. |
If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when MDCR_EL2.E2PB == 0b00.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Physical Address Sample Enable.
PA | Meaning |
---|---|
0b0 |
Physical addresses are not collected. |
0b1 |
Physical addresses are collected. |
If EL2 is implemented and enabled in the current Security state:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
CONTEXTIDR_EL1 Sample Enable.
CX | Meaning |
---|---|
0b0 |
CONTEXTIDR_EL1 is not collected. |
0b1 |
CONTEXTIDR_EL1 is collected. |
If EL2 is implemented and enabled in the current Security state:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EL1 Statistical Profiling Enable.
E1SPE | Meaning |
---|---|
0b0 |
Sampling disabled at EL1. |
0b1 |
Sampling enabled at EL1. |
If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
EL0 Statistical Profiling Enable. Controls sampling at EL0 when HCR_EL2.TGE == 0 or if EL2 is disabled or not implemented.
E0SPE | Meaning |
---|---|
0b0 |
Sampling disabled at EL0. |
0b1 |
Sampling enabled at EL0. |
If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1001 | 0b000 | 0b000 | 0b1001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x828]; else return PMSCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return PMSCR_EL2; else return PMSCR_EL1; elsif PSTATE.EL == EL3 then return PMSCR_EL1;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1001 | 0b000 | 0b000 | 0b1001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x828] = X[t]; else PMSCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then PMSCR_EL2 = X[t]; else PMSCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSCR_EL1 = X[t];
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1001 | 0b101 | 0b000 | 0b1001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x828]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMSCR_EL1; elsif PSTATE.EL == EL3 then return PMSCR_EL1; else UNDEFINED;
op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|
0b11 | 0b1001 | 0b101 | 0b000 | 0b1001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x828] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else PMSCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSCR_EL1 = X[t]; else UNDEFINED;
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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