The CTR_EL0 characteristics are:
Provides information about the architecture of the caches.
AArch64 System register CTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register CTR[31:0] .
CTR_EL0 is a 64-bit register.
The CTR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | TminLine | ||||||||||||||||||||||||||||||
RES1 | RES0 | DIC | IDC | CWG | ERG | DminLine | L1Ip | RES0 | IminLine | ||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Tag minimum Line. Log2 of the number of words covered by Allocation Tags in the smallest cache line of all caches which can contain Allocation tags that are controlled by the PE.
For an implementation with cache lines containing 64 bytes of data and 4 Allocation Tags this will be log2(64/4) = 4.
For an implementation with Allocations Tags in separate cache lines of 128 Allocation Tags per line this will be log2(128*16/4) = 9.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Instruction cache invalidation requirements for instruction to data coherence. The meaning of this bit is:
DIC | Meaning |
---|---|
0b0 |
Instruction cache invalidation to the Point of Unification is required for instruction to data coherence. |
0b1 |
Instruction cache cleaning to the Point of Unification is not required for instruction to data coherence. |
Data cache clean requirements for instruction to data coherence. The meaning of this bit is:
IDC | Meaning |
---|---|
0b0 |
Data cache clean to the Point of Unification is required for instruction to data coherence, unless CLIDR_EL1.LoC == 0b000 or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000). |
0b1 |
Data cache clean to the Point of Unification is not required for instruction to data coherence. |
Cache writeback granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified.
A value of 0b0000 indicates that this register does not provide Cache writeback granule information and either:
Values greater than 0b1001 are reserved.
Arm recommends that an implementation that does not support cache write-back implements this field as 0b0001. This applies, for example, to an implementation that supports only write-through caches.
Exclusives reservation granule. Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions.
A value of 0b0000 indicates that this register does not provide Exclusives reservation granule information and the architectural maximum of 512 words (2KB) must be assumed.
Values greater than 0b1001 are reserved.
Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE.
Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache. Possible values of this field are:
L1Ip | Meaning |
---|---|
0b00 |
VMID aware Physical Index, Physical tag (VPIPT) |
0b01 |
ASID-tagged Virtual Index, Virtual Tag (AIVIVT) |
0b10 |
Virtual Index, Physical Tag (VIPT) |
0b11 |
Physical Index, Physical Tag (PIPT) |
The value 0b01 is reserved in Armv8.
The value 0b00 is permitted only in an implementation that includes ARMv8.2-PIPTV, otherwise the value is reserved.
Reserved, RES0.
Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0000 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.UCT == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HCR_EL2.TID2 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.UCT == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else return CTR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID2 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return CTR_EL0; elsif PSTATE.EL == EL2 then return CTR_EL0; elsif PSTATE.EL == EL3 then return CTR_EL0;
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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