The AMCR characteristics are:
Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups.
External register AMCR bits [31:0] are architecturally mapped to AArch64 System register AMCR_EL0[31:0] .
External register AMCR bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0] .
The power domain of AMCR is IMPLEMENTATION DEFINED.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCR are RES0.
AMCR is a 32-bit register.
The AMCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | HDBG | RAZ/WI |
Reserved, RES0.
This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.
HDBG | Meaning |
---|---|
0b0 |
Activity monitors do not halt counting when the PE is halted in Debug state. |
0b1 |
Activity monitors halt counting when the PE is halted in Debug state. |
Reserved, RAZ/WI.
Component | Offset | Instance |
---|---|---|
AMU | 0xE04 | AMCR |
Access on this interface is RO.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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