The TLBI VMALLE1IS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry, from any level of the translation table walk.
When EL2 is implemented and enabled in the current Security state:
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
From Armv8.4, when a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
TLBI VMALLE1IS is a 64-bit System instruction.
TLBI VMALLE1IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
Rt | op0 | op1 | op2 | CRn | CRm |
---|---|---|---|---|---|
0b11111 | 0b01 | 0b000 | 0b000 | 0b1000 | 0b0011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_VMALLE1IS(); elsif PSTATE.EL == EL2 then TLBI_VMALLE1IS(); elsif PSTATE.EL == EL3 then TLBI_VMALLE1IS();
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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