AT S12E0R, Address Translate Stages 1 and 2 EL0 Read

The AT S12E0R characteristics are:

Purpose

Performs stage 1 and 2 address translations from EL0, with permissions as if reading from the given virtual address from EL0, using the following translation regime:

Configuration

Attributes

AT S12E0R is a 64-bit System instruction.

Field descriptions

The AT S12E0R input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Input address for translation
Input address for translation
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing the AT S12E0R instruction

Accesses to this instruction use the following encodings:

AT S12E0R, <Xt>

op0op1CRnCRmop2
0b010b1000b01110b10000b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' || HCR_EL2.<DC,VM> == '00' then AT_S1E0R(X[t]); else AT_S12E0R(X[t]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then AT_S1E0R(X[t]); elsif EL2Enabled() && (HCR_EL2.<E2H,TGE> == '11' || HCR_EL2.<DC,VM> == '00') then AT_S1E0R(X[t]); else AT_S12E0R(X[t]);




27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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