The PMMIR characteristics are:
Describes Performance Monitors parameters specific to the implementation.
PMMIR is in the Core power domain.
This register is present only when ARMv8.4-PMU is implemented. Otherwise, direct accesses to PMMIR are RES0.
PMMIR is a 32-bit register.
The PMMIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SLOTS |
Reserved, RES0.
Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is implemented, this field must not be zero.
If the Core power domain is off or in a low-power state, access on this interface returns an Error.
Component | Offset | Instance |
---|---|---|
PMU | 0xE40 | PMMIR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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