The AMPIDR3 characteristics are:
Provides information to identify an activity monitors component.
For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The power domain of AMPIDR3 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMPIDR3 are RES0.
AMPIDR3 is a 32-bit register.
The AMPIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | REVAND | CMOD |
Reserved, RES0.
Part minor revision. Parts using AMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.
The value of this field is IMPLEMENTATION DEFINED.
Customer modified. Indicates someone other than the Designer has modified the component.
The value of this field is IMPLEMENTATION DEFINED.
Component | Offset | Instance |
---|---|---|
AMU | 0xFEC | AMPIDR3 |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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