The ITLBIASID characteristics are:
Invalidate all cached copies of translation table entries from instruction TLBs that meet the following requirements:
From the entries that match these requirement, the entries that are invalidated are required for the following translation regime:
The invalidation only applies to the PE that executes this instruction.
Arm deprecates the use of this instruction. It is only provided for backwards compatibility with earlier versions of the Arm architecture.
ITLBIASID is a 32-bit System instruction.
The ITLBIASID input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ASID |
Reserved, RES0.
ASID value to match. Any TLB entries for non-global pages that match the ASID values will be affected by this operation.
Accesses to this instruction use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b000 | 0b010 | 0b1000 | 0b1111 | 0b0101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TTLB == '1' then AArch32.TakeHypTrapException(0x03); else ITLBIASID(R[t]); elsif PSTATE.EL == EL2 then ITLBIASID(R[t]); elsif PSTATE.EL == EL3 then ITLBIASID(R[t]);
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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