The ERRCIDR1 characteristics are:
Provides discovery information for the component.
Implementation of this register is OPTIONAL.
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRCIDR1 are RES0.
ERRCIDR1 is a 32-bit register.
The ERRCIDR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class.
CLASS | Meaning |
---|---|
0b1111 |
Generic peripheral with IMPLEMENTATION DEFINED register layout. |
This field reads as 0xF.
Other values are defined by the CoreSight Architecture.
Component identification preamble, segment 1. This field reads as 0x0.
Component | Offset | Instance |
---|---|---|
RAS | 0xFF4 | ERRCIDR1 |
Access on this interface is RO.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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