The TLBIMVALHIS characteristics are:
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from the final level of the translation table walk that would be required for the Non-secure EL2 translation regime and used to translate the specified address.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
This System instruction is not implemented in architecture versions before Armv8.
TLBIMVALHIS is a 32-bit System instruction.
The TLBIMVALHIS input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this operation.
Reserved, RES0.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
Accesses to this instruction use the following encodings:
opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|
0b100 | 0b101 | 0b1000 | 0b1111 | 0b0011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBIMVALHIS(R[t]); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then UNDEFINED; else TLBIMVALHIS(R[t]);
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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