The MPAMF_ESR characteristics are:
MPAMF_ESR is a 32-bit read-write register that give MPAM error status for this MSC.
Software should write this register after reading the status of an error to reset ERRCODE to 0x0000 and OVRWR to 0 so that future errors are not reported with OVRWR set.
The power domain of MPAMF_ESR is IMPLEMENTATION DEFINED.
If a MSC cannot encounter any of the error conditions listed in section 15.1, both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.
MPAMF_ESR is a 32-bit register.
The MPAMF_ESR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVRWR | RES0 | ERRCODE | PMG | PARTID_MON |
Overwritten.
If 0 and ERRCODE == 0b0000, no errors have occurred.
If 0 and ERRCODE is non-zero, a single error has occurred and is recorded in this register.
If 1 and ERRCODE is non-zero, multiple errors have occurred and this register records the most recent error.
The state where this bit is 1 and ERRCODE is zero must not be produced by hardware and is only reached when software writes this combination into this register.
Reserved, RES0.
Error code. See section 15.1
ERRCODE | Meaning |
---|---|
0b0000 |
No error |
0b0001 |
PARTID_SEL_Range |
0b0010 |
Req_PARTID_Range |
0b0011 |
MSMONCFG_ID_RANGE |
0b0100 |
Req_PMG_Range |
0b0101 |
Monitor_Range |
0b0110 |
intPARTID_Range |
0b0111 |
Unexpected_INTERNAL |
0b1000 |
Reserved |
0b1001 |
Reserved |
0b1010 |
Reserved |
0b1011 |
Reserved |
0b1100 |
Reserved |
0b1101 |
Reserved |
0b1110 |
Reserved |
0b1111 |
Reserved |
Program monitoring group.
Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG.
PARTID or monitor.
Set to the PARTID on an error that captures PARTID.
Set to the monitor index on an error that captures MON.
On an error that captures neither PARTID nor MON, this field is set to 0x0000.
This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.
MPAMF_ESR must be accessible from the Non-secure and Secure address maps.
MPAMF_ESR must be banked for the Secure and Non-secure address maps. The Secure instance accesses the error status used for Secure PARTIDs, and the Non-secure instance accesses the error status used for Non-secure PARTIDs.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_s | 0x00F8 | MPAMF_ESR_s |
Access on this interface is RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM.any | MPAMF_BASE_ns | 0x00F8 | MPAMF_ESR_ns |
Access on this interface is RW.
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
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