The CTIINEN<n> characteristics are:
Enables the signaling of an event on output channels when input trigger event n is received by the CTI.
CTIINEN<n> is in the Debug power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
If input trigger n is not connected, the behavior of CTIINEN<n> is IMPLEMENTATION DEFINED.
CTIINEN<n> is a 32-bit register.
The CTIINEN<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INEN<x>, bit [x] |
Input trigger <n> to output channel <x> enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
Possible values of this bit are:
INEN<x> | Meaning |
---|---|
0b0 |
Input trigger <n> will not generate an event on output channel <x>. |
0b1 |
Input trigger <n> will generate an event on output channel <x>. |
On a External debug reset, this field resets to an architecturally UNKNOWN value.
Component | Offset | Instance |
---|---|---|
CTI | 0x020 + 4n | CTIINEN<n> |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.