The ERR<n>PFGCDN characteristics are:
Generates one of the errors enabled in the corresponding ERR<n>PFGCTL register.
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERR<n>PFGCDN are RES0.
Present only when the RAS Common Fault Injection Model Extension is implemented by this node so that ERR<n>FR.INJ != 0b00, error record <n> is implemented, and error record <n> is the first error record owned by a node. Otherwise, RES0.
ERR<n>FR describes the features implemented by the node.
ERR<n>PFGCDN is a 64-bit register.
The ERR<n>PFGCDN bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
CDN | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Countdown value.
This field is copied to Error Generation Counter when either:
While ERR<n>PFGCTL.CDNEN == 1 and the Error Generation Counter is nonzero, the counter decrements by 1 for each cycle at an IMPLEMENTATION DEFINED clock rate. When the counter reaches 0, one of the errors enabled in the ERR<n>PFGCTL register is generated.
The current Error Generation Counter value is not visible to software.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Component | Offset | Instance |
---|---|---|
RAS | 0x810 + 64n | ERR<n>PFGCDN |
Access on this interface is RW.
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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