The GICV_STATUSR characteristics are:
Provides software with a mechanism to detect:
In systems where this register is implemented, Arm expects that when a virtual machine is scheduled, the hypervisor ensures that this register is cleared to 0. The hypervisor might check for illegal accesses when the virtual machine is unscheduled.
GICV_STATUSR is a 32-bit register.
The GICV_STATUSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | WROD | RWOD | WRD | RRD |
Reserved, RES0.
Write to an RO location.
WROD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to an RO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Read of a WO location.
RWOD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a WO location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Write to a reserved location.
WRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A write to a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
Read of a reserved location.
RRD | Meaning |
---|---|
0b0 |
Normal operation. |
0b1 |
A read of a reserved location has been detected. |
When a violation is detected, software must write 1 to this register to reset it.
This is an optional register. If the register is implemented, GICC_STATUSR must also be implemented. If the register is not implemented, the location is RAZ/WI.
This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent function might be provided by appropriate traps and exceptions.
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x002C | GICV_STATUSR |
This interface is accessible as follows:
27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.