The GICC_DIR characteristics are:
When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt.
GICC_DIR is a 32-bit register.
The GICC_DIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
This register is used only when System register access is not enabled. When System register access is enabled:
Writes to this register have an effect only in the following cases:
The following writes must be ignored:
If the corresponding EOImode field in GICC_CTLR is 1 and this register is written to without a corresponding write to GICC_EOIR or GICC_AEOIR, the interrupt is deactivated but the bit corresponding to it in the active priorities registers remains set.
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x1000 | GICC_DIR |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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