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PMSCR_EL1, Statistical Profiling Control Register (EL1)

The PMSCR_EL1 characteristics are:

Purpose

Provides EL1 controls for Statistical Profiling

Configuration

This register is present only when SPE is implemented. Otherwise, direct accesses to PMSCR_EL1 are UNDEFINED.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PMSCR_EL1 is a 64-bit register.

Field descriptions

The PMSCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0PCTTSPACXRES0E1SPEE0SPE
313029282726252423222120191817161514131211109876543210
6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000000000000000000000000PCTTSPACX0E1SPEE0SPE
313029282726252423222120191817161514131211109876543210

Bits [63:7]

Reserved, RES0.

PCT, bit [6]

When HaveEL(EL2):

Physical Timestamp.

If timestamp sampling is enabled, determines which counter is collected.

PCTMeaning
0b0

Virtual counter, CNTVCT_EL0, is collected.

0b1

Physical counter, CNTPCT_EL0, is collected.

If EL2 is implemented and enabled in the current Security state:

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES1.

TS, bit [5]

Timestamp Enable.

TSMeaning
0b0

Timestamp sampling disabled.

0b1

Timestamp sampling enabled.

If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when MDCR_EL2.E2PB == 0b00.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

PA, bit [4]

Physical Address Sample Enable.

PAMeaning
0b0

Physical addresses are not collected.

0b1

Physical addresses are collected.

If EL2 is implemented and enabled in the current Security state:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CX, bit [3]

CONTEXTIDR_EL1 Sample Enable.

CXMeaning
0b0

CONTEXTIDR_EL1 is not collected.

0b1

CONTEXTIDR_EL1 is collected.

If EL2 is implemented and enabled in the current Security state:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [2]

Reserved, RES0.

E1SPE, bit [1]

EL1 Statistical Profiling Enable.

E1SPEMeaning
0b0

Sampling disabled at EL1.

0b1

Sampling enabled at EL1.

If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

E0SPE, bit [0]

EL0 Statistical Profiling Enable. Controls sampling at EL0 when HCR_EL2.TGE == 0 or if EL2 is disabled or not implemented.

E0SPEMeaning
0b0

Sampling disabled at EL0.

0b1

Sampling enabled at EL0.

If EL2 is implemented and enabled in the current Security state, this bit is ignored by the PE when HCR_EL2.TGE == 1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the PMSCR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, PMSCR_EL1

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b10010b10010b000
0b110b10010b0000b0000b1001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x828]; else return PMSCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return PMSCR_EL2; else return PMSCR_EL1; elsif PSTATE.EL == EL3 then return PMSCR_EL1;

MSR PMSCR_EL1, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b0000b10010b10010b000
0b110b10010b0000b0000b1001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x828] = X[t]; else PMSCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then PMSCR_EL2 = X[t]; else PMSCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSCR_EL1 = X[t];

MRS <Xt>, PMSCR_EL12

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b1010b10010b10010b000
0b110b10010b1010b0000b1001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x828]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMSCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then return PMSCR_EL1; else else UNDEFINED;

MSR PMSCR_EL12, <Xt>

op0op1CRnCRmop2
op0CRnop1op2CRm
0b110b1010b10010b10010b000
0b110b10010b1010b0000b1001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x828] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else PMSCR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then PMSCR_EL1 = X[t]; else else UNDEFINED;




2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009

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