The GICD_ISENABLER<n> characteristics are:
Enables forwarding of the corresponding interrupt to the CPU interfaces.
RW fields in this register reset to architecturally UNKNOWN values.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
The number of implemented GICD_ISENABLER<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_ISENABLER0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ISENABLER0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
GICD_ISENABLER<n> is a 32-bit register.
The GICD_ISENABLER<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Set_enable_bit<x>, bit [x], for x = 0 to 31 |
For SPIs and PPIs, controls the forwarding of interrupt number 32n + x to the CPU interfaces. Reads and writes have the following behavior:
Set_enable_bit<x> | Meaning |
---|---|
0b0 |
If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
0b1 |
If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1. |
For SGIs, the behavior of this bit is IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
For INTID m, when DIV and MOD are the integer division and modulo operations:
At start-up, and after a reset, a PE can use this register to discover which peripheral INTIDs the GIC supports. If GICD_CTLR.DS==0 in a system that supports EL3, the PE must do this for the Secure view of the available interrupts, and Non-secure software running on the PE must do this discovery after the Secure software has configured interrupts as Group 0/Secure Group 1 and Non-secure Group 1.
For SGIs and PPIs:
Bits corresponding to unimplemented interrupts are RAZ/WI.
When GICD_CTLR.DS==0, bits corresponding to Group 0 or Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.
It is IMPLEMENTATION DEFINED whether implemented SGIs are permanently enabled, or can be enabled and disabled by writes to GICD_ISENABLER<n> and GICD_ICENABLER<n> where n=0.
For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x0100 + 4n | GICD_ISENABLER<n> |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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