The PMINTENSET_EL1 characteristics are:
Enables the generation of interrupt requests on overflows from the Cycle Count Register, PMCCNTR_EL0, and the event counters PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.
External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[31:0] .
External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENSET[31:0] .
PMINTENSET_EL1 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMINTENSET_EL1 is a 32-bit register.
The PMINTENSET_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P<n>, bit [n] |
PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are:
C | Meaning |
---|---|
0b0 |
When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means the cycle counter overflow interrupt request is enabled. When written, enables the cycle count overflow interrupt request. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Event counter overflow interrupt request enable bit for PMEVCNTR<n>_EL0.
If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.
P<n> | Meaning |
---|---|
0b0 |
When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, enables the PMEVCNTR<n>_EL0 interrupt request. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0xC40 | PMINTENSET_EL1 |
This interface is accessible as follows:
13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009
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