System Register XML
for Armv8.5
(00bet10)
28th March 2019
1. Introduction
This is the 00bet10 release
of the System Register XML for Armv8.5, describing:
-
The AArch64 and AArch32 views of the System registers
(including Debug, PMU, Generic Timer, and GIC).
-
The AArch32 and AArch32 system control operations.
-
The memory-mapped Debug, CTI, PMU, GIC, and Generic Timer registers.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "System Register XML for Armv8.5".
- The version, "00bet10".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
2. Contents
3. Release notes
Change history
-
Introduced the ARMv8.5-CP15DISABLE2 feature.
-
The description of PMU event counter ranges in MDCR_EL2.HPMN and associated registers has been corrected.
-
Clarified the reset value of the HCPTR.TAM field.
-
Corrected the description of the ID_AA64DFR0_EL1.DoubleLock, which identifies the presence of the OS Double Lock feature.
-
The behavior of reading APSR has been relaxed such that some bits are UNKNOWN.
-
Refinements to the descriptions of the Secure EL2 Generic timers.
-
Corrections to the mappings between DFAR, HDFAR, HIFAR, and IFAR.
-
Many simple clarifications and corrections are also present,
but are too small to be listed here. These can be seen in the
Change Markup PDF provided.
Known issues
-
The accessibility pseudocode for ID registers does not
explicitly describe the effect of the ARMv8.4-IDST feature on
the ESR_ELx.EC codes used for reads when an exception is
generated.
-
The memory-mapped Generic Timer register descriptions have
incorrect information, and so must not be relied upon.
This will be corrected in a future release. The definitive
source for these registers is the Arm Architecture Reference
Manual Armv8, for Armv8-A architecture profile.
-
There are differences in the GIC registers in this XML package
when compared to the GIC register descriptions in the Generic
Interrupt Controller Architecture Specification document. The
definitive source for these registers is the document, and
there will be corrections to these registers in the next
release.
-
There are stylistic differences in the descriptions of some
areas (e.g. ID register fields) for Armv8.3 when compared to
equivalent descriptions for earlier architectures. These
will be made consistent in a future release.
4. Documentation
General
A description within the XML contains the following sections:
- Purpose
-
A short description of the purpose of the register in the
Armv8 Architecture.
- Configuration
-
How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here. This section also
summarizes the behavior of the register on a reset.
- Attributes
-
The size of the register. For registers where the layouts of
the fields differ based on configuration, or other state
within the PE, this section also summarizes the different
layouts.
- Field descriptions
-
The register diagram, and a description of the behavior of
each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Accessing the ...
-
The address or offset of the register in the memory map, and
the accessibility.
System registers
A System register description also contains an "Accessing the
..." section, that includes:
-
The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
-
Pseudocode that describes the execution of all instructions
used to access the register, including information about
traps and enables that apply upon that access.
-
For some System registers, additional text is provided which
gives extra information regarding the access to the
register.
-
The accessibility pseudocode for a register assumes that
that register is implemented and that all features which
affects its accesses are implemented. In most cases, the
behaviour upon access to a register is determined in part or
in whole by the Exceptional Level at which it is accessed,
and so the pseudocode is structured around this assumption.