RVBAR_EL3, Reset Vector Base Address Register (if EL3 implemented)

The RVBAR_EL3 characteristics are:

Purpose

If EL3 is the highest Exception level implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch64 state.

Configuration

Only implemented if the highest Exception level implemented is EL3.

Attributes

RVBAR_EL3 is a 64-bit register.

Field descriptions

The RVBAR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Reset Address
Reset Address
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Reset Address. The IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 00, as this address must be aligned, and the address must be within the physical address size supported by the PE.

Accessing the RVBAR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, RVBAR_EL3

op0CRnop1op2CRm
0b110b11000b1100b0010b0000

if PSTATE.EL == EL3 && IsHighestEL(EL3) then return RVBAR_EL3; else UNDEFINED;




13/12/2018 16:42; 6379d01c197f1d40720d32d0f84c419c9187c009

Copyright © 2010-2018 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.