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The PMSEVFR_EL1 characteristics are:
Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 set (TLB walk) are recorded
This register is present only when SPE is implemented. Otherwise, direct accesses to PMSEVFR_EL1 are UNDEFINED.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMSEVFR_EL1 is a 64-bit register.
The PMSEVFR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
E[<z>], bit [z] | RAZ/WI | ||||||||||||||||||||||||||||||
E[<y>], bit [y] | RAZ/WI | E[18] | E[17] | RAZ/WI | E[<x>], bit [x] | E[11] | RAZ/WI | E[7] | RAZ/WI | E[5] | RAZ/WI | E[3] | RAZ/WI | E[1] | RAZ/WI | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E[<z>] is the event filter for event <z>. If event <z> is not implemented, or filtering on event <z> is not supported, the corresponding bit is RAZ/WI.
E[<z>] | Meaning |
---|---|
0b0 | Event <z> is ignored. |
0b1 | Do not record samples that have event <z> == 0. |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
E[<y>] is the event filter for event <y>. If event <y> is not implemented, or filtering on event <y> is not supported, the corresponding bit is RAZ/WI.
E[<y>] | Meaning |
---|---|
0b0 | Event <y> is ignored. |
0b1 | Do not record samples that have event <y> == 0. |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Empty predicate.
E[18] | Meaning |
---|---|
0b0 | Empty predicate event is ignored. |
0b1 | Do not record samples that have the Empty predicate event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Partial predicate.
E[17] | Meaning |
---|---|
0b0 | Partial predicate event is ignored. |
0b1 | Do not record samples that have the Partial predicate event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Reserved, RAZ/WI.
E[<x>] is the event filter for event <x>. If event <x> is not implemented, or filtering on event <x> is not supported, the corresponding bit is RAZ/WI.
E[<x>] | Meaning |
---|---|
0b0 | Event <x> is ignored. |
0b1 | Do not record samples that have event <x> == 0. |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Alignment.
E[11] | Meaning |
---|---|
0b0 | Alignment event is ignored. |
0b1 | Do not record samples that have the Alignment event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Mispredicted.
E[7] | Meaning |
---|---|
0b0 | Mispredicted event is ignored. |
0b1 | Do not record samples that have the Mispredicted event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
TLB walk.
E[5] | Meaning |
---|---|
0b0 | TLB walk event is ignored. |
0b1 | Do not record samples that have the TLB walk event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Level 1 data or unified cache refill.
E[3] | Meaning |
---|---|
0b0 | Level 1 data or unified cache refill event is ignored. |
0b1 | Do not record samples that have the Level 1 data or unified cache refill event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Architecturally retired.
When the PE supports sampling of speculative instructions:
E[1] | Meaning |
---|---|
0b0 | Architecturally retired event is ignored. |
0b1 | Do not record samples that have the Architecturally retired event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
If the PE does not support the sampling of speculative instructions, or always discards the sample record for speculative instructions, this bit reads as an UNKNOWN value and the PE ignores its value.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, UNKNOWN.
Reserved, RAZ/WI.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
return NVMem[0x830];
else
return PMSEVFR_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMSEVFR_EL1;
elsif PSTATE.EL == EL3 then
return PMSEVFR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
NVMem[0x830] = X[t];
else
PMSEVFR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NSSCR_ELR.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMSEVFR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
PMSEVFR_EL1 = X[t];
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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