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The NSACR characteristics are:
When EL3 is implemented and can use AArch32, defines the Non-secure access permissions to Trace, Advanced SIMD and floating-point functionality. Also includes IMPLEMENTATION DEFINED bits that can define Non-secure access permissions for IMPLEMENTATION DEFINED functionality.
In AArch64 state, the NSACR controls are replaced by controls in CPTR_EL3.
Some or all RW fields of this register have defined reset values. These apply whenever the register is accessible. This means they apply when the PE resets into EL3 using AArch32.
NSACR is a 32-bit register.
The NSACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | NSTRCDIS | RES0 | IMPLEMENTATION DEFINED | NSASEDIS | RES0 | cp11 | cp10 | RES0 |
If EL3 is implemented and is using AArch64 then:
If EL3 is not implemented, then any read of the NSACR from EL2 or EL1 returns a value of 0x00000C00.
Reserved, RES0.
Disables Non-secure System register accesses to all implemented trace registers.
NSTRCDIS | Meaning |
---|---|
0b0 | This control has no effect on: |
0b1 | Non-secure System register accesses to all implemented trace registers are disabled, meaning: |
The implementation of this field must correspond to the implementation of the CPACR.TRCDIS field:
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
In a system where the PE resets into EL3, this field resets to 0.
Reserved, RES0.
IMPLEMENTATION DEFINED.
Disables Non-secure access to the Advanced SIMD functionality.
NSASEDIS | Meaning |
---|---|
0b0 | This control has no effect on: |
0b1 | Non-secure access to the Advanced SIMD functionality is disabled, meaning: |
The implementation of this field must correspond to the implementation of the CPACR.ASEDIS field:
In a system where the PE resets into EL3, this field resets to 0.
Reserved, RES0.
The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the NSACR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Enable Non-secure access to the Advanced SIMD and floating-point features. Possible values of the fields are:
cp10 | Meaning |
---|---|
0b0 | Advanced SIMD and floating-point features can be accessed only from Secure state. Any attempt to access this functionality from Non-secure state is UNDEFINED. When the PE is in Non-secure state: |
0b1 | Advanced SIMD and floating-point features can be accessed from both Security states. |
If Non-secure access to the Advanced SIMD and floating-point functionality is enabled, the CPACR must be checked to determine the level of access that is permitted.
The Advanced SIMD and floating-point features controlled by these fields are:
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif !HaveEL(EL3) || (!ELUsingAArch32(EL3) && SCR_EL3.NS == '1') then return Zeros(20):'1100':Zeros(8); else return NSACR; elsif PSTATE.EL == EL2 then if !HaveEL(EL3) || (!ELUsingAArch32(EL3) && SCR_EL3.NS == '1') then return Zeros(20):'1100':Zeros(8); else return NSACR; elsif PSTATE.EL == EL3 then return NSACR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; else NSACR = R[t];
2713/0312/20192018 2116:5942; e5e4db499bf9867a4b93324c4dbac985d3da93766379d01c197f1d40720d32d0f84c419c9187c009
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