(old) | htmldiff from- | (new) |
Unsigned saturating shift left by immediate.
Shift left by immediate each active unsigned element of the source vector, and destructively place the results in the corresponding elements of the source vector. Each result element is saturated to the N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | tszh | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Pg | tszl | imm3 | Zdn |
if !HaveSVE2() then UNDEFINED; bits(4) tsize = tszh:tszl; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer g = UInt(Pg); integer dn = UInt(Zdn); integer shift = UInt(tsize:imm3) - esize;
<Zdn> | Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
tszh:tszl:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<const> | Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tsz:imm3". |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[dn]; bits(PL) mask = P[g]; bits(VL) result; for e = 0 to elements-1 integer element1 = UInt(Elem[operand1, e, esize]); if ElemP[mask, e, esize] == '1' then integer res = element1 << shift; Elem[result, e, esize] = UnsignedSat(res, esize); else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn] = result;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5
; Build timestamp: 2019-06-26T222019-04-17T09:0458
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |