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RAX1

Rotate and Exclusive OR rotates each 64-bit element of the 128-bit vector in a source SIMD&FP register left by 1, performs a bitwise exclusive OR of the resulting 128-bit vector and the vector in another source SIMD&FP register, and writes the result to the destination SIMD&FP register.

This instruction is implemented only when ARMv8.2-SHA is implemented.

Advanced SIMD
(Armv8.2)

313029282726252423222120191817161514131211109876543210
11001110011Rm100011RnRd

Advanced SIMD

RAX1 <Vd>.2D, <Vn>.2D, <Vm>.2D

if !HaveSHA3Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m]; bits(128) Vn = V[n]; V[d] = Vn EOR (ROL(Vm<127:64>, 1):(Vm<127:64>,1):ROL(Vm<63:0>, 1));

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:3004

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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