STTR

Store Register (unprivileged) stores a word or doubleword from a register to memory. The address that is used for the store is calculated from a base register and an immediate offset.

Memory accesses made by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:

Otherwise, the memory access operates with the restrictions determined by the Exception level at which the instruction is executed. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
1x111000000imm910RnRt
sizeopc

32-bit (size == 10)

STTR <Wt>, [<Xn|SP>{, #<simm>}]

64-bit (size == 11)

STTR <Xt>, [<Xn|SP>{, #<simm>}]

integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); unpriv_at_el1 = PSTATE.EL == EL1 && !(EL2Enabled() && HaveNVExt() && HCR_EL2.<NV,NV1> == '11'); unpriv_at_el2 = PSTATE.EL == EL2 && HaveVirtHostExt() && HCR_EL2.<E2H,TGE> == '11'; user_access_override = HaveUAOExt() && PSTATE.UAO == '1'; if !user_access_override && (unpriv_at_el1 || unpriv_at_el2) then acctype = AccType_UNPRIV; else acctype = AccType_NORMAL; integer datasize = 8 << scale; boolean tag_checked = n != 31;

Operation

if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); bits(64) address; bits(datasize) data; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; address = address + offset; data = X[t]; Mem[address, datasize DIV 8, acctype] = data;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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