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Bitwise Insert if True. This instruction inserts each bit from the first source SIMD&FP register into the SIMD&FP destination register if the corresponding bit of the second source SIMD&FP register is 1, otherwise leaves the bit in the destination register unchanged.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | Rm | 0 | 0 | 0 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
opc2 |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer datasize = if Q == '1' then 128 else 64;integer esize = 8;
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;VBitOp op;
case opc2 of
when '00' op = VBitOp_VEOR;
when '01' op = VBitOp_VBSL;
when '10' op = VBitOp_VBIT;
when '11' op = VBitOp_VBIF;
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
Q:
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1;
bits(datasize) operand2;
bits(datasize) operand3;
bits(datasize) operand4 = V[n];
operand1 =case op of
when VBitOp_VEOR
operand1 = V[m];
operand2 = Zeros();
operand3 = Ones();
when VBitOp_VBSL
operand1 = V[m];
operand2 = operand1;
operand3 = V[d];
when VBitOp_VBIT
operand1 = V[d];
operand2 = operand1;
operand3 = V[m];
when VBitOp_VBIF
operand1 = V[d];
operand3 = operand2 = operand1;
operand3 = NOT( V[m];[m]);
V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
If PSTATE.DIT is 1:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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