LDRSW (literal)

Load Register Signed Word (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
10011000imm19Rt
opc

Literal

LDRSW <Xt>, <label>

integer t = UInt(Rt); MemOp memop = MemOp_LOAD; boolean signed = FALSE; integer size; bits(64) offset; case opc of when '00' size = 4; when '01' size = 8; when '10' size = 4; signed = TRUE; when '11' memop = MemOp_PREFETCH; offset = SignExtend(imm19:'00', 64); boolean tag_checked = FALSE;

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<label>

Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

Operation

bits(64) address = PC[] + offset; bits(size*8) data; if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); case memop of when MemOp_LOAD data = Mem[address, size, AccType_NORMAL]; if signed then X[t] = SignExtend(data, 64); else X[t] = data; when MemOp_PREFETCH Prefetch(address, t<4:0>);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:04

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.