Signed byte / halfword / word extend (predicated).
Sign-extend the least-significant sub-element of each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.
It has encodings from 3 classes: Byte , Halfword and Word
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer s_esize = 8; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
if !HaveSVE() then UNDEFINED; if size != '1x' then UNDEFINED; integer esize = 8 << UInt(size); integer s_esize = 16; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
if !HaveSVE() then UNDEFINED; if size != '11' then UNDEFINED; integer esize = 8 << UInt(size); integer s_esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = FALSE;
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
For the byte variant: is the size specifier,
encoded in
size:
| ||||||||||
For the halfword variant: is the size specifier,
encoded in
size<0>:
|
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(esize) element = Elem[operand, e, esize]; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = Extend(element<s_esize-1:0>, esize, unsigned); Z[d] = result;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.