MLS (by element)
Multiply-Subtract from accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 0 | 1 | 0 | 0 | H | 0 | Rn | Rd |
| | | | | | | | | o2 | | | | | |
integer idxdsize = if H == '1' then 128 else 64;
integer index;
bit Rmhi;
case size of
when '01' index = UInt(H:L:M); Rmhi = '0';
when '10' index = UInt(H:L); Rmhi = M;
otherwise UNDEFINED;
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rmhi:Rm);
integer esize = 8 << UInt(size);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
boolean sub_op = (o2 == '1');
Assembler Symbols
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
size:Q :
size | Q | <T> |
---|
00 | x | RESERVED | 01 | 0 | 4H | 01 | 1 | 8H | 10 | 0 | 2S | 10 | 1 | 4S | 11 | x | RESERVED |
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register,
encoded in
size:M:Rm :
size | <Vm> |
---|
00 | RESERVED | 01 | 0:Rm | 10 | M:Rm | 11 | RESERVED |
Restricted to V0-V15 when element size <Ts> is H.
|
<Ts> |
Is an element size specifier,
encoded in
size :
size | <Ts> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | RESERVED |
|
<index> |
Is the element index,
encoded in
size:L:H:M :
size | <index> |
---|
00 | RESERVED | 01 | H:L:M | 10 | H:L | 11 | RESERVED |
|
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
integer element1;
integer element2;
bits(esize) product;
element2 = UInt(Elem[operand2, index, esize]);
for e = 0 to elements-1
element1 = UInt(Elem[operand1, e, esize]);
product = (element1*element2)<esize-1:0>;
product = (element1 * element2)<esize-1:0>;
if sub_op then
Elem[result, e, esize] = Elem[operand3, e, esize] - product;
else
Elem[result, e, esize] = Elem[operand3, e, esize] + product;
V[d] = result;
Operational information
If PSTATE.DIT is 1:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
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