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TLBI

TLB Invalidate operation. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.

This is an alias of SYS. This means:

313029282726252423222120191817161514131211109876543210
1101010100001op11000CRmop2Rt
LCRn

System

TLBI <tlbi_op>{, <Xt>}

is equivalent to

SYS #<op1>, C8, <Cm>, #<op2>{, <Xt>}

and is the preferred disassembly when SysOp(op1,'1000',CRm,op2) == Sys_TLBI.

Assembler Symbols

<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cm>

Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<tlbi_op> Is a TLBI instruction name, as listed for the TLBI system instruction group, encoded in op1:CRm:op2:
op1CRmop2<tlbi_op>Architectural Feature
0000001000VMALLE1OS ARMv8.4-TLBI
0000001001VAE1OS ARMv8.4-TLBI
0000001010ASIDE1OS ARMv8.4-TLBI
0000001011VAAE1OS ARMv8.4-TLBI
0000001101VALE1OS ARMv8.4-TLBI
0000001111VAALE1OS ARMv8.4-TLBI
0000010001RVAE1IS ARMv8.4-TLBI
0000010011RVAAE1IS ARMv8.4-TLBI
0000010101RVALE1IS ARMv8.4-TLBI
0000010111RVAALE1IS ARMv8.4-TLBI
0000011000VMALLE1IS -
0000011001VAE1IS -
0000011010ASIDE1IS -
0000011011VAAE1IS -
0000011101VALE1IS -
0000011111VAALE1IS -
0000101001RVAE1OS ARMv8.4-TLBI
0000101011RVAAE1OS ARMv8.4-TLBI
0000101101RVALE1OS ARMv8.4-TLBI
0000101111RVAALE1OS ARMv8.4-TLBI
0000110001RVAE1 ARMv8.4-TLBI
0000110011RVAAE1 ARMv8.4-TLBI
0000110101RVALE1 ARMv8.4-TLBI
0000110111RVAALE1 ARMv8.4-TLBI
0000111000VMALLE1 -
0000111001VAE1 -
0000111010ASIDE1 -
0000111011VAAE1 -
0000111101VALE1 -
0000111111VAALE1 -
1000000001IPAS2E1IS -
1000000010RIPAS2E1IS ARMv8.4-TLBI
1000000101IPAS2LE1IS -
1000000110RIPAS2LE1IS ARMv8.4-TLBI
1000001000ALLE2OS ARMv8.4-TLBI
1000001001VAE2OS ARMv8.4-TLBI
1000001100ALLE1OS ARMv8.4-TLBI
1000001101VALE2OS ARMv8.4-TLBI
1000001110VMALLS12E1OS ARMv8.4-TLBI
1000010001RVAE2IS ARMv8.4-TLBI
1000010101RVALE2IS ARMv8.4-TLBI
1000011000ALLE2IS -
1000011001VAE2IS -
1000011100ALLE1IS -
1000011101VALE2IS -
1000011110VMALLS12E1IS -
1000100000IPAS2E1OS ARMv8.4-TLBI
1000100001IPAS2E1 -
1000100010RIPAS2E1 ARMv8.4-TLBI
1000100011RIPAS2E1OS ARMv8.4-TLBI
1000100100IPAS2LE1OS ARMv8.4-TLBI
1000100101IPAS2LE1 -
1000100110RIPAS2LE1 ARMv8.4-TLBI
1000100111RIPAS2LE1OS ARMv8.4-TLBI
1000101001RVAE2OS ARMv8.4-TLBI
1000101101RVALE2OS ARMv8.4-TLBI
1000110001RVAE2 ARMv8.4-TLBI
1000110101RVALE2 ARMv8.4-TLBI
1000111000ALLE2 -
1000111001VAE2 -
1000111100ALLE1 -
1000111101VALE2 -
1000111110VMALLS12E1 -
1100001000ALLE3OS ARMv8.4-TLBI
1100001001VAE3OS ARMv8.4-TLBI
1100001101VALE3OS ARMv8.4-TLBI
1100010001RVAE3IS ARMv8.4-TLBI
1100010101RVALE3IS ARMv8.4-TLBI
1100011000ALLE3IS -
1100011001VAE3IS -
1100011101VALE3IS -
1100101001RVAE3OS ARMv8.4-TLBI
1100101101RVALE3OS ARMv8.4-TLBI
1100110001RVAE3 ARMv8.4-TLBI
1100110101RVALE3 ARMv8.4-TLBI
1100111000ALLE3 -
1100111001VAE3 -
1100111101VALE3 -
<Xt>

Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

Operation

The description of SYS gives the operational pseudocode for this instruction.


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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