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Floating-point Maximum (scalar). This instruction compares the two source SIMD&FP registers, and writes the larger of the two floating-point values to the destination SIMD&FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | Rm | 0 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||||||
op |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer datasize;
case ftype of
when '00' datasize = 32;
when '01' datasize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
datasize = 16;
else
UNDEFINED;FPMaxMinOp operation;
case op of
when '00' operation = FPMaxMinOp_MAX;
when '01' operation = FPMaxMinOp_MIN;
when '10' operation = FPMaxMinOp_MAXNUM;
when '11' operation = FPMaxMinOp_MINNUM;
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Dm> | Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> | Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Hm> | Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Sm> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64();
bits(datasize) result;
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
result =case operation of
when FPMaxMinOp_MAX result = FPMax(operand1, operand2, FPCR);
when FPMaxMinOp_MIN result = FPMin(operand1, operand2, FPCR);
when FPMaxMinOp_MAXNUM result = FPMaxNum(operand1, operand2, FPCR);
when FPMaxMinOp_MINNUM result = FPMinNum(operand1, operand2, FPCR);
V[d] = result;
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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