Bitwise clear and exclusive OR.
Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 0 | 0 | 1 | 1 | 1 | 0 | Zk | Zdn |
if !HaveSVE2() then UNDEFINED; integer m = UInt(Zm); integer k = UInt(Zk); integer dn = UInt(Zdn);
<Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
<Zk> |
Is the name of the third source scalable vector register, encoded in the "Zk" field. |
CheckSVEEnabled(); bits(VL) operand1 = Z[dn]; bits(VL) operand2 = Z[m]; bits(VL) operand3 = Z[k]; Z[dn] = operand1 EOR (operand2 AND NOT(operand3));
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30
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