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Copy SIMD&FP scalar register to vector elements (predicated).
Copy the SIMD & floating-point scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
This instruction is used by the alias MOV (SIMD&FP scalar, predicated).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Pg | Vn | Zd |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Vn); integer d = UInt(Zd);
<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<V> |
Is a width specifier,
encoded in
size:
|
<n> | Is the number [0-31] of the source SIMD&FP register, encoded in the "Vn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(esize) operand1 = V[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = operand1; Z[d] = result;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:
Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5
; Build timestamp: 2019-06-26T222019-04-17T09:0458
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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