EORBT

Interleaving exclusive OR (bottom, top).

Interleaving exclusive OR between the even-numbered elements of the first source vector register and the odd-numbered elements of the second source vector register, placing the result in the even-numbered elements of the destination vector, leaving the odd-numbered elements unchanged. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
01000101size0Zm100100ZnZd

SVE2

EORBT <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSVE2() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer sel1 = 0; integer sel2 = 1;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV (2 * esize); bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, 2*e + sel1, esize]; bits(esize) element2 = Elem[operand2, 2*e + sel2, esize]; Elem[result, 2*e + sel1, esize] = element1 EOR element2; Z[d] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:

The MOVPRFX instructions that can be used with this instruction are as follows:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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