(old) htmldiff from-(new)

UUNPKHI, UUNPKLO

Unsigned unpack and extend half of vector.

Unpack elements from the lowest or highest half of the source vector and then zero-extend them to place in elements of twice their size within the destination vector. This instruction is unpredicated.

It has encodings from 2 classes: High half and Low half

High half

313029282726252423222120191817161514131211109876543210
00000101size110011001110ZnZd

High half

UUNPKHI <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = TRUE; boolean hi = TRUE;

Low half

313029282726252423222120191817161514131211109876543210
00000101size110010001110ZnZd

Low half

UUNPKLO <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer d = UInt(Zd); boolean unsigned = TRUE; boolean hi = FALSE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in size:
size<Tb>
00RESERVED
01B
10H
11S

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; integer hsize = esize DIV 2; bits(VL) operand = Z[n]; bits(VL) result; for e = 0 to elements-1 bits(hsize) element = if hi then Elem[operand, e + elements, hsize] else Elem[operand, e, hsize]; Elem[result, e, esize] = Extend(element, esize, unsigned); Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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