LDURSH

Load Register Signed Halfword (unscaled) calculates an address from a base register and an immediate offset, loads a signed halfword from memory, sign-extends it, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
011110001x0imm900RnRt
sizeopc

32-bit (opc == 11)

LDURSH <Wt>, [<Xn|SP>{, #<simm>}]

64-bit (opc == 10)

LDURSH <Xt>, [<Xn|SP>{, #<simm>}]

bits(64) offset = SignExtend(imm9, 64);

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = 32; signed = FALSE; else // sign-extending load memop = MemOp_LOAD; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; boolean tag_checked = memop != MemOp_PREFETCH && (n != 31);

Operation

if HaveMTEExt() then SetNotTagCheckedInstruction(!tag_checked); bits(64) address; bits(16) data; if n == 31 then if memop != MemOp_PREFETCH then CheckSPAlignment(); address = SP[]; else address = X[n]; address = address + offset; case memop of when MemOp_STORE data = X[t]; Mem[address, 2, AccType_NORMAL] = data; when MemOp_LOAD data = Mem[address, 2, AccType_NORMAL]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCH Prefetch(address, t<4:0>);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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