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Prefetch Memory (immediate) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.
The effect of an PRFM instruction is implementation defined. For more information, see Prefetch memory.
For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | imm12 | Rn | Rt | |||||||||||||||||||
size | opc |
bits(64) offset =boolean wback = FALSE;
boolean postindex = FALSE;
integer scale = UInt(size);
bits(64) offset = LSL(ZeroExtend(imm12, 64), 3);(imm12, 64), scale);
<prfop> | Is the prefetch operation, defined as <type><target><policy>. <type> is one of:
<target> is one of:
<policy> is one of:
For more information on these prefetch operations, see Prefetch memory. For other encodings of the "Rt" field, use <imm5>. |
<imm5> | Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field. This syntax is only for encodings that are not accessible using <prfop>. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<pimm> | Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8. |
integer n = UInt(Rn);
integer t = UInt(Rt);AccType acctype = AccType_NORMAL;
MemOp memop;
boolean signed;
integer regsize;
if opc<1> == '0' then
// store or zero-extending load
memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
regsize = if size == '11' then 64 else 32;
signed = FALSE;
else
if size == '11' then
memop = MemOp_PREFETCH;
if opc<0> == '1' then UNDEFINED;
else
// sign-extending load
memop = MemOp_LOAD;
if size == '10' && opc<0> == '1' then UNDEFINED;
regsize = if opc<0> == '1' then 32 else 64;
signed = TRUE;
integer datasize = 8 << scale;
boolean tag_checked = memop != MemOp_PREFETCH && (wback || n != 31);
if HaveMTEExt() then
SetNotTagCheckedInstruction(TRUE);
SetNotTagCheckedInstruction(!tag_checked);
bits(64) address;
bits(datasize) data;
if n == 31 then
address =boolean wb_unknown = FALSE;
boolean rt_unknown = FALSE;
if memop == MemOp_LOAD && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed
when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if memop == MemOp_STORE && wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST);
assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_NONE rt_unknown = FALSE; // value stored is original value
when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if n == 31 then
if memop != MemOp_PREFETCH then CheckSPAlignment();
address = SP[];
else
address = X[n];
address = address + offset;if ! postindex then
address = address + offset;
case memop of
when
MemOp_STORE
if rt_unknown then
data = bits(datasize) UNKNOWN;
else
data = X[t];
Mem[address, datasize DIV 8, acctype] = data;
when MemOp_LOAD
data = Mem[address, datasize DIV 8, acctype];
if signed then
X[t] = SignExtend(data, regsize);
else
X[t] = ZeroExtend(data, regsize);
when MemOp_PREFETCHPrefetch(address, t<4:0>);
if wback then
if wb_unknown then
address = bits(64) UNKNOWN;
elsif postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X(address, t<4:0>);[n] = address;
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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