TSTART

This instruction starts a new transaction. If the transaction started successfully, the destination register is set to zero. If the transaction failed or was canceled, then all state modifications that were performed transactionally are discarded and the destination register is written with a non-zero value that encodes the cause of the failure.

System
(TME)

313029282726252423222120191817161514131211109876543210
110101010010001100110000011Rt

System

TSTART <Xt>

if !HaveTME() then UNDEFINED; integer t = UInt(Rt);

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field.

Operation

CheckTMEEnabled(); boolean IsEL1Regime; case PSTATE.EL of when EL0 IsEL1Regime = S1TranslationRegime() == EL1; if IsEL1Regime then tme = SCTLR_EL1.TME0; tmt = SCTLR_EL1.TMT0; else tme = SCTLR_EL2.TME0; tmt = SCTLR_EL2.TMT0; when EL1 tme = SCTLR_EL1.TME; tmt = SCTLR_EL1.TMT; when EL2 tme = SCTLR_EL2.TME; tmt = SCTLR_EL2.TMT; when EL3 tme = SCTLR_EL3.TME; tmt = SCTLR_EL3.TMT; otherwise Unreachable(); enable = tme == '1'; trivial = tmt == '1'; if !enable then TransactionStartTrap(t); elsif trivial then FailTransaction(TMFailure_TRIVIAL, FALSE); elsif TSTATE.depth == 255 then FailTransaction(TMFailure_NEST, FALSE); elsif TSTATE.depth == 0 then TSTATE.nPC = NextInstrAddr(); TSTATE.Rt = t; ClearExclusiveLocal(ProcessorID()); TakeTransactionCheckpoint(); StartTrackingTransactionalReadsWrites(); TSTATE.depth = TSTATE.depth + 1; X[t] = Zeros(64);


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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