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Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
U | o0 |
integer d = UInt(Rd);
integer n = UInt(Rn);
// size=esize: B(0), H(1), S(1), D(S)
integer esize = 8 << UInt(size);
integer datasize = if Q == '1' then 128 else 64;
// op=REVx: 64(0), 32(1), 16(2)
bits(2) op = o0:U;
// => op+size:
// 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X
// 32+B = 1, 32+H = 2, 32+S = X, 32+D = X
// 16+B = 2, 16+H = X, 16+S = X, 16+D = X
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
// => 3-(op+size) (index bits in group)
// 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X
// 32+B = 2, 32+H = 1, 32+S = X, 32+D = X
// 16+B = 1, 16+H = X, 16+S = X, 16+D = X
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
// index bits within group: 1, 2, 3
if UInt(op) +(op)+ UInt(size) >= 3 then UNDEFINED;
integer container_size;
case op of
when '10' container_size = 16;
when '01' container_size = 32;
when '00' container_size = 64;
integer containers = datasize DIV container_size;
integer elements_per_container = container_size DIV esize;
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
size:Q:
|
<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; integer element = 0; integer rev_element; for c = 0 to containers-1 rev_element = element + elements_per_container - 1; for e = 0 to elements_per_container-1 Elem[result, rev_element, esize] = Elem[operand, element, esize]; element = element + 1; rev_element = rev_element - 1; V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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