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Unigned Bitfield Move is usually accessed via one of its aliases, which are always preferred for disassembly.
If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register.
If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits.
In both cases the destination bits below and above the bitfield are set to zero.
This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | Rn | Rd | ||||||||||||||||||
opc |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer datasize = if sf == '1' then 64 else 32;
boolean inzero;
boolean extend;
integer R;
integer S;
bits(datasize) wmask;
bits(datasize) tmask;
case opc of
when '00' inzero = TRUE; extend = TRUE; // SBFM
when '01' inzero = FALSE; extend = FALSE; // BFM
when '10' inzero = TRUE; extend = FALSE; // UBFM
when '11' UNDEFINED;
if sf == '1' && N != '1' then UNDEFINED;
if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then UNDEFINED;
R = UInt(immr);
(wmask, tmask) =S = UInt(imms);
(wmask, tmask) = DecodeBitMasks(N, imms, immr, FALSE);
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> | Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> | Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
Alias | Of variant | Is preferred when |
---|---|---|
LSL (immediate) | 32-bit | imms != '011111' && imms + 1 == immr |
LSL (immediate) | 64-bit | imms != '111111' && imms + 1 == immr |
LSR (immediate) | 32-bit | imms == '011111' |
LSR (immediate) | 64-bit | imms == '111111' |
UBFIZ | UInt(imms) < UInt(immr) | |
UBFX | BFXPreferred(sf, opc<1>, imms, immr) | |
UXTB | immr == '000000' && imms == '000111' | |
UXTH | immr == '000000' && imms == '001111' |
bits(datasize) src =bits(datasize) dst = if inzero then Zeros() else X[n];
// perform bitfield move on low bits
bits(datasize) bot =[d];
bits(datasize) src = X[n];
// perform bitfield move on low bits
bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask);
// determine extension bits (sign, zero or dest register)
bits(datasize) top = if extend then Replicate(src, R) AND wmask;
(src<S>) else dst;
// combine extension bits and result bits
X[d] = bot AND tmask;[d] = (top AND NOT(tmask)) OR (bot AND tmask);
If PSTATE.DIT is 1:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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