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Load LOAcquire Register loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about memory accesses, see Load/Store addressing modes.
For this instruction, if the destination is WZR/ZXR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | x | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | (1) | (1) | (1) | (1) | (1) | 0 | (1) | (1) | (1) | (1) | (1) | Rn | Rt | ||||||||
size | L | Rs | o0 | Rt2 |
integer n = UInt(Rn);
integer t = UInt(Rt);
integer elsize = 8 <<integer t2 = UInt(size);
integer regsize = if elsize == 64 then 64 else 32;
boolean tag_checked = n != 31;(Rt2); // ignored by load/store single register
integer s =UInt(Rs); // ignored by all loads and store-release
AccType acctype = if o0 == '0' then AccType_LIMITEDORDERED else AccType_ORDERED;
MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE;
integer elsize = 8 << UInt(size);
integer regsize = if elsize == 64 then 64 else 32;
integer datasize = elsize;
boolean tag_checked = n != 31;
<Wt> | Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;
if HaveMTEExt() then
SetNotTagCheckedInstruction(!tag_checked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
data =case memop of
when MemOp_STORE
data = X[t];
Mem[address, dbytes,[address, dbytes, acctype] = data;
when
data = MemAccType_LIMITEDORDEREDMemOp_LOAD];[address, dbytes, acctype];
X[t] = ZeroExtend(data, regsize);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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