LDNT1B (vector plus scalar)

Gather load non-temporal unsigned bytes.

Gather load non-temporal of unsigned bytes to active elements of a vector register from memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements will not read Device memory or signal faults, and are set to zero in the destination vector.

A non-temporal load is a hint to the system that this data is unlikely to be referenced again soon.

It has encodings from 2 classes: 32-bit unscaled offset and 64-bit unscaled offset

32-bit unscaled offset

313029282726252423222120191817161514131211109876543210
10000100000Rm101PgZnZt

32-bit unscaled offset

LDNT1B { <Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]

if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 32; integer msize = 8; boolean unsigned = TRUE;

64-bit unscaled offset

313029282726252423222120191817161514131211109876543210
11000100000Rm110PgZnZt

64-bit unscaled offset

LDNT1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]

if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 64; integer msize = 8; boolean unsigned = TRUE;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<Xm>

Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) base = Z[n]; bits(64) offset = X[m]; bits(64) addr; bits(PL) mask = P[g]; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetNotTagCheckedInstruction(FALSE); for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then addr = ZeroExtend(Elem[base, e, esize], 64) + offset; data = Mem[addr, mbytes, AccType_STREAM]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(); Z[t] = result;


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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