TSB CSYNC

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions.

If ARMv8.4-Trace is not implemented, this instruction executes as a NOP.

System
(Armv8.4)

313029282726252423222120191817161514131211109876543210
11010101000000110010001001011111
CRmop2

System

TSB CSYNC

if !HaveSelfHostedTrace() then EndOfInstruction();

Operation

TraceSynchronizationBarrier();


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.