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Profiling Synchronization Barrier. This instruction is a barrier that ensures that all existing profiling data for the current PE has been formatted, and profiling buffer addresses have been translated such that all writes to the profiling buffer have been initiated. A following DSB instruction completes when the writes to the profiling buffer have completed.
If the Statistical Profiling Extension is not implemented, this instruction executes as a NOP.
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1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
CRm | op2 |
SystemHintOp op; case CRm:op2 of when '0000 000' op = SystemHintOp_NOP; when '0000 001' op = SystemHintOp_YIELD; when '0000 010' op = SystemHintOp_WFE; when '0000 011' op = SystemHintOp_WFI; when '0000 100' op = SystemHintOp_SEV; when '0000 101' op = SystemHintOp_SEVL; when '0000 111' SEE "XPACLRI"; when '0001 xxx' SEE "PACIA1716, PACIB1716, AUTIA1716, AUTIB1716"; when '0010 000' if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP op = SystemHintOp_ESB; when '0010 001' if !HaveStatisticalProfiling() then EndOfInstruction(); // Instruction executes as NOP op = SystemHintOp_PSB; when '0010 010' if !HaveSelfHostedTrace() then EndOfInstruction(); // Instruction executes as NOP op = SystemHintOp_TSB; when '0010 100' op = SystemHintOp_CSDB; when '0011 xxx' SEE "PACIAZ, PACIASP, PACIBZ, PACIBSP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP"; when '0100 xx0' op = SystemHintOp_BTI; // Check branch target compatibility between BTI instruction and PSTATE.BTYPE BTypeCompatible = BTypeCompatible_BTI(op2<2:1>); otherwise EndOfInstruction(); // Instruction executes as NOP
case op of
when SystemHintOp_YIELDHint_Yield();
when SystemHintOp_WFE
if IsEventRegisterSet() then
ClearEventRegister();
else
if PSTATE.EL == EL0 then
// Check for traps described by the OS which may be EL1 or EL2.
AArch64.CheckForWFxTrap(EL1, TRUE);
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() then
// Check for traps described by the Hypervisor.
AArch64.CheckForWFxTrap(EL2, TRUE);
if HaveEL(EL3) && PSTATE.EL != EL3 then
// Check for traps described by the Secure Monitor.
AArch64.CheckForWFxTrap(EL3, TRUE);
WaitForEvent();
when SystemHintOp_WFI
if !InterruptPending() then
if PSTATE.EL == EL0 then
// Check for traps described by the OS which may be EL1 or EL2.
AArch64.CheckForWFxTrap(EL1, FALSE);
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() then
// Check for traps described by the Hypervisor.
AArch64.CheckForWFxTrap(EL2, FALSE);
if HaveEL(EL3) && PSTATE.EL != EL3 then
// Check for traps described by the Secure Monitor.
AArch64.CheckForWFxTrap(EL3, FALSE);
WaitForInterrupt();
when SystemHintOp_SEVSendEvent();
when SystemHintOp_SEVLSendEventLocal();
when SystemHintOp_ESB
if TSTATE.depth > 0 then
FailTransaction(TMFailure_ERR, FALSE);
SynchronizeErrors();
AArch64.ESBOperation();
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch64.vESBOperation();
TakeUnmaskedSErrorInterrupts();
when SystemHintOp_PSBProfilingSynchronizationBarrier();
when SystemHintOp_TSBTraceSynchronizationBarrier();
TraceSynchronizationBarrier();
when SystemHintOp_CSDBConsumptionOfSpeculativeDataBarrier();
when SystemHintOp_BTI
BTypeNext = '00';
otherwise // do nothing
Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5
; Build timestamp: 2019-06-26T222019-04-17T09:0458
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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