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Move immediate value to Special Register moves an immediate value to selected bits of the PSTATE. For more information, see Process state, PSTATE.
The bits that can be written by this instruction are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | op1 | 0 | 1 | 0 | 0 | CRm | op2 | 1 | 1 | 1 | 1 | 1 |
MSR <pstatefield>, #<imm>
if op1 == '000' && op2 == '000' then SEE "CFINV";
if op1 == '000' && op2 == '001' then SEE "XAFlag";
if op1 == '000' && op2 == '010' then SEE "AXFlag";
AArch64.CheckSystemAccess('00', op1, '0100', CRm, op2, '11111', '0');('00', op1, '0100', CRm, op2, '11111', '0');
bits(4) operand = CRm;
PSTATEField field;
case op1:op2 of
when '000 011'
if !HaveUAOExt() then
UNDEFINED;
field = PSTATEField_UAO;
when '000 100'
if !HavePANExt() then
UNDEFINED;
field = PSTATEField_PAN;
when '000 101' field = PSTATEField_SP;
when '011 010'
if !HaveDITExt() then
UNDEFINED;
field = PSTATEField_DIT;
when '011 100'
if !HaveMTEExt() then
UNDEFINED;
field = PSTATEField_TCO;
when '011 110' field = PSTATEField_DAIFSet;
when '011 111' field = PSTATEField_DAIFClr;
when '011 001'
if !HaveSSBSExt() then
UNDEFINED;
field = PSTATEField_SSBS;
otherwise UNDEFINED;
// Check that an AArch64 MSR/MRS access to the DAIF flags is permitted
if PSTATE.EL == EL0 && field IN {PSTATEField_DAIFSet, PSTATEField_DAIFClr} then
if IsInHost() || SCTLR_EL1.UMA == '0' then
AArch64.SystemAccessTrap(EL1, 0x18); // Exception_SystemRegisterTrap
<pstatefield> |
Is a PSTATE field name,
encoded in
op1:op2:
|
<imm> | Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. |
case field of
when PSTATEField_SSBS
PSTATE.SSBS = CRm<0>;
PSTATE.SSBS = operand<0>;
when PSTATEField_SP
PSTATE.SP = CRm<0>;
PSTATE.SP = operand<0>;
when PSTATEField_DAIFSet
PSTATE.D = PSTATE.D OR CRm<3>;
PSTATE.A = PSTATE.A OR CRm<2>;
PSTATE.I = PSTATE.I OR CRm<1>;
PSTATE.F = PSTATE.F OR CRm<0>;
PSTATE.D = PSTATE.D OR operand<3>;
PSTATE.A = PSTATE.A OR operand<2>;
PSTATE.I = PSTATE.I OR operand<1>;
PSTATE.F = PSTATE.F OR operand<0>;
when PSTATEField_DAIFClr
PSTATE.D = PSTATE.D AND NOT(CRm<3>);
PSTATE.A = PSTATE.A AND NOT(CRm<2>);
PSTATE.I = PSTATE.I AND NOT(CRm<1>);
PSTATE.F = PSTATE.F AND NOT(CRm<0>);
PSTATE.D = PSTATE.D AND NOT(operand<3>);
PSTATE.A = PSTATE.A AND NOT(operand<2>);
PSTATE.I = PSTATE.I AND NOT(operand<1>);
PSTATE.F = PSTATE.F AND NOT(operand<0>);
when PSTATEField_PAN
PSTATE.PAN = CRm<0>;
PSTATE.PAN = operand<0>;
when PSTATEField_UAO
PSTATE.UAO = CRm<0>;
PSTATE.UAO = operand<0>;
when PSTATEField_DIT
PSTATE.DIT = CRm<0>;
PSTATE.DIT = operand<0>;
when PSTATEField_TCO
PSTATE.TCO = CRm<0>;PSTATE.TCO = operand<0>;
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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