Signed saturating shift right narrow by immediate (top).
Shift each signed integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | imm3 | 0 | 0 | 1 | 0 | 0 | 1 | Zn | Zd |
if !HaveSVE2() then UNDEFINED; bits(3) tsize = tszh:tszl; case tsize of when '000' UNDEFINED; when '001' esize = 8; when '01x' esize = 16; when '1xx' esize = 32; integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
tszh:tszl:
|
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Tb> |
Is the size specifier,
encoded in
tszh:tszl:
|
<const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3". |
CheckSVEEnabled(); integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(2*esize) element = Elem[operand, e, 2*esize]; integer res = SInt(element) >> shift; Elem[result, 2*e + 1, esize] = SignedSat(res, esize); Z[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30
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