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STZ2G

Store Allocation Tags, Zeroing stores an Allocation Tag to two Tag granules of memory, zeroing the associated data locations. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register.

This instruction generates an Unchecked access.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index
(Armv8.5)

313029282726252423222120191817161514131211109876543210
11011001111imm901XnXt

Post-index

STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = TRUE; boolean postindex = TRUE;boolean postindex = TRUE; boolean zero_data = TRUE;

Pre-index
(Armv8.5)

313029282726252423222120191817161514131211109876543210
11011001111imm911XnXt

Pre-index

STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!

integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = TRUE; boolean postindex = FALSE;boolean postindex = FALSE; boolean zero_data = TRUE;

Signed offset
(Armv8.5)

313029282726252423222120191817161514131211109876543210
11011001111imm910XnXt

Signed offset

STZ2G <Xt|SP>, [<Xn|SP>{, #<simm>}]

integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = FALSE; boolean postindex = FALSE;boolean postindex = FALSE; boolean zero_data = TRUE;

Assembler Symbols

<Xt|SP>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.

<simm>

Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

Operation

bits(64) address; bits(64) data = if t == 31 then SP[] else X[t]; bits(4) tag = AArch64.AllocationTagFromAddress(data); SetNotTagCheckedInstruction(TRUE); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; if !postindex then address = address + offset; address = address + offset; if zero_data then Mem[address, TAG_GRANULE, AccType_NORMAL] = Zeros(8 * TAG_GRANULE);(8*TAG_GRANULE); Mem[address+TAG_GRANULE, TAG_GRANULE, AccType_NORMAL] = Zeros(8 * TAG_GRANULE);(8*TAG_GRANULE); AArch64.MemTag[address] = tag; AArch64.MemTag[address+TAG_GRANULE] = tag; if writeback then if postindex then address = address + offset; if n == 31 then SP[] = address; else X[n] = address;


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:3004

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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