UADALP

Unsigned add and accumulate long pairwise.

Add pairs of adjacent unsigned integer values and accumulate the results into the overlapping double-width elements of the destination vector.

313029282726252423222120191817161514131211109876543210
01000100size000101101PgZnZda

SVE2

UADALP <Zda>.<T>, <Pg>/M, <Zn>.<Tb>

if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer da = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in size:
size <Tb>
00 RESERVED
01 B
10 H
11 S

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand_acc = Z[da]; bits(VL) operand_src = Z[n]; bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '0' then Elem[result, e, esize] = Elem[operand_acc, e, esize]; else integer element1 = UInt(Elem[operand_src, 2*e + 0, esize DIV 2]); integer element2 = UInt(Elem[operand_src, 2*e + 1, esize DIV 2]); integer element3 = UInt(Elem[operand_acc, e, esize]); Elem[result, e, esize] = (element1 + element2 + element3)<esize-1:0>; Z[da] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:

The MOVPRFX instructions that can be used with this instruction are as follows:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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