Store Allocation Tag stores an Allocation Tag to memory. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register.
This instruction generates an Unchecked access.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | imm9 | 0 | 1 | Xn | Xt |
integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = TRUE; boolean postindex = TRUE; boolean zero_data = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | imm9 | 1 | 1 | Xn | Xt |
integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = TRUE; boolean postindex = FALSE; boolean zero_data = FALSE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | imm9 | 1 | 0 | Xn | Xt |
integer n = UInt(Xn); integer t = UInt(Xt); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE); boolean writeback = FALSE; boolean postindex = FALSE; boolean zero_data = FALSE;
<Xt|SP> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field. |
<simm> |
Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field. |
bits(64) address; SetNotTagCheckedInstruction(TRUE); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; if !postindex then address = address + offset; if zero_data then Mem[address, TAG_GRANULE, AccType_NORMAL] = Zeros(TAG_GRANULE * 8); bits(64) data = if t == 31 then SP[] else X[t]; bits(4) tag = AArch64.AllocationTagFromAddress(data); AArch64.MemTag[address] = tag; if writeback then if postindex then address = address + offset; if n == 31 then SP[] = address; else X[n] = address;
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:04
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