(old) | htmldiff from- | (new) |
Atomic unsigned maximum on halfword in memory atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the larger value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
This instruction is used by the alias STUMAXH, STUMAXLH.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | A | R | 1 | Rs | 0 | 1 | 1 | 0 | 0 | 0 | Rn | Rt | ||||||||||||
size | opc |
if !HaveAtomicExt() then UNDEFINED;
integer t = UInt(Rt);
integer n = UInt(Rn);
integer s = UInt(Rs);(Rs);
integer datasize = 8 <<
UInt(size);
integer regsize = if datasize == 64 then 64 else 32;
AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW;
AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW;
MemAtomicOp op;
case opc of
when '000' op = MemAtomicOp_ADD;
when '001' op = MemAtomicOp_BIC;
when '010' op = MemAtomicOp_EOR;
when '011' op = MemAtomicOp_ORR;
when '100' op = MemAtomicOp_SMAX;
when '101' op = MemAtomicOp_SMIN;
when '110' op = MemAtomicOp_UMAX;
when '111' op = MemAtomicOp_UMIN;
boolean tag_checked = n != 31;
<Ws> | Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Wt> | Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
Alias | Is preferred when |
---|---|
STUMAXH, STUMAXLH | A == '0' && Rt == '11111' |
bits(64) address;
bits(16) value;
bits(16) data;
bits(datasize) value;
bits(datasize) data;
if HaveMTEExt() then
SetNotTagCheckedInstruction(!tag_checked);
value = X[s];
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
data = MemAtomic(address,(address, op, value, ldacctype, stacctype);
if t != 31 then MemAtomicOp_UMAX, value, ldacctype, stacctype);
if t != 31 then
X[t] = ZeroExtend(data, 32);(data, regsize);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |