(old) htmldiff from-(new)

RAX1

Bitwise rotate left by 1 and exclusive OR.

Rotate each 64-bit element of the second source vector left by 1 and exclusive OR with the corresponding elements of the first source vector. The results are placed in the corresponding elements of the destination vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
01000101001Zm111101ZnZd

SVE2

RAX1 <Zd>.D, <Zn>.D, <Zm>.D

if !HaveSVE2SHA3() then UNDEFINED; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV 64; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(64) element1 = Elem[operand1, e, 64]; bits(64) element2 = Elem[operand2, e, 64]; Elem[result, e, 64] = element1 EOR ROL(element2, 1); Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)