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STGM

Store Tag Multiple writes a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and the Allocation Tag written to address A is taken from the source register at 4*A<7:4>+3:4*A<7:4>.

This instruction is undefined at EL0.

This instruction generates an Unchecked access.

This instruction is Unallocated when ID_AA64PFR1_EL1.MTE == 0b0001.

Integer
(Armv8.5)

313029282726252423222120191817161514131211109876543210
1101100110100000000000XnXt

Integer

STGM <Xt>, [<Xn|SP>]

integer t = UInt(Xt); integer n = UInt(Xn);

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Xt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.

Operation

if PSTATE.EL == EL0 then UndefinedFault(); bits(64) data = X[t]; bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; integer size = 4*(2^(UInt(GMID_EL1.BS))); address = Align(address,size); integer count = size >> LOG2_TAG_GRANULE; integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>); for i = 0 to count-1 bits(4) tag = data<(index*4)+3:index*4>; AArch64.MemTag[address] = tag; address = address + TAG_GRANULE; index = index + 1;


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

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