(old) htmldiff from-(new)

Top-level encodings for A64

313029282726252423222120191817161514131211109876543210
op0
Decode fields Instruction details
op0
0000 Reserved
0001 UNALLOCATED
0010 SVE encodings
0011 UNALLOCATED
100x Data Processing -- Immediate
101x Branches, Exception Generating and System instructions
x1x0 Loads and Stores
x101 Data Processing -- Register
x111 Data Processing -- Scalar Floating-Point and Advanced SIMD

Reserved

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00000op1
Decode fields Instruction details
op0op1
000 000000000 UDF
!= 000000000 UNALLOCATED
!= 000 UNALLOCATED

SVE encodings

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00010op1op2op3
Decode fields Instruction details
op0op1op2op3
000 0x 0xxxx x1xxxx SVE Integer Multiply-Add - Predicated
000 0x 0xxxx 000xxx SVE Integer Binary Arithmetic - Predicated
000 0x 0xxxx 001xxx SVE Integer Reduction
000 0x 0xxxx 100xxx SVE Bitwise Shift - Predicated
000 0x 0xxxx 101xxx SVE Integer Unary Arithmetic - Predicated
000 0x 1xxxx 000xxx SVE integer add/subtract vectors (unpredicated)
000 0x 1xxxx 001xxx SVE Bitwise Logical - Unpredicated
000 0x 1xxxx 0100xx SVE Index Generation
000 0x 1xxxx 0101xx SVE Stack Allocation
000 0x 1xxxx 011xxx SVE2 Integer Multiply - Unpredicated
000 0x 1xxxx 100xxx SVE Bitwise Shift - Unpredicated
000 0x 1xxxx 1010xx SVE address generation
000 0x 1xxxx 1011xx SVE Integer Misc - Unpredicated
000 0x 1xxxx 11xxxx SVE Element Count
000 1x 00xxx SVE Bitwise Immediate
000 1x 01xxx SVE Integer Wide Immediate - Predicated
000 1x 1xxxx 001xxx SVE Permute Vector - Unpredicated
000 1x 1xxxx 010xxx SVE Permute Predicate
000 1x 1xxxx 011xxx SVE permute vector elements
000 1x 1xxxx 10xxxx SVE Permute Vector - Predicated
000 1x 1xxxx 11xxxx SEL (vectors)
000 10 1xxxx 000xxx SVE Permute Vector - Extract
000 11 1xxxx 000xxx UNALLOCATED
001 0x 0xxxx SVE Integer Compare - Vectors
001 0x 1xxxx SVE integer compare with unsigned immediate
001 1x 0xxxx x0xxxx SVE integer compare with signed immediate
001 1x 00xxx 01xxxx SVE predicate logical operations
001 1x 00xxx 11xxxx SVE Propagate Break
001 1x 01xxx 01xxxx SVE Partition Break
001 1x 01xxx 11xxxx SVE Predicate Misc
001 1x 1xxxx 00xxxx SVE Integer Compare - Scalars
001 1x 1xxxx 01xxxx UNALLOCATED
001 1x 1xxxx 11xxxx SVE Integer Wide Immediate - Unpredicated
001 1x 100xx 10xxxx SVE predicate count
001 1x 101xx 1000xx SVE Inc/Dec by Predicate Count
001 1x 101xx 1001xx SVE Write FFR
001 1x 101xx 101xxx UNALLOCATED
001 1x 11xxx 10xxxx UNALLOCATED
010 0x 0xxxx 0xxxxx SVE Integer Multiply-Add - Unpredicated
010 0x 0xxxx 10xxxx SVE2 Integer - Predicated
010 0x 0xxxx 11xxxx UNALLOCATED
010 0x 1xxxx SVE Multiply - Indexed
010 1x 0xxxx 0xxxxx SVE2 Widening Integer Arithmetic
010 1x 0xxxx 10xxxx SVE2 Misc
010 1x 0xxxx 11xxxx SVE2 Accumulate
010 1x 1xxxx 0xxxxx SVE2 Narrowing
010 1x 1xxxx 100xxx SVE2 character match
010 1x 1xxxx 101xxx SVE2 Histogram Computation - Segment
010 1x 1xxxx 110xxx HISTCNT
010 1x 1xxxx 111xxx SVE2 Crypto Extensions
011 0x 0xxxx 0xxxxx FCMLA (vectors)
011 0x 00x1x 1xxxxx UNALLOCATED
011 0x 00000 100xxx FCADD
011 0x 00000 101xxx UNALLOCATED
011 0x 00000 11xxxx UNALLOCATED
011 0x 00001 1xxxxx UNALLOCATED
011 0x 0010x 100xxx UNALLOCATED
011 0x 0010x 101xxx SVE2 floating-point convert precision
011 0x 0010x 11xxxx UNALLOCATED
011 0x 010xx 100xxx SVE2 floating-point pairwise operations
011 0x 010xx 101xxx UNALLOCATED
011 0x 010xx 11xxxx UNALLOCATED
011 0x 011xx 1xxxxx UNALLOCATED
011 0x 1xxxx x0x01x UNALLOCATED
011 0x 1xxxx 00000x SVE floating-point multiply-add (indexed)
011 0x 1xxxx 0001xx SVE floating-point complex multiply-add (indexed)
011 0x 1xxxx 001000 SVE floating-point multiply (indexed)
011 0x 1xxxx 001001 UNALLOCATED
011 0x 1xxxx 0011xx UNALLOCATED
011 0x 1xxxx 01x0xx SVE2 Floating Point Widening Multiply-Add - Indexed
011 0x 1xxxx 01x1xx UNALLOCATED
011 0x 1xxxx 10x00x SVE2 Floating Point Widening Multiply-Add
011 0x 1xxxx 10x1xx UNALLOCATED
011 0x 1xxxx 11xxxx UNALLOCATED
011 1x 0xxxx x1xxxx SVE floating-point compare vectors
011 1x 0xxxx 000xxx SVE floating-point arithmetic (unpredicated)
011 1x 0xxxx 100xxx SVE Floating Point Arithmetic - Predicated
011 1x 0xxxx 101xxx SVE Floating Point Unary Operations - Predicated
011 1x 000xx 001xxx SVE floating-point recursive reduction
011 1x 001xx 0010xx UNALLOCATED
011 1x 001xx 0011xx SVE Floating Point Unary Operations - Unpredicated
011 1x 010xx 001xxx SVE Floating Point Compare - with Zero
011 1x 011xx 001xxx SVE floating-point serial reduction (predicated)
011 1x 1xxxx SVE Floating Point Multiply-Add
100 SVE Memory - 32-bit Gather and Unsized Contiguous
101 SVE Memory - Contiguous Load
110 SVE Memory - 64-bit Gather
111 SVE Memory - Store

SVE Integer Multiply-Add - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op01
Decode fields Instruction details
op0
0 SVE integer multiply-accumulate writing addend (predicated)
1 SVE integer multiply-add writing multiplicand (predicated)

SVE integer multiply-accumulate writing addend (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm01opPgZnZda
Decode fields Instruction Details
op
0MLA (vectors)
1MLS (vectors)

SVE integer multiply-add writing multiplicand (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm11opPgZaZdn
Decode fields Instruction Details
op
0MAD
1MSB

SVE Integer Binary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0000
Decode fields Instruction details
op0
00x SVE integer add/subtract vectors (predicated)
01x SVE integer min/max/difference (predicated)
100 SVE integer multiply vectors (predicated)
101 SVE integer divide vectors (predicated)
11x SVE bitwise logical operations (predicated)

SVE integer add/subtract vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size000opc000PgZmZdn
Decode fields Instruction Details
opc
000ADD (vectors, predicated)
001SUB (vectors, predicated)
010UNALLOCATED
011SUBR (vectors)
1xxUNALLOCATED

SVE integer min/max/difference (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size001opcU000PgZmZdn
Decode fields Instruction Details
opcU
000SMAX (vectors)
001UMAX (vectors)
010SMIN (vectors)
011UMIN (vectors)
100SABD
101UABD
11UNALLOCATED

SVE integer multiply vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0100HU000PgZmZdn
Decode fields Instruction Details
HU
00MUL (vectors, predicated)
01UNALLOCATED
10SMULH (predicated)
11UMULH (predicated)

SVE integer divide vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0101RU000PgZmZdn
Decode fields Instruction Details
RU
00SDIV
01UDIV
10SDIVR
11UDIVR

SVE bitwise logical operations (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc000PgZmZdn
Decode fields Instruction Details
opc
000ORR (vectors, predicated)
001EOR (vectors, predicated)
010AND (vectors, predicated)
011BIC (vectors, predicated)
1xxUNALLOCATED

SVE Integer Reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0001
Decode fields Instruction details
op0
00 SVE integer add reduction (predicated)
01 SVE integer min/max reduction (predicated)
10 SVE constructive prefix (predicated)
11 SVE bitwise logical reduction (predicated)

SVE integer add reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size000opcU001PgZnVd
Decode fields Instruction Details
opcU
000SADDV
001UADDV
01UNALLOCATED
1xUNALLOCATED

SVE integer min/max reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size001opcU001PgZnVd
Decode fields Instruction Details
opcU
000SMAXV
001UMAXV
010SMINV
011UMINV
1xUNALLOCATED

SVE constructive prefix (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size010opcM001PgZnZd
Decode fields Instruction Details
opc
00MOVPRFX (predicated)
01UNALLOCATED
1xUNALLOCATED

SVE bitwise logical reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size011opc001PgZnVd
Decode fields Instruction Details
opc
000ORV
001EORV
010ANDV
011UNALLOCATED
1xxUNALLOCATED

SVE Bitwise Shift - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0100
Decode fields Instruction details
op0
0x SVE bitwise shift by immediate (predicated)
10 SVE bitwise shift by vector (predicated)
11 SVE bitwise shift by wide elements (predicated)

SVE bitwise shift by immediate (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100tszh00opcLU100Pgtszlimm3Zdn
Decode fields Instruction Details
opcLU
0000ASR (immediate, predicated)
0001LSR (immediate, predicated)
0010UNALLOCATED
0011LSL (immediate, predicated)
0100ASRD
0101UNALLOCATED
0110SQSHL (immediate)
0111UQSHL (immediate)
10UNALLOCATED
1100SRSHR
1101URSHR
1110UNALLOCATED
1111SQSHLU

SVE bitwise shift by vector (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010RLU100PgZmZdn
Decode fields Instruction Details
RLU
10UNALLOCATED
000ASR (vectors)
001LSR (vectors)
011LSL (vectors)
100ASRR
101LSRR
111LSLR

SVE bitwise shift by wide elements (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011RLU100PgZmZdn
Decode fields Instruction Details
RLU
000ASR (wide elements, predicated)
001LSR (wide elements, predicated)
010UNALLOCATED
011LSL (wide elements, predicated)
1UNALLOCATED

SVE Integer Unary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0101
Decode fields Instruction details
op0
0x UNALLOCATED
10 SVE integer unary operations (predicated)
11 SVE bitwise unary operations (predicated)

SVE integer unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010opc101PgZnZd
Decode fields Instruction Details
opc
000SXTB, SXTH, SXTWSXTB
001UXTB, UXTH, UXTWUXTB
010SXTB, SXTH, SXTWSXTH
011UXTB, UXTH, UXTWUXTH
100SXTB, SXTH, SXTWSXTW
101UXTB, UXTH, UXTWUXTW
110ABS
111NEG

SVE bitwise unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc101PgZnZd
Decode fields Instruction Details
opc
000CLS
001CLZ
010CNT
011CNOT
100FABS
101FNEG
110NOT (vector)
111UNALLOCATED

SVE integer add/subtract vectors (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100size1Zm000opcZnZd
Decode fields Instruction Details
opc
000ADD (vectors, unpredicated)
001SUB (vectors, unpredicated)
01xUNALLOCATED
100SQADD (vectors, unpredicated)
101UQADD (vectors, unpredicated)
110SQSUB (vectors, unpredicated)
111UQSUB (vectors, unpredicated)

SVE Bitwise Logical - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001001op0
Decode fields Instruction details
op0
0xx UNALLOCATED
100 SVE bitwise logical operations (unpredicated)
101 XAR
11x SVE2 bitwise ternary operations

SVE bitwise logical operations (unpredicated)

These instructions are under SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm001100ZnZd
Decode fields Instruction Details
opc
00AND (vectors, unpredicated)
01ORR (vectors, unpredicated)
10EOR (vectors, unpredicated)
11BIC (vectors, unpredicated)

SVE2 bitwise ternary operations

These instructions are under SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm00111o2ZkZdn
Decode fields Instruction Details
opco2
000EOR3
001BSL
010BCAX
011BSL1N
1x0UNALLOCATED
101BSL2N
111NBSL

SVE Index Generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010010100op0
Decode fields Instruction details
op0
00 INDEX (immediates)
01 INDEX (scalar, immediate)
10 INDEX (immediate, scalar)
11 INDEX (scalars)

SVE Stack Allocation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100op010101op1
Decode fields Instruction details
op0op1
0 0 SVE stack frame adjustment
1 0 SVE stack frame size
1 UNALLOCATED

SVE stack frame adjustment

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01010imm6Rd
Decode fields Instruction Details
op
0ADDVL
1ADDPL

SVE stack frame size

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201010imm6Rd
Decode fields Instruction Details
opopc2
00xxxxUNALLOCATED
010xxxUNALLOCATED
0110xxUNALLOCATED
01110xUNALLOCATED
011110UNALLOCATED
011111RDVL
1UNALLOCATED

SVE2 Integer Multiply - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001011op0
Decode fields Instruction details
op0
0x SVE2 integer multiply vectors (unpredicated)
10 SVE2 signed saturating doubling multiply high (unpredicated)
11 UNALLOCATED

SVE2 integer multiply vectors (unpredicated)

These instructions are under SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm0110opcZnZd
Decode fields Instruction Details
sizeopc
00MUL (vectors, unpredicated)
10SMULH (unpredicated)
11UMULH (unpredicated)
0001PMUL
0101UNALLOCATED
1x01UNALLOCATED

SVE2 signed saturating doubling multiply high (unpredicated)

These instructions are under SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm01110RZnZd
Decode fields Instruction Details
R
0SQDMULH (vectors)
1SQRDMULH (vectors)

SVE Bitwise Shift - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001100op0
Decode fields Instruction details
op0
0 SVE bitwise shift by wide elements (unpredicated)
1 SVE bitwise shift by immediate (unpredicated)

SVE bitwise shift by wide elements (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm1000opcZnZd
Decode fields Instruction Details
opc
00ASR (wide elements, unpredicated)
01LSR (wide elements, unpredicated)
10UNALLOCATED
11LSL (wide elements, unpredicated)

SVE bitwise shift by immediate (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100tszh1tszlimm31001opcZnZd
Decode fields Instruction Details
opc
00ASR (immediate, unpredicated)
01LSR (immediate, unpredicated)
10UNALLOCATED
11LSL (immediate, unpredicated)

SVE address generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm1010mszZnZd
Decode fields Instruction Details
opc
00ADRUnpacked 32-bit signed offsets
01ADRUnpacked 32-bit unsigned offsets
1xADRPacked offsets

SVE Integer Misc - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010011011op0
Decode fields Instruction details
op0
0x SVE floating-point trig select coefficient
10 SVE floating-point exponential accelerator
11 SVE constructive prefix (unpredicated)

SVE floating-point trig select coefficient

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm10110opZnZd
Decode fields Instruction Details
op
0FTSSEL
1UNALLOCATED

SVE floating-point exponential accelerator

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1opc101110ZnZd
Decode fields Instruction Details
opc
00000FEXPA
00001UNALLOCATED
0001xUNALLOCATED
001xxUNALLOCATED
01xxxUNALLOCATED
1xxxxUNALLOCATED

SVE constructive prefix (unpredicated)

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1opc2101111ZnZd
Decode fields Instruction Details
opcopc2
0000000MOVPRFX (unpredicated)
0000001UNALLOCATED
000001xUNALLOCATED
00001xxUNALLOCATED
0001xxxUNALLOCATED
001xxxxUNALLOCATED
01UNALLOCATED
1xUNALLOCATED

SVE Element Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001op011op1
Decode fields Instruction details
op0op1
0 00x SVE saturating inc/dec vector by element count
0 100 SVE element count
0 101 UNALLOCATED
1 000 SVE inc/dec vector by element count
1 100 SVE inc/dec register by element count
1 x01 UNALLOCATED
01x UNALLOCATED
11x SVE saturating inc/dec register by element count

SVE saturating inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm41100DUpatternZdn
Decode fields Instruction Details
sizeDU
00UNALLOCATED
0100SQINCH (vector)
0101UQINCH (vector)
0110SQDECH (vector)
0111UQDECH (vector)
1000SQINCW (vector)
1001UQINCW (vector)
1010SQDECW (vector)
1011UQDECW (vector)
1100SQINCD (vector)
1101UQINCD (vector)
1110SQDECD (vector)
1111UQDECD (vector)

SVE element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm411100oppatternRd
Decode fields Instruction Details
sizeop
1UNALLOCATED
000CNTB, CNTD, CNTH, CNTWCNTB
010CNTB, CNTD, CNTH, CNTWCNTH
100CNTB, CNTD, CNTH, CNTWCNTW
110CNTB, CNTD, CNTH, CNTWCNTD

SVE inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411000DpatternZdn
Decode fields Instruction Details
sizeD
00UNALLOCATED
010INCD, INCH, INCW (vector)INCH
011DECD, DECH, DECW (vector)DECH
100INCD, INCH, INCW (vector)INCW
101DECD, DECH, DECW (vector)DECW
110INCD, INCH, INCW (vector)INCD
111DECD, DECH, DECW (vector)DECD

SVE inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411100DpatternRdn
Decode fields Instruction Details
sizeD
000INCB, INCD, INCH, INCW (scalar)INCB
001DECB, DECD, DECH, DECW (scalar)DECB
010INCB, INCD, INCH, INCW (scalar)INCH
011DECB, DECD, DECH, DECW (scalar)DECH
100INCB, INCD, INCH, INCW (scalar)INCW
101DECB, DECD, DECH, DECW (scalar)DECW
110INCB, INCD, INCH, INCW (scalar)INCD
111DECB, DECD, DECH, DECW (scalar)DECD

SVE saturating inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size1sfimm41111DUpatternRdn
Decode fields Instruction Details
sizesfDU
00000SQINCB32-bit
00001UQINCB32-bit
00010SQDECB32-bit
00011UQDECB32-bit
00100SQINCB64-bit
00101UQINCB64-bit
00110SQDECB64-bit
00111UQDECB64-bit
01000SQINCH (scalar)32-bit
01001UQINCH (scalar)32-bit
01010SQDECH (scalar)32-bit
01011UQDECH (scalar)32-bit
01100SQINCH (scalar)64-bit
01101UQINCH (scalar)64-bit
01110SQDECH (scalar)64-bit
01111UQDECH (scalar)64-bit
10000SQINCW (scalar)32-bit
10001UQINCW (scalar)32-bit
10010SQDECW (scalar)32-bit
10011UQDECW (scalar)32-bit
10100SQINCW (scalar)64-bit
10101UQINCW (scalar)64-bit
10110SQDECW (scalar)64-bit
10111UQDECW (scalar)64-bit
11000SQINCD (scalar)32-bit
11001UQINCD (scalar)32-bit
11010SQDECD (scalar)32-bit
11011UQDECD (scalar)32-bit
11100SQINCD (scalar)64-bit
11101UQINCD (scalar)64-bit
11110SQDECD (scalar)64-bit
11111UQDECD (scalar)64-bit

SVE Bitwise Immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010100op0
Decode fields Instruction details
op0
00 SVE bitwise logical with immediate (unpredicated)
!= 00 UNALLOCATED

SVE bitwise logical with immediate (unpredicated)

These instructions are under SVE Bitwise Immediate.

313029282726252423222120191817161514131211109876543210
00000101opc0000imm13Zdn
Decode fields Instruction Details
opc
00ORR (immediate)
01EOR (immediate)
10AND (immediate)

SVE Integer Wide Immediate - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010101op0
Decode fields Instruction details
op0
0xx SVE copy integer immediate (predicated)
10x UNALLOCATED
110 FCPY
111 UNALLOCATED

SVE copy integer immediate (predicated)

These instructions are under SVE Integer Wide Immediate - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size01Pg0Mshimm8Zd
Decode fields Instruction Details
M
0CPY (immediate, zeroing)
1CPY (immediate, merging)

SVE Permute Vector - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1001op2
Decode fields Instruction details
op0op1op2
00 000 110 DUP (scalar)
00 100 110 INSR (scalar)
00 x00 001 UNALLOCATED
00 x00 1x1 UNALLOCATED
00 x!= 00 11x UNALLOCATED
00 x!= 00 x01 UNALLOCATED
01 11x UNALLOCATED
01 x01 UNALLOCATED
10 0xx 001 UNALLOCATED
10 0xx 110 SVE unpack vector elements
10 0xx 1x1 UNALLOCATED
10 100 001 UNALLOCATED
10 100 110 INSR (SIMD&FP scalar)
10 100 1x1 UNALLOCATED
10 1!= 00 11x UNALLOCATED
10 1!= 00 x01 UNALLOCATED
11 000 001 UNALLOCATED
11 000 110 REV (vector)
11 000 1x1 UNALLOCATED
11 0!= 00 x01 UNALLOCATED
11 1xx 001 UNALLOCATED
11 1xx 101 UNALLOCATED
11 != 000 11x UNALLOCATED
000 DUP (indexed)
01x SVE table lookup (three sources)
100 TBLSVE

SVE unpack vector elements

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size1100UH001110ZnZd
Decode fields Instruction Details
UH
00SUNPKHI, SUNPKLOSUNPKLO
01SUNPKHI, SUNPKLOSUNPKHI
10UUNPKHI, UUNPKLOUUNPKLO
11UUNPKHI, UUNPKLOUUNPKHI

SVE table lookup (three sources)

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size1Zm00101opZnZd
Decode fields Instruction Details
op
0TBL
1TBX

SVE Permute Predicate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1010op2op3
Decode fields Instruction details
op0op1op2op3
00 1000x 0000 0 SVE unpack predicate elements
01 1000x 0000 0 UNALLOCATED
10 1000x 0000 0 UNALLOCATED
11 1000x 0000 0 UNALLOCATED
0xxxx xxx0 0 SVE permute predicate elements
0xxxx xxx1 0 UNALLOCATED
10100 0000 0 REV (predicate)
10101 0000 0 UNALLOCATED
10x0x 1000 0 UNALLOCATED
10x0x x100 0 UNALLOCATED
10x0x xx10 0 UNALLOCATED
10x0x xxx1 0 UNALLOCATED
10x1x 0 UNALLOCATED
11xxx 0 UNALLOCATED
1 UNALLOCATED

SVE unpack predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
000001010011000H0100000Pn0Pd
Decode fields Instruction Details
H
0PUNPKHI, PUNPKLOPUNPKLO
1PUNPKHI, PUNPKLOPUNPKHI

SVE permute predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
00000101size10Pm010opcH0Pn0Pd
Decode fields Instruction Details
opcH
000ZIP1, ZIP2 (predicates)ZIP1
001ZIP1, ZIP2 (predicates)ZIP2
010UZP1, UZP2 (predicates)UZP1
011UZP1, UZP2 (predicates)UZP2
100TRN1, TRN2 (predicates)TRN1
101TRN1, TRN2 (predicates)TRN2
11UNALLOCATED

SVE permute vector elements

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm011opcZnZd
Decode fields Instruction Details
opc
000ZIP1, ZIP2 (vectors)ZIP1
001ZIP1, ZIP2 (vectors)ZIP2
010UZP1, UZP2 (vectors)UZP1
011UZP1, UZP2 (vectors)UZP2
100TRN1, TRN2 (vectors)TRN1
101TRN1, TRN2 (vectors)TRN2
11xUNALLOCATED

SVE Permute Vector - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1op2op310op4
Decode fields Instruction details
op0op1op2op3op4
0 0 000 1 0 UNALLOCATED
1 0 000 1 0 COMPACT
0 000 0 0 CPY (SIMD&FP scalar)
0 000 1 SVE extract element to general register
0 001 0 SVE extract element to SIMD&FP scalar register
0 01x 0 SVE reverse within elements
0 01x 1 UNALLOCATED
0 100 0 1 CPY (scalar)
0 100 1 1 UNALLOCATED
0 100 0 SVE conditionally broadcast element to vector
0 101 0 SVE conditionally extract element to SIMD&FP scalar
0 110 0 0 SPLICEDestructive
0 110 1 0 SPLICEConstructive
0 110 1 UNALLOCATED
0 111 0 UNALLOCATED
0 111 1 UNALLOCATED
0 x01 1 UNALLOCATED
1 000 0 UNALLOCATED
1 000 1 SVE conditionally extract element to general register
1 != 000 UNALLOCATED

SVE extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10000B101PgZnRd
Decode fields Instruction Details
B
0LASTA (scalar)
1LASTB (scalar)

SVE extract element to SIMD&FP scalar register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10001B100PgZnVd
Decode fields Instruction Details
B
0LASTA (SIMD&FP scalar)
1LASTB (SIMD&FP scalar)

SVE reverse within elements

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size1001opc100PgZnZd
Decode fields Instruction Details
opc
00REVB, REVH, REVWREVB
01REVB, REVH, REVWREVH
10REVB, REVH, REVWREVW
11RBIT

SVE conditionally broadcast element to vector

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10100B100PgZmZdn
Decode fields Instruction Details
B
0CLASTA (vectors)
1CLASTB (vectors)

SVE conditionally extract element to SIMD&FP scalar

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10101B100PgZmVdn
Decode fields Instruction Details
B
0CLASTA (SIMD&FP scalar)
1CLASTB (SIMD&FP scalar)

SVE conditionally extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size11000B101PgZmRdn
Decode fields Instruction Details
B
0CLASTA (scalar)
1CLASTB (scalar)

SVE Permute Vector - Extract

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001010op01000
Decode fields Instruction details
op0
0 EXTDestructive
1 EXTConstructive

SVE Integer Compare - Vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001000op0
Decode fields Instruction details
op0
0 SVE integer compare vectors
1 SVE integer compare with wide elements

SVE integer compare vectors

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0Zmop0o2PgZnnePd
Decode fields Instruction Details
opo2ne
000CMP<cc> (vectors)CMPHS
001CMP<cc> (vectors)CMPHI
010CMP<cc> (wide elements)CMPEQ
011CMP<cc> (wide elements)CMPNE
100CMP<cc> (vectors)CMPGE
101CMP<cc> (vectors)CMPGT
110CMP<cc> (vectors)CMPEQ
111CMP<cc> (vectors)CMPNE

SVE integer compare with wide elements

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0ZmU1ltPgZnnePd
Decode fields Instruction Details
Ultne
000CMP<cc> (wide elements)CMPGE
001CMP<cc> (wide elements)CMPGT
010CMP<cc> (wide elements)CMPLT
011CMP<cc> (wide elements)CMPLE
100CMP<cc> (wide elements)CMPHS
101CMP<cc> (wide elements)CMPHI
110CMP<cc> (wide elements)CMPLO
111CMP<cc> (wide elements)CMPLS

SVE integer compare with unsigned immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100100size1imm7ltPgZnnePd
Decode fields Instruction Details
ltne
00CMP<cc> (immediate)CMPHS
01CMP<cc> (immediate)CMPHI
10CMP<cc> (immediate)CMPLO
11CMP<cc> (immediate)CMPLS

SVE integer compare with signed immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size0imm5op0o2PgZnnePd
Decode fields Instruction Details
opo2ne
000CMP<cc> (immediate)CMPGE
001CMP<cc> (immediate)CMPGT
010CMP<cc> (immediate)CMPLT
011CMP<cc> (immediate)CMPLE
100CMP<cc> (immediate)CMPEQ
101CMP<cc> (immediate)CMPNE
11UNALLOCATED

SVE predicate logical operations

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm01Pgo2Pno3Pd
Decode fields Instruction Details
opSo2o3
0000AND, ANDS (predicates)not setting the condition flags
0001BIC, BICS (predicates)not setting the condition flags
0010EOR, EORS (predicates)not setting the condition flags
0011SEL (predicates)
0100AND, ANDS (predicates)setting the condition flags
0101BIC, BICS (predicates)setting the condition flags
0110EOR, EORS (predicates)setting the condition flags
0111UNALLOCATED
1000ORR, ORRS (predicates)not setting the condition flags
1001ORN, ORNS (predicates)not setting the condition flags
1010NOR, NORSnot setting the condition flags
1011NAND, NANDSnot setting the condition flags
1100ORR, ORRS (predicates)setting the condition flags
1101ORN, ORNS (predicates)setting the condition flags
1110NOR, NORSsetting the condition flags
1111NAND, NANDSsetting the condition flags

SVE Propagate Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001010011op0
Decode fields Instruction details
op0
0 SVE propagate break from previous partition
1 UNALLOCATED

SVE propagate break from previous partition

These instructions are under SVE Propagate Break.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm11Pg0PnBPd
Decode fields Instruction Details
opSB
000BRKPA, BRKPASnot setting the condition flags
001BRKPB, BRKPBSnot setting the condition flags
010BRKPA, BRKPASsetting the condition flags
011BRKPB, BRKPBSsetting the condition flags
1UNALLOCATED

SVE Partition Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101op001op101op2op3
Decode fields Instruction details
op0op1op2op3
0 1000 0 0 SVE propagate break to next partition
0 1000 0 1 UNALLOCATED
0 x000 1 UNALLOCATED
0 x1xx UNALLOCATED
0 xx1x UNALLOCATED
0 xxx1 UNALLOCATED
1 0000 1 UNALLOCATED
1 != 0000 UNALLOCATED
0000 0 SVE partition break condition

SVE propagate break to next partition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
001001010S01100001Pg0Pn0Pdm
Decode fields Instruction Details
S
0BRKN, BRKNSnot setting the condition flags
1BRKN, BRKNSsetting the condition flags

SVE partition break condition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
00100101BS01000001Pg0PnMPd
Decode fields Instruction Details
BSM
11UNALLOCATED
00BRKA, BRKASnot setting the condition flags
010BRKA, BRKASsetting the condition flags
10BRKB, BRKBSnot setting the condition flags
110BRKB, BRKBSsetting the condition flags

SVE Predicate Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010101op011op1op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0000 x0 0 SVE predicate test
0100 x0 0 UNALLOCATED
0x10 x0 0 UNALLOCATED
0xx1 x0 0 UNALLOCATED
0xxx x1 0 UNALLOCATED
1000 000 00 0 SVE predicate first active
1000 000 != 00 0 UNALLOCATED
1000 100 10 0000 0 SVE predicate zero
1000 100 10 != 0000 0 UNALLOCATED
1000 110 00 0 SVE predicate read from FFR (predicated)
1001 000 0x 0 UNALLOCATED
1001 000 10 0 PNEXT
1001 000 11 0 UNALLOCATED
1001 100 10 0 UNALLOCATED
1001 110 00 0000 0 SVE predicate read from FFR (unpredicated)
1001 110 00 != 0000 0 UNALLOCATED
100x 010 0 UNALLOCATED
100x 100 0x 0 SVE predicate initialize
100x 100 11 0 UNALLOCATED
100x 110 != 00 0 UNALLOCATED
100x xx1 0 UNALLOCATED
110x 0 UNALLOCATED
1x1x 0 UNALLOCATED
1 UNALLOCATED

SVE predicate test

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS01000011Pg0Pn0opc2
Decode fields Instruction Details
opSopc2
00UNALLOCATED
010000PTEST
010001UNALLOCATED
01001xUNALLOCATED
0101xxUNALLOCATED
011xxxUNALLOCATED
1UNALLOCATED

SVE predicate first active

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001100000Pg0Pdn
Decode fields Instruction Details
opS
00UNALLOCATED
01PFIRST
1UNALLOCATED

SVE predicate zero

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011000111001000000Pd
Decode fields Instruction Details
opS
00PFALSE
01UNALLOCATED
1UNALLOCATED

SVE predicate read from FFR (predicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001111000Pg0Pd
Decode fields Instruction Details
opS
00RDFFR, RDFFRS (predicated)not setting the condition flags
01RDFFR, RDFFRS (predicated)setting the condition flags
1UNALLOCATED

SVE predicate read from FFR (unpredicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011001111100000000Pd
Decode fields Instruction Details
opS
00RDFFR (unpredicated)
01UNALLOCATED
1UNALLOCATED

SVE predicate initialize

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101size01100S111000pattern0Pd
Decode fields Instruction Details
S
0PTRUE, PTRUESnot setting the condition flags
1PTRUE, PTRUESsetting the condition flags

SVE Integer Compare - Scalars

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101100op0op1op2
Decode fields Instruction details
op0op1op2
0x SVE integer compare scalar count and limit
10 00 0000 SVE conditionally terminate scalars
10 00 != 0000 UNALLOCATED
11 00 SVE pointer conflict compare
1x != 00 UNALLOCATED

SVE integer compare scalar count and limit

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm000sfUltRneqPd
Decode fields Instruction Details
Ulteq
000WHILEGE
001WHILEGT
010WHILELT
011WHILELE
100WHILEHS
101WHILEHI
110WHILELO
111WHILELS

SVE conditionally terminate scalars

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101opsz1Rm001000Rnne0000
Decode fields Instruction Details
opne
0UNALLOCATED
10CTERMEQ, CTERMNECTERMEQ
11CTERMEQ, CTERMNECTERMNE

SVE pointer conflict compare

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm001100RnrwPd
Decode fields Instruction Details
rw
0WHILEWR
1WHILERW

SVE Integer Wide Immediate - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op0op111
Decode fields Instruction details
op0op1
00 SVE integer add/subtract immediate (unpredicated)
01 SVE integer min/max immediate (unpredicated)
10 SVE integer multiply immediate (unpredicated)
11 0 SVE broadcast integer immediate (unpredicated)
11 1 SVE broadcast floating-point immediate (unpredicated)

SVE integer add/subtract immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size100opc11shimm8Zdn
Decode fields Instruction Details
opc
000ADD (immediate)
001SUB (immediate)
010UNALLOCATED
011SUBR (immediate)
100SQADD (immediate)
101UQADD (immediate)
110SQSUB (immediate)
111UQSUB (immediate)

SVE integer min/max immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size101opc11o2imm8Zdn
Decode fields Instruction Details
opco2
0xx1UNALLOCATED
0000SMAX (immediate)
0010UMAX (immediate)
0100SMIN (immediate)
0110UMIN (immediate)
1xxUNALLOCATED

SVE integer multiply immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size110opc11o2imm8Zdn
Decode fields Instruction Details
opco2
0000MUL (immediate)
0001UNALLOCATED
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

SVE broadcast integer immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc011shimm8Zd
Decode fields Instruction Details
opc
00DUP (immediate)
01UNALLOCATED
1xUNALLOCATED

SVE broadcast floating-point immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc111o2imm8Zd
Decode fields Instruction Details
opco2
000FDUP
001UNALLOCATED
01UNALLOCATED
1xUNALLOCATED

SVE predicate count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size100opc10Pgo2PnRd
Decode fields Instruction Details
opco2
0000CNTP
0001UNALLOCATED
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

SVE Inc/Dec by Predicate Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op01000op1
Decode fields Instruction details
op0op1
0 0 SVE saturating inc/dec vector by predicate count
0 1 SVE saturating inc/dec register by predicate count
1 0 SVE inc/dec vector by predicate count
1 1 SVE inc/dec register by predicate count

SVE saturating inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10000opcPmZdn
Decode fields Instruction Details
DUopc
01UNALLOCATED
1xUNALLOCATED
0000SQINCP (vector)
0100UQINCP (vector)
1000SQDECP (vector)
1100UQDECP (vector)

SVE saturating inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10001sfopPmRdn
Decode fields Instruction Details
DUsfop
1UNALLOCATED
0000SQINCP (scalar)32-bit
0010SQINCP (scalar)64-bit
0100UQINCP (scalar)32-bit
0110UQINCP (scalar)64-bit
1000SQDECP (scalar)32-bit
1010SQDECP (scalar)64-bit
1100UQDECP (scalar)32-bit
1110UQDECP (scalar)64-bit

SVE inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10000opc2PmZdn
Decode fields Instruction Details
opDopc2
001UNALLOCATED
01xUNALLOCATED
0000INCP (vector)
0100DECP (vector)
1UNALLOCATED

SVE inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10001opc2PmRdn
Decode fields Instruction Details
opDopc2
001UNALLOCATED
01xUNALLOCATED
0000INCP (scalar)
0100DECP (scalar)
1UNALLOCATED

SVE Write FFR

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op0op11001op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0 00 000 00000 SVE FFR write from predicate
1 00 000 0000 00000 SVE FFR initialise
1 00 000 1xxx 00000 UNALLOCATED
1 00 000 x1xx 00000 UNALLOCATED
1 00 000 xx1x 00000 UNALLOCATED
1 00 000 xxx1 00000 UNALLOCATED
00 000 != 00000 UNALLOCATED
00 != 000 UNALLOCATED
!= 00 UNALLOCATED

SVE FFR write from predicate

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1010001001000Pn00000
Decode fields Instruction Details
opc
00WRFFR
01UNALLOCATED
1xUNALLOCATED

SVE FFR initialise

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1011001001000000000000
Decode fields Instruction Details
opc
00SETFFR
01UNALLOCATED
1xUNALLOCATED

SVE Integer Multiply-Add - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010000op0
Decode fields Instruction details
op0
0000 SVE integer dot product (unpredicated)
0001 SVE2 saturating multiply-add interleaved long
001x CDOT (vectors)
01xx SVE2 complex integer multiply-add
10xx SVE2 integer multiply-add long
110x SVE2 saturating multiply-add long
1110 SVE2 saturating multiply-add high
1111 UNALLOCATED

SVE integer dot product (unpredicated)

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00000UZnZda
Decode fields Instruction Details
U
0SDOT (vectors)
1UDOT (vectors)

SVE2 saturating multiply-add interleaved long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00001SZnZda
Decode fields Instruction Details
S
0SQDMLALBT
1SQDMLSLBT

SVE2 complex integer multiply-add

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm001oprotZnZda
Decode fields Instruction Details
op
0CMLA (vectors)
1SQRDCMLAH (vectors)

SVE2 integer multiply-add long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm010SUTZnZda
Decode fields Instruction Details
SUT
000SMLALB (vectors)
001SMLALT (vectors)
010UMLALB (vectors)
011UMLALT (vectors)
100SMLSLB (vectors)
101SMLSLT (vectors)
110UMLSLB (vectors)
111UMLSLT (vectors)

SVE2 saturating multiply-add long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm0110STZnZda
Decode fields Instruction Details
ST
00SQDMLALB (vectors)
01SQDMLALT (vectors)
10SQDMLSLB (vectors)
11SQDMLSLT (vectors)

SVE2 saturating multiply-add high

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm01110SZnZda
Decode fields Instruction Details
S
0SQRDMLAH (vectors)
1SQRDMLSH (vectors)

SVE2 Integer - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001000op010op1
Decode fields Instruction details
op0op1
0010 1 SVE2 integer pairwise add and accumulate long
0011 1 UNALLOCATED
011x 1 UNALLOCATED
0x0x 1 SVE2 integer unary operations (predicated)
0xxx 0 SVE2 saturating/rounding bitwise shift left (predicated)
10xx 0 SVE2 integer halving add/subtract (predicated)
10xx 1 SVE2 integer pairwise arithmetic
11xx 0 SVE2 saturating add/subtract
11xx 1 UNALLOCATED

SVE2 integer pairwise add and accumulate long

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00010U101PgZnZda
Decode fields Instruction Details
U
0SADALP
1UADALP

SVE2 integer unary operations (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00Q0opc101PgZnZd
Decode fields Instruction Details
Qopc
1xUNALLOCATED
000URECPE
001URSQRTE
100SQABS
101SQNEG

SVE2 saturating/rounding bitwise shift left (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00QRNU100PgZmZdn
Decode fields Instruction Details
QRNU
00UNALLOCATED
0010SRSHL
0011URSHL
0110SRSHLR
0111URSHLR
1000SQSHL (vectors)
1001UQSHL (vectors)
1010SQRSHL
1011UQRSHL
1100SQSHLR
1101UQSHLR
1110SQRSHLR
1111UQRSHLR

SVE2 integer halving add/subtract (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010RSU100PgZmZdn
Decode fields Instruction Details
RSU
000SHADD
001UHADD
010SHSUB
011UHSUB
100SRHADD
101URHADD
110SHSUBR
111UHSUBR

SVE2 integer pairwise arithmetic

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010opcU101PgZmZdn
Decode fields Instruction Details
opcU
000UNALLOCATED
001ADDP
01UNALLOCATED
100SMAXP
101UMAXP
110SMINP
111UMINP

SVE2 saturating add/subtract

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size011opSU100PgZmZdn
Decode fields Instruction Details
opSU
000SQADD (vectors, predicated)
001UQADD (vectors, predicated)
010SQSUB (vectors, predicated)
011UQSUB (vectors, predicated)
100SUQADD
101USQADD
110SQSUBR
111UQSUBR

SVE Multiply - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001001op0
Decode fields Instruction details
op0
00000x SVE integer dot product (indexed)
00001x SVE2 integer multiply-add (indexed)
00010x SVE2 saturating multiply-add high (indexed)
00011x UNALLOCATED
001xxx SVE2 saturating multiply-add (indexed)
0100xx SVE2 complex integer dot product (indexed)
0101xx UNALLOCATED
0110xx SVE2 complex integer multiply-add (indexed)
0111xx SVE2 complex saturating multiply-add (indexed)
10xxxx SVE2 integer multiply-add long (indexed)
110xxx SVE2 integer multiply long (indexed)
1110xx SVE2 saturating multiply (indexed)
11110x SVE2 saturating multiply high (indexed)
111110 SVE2 integer multiply (indexed)
111111 UNALLOCATED

SVE integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00000UZnZda
Decode fields Instruction Details
sizeU
0xUNALLOCATED
100SDOT (indexed)32-bit
101UDOT (indexed)32-bit
110SDOT (indexed)64-bit
111UDOT (indexed)64-bit

SVE2 integer multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00001SZnZda
Decode fields Instruction Details
sizeS
0x0MLA (indexed)16-bit
0x1MLS (indexed)16-bit
100MLA (indexed)32-bit
101MLS (indexed)32-bit
110MLA (indexed)64-bit
111MLS (indexed)64-bit

SVE2 saturating multiply-add high (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00010SZnZda
Decode fields Instruction Details
sizeS
0x0SQRDMLAH (indexed)16-bit
0x1SQRDMLSH (indexed)16-bit
100SQRDMLAH (indexed)32-bit
101SQRDMLSH (indexed)32-bit
110SQRDMLAH (indexed)64-bit
111SQRDMLSH (indexed)64-bit

SVE2 saturating multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc001SilTZnZda
Decode fields Instruction Details
sizeST
0xUNALLOCATED
1000SQDMLALB (indexed)32-bit
1001SQDMLALT (indexed)32-bit
1010SQDMLSLB (indexed)32-bit
1011SQDMLSLT (indexed)32-bit
1100SQDMLALB (indexed)64-bit
1101SQDMLALT (indexed)64-bit
1110SQDMLSLB (indexed)64-bit
1111SQDMLSLT (indexed)64-bit

SVE2 complex integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0100rotZnZda
Decode fields Instruction Details
size
0xUNALLOCATED
10CDOT (indexed)32-bit
11CDOT (indexed)64-bit

SVE2 complex integer multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0110rotZnZda
Decode fields Instruction Details
size
0xUNALLOCATED
10CMLA (indexed)16-bit
11CMLA (indexed)32-bit

SVE2 complex saturating multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0111rotZnZda
Decode fields Instruction Details
size
0xUNALLOCATED
10SQRDCMLAH (indexed)16-bit
11SQRDCMLAH (indexed)32-bit

SVE2 integer multiply-add long (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc10SUilTZnZda
Decode fields Instruction Details
sizeSUT
0xUNALLOCATED
10000SMLALB (indexed)32-bit
10001SMLALT (indexed)32-bit
10010UMLALB (indexed)32-bit
10011UMLALT (indexed)32-bit
10100SMLSLB (indexed)32-bit
10101SMLSLT (indexed)32-bit
10110UMLSLB (indexed)32-bit
10111UMLSLT (indexed)32-bit
11000SMLALB (indexed)64-bit
11001SMLALT (indexed)64-bit
11010UMLALB (indexed)64-bit
11011UMLALT (indexed)64-bit
11100SMLSLB (indexed)64-bit
11101SMLSLT (indexed)64-bit
11110UMLSLB (indexed)64-bit
11111UMLSLT (indexed)64-bit

SVE2 integer multiply long (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc110UilTZnZd
Decode fields Instruction Details
sizeUT
0xUNALLOCATED
1000SMULLB (indexed)32-bit
1001SMULLT (indexed)32-bit
1010UMULLB (indexed)32-bit
1011UMULLT (indexed)32-bit
1100SMULLB (indexed)64-bit
1101SMULLT (indexed)64-bit
1110UMULLB (indexed)64-bit
1111UMULLT (indexed)64-bit

SVE2 saturating multiply (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc1110ilTZnZd
Decode fields Instruction Details
sizeT
0xUNALLOCATED
100SQDMULLB (indexed)32-bit
101SQDMULLT (indexed)32-bit
110SQDMULLB (indexed)64-bit
111SQDMULLT (indexed)64-bit

SVE2 saturating multiply high (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc11110RZnZd
Decode fields Instruction Details
sizeR
0x0SQDMULH (indexed)16-bit
0x1SQRDMULH (indexed)16-bit
100SQDMULH (indexed)32-bit
101SQRDMULH (indexed)32-bit
110SQDMULH (indexed)64-bit
111SQRDMULH (indexed)64-bit

SVE2 integer multiply (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc111110ZnZd
Decode fields Instruction Details
size
0xMUL (indexed)16-bit
10MUL (indexed)32-bit
11MUL (indexed)64-bit

SVE2 Widening Integer Arithmetic

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010100op0
Decode fields Instruction details
op0
0x SVE2 integer add/subtract long
10 SVE2 integer add/subtract wide
11 SVE2 integer multiply long

SVE2 integer add/subtract long

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm00opSUTZnZd
Decode fields Instruction Details
opSUT
0000SADDLB
0001SADDLT
0010UADDLB
0011UADDLT
0100SSUBLB
0101SSUBLT
0110USUBLB
0111USUBLT
10UNALLOCATED
1100SABDLB
1101SABDLT
1110UABDLB
1111UABDLT

SVE2 integer add/subtract wide

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm010SUTZnZd
Decode fields Instruction Details
SUT
000SADDWB
001SADDWT
010UADDWB
011UADDWT
100SSUBWB
101SSUBWT
110USUBWB
111USUBWT

SVE2 integer multiply long

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm011opUTZnZd
Decode fields Instruction Details
opUT
000SQDMULLB (vectors)
001SQDMULLT (vectors)
010PMULLB
011PMULLT
100SMULLB (vectors)
101SMULLT (vectors)
110UMULLB (vectors)
111UMULLT (vectors)

SVE2 Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op0010op1
Decode fields Instruction details
op0op1
0 10x SVE2 bitwise shift left long
1 10x UNALLOCATED
00x SVE2 integer add/subtract interleaved long
010 SVE2 bitwise exclusive-or interleaved
011 UNALLOCATED
11x SVE2 bitwise permute

SVE2 bitwise shift left long

These instructions are under SVE2 Misc.

313029282726252423222120191817161514131211109876543210
010001010tszh0tszlimm31010UTZnZd
Decode fields Instruction Details
UT
00SSHLLB
01SSHLLT
10USHLLB
11USHLLT

SVE2 integer add/subtract interleaved long

These instructions are under SVE2 Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1000StbZnZd
Decode fields Instruction Details
Stb
00SADDLBT
01UNALLOCATED
10SSUBLBT
11SSUBLTB

SVE2 bitwise exclusive-or interleaved

These instructions are under SVE2 Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm10010tbZnZd
Decode fields Instruction Details
tb
0EORBT
1EORTB

SVE2 bitwise permute

These instructions are under SVE2 Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1011opcZnZd
Decode fields Instruction Details
opc
00BEXT
01BDEP
10BGRP
11UNALLOCATED

SVE2 Accumulate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001010op011op1
Decode fields Instruction details
op0op1
0000 011 SVE2 complex integer add
!= 0000 011 UNALLOCATED
00x SVE2 integer absolute difference and accumulate long
010 SVE2 integer add/subtract long with carry
10x SVE2 bitwise shift right and accumulate
110 SVE2 bitwise shift and insert
111 SVE2 integer absolute difference and accumulate

SVE2 complex integer add

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size00000op11011rotZmZdn
Decode fields Instruction Details
op
0CADD
1SQCADD

SVE2 integer absolute difference and accumulate long

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1100UTZnZda
Decode fields Instruction Details
UT
00SABALB
01SABALT
10UABALB
11UABALT

SVE2 integer add/subtract long with carry

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11010TZnZda
Decode fields Instruction Details
sizeT
0x0ADCLB
0x1ADCLT
1x0SBCLB
1x1SBCLT

SVE2 bitwise shift right and accumulate

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm31110RUZnZda
Decode fields Instruction Details
RU
00SSRA
01USRA
10SRSRA
11URSRA

SVE2 bitwise shift and insert

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm311110opZnZd
Decode fields Instruction Details
op
0SRI
1SLI

SVE2 integer absolute difference and accumulate

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11111UZnZda
Decode fields Instruction Details
U
0SABA
1UABA

SVE2 Narrowing

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op01op10op2
Decode fields Instruction details
op0op1op2
0 000 10 SVE2 saturating extract narrow
0 != 000 10 UNALLOCATED
0 0x SVE2 bitwise shift right narrow
1 0x UNALLOCATED
1 10 UNALLOCATED
11 SVE2 integer add/subtract narrow high part

SVE2 saturating extract narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010opcTZnZd
Decode fields Instruction Details
opcT
000SQXTNB
001SQXTNT
010UQXTNB
011UQXTNT
100SQXTUNB
101SQXTUNT
11UNALLOCATED

SVE2 bitwise shift right narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm300opURTZnZd
Decode fields Instruction Details
opURT
0000SQSHRUNB
0001SQSHRUNT
0010SQRSHRUNB
0011SQRSHRUNT
0100SHRNB
0101SHRNT
0110RSHRNB
0111RSHRNT
1000SQSHRNB
1001SQSHRNT
1010SQRSHRNB
1011SQRSHRNT
1100UQSHRNB
1101UQSHRNT
1110UQRSHRNB
1111UQRSHRNT

SVE2 integer add/subtract narrow high part

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
01000101size1Zm011SRTZnZd
Decode fields Instruction Details
SRT
000ADDHNB
001ADDHNT
010RADDHNB
011RADDHNT
100SUBHNB
101SUBHNT
110RSUBHNB
111RSUBHNT

SVE2 character match

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101size1Zm100PgZnopPd
Decode fields Instruction Details
op
0MATCH
1NMATCH

SVE2 Histogram Computation - Segment

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001011101op0
Decode fields Instruction details
op0
000 HISTSEG
!= 000 UNALLOCATED

SVE2 Crypto Extensions

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001011op0op1111op2op3
Decode fields Instruction details
op0op1op2op3
000 00 00 00000 SVE2 crypto unary operations
000 00 00 != 00000 UNALLOCATED
000 00 x1 UNALLOCATED
000 01 0x UNALLOCATED
000 01 11 UNALLOCATED
000 1x 00 SVE2 crypto destructive binary operations
000 1x x1 UNALLOCATED
!= 000 0x UNALLOCATED
!= 000 11 UNALLOCATED
10 SVE2 crypto constructive binary operations

SVE2 crypto unary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10000011100op00000Zdn
Decode fields Instruction Details
sizeop
000AESMC
001AESIMC
01UNALLOCATED
1xUNALLOCATED

SVE2 crypto destructive binary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10001op11100o2ZmZdn
Decode fields Instruction Details
sizeopo2
0000AESE
0001AESD
0010SM4E
0011UNALLOCATED
01UNALLOCATED
1xUNALLOCATED

SVE2 crypto constructive binary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1Zm11110opZnZd
Decode fields Instruction Details
sizeop
000SM4EKEY
001RAX1
01UNALLOCATED
1xUNALLOCATED

SVE2 floating-point convert precision

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc0010opc2101PgZnZd
Decode fields Instruction Details
opcopc2
000xUNALLOCATED
0010FCVTXNT
0011UNALLOCATED
01UNALLOCATED
1000FCVTNTsingle-precision to half-precision
1001FCVTLThalf-precision to single-precision
101xUNALLOCATED
110xUNALLOCATED
1110FCVTNTdouble-precision to single-precision
1111FCVTLTsingle-precision to double-precision

SVE2 floating-point pairwise operations

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size010opc100PgZmZdn
Decode fields Instruction Details
opc
000FADDP
001UNALLOCATED
01xUNALLOCATED
100FMAXNMP
101FMINNMP
110FMAXP
111FMINP

SVE floating-point multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc00000opZnZda
Decode fields Instruction Details
sizeop
0x0FMLA (indexed)half-precision
0x1FMLS (indexed)half-precision
100FMLA (indexed)single-precision
101FMLS (indexed)single-precision
110FMLA (indexed)double-precision
111FMLS (indexed)double-precision

SVE floating-point complex multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0001rotZnZda
Decode fields Instruction Details
size
0xUNALLOCATED
10FCMLA (indexed)half-precision
11FCMLA (indexed)single-precision

SVE floating-point multiply (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc001000ZnZd
Decode fields Instruction Details
size
0xFMUL (indexed)half-precision
10FMUL (indexed)single-precision
11FMUL (indexed)double-precision

SVE2 Floating Point Widening Multiply-Add - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op01010
Decode fields Instruction details
op0
0 UNALLOCATED
1 SVE2 floating-point multiply-add long (indexed)

SVE2 floating-point multiply-add long (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details
o2opT
000FMLALB (indexed)
001FMLALT (indexed)
010FMLSLB (indexed)
011FMLSLT (indexed)
1UNALLOCATED

SVE2 floating-point multiply-add long (indexed)

These instructions are under SVE2 Floating Point Widening Multiply-Add - Indexed.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details
o2opT
000FMLALB (indexed)
001FMLALT (indexed)
010FMLSLB (indexed)
011FMLSLT (indexed)
1UNALLOCATED

SVE2 Floating Point Widening Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op011000
Decode fields Instruction details
op0
0 UNALLOCATED
1 SVE2 floating-point multiply-add long

SVE2 floating-point multiply-add long

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details
o2opT
000FMLALB (vectors)
001FMLALT (vectors)
010FMLSLB (vectors)
011FMLSLT (vectors)
1UNALLOCATED

SVE2 floating-point multiply-add long

These instructions are under SVE2 Floating Point Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details
o2opT
000FMLALB (vectors)
001FMLALT (vectors)
010FMLSLB (vectors)
011FMLSLT (vectors)
1UNALLOCATED

SVE floating-point compare vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zmop1o2PgZno3Pd
Decode fields Instruction Details
opo2o3
000FCM<cc> (vectors)FCMGE
001FCM<cc> (vectors)FCMGT
010FCM<cc> (vectors)FCMEQ
011FCM<cc> (vectors)FCMNE
100FCM<cc> (vectors)FCMUO
101FAC<cc>FACGE
110UNALLOCATED
111FAC<cc>FACGT

SVE floating-point arithmetic (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zm000opcZnZd
Decode fields Instruction Details
opc
000FADD (vectors, unpredicated)
001FSUB (vectors, unpredicated)
010FMUL (vectors, unpredicated)
011FTSMUL
10xUNALLOCATED
110FRECPS
111FRSQRTS

SVE Floating Point Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0100op1op2
Decode fields Instruction details
op0op1op2
0x SVE floating-point arithmetic (predicated)
10 000 FTMAD
10 != 000 UNALLOCATED
11 0000 SVE floating-point arithmetic with immediate (predicated)
11 != 0000 UNALLOCATED

SVE floating-point arithmetic (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size00opc100PgZmZdn
Decode fields Instruction Details
opc
0000FADD (vectors, predicated)
0001FSUB (vectors, predicated)
0010FMUL (vectors, predicated)
0011FSUBR (vectors)
0100FMAXNM (vectors)
0101FMINNM (vectors)
0110FMAX (vectors)
0111FMIN (vectors)
1000FABD
1001FSCALE
1010FMULX
1011UNALLOCATED
1100FDIVR
1101FDIV
111xUNALLOCATED

SVE floating-point arithmetic with immediate (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size011opc100Pg0000i1Zdn
Decode fields Instruction Details
opc
000FADD (immediate)
001FSUB (immediate)
010FMUL (immediate)
011FSUBR (immediate)
100FMAXNM (immediate)
101FMINNM (immediate)
110FMAX (immediate)
111FMIN (immediate)

SVE Floating Point Unary Operations - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0101
Decode fields Instruction details
op0
00x SVE floating-point round to integral value
010 SVE floating-point convert precision
011 SVE floating-point unary operations
10x SVE integer convert to floating-point
11x SVE floating-point convert to integer

SVE floating-point round to integral value

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size000opc101PgZnZd
Decode fields Instruction Details
opc
000FRINT<r>nearest with ties to even
001FRINT<r>toward plus infinity
010FRINT<r>toward minus infinity
011FRINT<r>toward zero
100FRINT<r>nearest with ties to away
101UNALLOCATED
110FRINT<r>current mode signalling inexact
111FRINT<r>current mode

SVE floating-point convert precision

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc0010opc2101PgZnZd
Decode fields Instruction Details
opcopc2
000xUNALLOCATED
0010FCVTX
0011UNALLOCATED
01UNALLOCATED
1000FCVTsingle-precision to half-precision
1001FCVThalf-precision to single-precision
101xUNALLOCATED
1100FCVTdouble-precision to half-precision
1101FCVThalf-precision to double-precision
1110FCVTdouble-precision to single-precision
1111FCVTsingle-precision to double-precision

SVE floating-point unary operations

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size0011opc101PgZnZd
Decode fields Instruction Details
opc
00FRECPX
01FSQRT
1xUNALLOCATED

SVE integer convert to floating-point

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc010opc2U101PgZnZd
Decode fields Instruction Details
opcopc2U
00UNALLOCATED
0100UNALLOCATED
01010SCVTF16-bit to half-precision
01011UCVTF16-bit to half-precision
01100SCVTF32-bit to half-precision
01101UCVTF32-bit to half-precision
01110SCVTF64-bit to half-precision
01111UCVTF64-bit to half-precision
100xUNALLOCATED
10100SCVTF32-bit to single-precision
10101UCVTF32-bit to single-precision
1011UNALLOCATED
11000SCVTF32-bit to double-precision
11001UCVTF32-bit to double-precision
1101UNALLOCATED
11100SCVTF64-bit to single-precision
11101UCVTF64-bit to single-precision
11110SCVTF64-bit to double-precision
11111UCVTF64-bit to double-precision

SVE floating-point convert to integer

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc011opc2U101PgZnZd
Decode fields Instruction Details
opcopc2U
000FLOGB
001UNALLOCATED
0100UNALLOCATED
01010FCVTZShalf-precision to 16-bit
01011FCVTZUhalf-precision to 16-bit
01100FCVTZShalf-precision to 32-bit
01101FCVTZUhalf-precision to 32-bit
01110FCVTZShalf-precision to 64-bit
01111FCVTZUhalf-precision to 64-bit
100xUNALLOCATED
10100FCVTZSsingle-precision to 32-bit
10101FCVTZUsingle-precision to 32-bit
1011UNALLOCATED
11000FCVTZSdouble-precision to 32-bit
11001FCVTZUdouble-precision to 32-bit
1101UNALLOCATED
11100FCVTZSsingle-precision to 64-bit
11101FCVTZUsingle-precision to 64-bit
11110FCVTZSdouble-precision to 64-bit
11111FCVTZUdouble-precision to 64-bit

SVE floating-point recursive reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size000opc001PgZnVd
Decode fields Instruction Details
opc
000FADDV
001UNALLOCATED
01xUNALLOCATED
100FMAXNMV
101FMINNMV
110FMAXV
111FMINV

SVE Floating Point Unary Operations - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010010011op0
Decode fields Instruction details
op0
00 SVE floating-point reciprocal estimate (unpredicated)
!= 00 UNALLOCATED

SVE floating-point reciprocal estimate (unpredicated)

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

313029282726252423222120191817161514131211109876543210
01100101size001opc001100ZnZd
Decode fields Instruction Details
opc
0xxUNALLOCATED
10xUNALLOCATED
110FRECPE
111FRSQRTE

SVE Floating Point Compare - with Zero

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101010op0001
Decode fields Instruction details
op0
0 SVE floating-point compare with zero
1 UNALLOCATED

SVE floating-point compare with zero

These instructions are under SVE Floating Point Compare - with Zero.

313029282726252423222120191817161514131211109876543210
01100101size0100eqlt001PgZnnePd
Decode fields Instruction Details
eqltne
000FCM<cc> (zero)FCMGE
001FCM<cc> (zero)FCMGT
010FCM<cc> (zero)FCMLT
011FCM<cc> (zero)FCMLE
11UNALLOCATED
100FCM<cc> (zero)FCMEQ
110FCM<cc> (zero)FCMNE

SVE floating-point serial reduction (predicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size011opc001PgZmVdn
Decode fields Instruction Details
opc
000FADDA
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

SVE Floating Point Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001011op0
Decode fields Instruction details
op0
0 SVE floating-point multiply-accumulate writing addend
1 SVE floating-point multiply-accumulate writing multiplicand

SVE floating-point multiply-accumulate writing addend

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Zm0opcPgZnZda
Decode fields Instruction Details
opc
00FMLA (vectors)
01FMLS (vectors)
10FNMLA
11FNMLS

SVE floating-point multiply-accumulate writing multiplicand

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Za1opcPgZmZdn
Decode fields Instruction Details
opc
00FMAD
01FMSB
10FNMAD
11FNMSB

SVE Memory - 32-bit Gather and Unsized Contiguous

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1000010op0op1op2
Decode fields Instruction details
op0op1op2
00x1 0xx 0 SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
00x1 0xx 1 UNALLOCATED
01x1 0xx SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)
10x1 0xx SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)
1101 000 1 UNALLOCATED
1101 0x1 UNALLOCATED
110x 000 0 LDR (predicate)
110x 010 LDR (vector)
1111 0xx 1 UNALLOCATED
111x 0xx 0 SVE contiguous prefetch (scalar plus immediate)
xx00 10x SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
xx00 110 0 SVE contiguous prefetch (scalar plus scalar)
xx00 111 0 SVE 32-bit gather prefetch (vector plus immediate)
xx00 11x 1 UNALLOCATED
xx01 1xx SVE 32-bit gather load (vector plus immediate)
xx1x 1xx SVE load and broadcast element
xxx0 0xx SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001000xs1Zm0mszPgRn0prfop
Decode fields Instruction Details
msz
00PRFB (scalar plus vector)
01PRFH (scalar plus vector)
10PRFW (scalar plus vector)
11PRFD (scalar plus vector)

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001001xs1Zm0UffPgRnZt
Decode fields Instruction Details
Uff
00LD1SH (scalar plus vector)
01LDFF1SH (scalar plus vector)
10LD1H (scalar plus vector)
11LDFF1H (scalar plus vector)

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001010xs1Zm0UffPgRnZt
Decode fields Instruction Details
Uff
0UNALLOCATED
10LD1W (scalar plus vector)
11LDFF1W (scalar plus vector)

SVE contiguous prefetch (scalar plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010111imm60mszPgRn0prfop
Decode fields Instruction Details
msz
00PRFB (scalar plus immediate)
01PRFH (scalar plus immediate)
10PRFW (scalar plus immediate)
11PRFD (scalar plus immediate)

SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm10UPgZnZt
Decode fields Instruction Details
mszU
000LDNT1SB
001LDNT1B (vector plus scalar)
010LDNT1SH
011LDNT1H (vector plus scalar)
100UNALLOCATED
101LDNT1W (vector plus scalar)
11UNALLOCATED

SVE contiguous prefetch (scalar plus scalar)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm110PgRn0prfop
Decode fields Instruction Details
msz
00PRFB (scalar plus scalar)
01PRFH (scalar plus scalar)
10PRFW (scalar plus scalar)
11PRFD (scalar plus scalar)

SVE 32-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00imm5111PgZn0prfop
Decode fields Instruction Details
msz
00PRFB (vector plus immediate)
01PRFH (vector plus immediate)
10PRFW (vector plus immediate)
11PRFD (vector plus immediate)

SVE 32-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz01imm51UffPgZnZt
Decode fields Instruction Details
mszUff
0000LD1SB (vector plus immediate)
0001LDFF1SB (vector plus immediate)
0010LD1B (vector plus immediate)
0011LDFF1B (vector plus immediate)
0100LD1SH (vector plus immediate)
0101LDFF1SH (vector plus immediate)
0110LD1H (vector plus immediate)
0111LDFF1H (vector plus immediate)
100UNALLOCATED
1010LD1W (vector plus immediate)
1011LDFF1W (vector plus immediate)
11UNALLOCATED

SVE load and broadcast element

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010dtypeh1imm61dtypelPgRnZt
Decode fields Instruction Details
dtypehdtypel
0000LD1RB8-bit element
0001LD1RB16-bit element
0010LD1RB32-bit element
0011LD1RB64-bit element
0100LD1RSW
0101LD1RH16-bit element
0110LD1RH32-bit element
0111LD1RH64-bit element
1000LD1RSH64-bit element
1001LD1RSH32-bit element
1010LD1RW32-bit element
1011LD1RW64-bit element
1100LD1RSB64-bit element
1101LD1RSB32-bit element
1110LD1RSB16-bit element
1111LD1RD

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010mszxs0Zm0UffPgRnZt
Decode fields Instruction Details
mszxsUffZt
0000LD1SB (scalar plus vector)
0001LDFF1SB (scalar plus vector)
0010LD1B (scalar plus vector)
0011LDFF1B (scalar plus vector)
0100LD1SH (scalar plus vector)
0101LDFF1SH (scalar plus vector)
0110LD1H (scalar plus vector)
0111LDFF1H (scalar plus vector)
100UNALLOCATED
1010LD1W (scalar plus vector)
1011LDFF1W (scalar plus vector)
1101UNALLOCATED
110001xxxxUNALLOCATED
1111xxxxUNALLOCATED

SVE Memory - Contiguous Load

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1010010op0op1
Decode fields Instruction details
op0op1
0 001 SVE load and broadcast quadword (scalar plus immediate)
0 101 SVE contiguous load (scalar plus immediate)
0 111 SVE load multiple structures (scalar plus immediate)
1 001 UNALLOCATED
1 101 SVE contiguous non-fault load (scalar plus immediate)
1 111 UNALLOCATED
000 SVE load and broadcast quadword (scalar plus scalar)
010 SVE contiguous load (scalar plus scalar)
011 SVE contiguous first-fault load (scalar plus scalar)
100 UNALLOCATED
110 SVE load multiple structures (scalar plus scalar)

SVE load and broadcast quadword (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszssz0imm4001PgRnZt
Decode fields Instruction Details
mszssz
01UNALLOCATED
1xUNALLOCATED
0000LD1RQB (scalar plus immediate)
0100LD1RQH (scalar plus immediate)
1000LD1RQW (scalar plus immediate)
1100LD1RQD (scalar plus immediate)

SVE contiguous load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype0imm4101PgRnZt
Decode fields Instruction Details
dtype
0000LD1B (scalar plus immediate)8-bit element
0001LD1B (scalar plus immediate)16-bit element
0010LD1B (scalar plus immediate)32-bit element
0011LD1B (scalar plus immediate)64-bit element
0100LD1SW (scalar plus immediate)
0101LD1H (scalar plus immediate)16-bit element
0110LD1H (scalar plus immediate)32-bit element
0111LD1H (scalar plus immediate)64-bit element
1000LD1SH (scalar plus immediate)64-bit element
1001LD1SH (scalar plus immediate)32-bit element
1010LD1W (scalar plus immediate)32-bit element
1011LD1W (scalar plus immediate)64-bit element
1100LD1SB (scalar plus immediate)64-bit element
1101LD1SB (scalar plus immediate)32-bit element
1110LD1SB (scalar plus immediate)16-bit element
1111LD1D (scalar plus immediate)

SVE load multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msznum0imm4111PgRnZt
Decode fields Instruction Details
msznum
0001LD2B (scalar plus immediate)
0010LD3B (scalar plus immediate)
0011LD4B (scalar plus immediate)
0101LD2H (scalar plus immediate)
0110LD3H (scalar plus immediate)
0111LD4H (scalar plus immediate)
1001LD2W (scalar plus immediate)
1010LD3W (scalar plus immediate)
1011LD4W (scalar plus immediate)
1101LD2D (scalar plus immediate)
1110LD3D (scalar plus immediate)
1111LD4D (scalar plus immediate)

SVE contiguous non-fault load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype1imm4101PgRnZt
Decode fields Instruction Details
dtype
0000LDNF1B8-bit element
0001LDNF1B16-bit element
0010LDNF1B32-bit element
0011LDNF1B64-bit element
0100LDNF1SW
0101LDNF1H16-bit element
0110LDNF1H32-bit element
0111LDNF1H64-bit element
1000LDNF1SH64-bit element
1001LDNF1SH32-bit element
1010LDNF1W32-bit element
1011LDNF1W64-bit element
1100LDNF1SB64-bit element
1101LDNF1SB32-bit element
1110LDNF1SB16-bit element
1111LDNF1D

SVE load and broadcast quadword (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszsszRm000PgRnZt
Decode fields Instruction Details
mszssz
01UNALLOCATED
1xUNALLOCATED
0000LD1RQB (scalar plus scalar)
0100LD1RQH (scalar plus scalar)
1000LD1RQW (scalar plus scalar)
1100LD1RQD (scalar plus scalar)

SVE contiguous load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm010PgRnZt
Decode fields Instruction Details
dtype
0000LD1B (scalar plus scalar)8-bit element
0001LD1B (scalar plus scalar)16-bit element
0010LD1B (scalar plus scalar)32-bit element
0011LD1B (scalar plus scalar)64-bit element
0100LD1SW (scalar plus scalar)
0101LD1H (scalar plus scalar)16-bit element
0110LD1H (scalar plus scalar)32-bit element
0111LD1H (scalar plus scalar)64-bit element
1000LD1SH (scalar plus scalar)64-bit element
1001LD1SH (scalar plus scalar)32-bit element
1010LD1W (scalar plus scalar)32-bit element
1011LD1W (scalar plus scalar)64-bit element
1100LD1SB (scalar plus scalar)64-bit element
1101LD1SB (scalar plus scalar)32-bit element
1110LD1SB (scalar plus scalar)16-bit element
1111LD1D (scalar plus scalar)

SVE contiguous first-fault load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm011PgRnZt
Decode fields Instruction Details
dtype
0000LDFF1B (scalar plus scalar)8-bit element
0001LDFF1B (scalar plus scalar)16-bit element
0010LDFF1B (scalar plus scalar)32-bit element
0011LDFF1B (scalar plus scalar)64-bit element
0100LDFF1SW (scalar plus scalar)
0101LDFF1H (scalar plus scalar)16-bit element
0110LDFF1H (scalar plus scalar)32-bit element
0111LDFF1H (scalar plus scalar)64-bit element
1000LDFF1SH (scalar plus scalar)64-bit element
1001LDFF1SH (scalar plus scalar)32-bit element
1010LDFF1W (scalar plus scalar)32-bit element
1011LDFF1W (scalar plus scalar)64-bit element
1100LDFF1SB (scalar plus scalar)64-bit element
1101LDFF1SB (scalar plus scalar)32-bit element
1110LDFF1SB (scalar plus scalar)16-bit element
1111LDFF1D (scalar plus scalar)

SVE load multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msznumRm110PgRnZt
Decode fields Instruction Details
msznum
0001LD2B (scalar plus scalar)
0010LD3B (scalar plus scalar)
0011LD4B (scalar plus scalar)
0101LD2H (scalar plus scalar)
0110LD3H (scalar plus scalar)
0111LD4H (scalar plus scalar)
1001LD2W (scalar plus scalar)
1010LD3W (scalar plus scalar)
1011LD4W (scalar plus scalar)
1101LD2D (scalar plus scalar)
1110LD3D (scalar plus scalar)
1111LD4D (scalar plus scalar)

SVE Memory - 64-bit Gather

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1100010op0op1op2
Decode fields Instruction details
op0op1op2
00 101 UNALLOCATED
00 111 0 SVE 64-bit gather prefetch (vector plus immediate)
00 111 1 UNALLOCATED
00 1x0 SVE2 64-bit gather non-temporal load (scalar plus unpacked 32-bit unscaled offsets)
01 1xx SVE 64-bit gather load (vector plus immediate)
10 1xx SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
11 1xx SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
x0 0xx SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)
x1 0xx SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

SVE 64-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00imm5111PgZn0prfop
Decode fields Instruction Details
msz
00PRFB (vector plus immediate)
01PRFH (vector plus immediate)
10PRFW (vector plus immediate)
11PRFD (vector plus immediate)

SVE2 64-bit gather non-temporal load (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00Rm1U0PgZnZt
Decode fields Instruction Details
mszU
000LDNT1SB
001LDNT1B (vector plus scalar)
010LDNT1SH
011LDNT1H (vector plus scalar)
100LDNT1SW
101LDNT1W (vector plus scalar)
110UNALLOCATED
111LDNT1D (vector plus scalar)

SVE 64-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz01imm51UffPgZnZt
Decode fields Instruction Details
mszUff
0000LD1SB (vector plus immediate)
0001LDFF1SB (vector plus immediate)
0010LD1B (vector plus immediate)
0011LDFF1B (vector plus immediate)
0100LD1SH (vector plus immediate)
0101LDFF1SH (vector plus immediate)
0110LD1H (vector plus immediate)
0111LDFF1H (vector plus immediate)
1000LD1SW (vector plus immediate)
1001LDFF1SW (vector plus immediate)
1010LD1W (vector plus immediate)
1011LDFF1W (vector plus immediate)
110UNALLOCATED
1110LD1D (vector plus immediate)
1111LDFF1D (vector plus immediate)

SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz10Zm1UffPgRnZt
Decode fields Instruction Details
mszUff
0000LD1SB (scalar plus vector)
0001LDFF1SB (scalar plus vector)
0010LD1B (scalar plus vector)
0011LDFF1B (scalar plus vector)
0100LD1SH (scalar plus vector)
0101LDFF1SH (scalar plus vector)
0110LD1H (scalar plus vector)
0111LDFF1H (scalar plus vector)
1000LD1SW (scalar plus vector)
1001LDFF1SW (scalar plus vector)
1010LD1W (scalar plus vector)
1011LDFF1W (scalar plus vector)
110UNALLOCATED
1110LD1D (scalar plus vector)
1111LDFF1D (scalar plus vector)

SVE 64-bit gather load (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz11Zm1UffPgRnZt
Decode fields Instruction Details
mszUffZt
001xxxxUNALLOCATED
0100LD1SH (scalar plus vector)
0101LDFF1SH (scalar plus vector)
0110LD1H (scalar plus vector)
0111LDFF1H (scalar plus vector)
1000LD1SW (scalar plus vector)
1001LDFF1SW (scalar plus vector)
1010LD1W (scalar plus vector)
1011LDFF1W (scalar plus vector)
110UNALLOCATED
1110LD1D (scalar plus vector)
1111LDFF1D (scalar plus vector)

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010mszxs0Zm0UffPgRnZt
Decode fields Instruction Details
mszUff
0000LD1SB (scalar plus vector)
0001LDFF1SB (scalar plus vector)
0010LD1B (scalar plus vector)
0011LDFF1B (scalar plus vector)
0100LD1SH (scalar plus vector)
0101LDFF1SH (scalar plus vector)
0110LD1H (scalar plus vector)
0111LDFF1H (scalar plus vector)
1000LD1SW (scalar plus vector)
1001LDFF1SW (scalar plus vector)
1010LD1W (scalar plus vector)
1011LDFF1W (scalar plus vector)
110UNALLOCATED
1110LD1D (scalar plus vector)
1111LDFF1D (scalar plus vector)

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010mszxs1Zm0UffPgRnZt
Decode fields Instruction Details
mszUffZt
001xxxxUNALLOCATED
0100LD1SH (scalar plus vector)
0101LDFF1SH (scalar plus vector)
0110LD1H (scalar plus vector)
0111LDFF1H (scalar plus vector)
1000LD1SW (scalar plus vector)
1001LDFF1SW (scalar plus vector)
1010LD1W (scalar plus vector)
1011LDFF1W (scalar plus vector)
110UNALLOCATED
1110LD1D (scalar plus vector)
1111LDFF1D (scalar plus vector)

SVE Memory - Store

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1op2
Decode fields Instruction details
op0op1op2
0xx0x 000 UNALLOCATED
0xx1x 00x UNALLOCATED
10x0x 000 UNALLOCATED
10x1x 00x UNALLOCATED
1101x 001 UNALLOCATED
110xx 000 0 STR (predicate)
110xx 000 1 UNALLOCATED
1110x 000 UNALLOCATED
1111x 00x UNALLOCATED
xx00x 001 SVE2 64-bit scatter non-temporal store (vector plus scalar)
xx00x 101 SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)
xx00x 1x0 SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)
xx01x 101 SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)
xx01x 1x0 SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
xx10x 001 SVE2 32-bit scatter non-temporal store (vector plus scalar)
xx10x 101 SVE 64-bit scatter store (vector plus immediate)
xx10x 1x0 SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
xx11x 101 SVE 32-bit scatter store (vector plus immediate)
xx11x 1x0 SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
xxxx0 111 SVE contiguous store (scalar plus immediate)
xxxx1 111 SVE store multiple structures (scalar plus immediate)
010 SVE contiguous store (scalar plus scalar)
011 SVE store multiple structures (scalar plus scalar)

SVE2 64-bit scatter non-temporal store (vector plus scalar)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm001PgZnZt
Decode fields Instruction Details
msz
00STNT1B (vector plus scalar)
01STNT1H (vector plus scalar)
10STNT1W (vector plus scalar)
11STNT1D (vector plus scalar)

SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm101PgRnZt
Decode fields Instruction Details
msz
00ST1B (scalar plus vector)
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00ST1B (scalar plus vector)
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm101PgRnZt
Decode fields Instruction Details
msz
00UNALLOCATED
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00UNALLOCATED
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11ST1D (scalar plus vector)

SVE2 32-bit scatter non-temporal store (vector plus scalar)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz10Rm001PgZnZt
Decode fields Instruction Details
msz
00STNT1B (vector plus scalar)
01STNT1H (vector plus scalar)
10STNT1W (vector plus scalar)
11UNALLOCATED

SVE 64-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz10imm5101PgZnZt
Decode fields Instruction Details
msz
00ST1B (vector plus immediate)
01ST1H (vector plus immediate)
10ST1W (vector plus immediate)
11ST1D (vector plus immediate)

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz10Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00ST1B (scalar plus vector)
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11UNALLOCATED

SVE 32-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz11imm5101PgZnZt
Decode fields Instruction Details
msz
00ST1B (vector plus immediate)
01ST1H (vector plus immediate)
10ST1W (vector plus immediate)
11UNALLOCATED

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msz11Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00UNALLOCATED
01ST1H (scalar plus vector)
10ST1W (scalar plus vector)
11UNALLOCATED

SVE contiguous store (scalar plus immediate)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010mszsize0imm4111PgRnZt
Decode fields Instruction Details
msz
00ST1B (scalar plus immediate)
01ST1H (scalar plus immediate)
10ST1W (scalar plus immediate)
11ST1D (scalar plus immediate)

SVE store multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msznum1imm4111PgRnZt
Decode fields Instruction Details
msznum
0001ST2B (scalar plus immediate)
0010ST3B (scalar plus immediate)
0011ST4B (scalar plus immediate)
0101ST2H (scalar plus immediate)
0110ST3H (scalar plus immediate)
0111ST4H (scalar plus immediate)
1001ST2W (scalar plus immediate)
1010ST3W (scalar plus immediate)
1011ST4W (scalar plus immediate)
1101ST2D (scalar plus immediate)
1110ST3D (scalar plus immediate)
1111ST4D (scalar plus immediate)

SVE contiguous store (scalar plus scalar)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010mszsizeRm010PgRnZt
Decode fields Instruction Details
mszsize
00ST1B (scalar plus scalar)
01ST1H (scalar plus scalar)
10ST1W (scalar plus scalar)
1110UNALLOCATED
1111ST1D (scalar plus scalar)

SVE store multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Store.

313029282726252423222120191817161514131211109876543210
1110010msznumRm011PgRnZt
Decode fields Instruction Details
msznum
0001ST2B (scalar plus scalar)
0010ST3B (scalar plus scalar)
0011ST4B (scalar plus scalar)
0101ST2H (scalar plus scalar)
0110ST3H (scalar plus scalar)
0111ST4H (scalar plus scalar)
1001ST2W (scalar plus scalar)
1010ST3W (scalar plus scalar)
1011ST4W (scalar plus scalar)
1101ST2D (scalar plus scalar)
1110ST3D (scalar plus scalar)
1111ST4D (scalar plus scalar)

Data Processing -- Immediate

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
100op0
Decode fields Instruction details
op0
00x PC-rel. addressing
010 Add/subtract (immediate)
011 Add/subtract (immediate, with tags)
100 Logical (immediate)
101 Move wide (immediate)
110 Bitfield
111 Extract

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0ADR
1ADRP

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100010shimm12RnRd
Decode fields Instruction Details
sfopS
000ADD (immediate)32-bit
001ADDS (immediate)32-bit
010SUB (immediate)32-bit
011SUBS (immediate)32-bit
100ADD (immediate)64-bit
101ADDS (immediate)64-bit
110SUB (immediate)64-bit
111SUBS (immediate)64-bit

Add/subtract (immediate, with tags)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100011o2uimm6op3uimm4RnRd
Decode fields Instruction Details Architecture Version
sfopS
0UNALLOCATED-
11UNALLOCATED-
100ADDGArmv8.5
110SUBGArmv8.5

Logical (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sfopcN
01UNALLOCATED
0000AND (immediate)32-bit
0010ORR (immediate)32-bit
0100EOR (immediate)32-bit
0110ANDS (immediate)32-bit
100AND (immediate)64-bit
101ORR (immediate)64-bit
110EOR (immediate)64-bit
111ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sfopchw
01UNALLOCATED
01xUNALLOCATED
000MOVN32-bit
010MOVZ32-bit
011MOVK32-bit
100MOVN64-bit
110MOVZ64-bit
111MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sfopcN
11UNALLOCATED
01UNALLOCATED
0000SBFM32-bit
0010BFM32-bit
0100UBFM32-bit
10UNALLOCATED
1001SBFM64-bit
1011BFM64-bit
1101UBFM64-bit

Extract

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfop21100111No0RmimmsRnRd
Decode fields Instruction Details
sfop21No0imms
x1UNALLOCATED
001UNALLOCATED
1xUNALLOCATED
01xxxxxUNALLOCATED
01UNALLOCATED
000000xxxxxEXTR32-bit
10UNALLOCATED
10010EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0101op1op2
Decode fields Instruction details
op0op1op2
010 0xxxxxxxxxxxxx Conditional branch (immediate)
110 00xxxxxxxxxxxx Exception generation
110 01000000110010 11111 Hints
110 01000000110011 Barriers
110 0100000xxx0100 PSTATE
110 0100100xxxxxxx System with result
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 1xxxxxxxxxxxxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
0101010o1imm19o0cond
Decode fields Instruction Details
o1o0
00B.cond
01UNALLOCATED
1UNALLOCATED

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details Architecture Version
opcop2LL
xx1UNALLOCATED-
x1xUNALLOCATED-
1xxUNALLOCATED-
00000000UNALLOCATED-
00000001SVC-
00000010HVC-
00000011SMC-
001000x1UNALLOCATED-
00100000BRK-
0010001xUNALLOCATED-
010000x1UNALLOCATED-
01000000HLT-
0100001xUNALLOCATED-
01100000TCANCELTME
01100001UNALLOCATED-
0110001xUNALLOCATED-
10000000UNALLOCATED-
10100000UNALLOCATED-
10100001DCPS1-
10100010DCPS2-
10100011DCPS3-
110000UNALLOCATED-
11100001UNALLOCATED-
1110001xUNALLOCATED-

Hints

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111
Decode fields Instruction Details Architecture Version
CRmop2
HINT-
0000000NOP-
0000001YIELD-
0000010WFE-
0000011WFI-
0000100SEV-
0000101SEVL-
0000111XPACD, XPACI, XPACLRIArmv8.3
0001000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIA1716Armv8.3
0001010PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIB1716Armv8.3
0001100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIA1716Armv8.3
0001110AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIB1716Armv8.3
0010000ESBArmv8.2
0010001PSB CSYNCArmv8.2
0010010TSB CSYNCArmv8.4
0010100CSDB-
0011000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAZArmv8.3
0011001PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIASPArmv8.3
0011010PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBZArmv8.3
0011011PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBSPArmv8.3
0011100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAZArmv8.3
0011101AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIASPArmv8.3
0011110AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBZArmv8.3
0011111AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBSPArmv8.3
0100xx0BTIArmv8.5

Barriers

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110011CRmop2Rt
Decode fields Instruction Details Architecture Version
CRmop2Rt
000UNALLOCATED-
001UNALLOCATED-
01011111CLREX-
10111111DMB-
11011111ISB-
111!= 11111UNALLOCATED-
11111111SB-
!= 0x0010011111DSB-
000001111111TCOMMITTME
000010011111SSBB-
0001011UNALLOCATED-
001x011UNALLOCATED-
01xx011UNALLOCATED-
010010011111PSSBB-
1xxx011UNALLOCATED-

PSTATE

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop2Rt
Decode fields Instruction Details Architecture Version
op1op2Rt
!= 11111UNALLOCATED-
11111MSR (immediate)-
00000011111CFINVArmv8.4
00000111111XAFLAGArmv8.5
00001011111AXFLAGArmv8.5

System with result

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100100op1CRnCRmop2Rt
Decode fields Instruction Details Architecture Version
op1CRnCRmop2
!= 011UNALLOCATED-
011!= 0011UNALLOCATED-
0110011!= 011UNALLOCATED-
0110011!= 000x011UNALLOCATED-
01100110000011TSTARTTME
01100110001011TTESTTME

System instructions

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L01op1CRnCRmop2Rt
Decode fields Instruction Details
L
0SYS
1SYSL

System register move

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L1o0op1CRnCRmop2Rt
Decode fields Instruction Details
L
0MSR (register)
1MRS

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details Architecture Version
opcop2op3Rnop4
!= 11111UNALLOCATED-
000011111000000!= 00000UNALLOCATED-
00001111100000000000BR-
000011111000001UNALLOCATED-
000011111000010!= 11111UNALLOCATED-
00001111100001011111BRAA, BRAAZ, BRAB, BRABZkey A, zero modifierArmv8.3
000011111000011!= 11111UNALLOCATED-
00001111100001111111BRAA, BRAAZ, BRAB, BRABZkey B, zero modifierArmv8.3
0000111110001xxUNALLOCATED-
000011111001xxxUNALLOCATED-
00001111101xxxxUNALLOCATED-
0000111111xxxxxUNALLOCATED-
000111111000000!= 00000UNALLOCATED-
00011111100000000000BLR-
000111111000001UNALLOCATED-
000111111000010!= 11111UNALLOCATED-
00011111100001011111BLRAA, BLRAAZ, BLRAB, BLRABZkey A, zero modifierArmv8.3
000111111000011!= 11111UNALLOCATED-
00011111100001111111BLRAA, BLRAAZ, BLRAB, BLRABZkey B, zero modifierArmv8.3
0001111110001xxUNALLOCATED-
000111111001xxxUNALLOCATED-
00011111101xxxxUNALLOCATED-
0001111111xxxxxUNALLOCATED-
001011111000000!= 00000UNALLOCATED-
00101111100000000000RET-
001011111000001UNALLOCATED-
001011111000010!= 11111!= 11111UNALLOCATED-
0010111110000101111111111RETAA, RETABRETAAArmv8.3
001011111000011!= 11111!= 11111UNALLOCATED-
0010111110000111111111111RETAA, RETABRETABArmv8.3
0010111110001xxUNALLOCATED-
001011111001xxxUNALLOCATED-
00101111101xxxxUNALLOCATED-
0010111111xxxxxUNALLOCATED-
001111111UNALLOCATED-
010011111000000!= 11111!= 00000UNALLOCATED-
010011111000000!= 1111100000UNALLOCATED-
01001111100000011111!= 00000UNALLOCATED-
0100111110000001111100000ERET-
010011111000001UNALLOCATED-
010011111000010!= 11111!= 11111UNALLOCATED-
010011111000010!= 1111111111UNALLOCATED-
01001111100001011111!= 11111UNALLOCATED-
0100111110000101111111111ERETAA, ERETABERETAAArmv8.3
010011111000011!= 11111!= 11111UNALLOCATED-
010011111000011!= 1111111111UNALLOCATED-
01001111100001111111!= 11111UNALLOCATED-
0100111110000111111111111ERETAA, ERETABERETABArmv8.3
0100111110001xxUNALLOCATED-
010011111001xxxUNALLOCATED-
01001111101xxxxUNALLOCATED-
0100111111xxxxxUNALLOCATED-
010111111!= 000000UNALLOCATED-
010111111000000!= 11111!= 00000UNALLOCATED-
010111111000000!= 1111100000UNALLOCATED-
01011111100000011111!= 00000UNALLOCATED-
0101111110000001111100000DRPS-
011x11111UNALLOCATED-
10001111100000xUNALLOCATED-
100011111000010BRAA, BRAAZ, BRAB, BRABZkey A, register modifierArmv8.3
100011111000011BRAA, BRAAZ, BRAB, BRABZkey B, register modifierArmv8.3
1000111110001xxUNALLOCATED-
100011111001xxxUNALLOCATED-
10001111101xxxxUNALLOCATED-
1000111111xxxxxUNALLOCATED-
10011111100000xUNALLOCATED-
100111111000010BLRAA, BLRAAZ, BLRAB, BLRABZkey A, register modifierArmv8.3
100111111000011BLRAA, BLRAAZ, BLRAB, BLRABZkey B, register modifierArmv8.3
1001111110001xxUNALLOCATED-
100111111001xxxUNALLOCATED-
10011111101xxxxUNALLOCATED-
1001111111xxxxxUNALLOCATED-
101x11111UNALLOCATED-
11xx11111UNALLOCATED-

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0B
1BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sfop
00CBZ32-bit
01CBNZ32-bit
10CBZ64-bit
11CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0TBZ
1TBNZ

Loads and Stores

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op01op10op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0x00 1 00 000000 Advanced SIMD load/store multiple structures
0x00 1 01 0xxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0x 1xxxxx UNALLOCATED
0x00 1 10 x00000 Advanced SIMD load/store single structure
0x00 1 11 Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0 x1xxxx UNALLOCATED
0x00 1 x0 xx1xxx UNALLOCATED
0x00 1 x0 xxx1xx UNALLOCATED
0x00 1 x0 xxxx1x UNALLOCATED
0x00 1 x0 xxxxx1 UNALLOCATED
1101 0 1x 1xxxxx Load/store memory tags
1x00 1 UNALLOCATED
xx00 0 0x Load/store exclusive
xx01 0 1x 0xxxxx 00 LDAPR/STLR (unscaled immediate)
xx01 0x Load register (literal)
xx10 00 Load/store no-allocate pair (offset)
xx10 01 Load/store register pair (post-indexed)
xx10 10 Load/store register pair (offset)
xx10 11 Load/store register pair (pre-indexed)
xx11 0x 0xxxxx 00 Load/store register (unscaled immediate)
xx11 0x 0xxxxx 01 Load/store register (immediate post-indexed)
xx11 0x 0xxxxx 10 Load/store register (unprivileged)
xx11 0x 0xxxxx 11 Load/store register (immediate pre-indexed)
xx11 0x 1xxxxx 00 Atomic memory operations
xx11 0x 1xxxxx 10 Load/store register (register offset)
xx11 0x 1xxxxx x1 Load/store register (pac)
xx11 1x Load/store register (unsigned immediate)

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details
Lopcode
00000ST4 (multiple structures)
00001UNALLOCATED
00010ST1 (multiple structures)four registers
00011UNALLOCATED
00100ST3 (multiple structures)
00101UNALLOCATED
00110ST1 (multiple structures)three registers
00111ST1 (multiple structures)one register
01000ST2 (multiple structures)
01001UNALLOCATED
01010ST1 (multiple structures)two registers
01011UNALLOCATED
011xxUNALLOCATED
10000LD4 (multiple structures)
10001UNALLOCATED
10010LD1 (multiple structures)four registers
10011UNALLOCATED
10100LD3 (multiple structures)
10101UNALLOCATED
10110LD1 (multiple structures)three registers
10111LD1 (multiple structures)one register
11000LD2 (multiple structures)
11001UNALLOCATED
11010LD1 (multiple structures)two registers
11011UNALLOCATED
111xxUNALLOCATED

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details
LRmopcode
00001UNALLOCATED
00011UNALLOCATED
00101UNALLOCATED
01001UNALLOCATED
01011UNALLOCATED
011xxUNALLOCATED
0!= 111110000ST4 (multiple structures)register offset
0!= 111110010ST1 (multiple structures)four registers, register offset
0!= 111110100ST3 (multiple structures)register offset
0!= 111110110ST1 (multiple structures)three registers, register offset
0!= 111110111ST1 (multiple structures)one register, register offset
0!= 111111000ST2 (multiple structures)register offset
0!= 111111010ST1 (multiple structures)two registers, register offset
0111110000ST4 (multiple structures)immediate offset
0111110010ST1 (multiple structures)four registers, immediate offset
0111110100ST3 (multiple structures)immediate offset
0111110110ST1 (multiple structures)three registers, immediate offset
0111110111ST1 (multiple structures)one register, immediate offset
0111111000ST2 (multiple structures)immediate offset
0111111010ST1 (multiple structures)two registers, immediate offset
10001UNALLOCATED
10011UNALLOCATED
10101UNALLOCATED
11001UNALLOCATED
11011UNALLOCATED
111xxUNALLOCATED
1!= 111110000LD4 (multiple structures)register offset
1!= 111110010LD1 (multiple structures)four registers, register offset
1!= 111110100LD3 (multiple structures)register offset
1!= 111110110LD1 (multiple structures)three registers, register offset
1!= 111110111LD1 (multiple structures)one register, register offset
1!= 111111000LD2 (multiple structures)register offset
1!= 111111010LD1 (multiple structures)two registers, register offset
1111110000LD4 (multiple structures)immediate offset
1111110010LD1 (multiple structures)four registers, immediate offset
1111110100LD3 (multiple structures)immediate offset
1111110110LD1 (multiple structures)three registers, immediate offset
1111110111LD1 (multiple structures)one register, immediate offset
1111111000LD2 (multiple structures)immediate offset
1111111010LD1 (multiple structures)two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR00000opcodeSsizeRnRt
Decode fields Instruction Details
LRopcodeSsize
011xUNALLOCATED
00000ST1 (single structure)8-bit
00001ST3 (single structure)8-bit
00010x0ST1 (single structure)16-bit
00010x1UNALLOCATED
00011x0ST3 (single structure)16-bit
00011x1UNALLOCATED
0010000ST1 (single structure)32-bit
001001xUNALLOCATED
00100001ST1 (single structure)64-bit
00100101UNALLOCATED
0010100ST3 (single structure)32-bit
0010110UNALLOCATED
00101001ST3 (single structure)64-bit
00101011UNALLOCATED
001011x1UNALLOCATED
01000ST2 (single structure)8-bit
01001ST4 (single structure)8-bit
01010x0ST2 (single structure)16-bit
01010x1UNALLOCATED
01011x0ST4 (single structure)16-bit
01011x1UNALLOCATED
0110000ST2 (single structure)32-bit
0110010UNALLOCATED
01100001ST2 (single structure)64-bit
01100011UNALLOCATED
011001x1UNALLOCATED
0110100ST4 (single structure)32-bit
0110110UNALLOCATED
01101001ST4 (single structure)64-bit
01101011UNALLOCATED
011011x1UNALLOCATED
10000LD1 (single structure)8-bit
10001LD3 (single structure)8-bit
10010x0LD1 (single structure)16-bit
10010x1UNALLOCATED
10011x0LD3 (single structure)16-bit
10011x1UNALLOCATED
1010000LD1 (single structure)32-bit
101001xUNALLOCATED
10100001LD1 (single structure)64-bit
10100101UNALLOCATED
1010100LD3 (single structure)32-bit
1010110UNALLOCATED
10101001LD3 (single structure)64-bit
10101011UNALLOCATED
101011x1UNALLOCATED
101100LD1R
101101UNALLOCATED
101110LD3R
101111UNALLOCATED
11000LD2 (single structure)8-bit
11001LD4 (single structure)8-bit
11010x0LD2 (single structure)16-bit
11010x1UNALLOCATED
11011x0LD4 (single structure)16-bit
11011x1UNALLOCATED
1110000LD2 (single structure)32-bit
1110010UNALLOCATED
11100001LD2 (single structure)64-bit
11100011UNALLOCATED
111001x1UNALLOCATED
1110100LD4 (single structure)32-bit
1110110UNALLOCATED
11101001LD4 (single structure)64-bit
11101011UNALLOCATED
111011x1UNALLOCATED
111100LD2R
111101UNALLOCATED
111110LD4R
111111UNALLOCATED

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details
LRRmopcodeSsize
011xUNALLOCATED
00010x1UNALLOCATED
00011x1UNALLOCATED
001001xUNALLOCATED
00100101UNALLOCATED
0010110UNALLOCATED
00101011UNALLOCATED
001011x1UNALLOCATED
00!= 11111000ST1 (single structure)8-bit, register offset
00!= 11111001ST3 (single structure)8-bit, register offset
00!= 11111010x0ST1 (single structure)16-bit, register offset
00!= 11111011x0ST3 (single structure)16-bit, register offset
00!= 1111110000ST1 (single structure)32-bit, register offset
00!= 11111100001ST1 (single structure)64-bit, register offset
00!= 1111110100ST3 (single structure)32-bit, register offset
00!= 11111101001ST3 (single structure)64-bit, register offset
0011111000ST1 (single structure)8-bit, immediate offset
0011111001ST3 (single structure)8-bit, immediate offset
0011111010x0ST1 (single structure)16-bit, immediate offset
0011111011x0ST3 (single structure)16-bit, immediate offset
001111110000ST1 (single structure)32-bit, immediate offset
0011111100001ST1 (single structure)64-bit, immediate offset
001111110100ST3 (single structure)32-bit, immediate offset
0011111101001ST3 (single structure)64-bit, immediate offset
01010x1UNALLOCATED
01011x1UNALLOCATED
0110010UNALLOCATED
01100011UNALLOCATED
011001x1UNALLOCATED
0110110UNALLOCATED
01101011UNALLOCATED
011011x1UNALLOCATED
01!= 11111000ST2 (single structure)8-bit, register offset
01!= 11111001ST4 (single structure)8-bit, register offset
01!= 11111010x0ST2 (single structure)16-bit, register offset
01!= 11111011x0ST4 (single structure)16-bit, register offset
01!= 1111110000ST2 (single structure)32-bit, register offset
01!= 11111100001ST2 (single structure)64-bit, register offset
01!= 1111110100ST4 (single structure)32-bit, register offset
01!= 11111101001ST4 (single structure)64-bit, register offset
0111111000ST2 (single structure)8-bit, immediate offset
0111111001ST4 (single structure)8-bit, immediate offset
0111111010x0ST2 (single structure)16-bit, immediate offset
0111111011x0ST4 (single structure)16-bit, immediate offset
011111110000ST2 (single structure)32-bit, immediate offset
0111111100001ST2 (single structure)64-bit, immediate offset
011111110100ST4 (single structure)32-bit, immediate offset
0111111101001ST4 (single structure)64-bit, immediate offset
10010x1UNALLOCATED
10011x1UNALLOCATED
101001xUNALLOCATED
10100101UNALLOCATED
1010110UNALLOCATED
10101011UNALLOCATED
101011x1UNALLOCATED
101101UNALLOCATED
101111UNALLOCATED
10!= 11111000LD1 (single structure)8-bit, register offset
10!= 11111001LD3 (single structure)8-bit, register offset
10!= 11111010x0LD1 (single structure)16-bit, register offset
10!= 11111011x0LD3 (single structure)16-bit, register offset
10!= 1111110000LD1 (single structure)32-bit, register offset
10!= 11111100001LD1 (single structure)64-bit, register offset
10!= 1111110100LD3 (single structure)32-bit, register offset
10!= 11111101001LD3 (single structure)64-bit, register offset
10!= 111111100LD1Rregister offset
10!= 111111110LD3Rregister offset
1011111000LD1 (single structure)8-bit, immediate offset
1011111001LD3 (single structure)8-bit, immediate offset
1011111010x0LD1 (single structure)16-bit, immediate offset
1011111011x0LD3 (single structure)16-bit, immediate offset
101111110000LD1 (single structure)32-bit, immediate offset
1011111100001LD1 (single structure)64-bit, immediate offset
101111110100LD3 (single structure)32-bit, immediate offset
1011111101001LD3 (single structure)64-bit, immediate offset
10111111100LD1Rimmediate offset
10111111110LD3Rimmediate offset
11010x1UNALLOCATED
11011x1UNALLOCATED
1110010UNALLOCATED
11100011UNALLOCATED
111001x1UNALLOCATED
1110110UNALLOCATED
11101011UNALLOCATED
111011x1UNALLOCATED
111101UNALLOCATED
111111UNALLOCATED
11!= 11111000LD2 (single structure)8-bit, register offset
11!= 11111001LD4 (single structure)8-bit, register offset
11!= 11111010x0LD2 (single structure)16-bit, register offset
11!= 11111011x0LD4 (single structure)16-bit, register offset
11!= 1111110000LD2 (single structure)32-bit, register offset
11!= 11111100001LD2 (single structure)64-bit, register offset
11!= 1111110100LD4 (single structure)32-bit, register offset
11!= 11111101001LD4 (single structure)64-bit, register offset
11!= 111111100LD2Rregister offset
11!= 111111110LD4Rregister offset
1111111000LD2 (single structure)8-bit, immediate offset
1111111001LD4 (single structure)8-bit, immediate offset
1111111010x0LD2 (single structure)16-bit, immediate offset
1111111011x0LD4 (single structure)16-bit, immediate offset
111111110000LD2 (single structure)32-bit, immediate offset
1111111100001LD2 (single structure)64-bit, immediate offset
111111110100LD4 (single structure)32-bit, immediate offset
1111111101001LD4 (single structure)64-bit, immediate offset
11111111100LD2Rimmediate offset
11111111110LD4Rimmediate offset

Load/store memory tags

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001opc1imm9op2RnRt
Decode fields Instruction Details Architecture Version
opcimm9op2
0001STGpost-indexArmv8.5
0010STGsigned offsetArmv8.5
0011STGpre-indexArmv8.5
0000000000000STZGMArmv8.5
0100LDGArmv8.5
0101STZGpost-indexArmv8.5
0110STZGsigned offsetArmv8.5
0111STZGpre-indexArmv8.5
1001ST2Gpost-indexArmv8.5
1010ST2Gsigned offsetArmv8.5
1011ST2Gpre-indexArmv8.5
10!= 00000000000UNALLOCATED-
1000000000000STGMArmv8.5
1101STZ2Gpost-indexArmv8.5
1110STZ2Gsigned offsetArmv8.5
1111STZ2Gpre-indexArmv8.5
11!= 00000000000UNALLOCATED-
1100000000000LDGMArmv8.5

Load/store exclusive

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size001000o2Lo1Rso0Rt2RnRt
Decode fields Instruction Details Architecture Version
sizeo2Lo1o0Rt2
11!= 11111UNALLOCATED-
0x01!= 11111UNALLOCATED-
000000STXRB-
000001STLXRB-
00001011111CASP, CASPA, CASPAL, CASPL32-bit CASPArmv8.1
00001111111CASP, CASPA, CASPAL, CASPL32-bit CASPLArmv8.1
000100LDXRB-
000101LDAXRB-
00011011111CASP, CASPA, CASPAL, CASPL32-bit CASPAArmv8.1
00011111111CASP, CASPA, CASPAL, CASPL32-bit CASPALArmv8.1
001000STLLRBArmv8.1
001001STLRB-
00101011111CASB, CASAB, CASALB, CASLBCASBArmv8.1
00101111111CASB, CASAB, CASALB, CASLBCASLBArmv8.1
001100LDLARBArmv8.1
001101LDARB-
00111011111CASB, CASAB, CASALB, CASLBCASABArmv8.1
00111111111CASB, CASAB, CASALB, CASLBCASALBArmv8.1
010000STXRH-
010001STLXRH-
01001011111CASP, CASPA, CASPAL, CASPL64-bit CASPArmv8.1
01001111111CASP, CASPA, CASPAL, CASPL64-bit CASPLArmv8.1
010100LDXRH-
010101LDAXRH-
01011011111CASP, CASPA, CASPAL, CASPL64-bit CASPAArmv8.1
01011111111CASP, CASPA, CASPAL, CASPL64-bit CASPALArmv8.1
011000STLLRHArmv8.1
011001STLRH-
01101011111CASH, CASAH, CASALH, CASLHCASHArmv8.1
01101111111CASH, CASAH, CASALH, CASLHCASLHArmv8.1
011100LDLARHArmv8.1
011101LDARH-
01111011111CASH, CASAH, CASALH, CASLHCASAHArmv8.1
01111111111CASH, CASAH, CASALH, CASLHCASALHArmv8.1
100000STXR32-bit-
100001STLXR32-bit-
100010STXP32-bit-
100011STLXP32-bit-
100100LDXR32-bit-
100101LDAXR32-bit-
100110LDXP32-bit-
100111LDAXP32-bit-
101000STLLR32-bitArmv8.1
101001STLR32-bit-
10101011111CAS, CASA, CASAL, CASL32-bit CASArmv8.1
10101111111CAS, CASA, CASAL, CASL32-bit CASLArmv8.1
101100LDLAR32-bitArmv8.1
101101LDAR32-bit-
10111011111CAS, CASA, CASAL, CASL32-bit CASAArmv8.1
10111111111CAS, CASA, CASAL, CASL32-bit CASALArmv8.1
110000STXR64-bit-
110001STLXR64-bit-
110010STXP64-bit-
110011STLXP64-bit-
110100LDXR64-bit-
110101LDAXR64-bit-
110110LDXP64-bit-
110111LDAXP64-bit-
111000STLLR64-bitArmv8.1
111001STLR64-bit-
11101011111CAS, CASA, CASAL, CASL64-bit CASArmv8.1
11101111111CAS, CASA, CASAL, CASL64-bit CASLArmv8.1
111100LDLAR64-bitArmv8.1
111101LDAR64-bit-
11111011111CAS, CASA, CASAL, CASL64-bit CASAArmv8.1
11111111111CAS, CASA, CASAL, CASL64-bit CASALArmv8.1

LDAPR/STLR (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011001opc0imm900RnRt
Decode fields Instruction Details Architecture Version
sizeopc
0000STLURBArmv8.4
0001LDAPURBArmv8.4
0010LDAPURSB64-bitArmv8.4
0011LDAPURSB32-bitArmv8.4
0100STLURHArmv8.4
0101LDAPURHArmv8.4
0110LDAPURSH64-bitArmv8.4
0111LDAPURSH32-bitArmv8.4
1000STLUR32-bitArmv8.4
1001LDAPUR32-bitArmv8.4
1010LDAPURSWArmv8.4
1011UNALLOCATED-
1100STLUR64-bitArmv8.4
1101LDAPUR64-bitArmv8.4
1110UNALLOCATED-
1111UNALLOCATED-

Load register (literal)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc011V00imm19Rt
Decode fields Instruction Details
opcV
000LDR (literal)32-bit
001LDR (literal, SIMD&FP)32-bit
010LDR (literal)64-bit
011LDR (literal, SIMD&FP)64-bit
100LDRSW (literal)
101LDR (literal, SIMD&FP)128-bit
110PRFM (literal)
111UNALLOCATED

Load/store no-allocate pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V000Limm7Rt2RnRt
Decode fields Instruction Details
opcVL
0000STNP32-bit
0001LDNP32-bit
0010STNP (SIMD&FP)32-bit
0011LDNP (SIMD&FP)32-bit
010UNALLOCATED
0110STNP (SIMD&FP)64-bit
0111LDNP (SIMD&FP)64-bit
1000STNP64-bit
1001LDNP64-bit
1010STNP (SIMD&FP)128-bit
1011LDNP (SIMD&FP)128-bit
11UNALLOCATED

Load/store register pair (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V001Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPArmv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V010Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPArmv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register pair (pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V011Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPArmv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm900RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STURB
00001LDURB
00010LDURSB64-bit
00011LDURSB32-bit
00100STUR (SIMD&FP)8-bit
00101LDUR (SIMD&FP)8-bit
00110STUR (SIMD&FP)128-bit
00111LDUR (SIMD&FP)128-bit
01000STURH
01001LDURH
01010LDURSH64-bit
01011LDURSH32-bit
01100STUR (SIMD&FP)16-bit
01101LDUR (SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STUR32-bit
10001LDUR32-bit
10010LDURSW
10100STUR (SIMD&FP)32-bit
10101LDUR (SIMD&FP)32-bit
11000STUR64-bit
11001LDUR64-bit
11010PRFUM
11100STUR (SIMD&FP)64-bit
11101LDUR (SIMD&FP)64-bit

Load/store register (immediate post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm901RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010UNALLOCATED
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Load/store register (unprivileged)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm910RnRt
Decode fields Instruction Details
sizeVopc
1UNALLOCATED
00000STTRB
00001LDTRB
00010LDTRSB64-bit
00011LDTRSB32-bit
01000STTRH
01001LDTRH
01010LDTRSH64-bit
01011LDTRSH32-bit
1x011UNALLOCATED
10000STTR32-bit
10001LDTR32-bit
10010LDTRSW
11000STTR64-bit
11001LDTR64-bit
11010UNALLOCATED

Load/store register (immediate pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm911RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010UNALLOCATED
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Atomic memory operations

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00AR1Rso3opc00RnRt
Decode fields Instruction Details Architecture Version
sizeVARo3opc
01001UNALLOCATED-
0101xUNALLOCATED-
01101UNALLOCATED-
0111xUNALLOCATED-
001100UNALLOCATED-
0111100UNALLOCATED-
1UNALLOCATED-
000000000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDBArmv8.1
000000001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRBArmv8.1
000000010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORBArmv8.1
000000011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETBArmv8.1
000000100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXBArmv8.1
000000101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINBArmv8.1
000000110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXBArmv8.1
000000111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINBArmv8.1
000001000SWPB, SWPAB, SWPALB, SWPLBSWPBArmv8.1
000010000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDLBArmv8.1
000010001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRLBArmv8.1
000010010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORLBArmv8.1
000010011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETLBArmv8.1
000010100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXLBArmv8.1
000010101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINLBArmv8.1
000010110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXLBArmv8.1
000010111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINLBArmv8.1
000011000SWPB, SWPAB, SWPALB, SWPLBSWPLBArmv8.1
000100000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDABArmv8.1
000100001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRABArmv8.1
000100010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORABArmv8.1
000100011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETABArmv8.1
000100100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXABArmv8.1
000100101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINABArmv8.1
000100110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXABArmv8.1
000100111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINABArmv8.1
000101000SWPB, SWPAB, SWPALB, SWPLBSWPABArmv8.1
000101100LDAPRBArmv8.3
000110000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDALBArmv8.1
000110001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRALBArmv8.1
000110010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORALBArmv8.1
000110011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETALBArmv8.1
000110100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXALBArmv8.1
000110101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINALBArmv8.1
000110110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXALBArmv8.1
000110111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINALBArmv8.1
000111000SWPB, SWPAB, SWPALB, SWPLBSWPALBArmv8.1
010000000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDHArmv8.1
010000001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRHArmv8.1
010000010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORHArmv8.1
010000011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETHArmv8.1
010000100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXHArmv8.1
010000101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINHArmv8.1
010000110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXHArmv8.1
010000111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINHArmv8.1
010001000SWPH, SWPAH, SWPALH, SWPLHSWPHArmv8.1
010010000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDLHArmv8.1
010010001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRLHArmv8.1
010010010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORLHArmv8.1
010010011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETLHArmv8.1
010010100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXLHArmv8.1
010010101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINLHArmv8.1
010010110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXLHArmv8.1
010010111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINLHArmv8.1
010011000SWPH, SWPAH, SWPALH, SWPLHSWPLHArmv8.1
010100000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDAHArmv8.1
010100001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRAHArmv8.1
010100010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORAHArmv8.1
010100011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETAHArmv8.1
010100100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXAHArmv8.1
010100101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINAHArmv8.1
010100110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXAHArmv8.1
010100111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINAHArmv8.1
010101000SWPH, SWPAH, SWPALH, SWPLHSWPAHArmv8.1
010101100LDAPRHArmv8.3
010110000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDALHArmv8.1
010110001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRALHArmv8.1
010110010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORALHArmv8.1
010110011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETALHArmv8.1
010110100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXALHArmv8.1
010110101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINALHArmv8.1
010110110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXALHArmv8.1
010110111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINALHArmv8.1
010111000SWPH, SWPAH, SWPALH, SWPLHSWPALHArmv8.1
100000000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDArmv8.1
100000001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRArmv8.1
100000010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORArmv8.1
100000011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETArmv8.1
100000100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXArmv8.1
100000101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINArmv8.1
100000110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXArmv8.1
100000111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINArmv8.1
100001000SWP, SWPA, SWPAL, SWPL32-bit SWPArmv8.1
100010000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDLArmv8.1
100010001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRLArmv8.1
100010010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORLArmv8.1
100010011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETLArmv8.1
100010100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXLArmv8.1
100010101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINLArmv8.1
100010110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXLArmv8.1
100010111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINLArmv8.1
100011000SWP, SWPA, SWPAL, SWPL32-bit SWPLArmv8.1
100100000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDAArmv8.1
100100001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRAArmv8.1
100100010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORAArmv8.1
100100011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETAArmv8.1
100100100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXAArmv8.1
100100101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINAArmv8.1
100100110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXAArmv8.1
100100111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINAArmv8.1
100101000SWP, SWPA, SWPAL, SWPL32-bit SWPAArmv8.1
100101100LDAPR32-bitArmv8.3
100110000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDALArmv8.1
100110001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRALArmv8.1
100110010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORALArmv8.1
100110011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETALArmv8.1
100110100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXALArmv8.1
100110101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINALArmv8.1
100110110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXALArmv8.1
100110111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINALArmv8.1
100111000SWP, SWPA, SWPAL, SWPL32-bit SWPALArmv8.1
110000000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDArmv8.1
110000001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRArmv8.1
110000010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORArmv8.1
110000011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETArmv8.1
110000100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXArmv8.1
110000101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINArmv8.1
110000110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXArmv8.1
110000111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINArmv8.1
110001000SWP, SWPA, SWPAL, SWPL64-bit SWPArmv8.1
110010000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDLArmv8.1
110010001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRLArmv8.1
110010010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORLArmv8.1
110010011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETLArmv8.1
110010100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXLArmv8.1
110010101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINLArmv8.1
110010110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXLArmv8.1
110010111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINLArmv8.1
110011000SWP, SWPA, SWPAL, SWPL64-bit SWPLArmv8.1
110100000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDAArmv8.1
110100001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRAArmv8.1
110100010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORAArmv8.1
110100011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETAArmv8.1
110100100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXAArmv8.1
110100101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINAArmv8.1
110100110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXAArmv8.1
110100111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINAArmv8.1
110101000SWP, SWPA, SWPAL, SWPL64-bit SWPAArmv8.1
110101100LDAPR64-bitArmv8.3
110110000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDALArmv8.1
110110001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRALArmv8.1
110110010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORALArmv8.1
110110011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETALArmv8.1
110110100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXALArmv8.1
110110101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINALArmv8.1
110110110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXALArmv8.1
110110111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINALArmv8.1
110111000SWP, SWPA, SWPAL, SWPL64-bit SWPALArmv8.1

Load/store register (register offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc1RmoptionS10RnRt
Decode fields Instruction Details
sizeVopcoption
x0xUNALLOCATED
x111xUNALLOCATED
00000!= 011STRB (register)extended register
00000011STRB (register)shifted register
00001!= 011LDRB (register)extended register
00001011LDRB (register)shifted register
00010!= 011LDRSB (register)64-bit with extended register offset
00010011LDRSB (register)64-bit with shifted register offset
00011!= 011LDRSB (register)32-bit with extended register offset
00011011LDRSB (register)32-bit with shifted register offset
00100!= 011STR (register, SIMD&FP)
00100011STR (register, SIMD&FP)
00101!= 011LDR (register, SIMD&FP)
00101011LDR (register, SIMD&FP)
00110STR (register, SIMD&FP)
00111LDR (register, SIMD&FP)
01000STRH (register)
01001LDRH (register)
01010LDRSH (register)64-bit
01011LDRSH (register)32-bit
01100STR (register, SIMD&FP)
01101LDR (register, SIMD&FP)
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (register)32-bit
10001LDR (register)32-bit
10010LDRSW (register)
10100STR (register, SIMD&FP)
10101LDR (register, SIMD&FP)
11000STR (register)64-bit
11001LDR (register)64-bit
11010PRFM (register)
11100STR (register, SIMD&FP)
11101LDR (register, SIMD&FP)

Load/store register (pac)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00MS1imm9W1RnRt
Decode fields Instruction Details Architecture Version
sizeVMW
!= 11UNALLOCATED-
11000LDRAA, LDRABkey A, offsetArmv8.3
11001LDRAA, LDRABkey A, pre-indexedArmv8.3
11010LDRAA, LDRABkey B, offsetArmv8.3
11011LDRAA, LDRABkey B, pre-indexedArmv8.3
111UNALLOCATED-

Load/store register (unsigned immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V01opcimm12RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010PRFM (immediate)
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Data Processing -- Register

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0op1101op2op3
Decode fields Instruction details
op0op1op2op3
0 1 0110 Data-processing (2 source)
1 1 0110 Data-processing (1 source)
0 0xxx Logical (shifted register)
0 1xx0 Add/subtract (shifted register)
0 1xx1 Add/subtract (extended register)
1 0000 000000 Add/subtract (with carry)
1 0000 x00001 Rotate right into flags
1 0000 xx0010 Evaluate into flags
1 0010 xxxx0x Conditional compare (register)
1 0010 xxxx1x Conditional compare (immediate)
1 0100 Conditional select
1 1xxx Data-processing (3 source)

Data-processing (2 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf0S11010110RmopcodeRnRd
Decode fields Instruction Details Architecture Version
sfSopcode
000001UNALLOCATED-
011xxxUNALLOCATED-
1xxxxxUNALLOCATED-
000011xUNALLOCATED-
0001101UNALLOCATED-
000111xUNALLOCATED-
100001xUNALLOCATED-
10001xxUNALLOCATED-
1001xxxUNALLOCATED-
101xxxxUNALLOCATED-
0000000UNALLOCATED-
00000010UDIV32-bit-
00000011SDIV32-bit-
0000010xUNALLOCATED-
00001000LSLV32-bit-
00001001LSRV32-bit-
00001010ASRV32-bit-
00001011RORV32-bit-
00001100UNALLOCATED-
00010x11UNALLOCATED-
00010000CRC32B, CRC32H, CRC32W, CRC32XCRC32B-
00010001CRC32B, CRC32H, CRC32W, CRC32XCRC32H-
00010010CRC32B, CRC32H, CRC32W, CRC32XCRC32W-
00010100CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CB-
00010101CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CH-
00010110CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CW-
10000000SUBPArmv8.5
10000010UDIV64-bit-
10000011SDIV64-bit-
10000100IRGArmv8.5
10000101GMIArmv8.5
10001000LSLV64-bit-
10001001LSRV64-bit-
10001010ASRV64-bit-
10001011RORV64-bit-
10001100PACGAArmv8.3
10010xx0UNALLOCATED-
10010x0xUNALLOCATED-
10010011CRC32B, CRC32H, CRC32W, CRC32XCRC32X-
10010111CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CX-
11000000SUBPSArmv8.5

Data-processing (1 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf1S11010110opcode2opcodeRnRd
Decode fields Instruction Details Architecture Version
sfSopcode2opcodeRn
1xxxxxUNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1xxxUNALLOCATED-
1xxxxUNALLOCATED-
00000000011xUNALLOCATED-
000000001xxxUNALLOCATED-
00000001xxxxUNALLOCATED-
1UNALLOCATED-
000001UNALLOCATED-
0000000000000RBIT32-bit-
0000000000001REV1632-bit-
0000000000010REV32-bit-
0000000000011UNALLOCATED-
0000000000100CLZ32-bit-
0000000000101CLS32-bit-
1000000000000RBIT64-bit-
1000000000001REV1664-bit-
1000000000010REV32-
1000000000011REV64-bit-
1000000000100CLZ64-bit-
1000000000101CLS64-bit-
1000001000000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAArmv8.3
1000001000001PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBArmv8.3
1000001000010PACDA, PACDZAPACDAArmv8.3
1000001000011PACDB, PACDZBPACDBArmv8.3
1000001000100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAArmv8.3
1000001000101AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBArmv8.3
1000001000110AUTDA, AUTDZAAUTDAArmv8.3
1000001000111AUTDB, AUTDZBAUTDBArmv8.3
100000100100011111PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIZAArmv8.3
100000100100111111PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIZBArmv8.3
100000100101011111PACDA, PACDZAPACDZAArmv8.3
100000100101111111PACDB, PACDZBPACDZBArmv8.3
100000100110011111AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIZAArmv8.3
100000100110111111AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIZBArmv8.3
100000100111011111AUTDA, AUTDZAAUTDZAArmv8.3
100000100111111111AUTDB, AUTDZBAUTDZBArmv8.3
100000101000011111XPACD, XPACI, XPACLRIXPACIArmv8.3
100000101000111111XPACD, XPACI, XPACLRIXPACDArmv8.3
100000101001xUNALLOCATED-
10000010101xxUNALLOCATED-
1000001011xxxUNALLOCATED-

Logical (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopc01010shiftNRmimm6RnRd
Decode fields Instruction Details
sfopcNimm6
01xxxxxUNALLOCATED
0000AND (shifted register)32-bit
0001BIC (shifted register)32-bit
0010ORR (shifted register)32-bit
0011ORN (shifted register)32-bit
0100EOR (shifted register)32-bit
0101EON (shifted register)32-bit
0110ANDS (shifted register)32-bit
0111BICS (shifted register)32-bit
1000AND (shifted register)64-bit
1001BIC (shifted register)64-bit
1010ORR (shifted register)64-bit
1011ORN (shifted register)64-bit
1100EOR (shifted register)64-bit
1101EON (shifted register)64-bit
1110ANDS (shifted register)64-bit
1111BICS (shifted register)64-bit

Add/subtract (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011shift0Rmimm6RnRd
Decode fields Instruction Details
sfopSshiftimm6
11UNALLOCATED
01xxxxxUNALLOCATED
000ADD (shifted register)32-bit
001ADDS (shifted register)32-bit
010SUB (shifted register)32-bit
011SUBS (shifted register)32-bit
100ADD (shifted register)64-bit
101ADDS (shifted register)64-bit
110SUB (shifted register)64-bit
111SUBS (shifted register)64-bit

Add/subtract (extended register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011opt1Rmoptionimm3RnRd
Decode fields Instruction Details
sfopSoptimm3
1x1UNALLOCATED
11xUNALLOCATED
x1UNALLOCATED
1xUNALLOCATED
00000ADD (extended register)32-bit
00100ADDS (extended register)32-bit
01000SUB (extended register)32-bit
01100SUBS (extended register)32-bit
10000ADD (extended register)64-bit
10100ADDS (extended register)64-bit
11000SUB (extended register)64-bit
11100SUBS (extended register)64-bit

Add/subtract (with carry)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm000000RnRd
Decode fields Instruction Details
sfopS
000ADC32-bit
001ADCS32-bit
010SBC32-bit
011SBCS32-bit
100ADC64-bit
101ADCS64-bit
110SBC64-bit
111SBCS64-bit

Rotate right into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000imm600001Rno2mask
Decode fields Instruction Details Architecture Version
sfopSo2
0UNALLOCATED-
100UNALLOCATED-
1010RMIFArmv8.4
1011UNALLOCATED-
11UNALLOCATED-

Evaluate into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000opcode2sz0010Rno3mask
Decode fields Instruction Details Architecture Version
sfopSopcode2szo3mask
000UNALLOCATED-
001!= 000000UNALLOCATED-
0010000000!= 1101UNALLOCATED-
0010000001UNALLOCATED-
001000000001101SETF8, SETF16SETF8Armv8.4
001000000101101SETF8, SETF16SETF16Armv8.4
01UNALLOCATED-
1UNALLOCATED-

Conditional compare (register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010Rmcond0o2Rno3nzcv
Decode fields Instruction Details
sfopSo2o3
1UNALLOCATED
1UNALLOCATED
0UNALLOCATED
00100CCMN (register)32-bit
01100CCMP (register)32-bit
10100CCMN (register)64-bit
11100CCMP (register)64-bit

Conditional compare (immediate)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010imm5cond1o2Rno3nzcv
Decode fields Instruction Details
sfopSo2o3
1UNALLOCATED
1UNALLOCATED
0UNALLOCATED
00100CCMN (immediate)32-bit
01100CCMP (immediate)32-bit
10100CCMN (immediate)64-bit
11100CCMP (immediate)64-bit

Conditional select

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010100Rmcondop2RnRd
Decode fields Instruction Details
sfopSop2
1xUNALLOCATED
1UNALLOCATED
00000CSEL32-bit
00001CSINC32-bit
01000CSINV32-bit
01001CSNEG32-bit
10000CSEL64-bit
10001CSINC64-bit
11000CSINV64-bit
11001CSNEG64-bit

Data-processing (3 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfop5411011op31Rmo0RaRnRd
Decode fields Instruction Details
sfop54op31o0
000101UNALLOCATED
00011UNALLOCATED
00100UNALLOCATED
001101UNALLOCATED
00111UNALLOCATED
01UNALLOCATED
1xUNALLOCATED
0000000MADD32-bit
0000001MSUB32-bit
0000010UNALLOCATED
0000011UNALLOCATED
0000100UNALLOCATED
0001010UNALLOCATED
0001011UNALLOCATED
0001100UNALLOCATED
1000000MADD64-bit
1000001MSUB64-bit
1000010SMADDL
1000011SMSUBL
1000100SMULH
1001010UMADDL
1001011UMSUBL
1001100UMULH

Data Processing -- Scalar Floating-Point and Advanced SIMD

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0111op1op2op3
Decode fields Instruction details Architecture version
op0op1op2op3
0000 0x x101 00xxxxx10 UNALLOCATED-
0010 0x x101 00xxxxx10 UNALLOCATED-
0100 0x x101 00xxxxx10 Cryptographic AES-
0101 0x x0xx xxx0xxx00 Cryptographic three-register SHA-
0101 0x x0xx xxx0xxx10 UNALLOCATED-
0101 0x x101 00xxxxx10 Cryptographic two-register SHA-
0110 0x x101 00xxxxx10 UNALLOCATED-
0111 0x x0xx xxx0xxxx0 UNALLOCATED-
0111 0x x101 00xxxxx10 UNALLOCATED-
01x1 00 00xx xxx0xxxx1 Advanced SIMD scalar copy-
01x1 01 00xx xxx0xxxx1 UNALLOCATED-
01x1 0x 0111 00xxxxx10 UNALLOCATED-
01x1 0x 10xx xxx00xxx1 Advanced SIMD scalar three same FP16Armv8.2
01x1 0x 10xx xxx01xxx1 UNALLOCATED-
01x1 0x 1111 00xxxxx10 Advanced SIMD scalar two-register miscellaneous FP16Armv8.2
01x1 0x x0xx xxx1xxxx0 UNALLOCATED-
01x1 0x x0xx xxx1xxxx1 Advanced SIMD scalar three same extraArmv8.1
01x1 0x x100 00xxxxx10 Advanced SIMD scalar two-register miscellaneous-
01x1 0x x110 00xxxxx10 Advanced SIMD scalar pairwiseArmv8.2
01x1 0x x1xx 1xxxxxx10 UNALLOCATED-
01x1 0x x1xx x1xxxxx10 UNALLOCATED-
01x1 0x x1xx xxxxxxx00 Advanced SIMD scalar three different-
01x1 0x x1xx xxxxxxxx1 Advanced SIMD scalar three same-
01x1 10 xxxxxxxx1 Advanced SIMD scalar shift by immediate-
01x1 11 xxxxxxxx1 UNALLOCATED-
01x1 1x xxxxxxxx0 Advanced SIMD scalar x indexed elementArmv8.2
0x00 0x x0xx xxx0xxx00 Advanced SIMD table lookup-
0x00 0x x0xx xxx0xxx10 Advanced SIMD permute-
0x10 0x x0xx xxx0xxxx0 Advanced SIMD extract-
0xx0 00 00xx xxx0xxxx1 Advanced SIMD copy-
0xx0 01 00xx xxx0xxxx1 UNALLOCATED-
0xx0 0x 0111 00xxxxx10 UNALLOCATED-
0xx0 0x 10xx xxx00xxx1 Advanced SIMD three same (FP16)Armv8.2
0xx0 0x 10xx xxx01xxx1 UNALLOCATED-
0xx0 0x 1111 00xxxxx10 Advanced SIMD two-register miscellaneous (FP16)Armv8.2
0xx0 0x x0xx xxx1xxxx0 UNALLOCATED-
0xx0 0x x0xx xxx1xxxx1 Advanced SIMD three same extraArmv8.2
0xx0 0x x100 00xxxxx10 Advanced SIMD two-register miscellaneousArmv8.5
0xx0 0x x110 00xxxxx10 Advanced SIMD across lanesArmv8.2
0xx0 0x x1xx 1xxxxxx10 UNALLOCATED-
0xx0 0x x1xx x1xxxxx10 UNALLOCATED-
0xx0 0x x1xx xxxxxxx00 Advanced SIMD three different-
0xx0 0x x1xx xxxxxxxx1 Advanced SIMD three sameArmv8.2
0xx0 10 0000 xxxxxxxx1 Advanced SIMD modified immediateArmv8.2
0xx0 10 != 0000 xxxxxxxx1 Advanced SIMD shift by immediate-
0xx0 11 xxxxxxxx1 UNALLOCATED-
0xx0 1x xxxxxxxx0 Advanced SIMD vector x indexed elementArmv8.2
1100 00 10xx xxx10xxxx Cryptographic three-register, imm2Armv8.2
1100 00 11xx xxx1x00xx Cryptographic three-register SHA 512Armv8.2
1100 00 xxx0xxxxx Cryptographic four-registerArmv8.2
1100 01 00xx XARArmv8.2
1100 01 1000 0001000xx Cryptographic two-register SHA 512Armv8.2
1xx0 1x UNALLOCATED-
x0x1 0x x0xx Conversion between floating-point and fixed-pointArmv8.2
x0x1 0x x1xx xxx000000 Conversion between floating-point and integerArmv8.3
x0x1 0x x1xx xxxx10000 Floating-point data-processing (1 source)Armv8.5
x0x1 0x x1xx xxxxx1000 Floating-point compareArmv8.2
x0x1 0x x1xx xxxxxx100 Floating-point immediateArmv8.2
x0x1 0x x1xx xxxxxxx01 Floating-point conditional compareArmv8.2
x0x1 0x x1xx xxxxxxx10 Floating-point data-processing (2 source)Armv8.2
x0x1 0x x1xx xxxxxxx11 Floating-point conditional selectArmv8.2
x0x1 1x Floating-point data-processing (3 source)Armv8.2

Cryptographic AES

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01001110size10100opcode10RnRd
Decode fields Instruction Details
sizeopcode
x1xxxUNALLOCATED
000xxUNALLOCATED
1xxxxUNALLOCATED
x1UNALLOCATED
0000100AESE
0000101AESD
0000110AESMC
0000111AESIMC
1xUNALLOCATED

Cryptographic three-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size0Rm0opcode00RnRd
Decode fields Instruction Details
sizeopcode
111UNALLOCATED
x1UNALLOCATED
00000SHA1C
00001SHA1P
00010SHA1M
00011SHA1SU0
00100SHA256H
00101SHA256H2
00110SHA256SU1
1xUNALLOCATED

Cryptographic two-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size10100opcode10RnRd
Decode fields Instruction Details
sizeopcode
xx1xxUNALLOCATED
x1xxxUNALLOCATED
1xxxxUNALLOCATED
x1UNALLOCATED
0000000SHA1H
0000001SHA1SU1
0000010SHA256SU0
0000011UNALLOCATED
1xUNALLOCATED

Advanced SIMD scalar copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01op11110000imm50imm41RnRd
Decode fields Instruction Details
opimm5imm4
0xxx1UNALLOCATED
0xx1xUNALLOCATED
0x1xxUNALLOCATED
00000DUP (element)
01xxxUNALLOCATED
0x00000000UNALLOCATED
1UNALLOCATED

Advanced SIMD scalar three same FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
110UNALLOCATED-
1011UNALLOCATED-
00011FMULXArmv8.2
00100FCMEQ (register)Armv8.2
00101UNALLOCATED-
00111FRECPSArmv8.2
01100UNALLOCATED-
01101UNALLOCATED-
01111FRSQRTSArmv8.2
10011UNALLOCATED-
10100FCMGE (register)Armv8.2
10101FACGEArmv8.2
10111UNALLOCATED-
11010FABDArmv8.2
11100FCMGT (register)Armv8.2
11101FACGTArmv8.2
11111UNALLOCATED-

Advanced SIMD scalar two-register miscellaneous FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
11110UNALLOCATED-
0011xxUNALLOCATED-
011111UNALLOCATED-
101111UNALLOCATED-
111100UNALLOCATED-
0011010FCVTNS (vector)Armv8.2
0011011FCVTMS (vector)Armv8.2
0011100FCVTAS (vector)Armv8.2
0011101SCVTF (vector, integer)Armv8.2
0101100FCMGT (zero)Armv8.2
0101101FCMEQ (zero)Armv8.2
0101110FCMLT (zero)Armv8.2
0111010FCVTPS (vector)Armv8.2
0111011FCVTZS (vector, integer)Armv8.2
0111101FRECPEArmv8.2
0111111FRECPXArmv8.2
1011010FCVTNU (vector)Armv8.2
1011011FCVTMU (vector)Armv8.2
1011100FCVTAU (vector)Armv8.2
1011101UCVTF (vector, integer)Armv8.2
1101100FCMGE (zero)Armv8.2
1101101FCMLE (zero)Armv8.2
1101110UNALLOCATED-
1111010FCVTPU (vector)Armv8.2
1111011FCVTZU (vector, integer)Armv8.2
1111101FRSQRTEArmv8.2
1111111UNALLOCATED-

Advanced SIMD scalar three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
Uopcode
001xUNALLOCATED-
01xxUNALLOCATED-
1xxxUNALLOCATED-
00000UNALLOCATED-
00001UNALLOCATED-
10000SQRDMLAH (vector)Armv8.1
10001SQRDMLSH (vector)Armv8.1

Advanced SIMD scalar two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size10000opcode10RnRd
Decode fields Instruction Details
Usizeopcode
0000xUNALLOCATED
00010UNALLOCATED
0010xUNALLOCATED
00110UNALLOCATED
01111UNALLOCATED
1000xUNALLOCATED
10011UNALLOCATED
10101UNALLOCATED
10111UNALLOCATED
1100xUNALLOCATED
11110UNALLOCATED
0x011xxUNALLOCATED
0x11111UNALLOCATED
1x10110UNALLOCATED
1x11100UNALLOCATED
000011SUQADD
000111SQABS
001000CMGT (zero)
001001CMEQ (zero)
001010CMLT (zero)
001011ABS
010010UNALLOCATED
010100SQXTN, SQXTN2
00x10110UNALLOCATED
00x11010FCVTNS (vector)
00x11011FCVTMS (vector)
00x11100FCVTAS (vector)
00x11101SCVTF (vector, integer)
01x01100FCMGT (zero)
01x01101FCMEQ (zero)
01x01110FCMLT (zero)
01x11010FCVTPS (vector)
01x11011FCVTZS (vector, integer)
01x11101FRECPE
01x11111FRECPX
100011USQADD
100111SQNEG
101000CMGE (zero)
101001CMLE (zero)
101010UNALLOCATED
101011NEG (vector)
110010SQXTUN, SQXTUN2
110100UQXTN, UQXTN2
10x10110FCVTXN, FCVTXN2
10x11010FCVTNU (vector)
10x11011FCVTMU (vector)
10x11100FCVTAU (vector)
10x11101UCVTF (vector, integer)
11x01100FCMGE (zero)
11x01101FCMLE (zero)
11x01110UNALLOCATED
11x11010FCVTPU (vector)
11x11011FCVTZU (vector, integer)
11x11101FRSQRTE
11x11111UNALLOCATED

Advanced SIMD scalar pairwise

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
01110UNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
11010UNALLOCATED-
111xxUNALLOCATED-
1x01101UNALLOCATED-
011011ADDP (scalar)-
00001100FMAXNMP (scalar)half-precisionArmv8.2
00001101FADDP (scalar)half-precisionArmv8.2
00001111FMAXP (scalar)half-precisionArmv8.2
00101100UNALLOCATED-
00101101UNALLOCATED-
00101111UNALLOCATED-
01001100FMINNMP (scalar)half-precisionArmv8.2
01001111FMINP (scalar)half-precisionArmv8.2
01101100UNALLOCATED-
01101111UNALLOCATED-
111011UNALLOCATED-
10x01100FMAXNMP (scalar)single-precision and double-precision-
10x01101FADDP (scalar)single-precision and double-precision-
10x01111FMAXP (scalar)single-precision and double-precision-
11x01100FMINNMP (scalar)single-precision and double-precision-
11x01111FMINP (scalar)single-precision and double-precision-

Advanced SIMD scalar three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode00RnRd
Decode fields Instruction Details
Uopcode
00xxUNALLOCATED
01xxUNALLOCATED
1000UNALLOCATED
1010UNALLOCATED
1100UNALLOCATED
111xUNALLOCATED
01001SQDMLAL, SQDMLAL2 (vector)
01011SQDMLSL, SQDMLSL2 (vector)
01101SQDMULL, SQDMULL2 (vector)
11001UNALLOCATED
11011UNALLOCATED
11101UNALLOCATED

Advanced SIMD scalar three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode1RnRd
Decode fields Instruction Details
Usizeopcode
00000UNALLOCATED
0001xUNALLOCATED
00100UNALLOCATED
011xxUNALLOCATED
1001xUNALLOCATED
1x11011UNALLOCATED
000001SQADD
000101SQSUB
000110CMGT (register)
000111CMGE (register)
001000SSHL
001001SQSHL (register)
001010SRSHL
001011SQRSHL
010000ADD (vector)
010001CMTST
010100UNALLOCATED
010101UNALLOCATED
010110SQDMULH (vector)
010111UNALLOCATED
00x11000UNALLOCATED
00x11001UNALLOCATED
00x11010UNALLOCATED
00x11011FMULX
00x11100FCMEQ (register)
00x11101UNALLOCATED
00x11110UNALLOCATED
00x11111FRECPS
01x11000UNALLOCATED
01x11001UNALLOCATED
01x11010UNALLOCATED
01x11100UNALLOCATED
01x11101UNALLOCATED
01x11110UNALLOCATED
01x11111FRSQRTS
100001UQADD
100101UQSUB
100110CMHI (register)
100111CMHS (register)
101000USHL
101001UQSHL (register)
101010URSHL
101011UQRSHL
110000SUB (vector)
110001CMEQ (register)
110100UNALLOCATED
110101UNALLOCATED
110110SQRDMULH (vector)
110111UNALLOCATED
10x11000UNALLOCATED
10x11001UNALLOCATED
10x11010UNALLOCATED
10x11011UNALLOCATED
10x11100FCMGE (register)
10x11101FACGE
10x11110UNALLOCATED
10x11111UNALLOCATED
11x11000UNALLOCATED
11x11001UNALLOCATED
11x11010FABD
11x11100FCMGT (register)
11x11101FACGT
11x11110UNALLOCATED
11x11111UNALLOCATED

Advanced SIMD scalar shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U111110immhimmbopcode1RnRd
Decode fields Instruction Details
Uimmhopcode
!= 000000001UNALLOCATED
!= 000000011UNALLOCATED
!= 000000101UNALLOCATED
!= 000000111UNALLOCATED
!= 000001001UNALLOCATED
!= 000001011UNALLOCATED
!= 000001101UNALLOCATED
!= 000001111UNALLOCATED
!= 0000101xxUNALLOCATED
!= 0000110xxUNALLOCATED
!= 000011101UNALLOCATED
!= 000011110UNALLOCATED
0000UNALLOCATED
0!= 000000000SSHR
0!= 000000010SSRA
0!= 000000100SRSHR
0!= 000000110SRSRA
0!= 000001000UNALLOCATED
0!= 000001010SHL
0!= 000001100UNALLOCATED
0!= 000001110SQSHL (immediate)
0!= 000010000UNALLOCATED
0!= 000010001UNALLOCATED
0!= 000010010SQSHRN, SQSHRN2
0!= 000010011SQRSHRN, SQRSHRN2
0!= 000011100SCVTF (vector, fixed-point)
0!= 000011111FCVTZS (vector, fixed-point)
1!= 000000000USHR
1!= 000000010USRA
1!= 000000100URSHR
1!= 000000110URSRA
1!= 000001000SRI
1!= 000001010SLI
1!= 000001100SQSHLU
1!= 000001110UQSHL (immediate)
1!= 000010000SQSHRUN, SQSHRUN2
1!= 000010001SQRSHRUN, SQRSHRUN2
1!= 000010010UQSHRN, UQSHRN2
1!= 000010011UQRSHRN, UQRSHRN2
1!= 000011100UCVTF (vector, fixed-point)
1!= 000011111FCVTZU (vector, fixed-point)

Advanced SIMD scalar x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
0000UNALLOCATED-
0010UNALLOCATED-
0100UNALLOCATED-
0110UNALLOCATED-
1000UNALLOCATED-
1010UNALLOCATED-
1110UNALLOCATED-
010001UNALLOCATED-
010101UNALLOCATED-
011001UNALLOCATED-
00011SQDMLAL, SQDMLAL2 (by element)-
00111SQDMLSL, SQDMLSL2 (by element)-
01011SQDMULL, SQDMULL2 (by element)-
01100SQDMULH (by element)-
01101SQRDMULH (by element)-
01111UNALLOCATED-
0000001FMLA (by element)half-precisionArmv8.2
0000101FMLS (by element)half-precisionArmv8.2
0001001FMUL (by element)half-precisionArmv8.2
01x0001FMLA (by element)single-precision and double-precision-
01x0101FMLS (by element)single-precision and double-precision-
01x1001FMUL (by element)single-precision and double-precision-
10011UNALLOCATED-
10111UNALLOCATED-
11011UNALLOCATED-
11100UNALLOCATED-
11101SQRDMLAH (by element)Armv8.1
11111SQRDMLSH (by element)Armv8.1
1000001UNALLOCATED-
1000101UNALLOCATED-
1001001FMULX (by element)half-precisionArmv8.2
11x0001UNALLOCATED-
11x0101UNALLOCATED-
11x1001FMULX (by element)single-precision and double-precision-

Advanced SIMD table lookup

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110op20Rm0lenop00RnRd
Decode fields Instruction Details
op2lenop
x1UNALLOCATED
00000TBLsingle register table
00001TBXsingle register table
00010TBLtwo register table
00011TBXtwo register table
00100TBLthree register table
00101TBXthree register table
00110TBLfour register table
00111TBXfour register table
1xUNALLOCATED

Advanced SIMD permute

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110size0Rm0opcode10RnRd
Decode fields Instruction Details
opcode
000UNALLOCATED
001UZP1
010TRN1
011ZIP1
100UNALLOCATED
101UZP2
110TRN2
111ZIP2

Advanced SIMD extract

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q101110op20Rm0imm40RnRd
Decode fields Instruction Details
op2
x1UNALLOCATED
00EXT
1xUNALLOCATED

Advanced SIMD copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop01110000imm50imm41RnRd
Decode fields Instruction Details
Qopimm5imm4
x0000UNALLOCATED
00000DUP (element)
00001DUP (general)
00010UNALLOCATED
00100UNALLOCATED
00110UNALLOCATED
01xxxUNALLOCATED
000011UNALLOCATED
000101SMOV
000111UMOV
01UNALLOCATED
100011INS (general)
100101SMOV
10x10000111UMOV
11INS (element)

Advanced SIMD three same (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00000FMAXNM (vector)Armv8.2
00001FMLA (vector)Armv8.2
00010FADD (vector)Armv8.2
00011FMULXArmv8.2
00100FCMEQ (register)Armv8.2
00101UNALLOCATED-
00110FMAX (vector)Armv8.2
00111FRECPSArmv8.2
01000FMINNM (vector)Armv8.2
01001FMLS (vector)Armv8.2
01010FSUB (vector)Armv8.2
01011UNALLOCATED-
01100UNALLOCATED-
01101UNALLOCATED-
01110FMIN (vector)Armv8.2
01111FRSQRTSArmv8.2
10000FMAXNMP (vector)Armv8.2
10001UNALLOCATED-
10010FADDP (vector)Armv8.2
10011FMUL (vector)Armv8.2
10100FCMGE (register)Armv8.2
10101FACGEArmv8.2
10110FMAXP (vector)Armv8.2
10111FDIV (vector)Armv8.2
11000FMINNMP (vector)Armv8.2
11001UNALLOCATED-
11010FABDArmv8.2
11011UNALLOCATED-
11100FCMGT (register)Armv8.2
11101FACGTArmv8.2
11110FMINP (vector)Armv8.2
11111UNALLOCATED-

Advanced SIMD two-register miscellaneous (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
10xxxUNALLOCATED-
11110UNALLOCATED-
0011xxUNALLOCATED-
011111UNALLOCATED-
111100UNALLOCATED-
0011000FRINTN (vector)Armv8.2
0011001FRINTM (vector)Armv8.2
0011010FCVTNS (vector)Armv8.2
0011011FCVTMS (vector)Armv8.2
0011100FCVTAS (vector)Armv8.2
0011101SCVTF (vector, integer)Armv8.2
0101100FCMGT (zero)Armv8.2
0101101FCMEQ (zero)Armv8.2
0101110FCMLT (zero)Armv8.2
0101111FABS (vector)Armv8.2
0111000FRINTP (vector)Armv8.2
0111001FRINTZ (vector)Armv8.2
0111010FCVTPS (vector)Armv8.2
0111011FCVTZS (vector, integer)Armv8.2
0111101FRECPEArmv8.2
0111111UNALLOCATED-
1011000FRINTA (vector)Armv8.2
1011001FRINTX (vector)Armv8.2
1011010FCVTNU (vector)Armv8.2
1011011FCVTMU (vector)Armv8.2
1011100FCVTAU (vector)Armv8.2
1011101UCVTF (vector, integer)Armv8.2
1101100FCMGE (zero)Armv8.2
1101101FCMLE (zero)Armv8.2
1101110UNALLOCATED-
1101111FNEG (vector)Armv8.2
1111000UNALLOCATED-
1111001FRINTI (vector)Armv8.2
1111010FCVTPU (vector)Armv8.2
1111011FCVTZU (vector, integer)Armv8.2
1111101FRSQRTEArmv8.2
1111111FSQRT (vector)Armv8.2

Advanced SIMD three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
0011UNALLOCATED-
01xxUNALLOCATED-
00000UNALLOCATED-
00001UNALLOCATED-
00010SDOT (vector)Armv8.2
01xxxUNALLOCATED-
10000SQRDMLAH (vector)Armv8.1
10001SQRDMLSH (vector)Armv8.1
10010UDOT (vector)Armv8.2
110xxFCMLAArmv8.3
111x0FCADDArmv8.3
1001101UNALLOCATED-
1001111UNALLOCATED-
11x1101UNALLOCATED-
1101111UNALLOCATED-

Advanced SIMD two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size10000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
1000xUNALLOCATED-
10101UNALLOCATED-
0x011xxUNALLOCATED-
1x10111UNALLOCATED-
1x11110UNALLOCATED-
1110110UNALLOCATED-
000000REV64-
000001REV16 (vector)-
000010SADDLP-
000011SUQADD-
000100CLS (vector)-
000101CNT-
000110SADALP-
000111SQABS-
001000CMGT (zero)-
001001CMEQ (zero)-
001010CMLT (zero)-
001011ABS-
010010XTN, XTN2-
010011UNALLOCATED-
010100SQXTN, SQXTN2-
00x10110FCVTN, FCVTN2-
00x10111FCVTL, FCVTL2-
00x11000FRINTN (vector)-
00x11001FRINTM (vector)-
00x11010FCVTNS (vector)-
00x11011FCVTMS (vector)-
00x11100FCVTAS (vector)-
00x11101SCVTF (vector, integer)-
00x11110FRINT32Z (vector)Armv8.5
00x11111FRINT64Z (vector)Armv8.5
01x01100FCMGT (zero)-
01x01101FCMEQ (zero)-
01x01110FCMLT (zero)-
01x01111FABS (vector)-
01x11000FRINTP (vector)-
01x11001FRINTZ (vector)-
01x11010FCVTPS (vector)-
01x11011FCVTZS (vector, integer)-
01x11100URECPE-
01x11101FRECPE-
01x11111UNALLOCATED-
100000REV32 (vector)-
100001UNALLOCATED-
100010UADDLP-
100011USQADD-
100100CLZ (vector)-
100110UADALP-
100111SQNEG-
101000CMGE (zero)-
101001CMLE (zero)-
101010UNALLOCATED-
101011NEG (vector)-
110010SQXTUN, SQXTUN2-
110011SHLL, SHLL2-
110100UQXTN, UQXTN2-
10x10110FCVTXN, FCVTXN2-
10x10111UNALLOCATED-
10x11000FRINTA (vector)-
10x11001FRINTX (vector)-
10x11010FCVTNU (vector)-
10x11011FCVTMU (vector)-
10x11100FCVTAU (vector)-
10x11101UCVTF (vector, integer)-
10x11110FRINT32X (vector)Armv8.5
10x11111FRINT64X (vector)Armv8.5
10000101NOT-
10100101RBIT (vector)-
11x00101UNALLOCATED-
11x01100FCMGE (zero)-
11x01101FCMLE (zero)-
11x01110UNALLOCATED-
11x01111FNEG (vector)-
11x11000UNALLOCATED-
11x11001FRINTI (vector)-
11x11010FCVTPU (vector)-
11x11011FCVTZU (vector, integer)-
11x11100URSQRTE-
11x11101FRSQRTE-
11x11111FSQRT (vector)-
11010110UNALLOCATED-

Advanced SIMD across lanes

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
0000xUNALLOCATED-
00010UNALLOCATED-
001xxUNALLOCATED-
0100xUNALLOCATED-
01011UNALLOCATED-
01101UNALLOCATED-
01110UNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
111xxUNALLOCATED-
000011SADDLV-
001010SMAXV-
011010SMINV-
011011ADDV-
00001100FMAXNMVhalf-precisionArmv8.2
00001111FMAXVhalf-precisionArmv8.2
00101100UNALLOCATED-
00101111UNALLOCATED-
01001100FMINNMVhalf-precisionArmv8.2
01001111FMINVhalf-precisionArmv8.2
01101100UNALLOCATED-
01101111UNALLOCATED-
100011UADDLV-
101010UMAXV-
111010UMINV-
111011UNALLOCATED-
10x01100FMAXNMVsingle-precision and double-precision-
10x01111FMAXVsingle-precision and double-precision-
11x01100FMINNMVsingle-precision and double-precision-
11x01111FMINVsingle-precision and double-precision-

Advanced SIMD three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode00RnRd
Decode fields Instruction Details
Uopcode
1111UNALLOCATED
00000SADDL, SADDL2
00001SADDW, SADDW2
00010SSUBL, SSUBL2
00011SSUBW, SSUBW2
00100ADDHN, ADDHN2
00101SABAL, SABAL2
00110SUBHN, SUBHN2
00111SABDL, SABDL2
01000SMLAL, SMLAL2 (vector)
01001SQDMLAL, SQDMLAL2 (vector)
01010SMLSL, SMLSL2 (vector)
01011SQDMLSL, SQDMLSL2 (vector)
01100SMULL, SMULL2 (vector)
01101SQDMULL, SQDMULL2 (vector)
01110PMULL, PMULL2
10000UADDL, UADDL2
10001UADDW, UADDW2
10010USUBL, USUBL2
10011USUBW, USUBW2
10100RADDHN, RADDHN2
10101UABAL, UABAL2
10110RSUBHN, RSUBHN2
10111UABDL, UABDL2
11000UMLAL, UMLAL2 (vector)
11001UNALLOCATED
11010UMLSL, UMLSL2 (vector)
11011UNALLOCATED
11100UMULL, UMULL2 (vector)
11101UNALLOCATED
11110UNALLOCATED

Advanced SIMD three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode1RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
000000SHADD-
000001SQADD-
000010SRHADD-
000100SHSUB-
000101SQSUB-
000110CMGT (register)-
000111CMGE (register)-
001000SSHL-
001001SQSHL (register)-
001010SRSHL-
001011SQRSHL-
001100SMAX-
001101SMIN-
001110SABD-
001111SABA-
010000ADD (vector)-
010001CMTST-
010010MLA (vector)-
010011MUL (vector)-
010100SMAXP-
010101SMINP-
010110SQDMULH (vector)-
010111ADDP (vector)-
00x11000FMAXNM (vector)-
00x11001FMLA (vector)-
00x11010FADD (vector)-
00x11011FMULX-
00x11100FCMEQ (register)-
00x11110FMAX (vector)-
00x11111FRECPS-
00000011AND (vector)-
00011101FMLAL, FMLAL2 (vector)FMLALArmv8.2
00100011BIC (vector, register)-
00111101UNALLOCATED-
01x11000FMINNM (vector)-
01x11001FMLS (vector)-
01x11010FSUB (vector)-
01x11011UNALLOCATED-
01x11100UNALLOCATED-
01x11110FMIN (vector)-
01x11111FRSQRTS-
01000011ORR (vector, register)-
01011101FMLSL, FMLSL2 (vector)FMLSLArmv8.2
01100011ORN (vector)-
01111101UNALLOCATED-
100000UHADD-
100001UQADD-
100010URHADD-
100100UHSUB-
100101UQSUB-
100110CMHI (register)-
100111CMHS (register)-
101000USHL-
101001UQSHL (register)-
101010URSHL-
101011UQRSHL-
101100UMAX-
101101UMIN-
101110UABD-
101111UABA-
110000SUB (vector)-
110001CMEQ (register)-
110010MLS (vector)-
110011PMUL-
110100UMAXP-
110101UMINP-
110110SQRDMULH (vector)-
110111UNALLOCATED-
10x11000FMAXNMP (vector)-
10x11010FADDP (vector)-
10x11011FMUL (vector)-
10x11100FCMGE (register)-
10x11101FACGE-
10x11110FMAXP (vector)-
10x11111FDIV (vector)-
10000011EOR (vector)-
10011001FMLAL, FMLAL2 (vector)FMLAL2Armv8.2
10100011BSL-
10111001UNALLOCATED-
11x11000FMINNMP (vector)-
11x11010FABD-
11x11011UNALLOCATED-
11x11100FCMGT (register)-
11x11101FACGT-
11x11110FMINP (vector)-
11x11111UNALLOCATED-
11000011BIT-
11011001FMLSL, FMLSL2 (vector)FMLSL2Armv8.2
11100011BIF-
11111001UNALLOCATED-

Advanced SIMD modified immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmodeo21defghRd
Decode fields Instruction Details Architecture Version
Qopcmodeo2
00xxx1UNALLOCATED-
00xx00MOVI32-bit shifted immediate-
00xx10ORR (vector, immediate)32-bit-
010xx1UNALLOCATED-
010x00MOVI16-bit shifted immediate-
010x10ORR (vector, immediate)16-bit-
0110x0MOVI32-bit shifting ones-
0110x1UNALLOCATED-
011100MOVI8-bit-
011101UNALLOCATED-
011110FMOV (vector, immediate)single-precision-
011111FMOV (vector, immediate)half-precisionArmv8.2
11UNALLOCATED-
10xx00MVNI32-bit shifted immediate-
10xx10BIC (vector, immediate)32-bit-
110x00MVNI16-bit shifted immediate-
110x10BIC (vector, immediate)16-bit-
1110x0MVNI32-bit shifting ones-
0111100MOVI64-bit scalar-
0111110UNALLOCATED-
1111100MOVI64-bit vector-
1111110FMOV (vector, immediate)double-precision-

Advanced SIMD shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU011110!= 0000immbopcode1RnRd
immh

The following constraints also apply to this encoding: immh != 0000 && immh != 0000

Decode fields Instruction Details
Uopcode
00001UNALLOCATED
00011UNALLOCATED
00101UNALLOCATED
00111UNALLOCATED
01001UNALLOCATED
01011UNALLOCATED
01101UNALLOCATED
01111UNALLOCATED
10101UNALLOCATED
1011xUNALLOCATED
110xxUNALLOCATED
11101UNALLOCATED
11110UNALLOCATED
000000SSHR
000010SSRA
000100SRSHR
000110SRSRA
001000UNALLOCATED
001010SHL
001100UNALLOCATED
001110SQSHL (immediate)
010000SHRN, SHRN2
010001RSHRN, RSHRN2
010010SQSHRN, SQSHRN2
010011SQRSHRN, SQRSHRN2
010100SSHLL, SSHLL2
011100SCVTF (vector, fixed-point)
011111FCVTZS (vector, fixed-point)
100000USHR
100010USRA
100100URSHR
100110URSRA
101000SRI
101010SLI
101100SQSHLU
101110UQSHL (immediate)
110000SQSHRUN, SQSHRUN2
110001SQRSHRUN, SQRSHRUN2
110010UQSHRN, UQSHRN2
110011UQRSHRN, UQRSHRN2
110100USHLL, USHLL2
111100UCVTF (vector, fixed-point)
111111FCVTZU (vector, fixed-point)

Advanced SIMD vector x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
011001UNALLOCATED-
00010SMLAL, SMLAL2 (by element)-
00011SQDMLAL, SQDMLAL2 (by element)-
00110SMLSL, SMLSL2 (by element)-
00111SQDMLSL, SQDMLSL2 (by element)-
01000MUL (by element)-
01010SMULL, SMULL2 (by element)-
01011SQDMULL, SQDMULL2 (by element)-
01100SQDMULH (by element)-
01101SQRDMULH (by element)-
01110SDOT (by element)Armv8.2
00x0000UNALLOCATED-
00x0100UNALLOCATED-
0000001FMLA (by element)half-precisionArmv8.2
0000101FMLS (by element)half-precisionArmv8.2
0001001FMUL (by element)half-precisionArmv8.2
0001111UNALLOCATED-
0010001UNALLOCATED-
0010101UNALLOCATED-
01x0001FMLA (by element)single-precision and double-precision-
01x0101FMLS (by element)single-precision and double-precision-
01x1001FMUL (by element)single-precision and double-precision-
0100000FMLAL, FMLAL2 (by element)FMLALArmv8.2
0100100FMLSL, FMLSL2 (by element)FMLSLArmv8.2
0101111UNALLOCATED-
0110000UNALLOCATED-
0110100UNALLOCATED-
10000MLA (by element)-
10010UMLAL, UMLAL2 (by element)-
10100MLS (by element)-
10110UMLSL, UMLSL2 (by element)-
11010UMULL, UMULL2 (by element)-
11011UNALLOCATED-
11101SQRDMLAH (by element)Armv8.1
11110UDOT (by element)Armv8.2
11111SQRDMLSH (by element)Armv8.1
10x1000UNALLOCATED-
10x1100UNALLOCATED-
1000001UNALLOCATED-
1000011UNALLOCATED-
1000101UNALLOCATED-
1000111UNALLOCATED-
1001001FMULX (by element)half-precisionArmv8.2
1010xx1FCMLA (by element)Armv8.3
11x1001FMULX (by element)single-precision and double-precision-
1100xx1FCMLA (by element)Armv8.3
1101000FMLAL, FMLAL2 (by element)FMLAL2Armv8.2
1101100FMLSL, FMLSL2 (by element)FMLSL2Armv8.2
1110001UNALLOCATED-
1110011UNALLOCATED-
1110101UNALLOCATED-
1110111UNALLOCATED-
1111000UNALLOCATED-
1111100UNALLOCATED-

Cryptographic three-register, imm2

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110010Rm10imm2opcodeRnRd
Decode fields Instruction Details Architecture Version
opcode
00SM3TT1AArmv8.2
01SM3TT1BArmv8.2
10SM3TT2AArmv8.2
11SM3TT2BArmv8.2

Cryptographic three-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110011Rm1O00opcodeRnRd
Decode fields Instruction Details Architecture Version
Oopcode
000SHA512HArmv8.2
001SHA512H2Armv8.2
010SHA512SU1Armv8.2
011RAX1Armv8.2
100SM3PARTW1Armv8.2
101SM3PARTW2Armv8.2
110SM4EKEYArmv8.2
111UNALLOCATED-

Cryptographic four-register

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
110011100Op0Rm0RaRnRd
Decode fields Instruction Details Architecture Version
Op0
00EOR3Armv8.2
01BCAXArmv8.2
10SM3SS1Armv8.2
11UNALLOCATED-

Cryptographic two-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110110000001000opcodeRnRd
Decode fields Instruction Details Architecture Version
opcode
00SHA512SU0Armv8.2
01SM4EArmv8.2
1xUNALLOCATED-

Conversion between floating-point and fixed-point

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ptype0rmodeopcodescaleRnRd
Decode fields Instruction Details Architecture Version
sfSptypermodeopcodescale
1xxUNALLOCATED-
x000xUNALLOCATED-
x101xUNALLOCATED-
0x00xUNALLOCATED-
1x01xUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00xxxxxUNALLOCATED-
000000010SCVTF (scalar, fixed-point)32-bit to single-precision-
000000011UCVTF (scalar, fixed-point)32-bit to single-precision-
000011000FCVTZS (scalar, fixed-point)single-precision to 32-bit-
000011001FCVTZU (scalar, fixed-point)single-precision to 32-bit-
000100010SCVTF (scalar, fixed-point)32-bit to double-precision-
000100011UCVTF (scalar, fixed-point)32-bit to double-precision-
000111000FCVTZS (scalar, fixed-point)double-precision to 32-bit-
000111001FCVTZU (scalar, fixed-point)double-precision to 32-bit-
001100010SCVTF (scalar, fixed-point)32-bit to half-precisionArmv8.2
001100011UCVTF (scalar, fixed-point)32-bit to half-precisionArmv8.2
001111000FCVTZS (scalar, fixed-point)half-precision to 32-bitArmv8.2
001111001FCVTZU (scalar, fixed-point)half-precision to 32-bitArmv8.2
100000010SCVTF (scalar, fixed-point)64-bit to single-precision-
100000011UCVTF (scalar, fixed-point)64-bit to single-precision-
100011000FCVTZS (scalar, fixed-point)single-precision to 64-bit-
100011001FCVTZU (scalar, fixed-point)single-precision to 64-bit-
100100010SCVTF (scalar, fixed-point)64-bit to double-precision-
100100011UCVTF (scalar, fixed-point)64-bit to double-precision-
100111000FCVTZS (scalar, fixed-point)double-precision to 64-bit-
100111001FCVTZU (scalar, fixed-point)double-precision to 64-bit-
101100010SCVTF (scalar, fixed-point)64-bit to half-precisionArmv8.2
101100011UCVTF (scalar, fixed-point)64-bit to half-precisionArmv8.2
101111000FCVTZS (scalar, fixed-point)half-precision to 64-bitArmv8.2
101111001FCVTZU (scalar, fixed-point)half-precision to 64-bitArmv8.2

Conversion between floating-point and integer

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ptype1rmodeopcode000000RnRd
Decode fields Instruction Details Architecture Version
sfSptypermodeopcode
x101xUNALLOCATED-
x110xUNALLOCATED-
1x01xUNALLOCATED-
1x10xUNALLOCATED-
0100xxUNALLOCATED-
01010xUNALLOCATED-
1UNALLOCATED-
0000x111xUNALLOCATED-
000000000FCVTNS (scalar)single-precision to 32-bit-
000000001FCVTNU (scalar)single-precision to 32-bit-
000000010SCVTF (scalar, integer)32-bit to single-precision-
000000011UCVTF (scalar, integer)32-bit to single-precision-
000000100FCVTAS (scalar)single-precision to 32-bit-
000000101FCVTAU (scalar)single-precision to 32-bit-
000000110FMOV (general)single-precision to 32-bit-
000000111FMOV (general)32-bit to single-precision-
000001000FCVTPS (scalar)single-precision to 32-bit-
000001001FCVTPU (scalar)single-precision to 32-bit-
00001x11xUNALLOCATED-
000010000FCVTMS (scalar)single-precision to 32-bit-
000010001FCVTMU (scalar)single-precision to 32-bit-
000011000FCVTZS (scalar, integer)single-precision to 32-bit-
000011001FCVTZU (scalar, integer)single-precision to 32-bit-
00010x11xUNALLOCATED-
000100000FCVTNS (scalar)double-precision to 32-bit-
000100001FCVTNU (scalar)double-precision to 32-bit-
000100010SCVTF (scalar, integer)32-bit to double-precision-
000100011UCVTF (scalar, integer)32-bit to double-precision-
000100100FCVTAS (scalar)double-precision to 32-bit-
000100101FCVTAU (scalar)double-precision to 32-bit-
000101000FCVTPS (scalar)double-precision to 32-bit-
000101001FCVTPU (scalar)double-precision to 32-bit-
000110000FCVTMS (scalar)double-precision to 32-bit-
000110001FCVTMU (scalar)double-precision to 32-bit-
00011011xUNALLOCATED-
000111000FCVTZS (scalar, integer)double-precision to 32-bit-
000111001FCVTZU (scalar, integer)double-precision to 32-bit-
000111110FJCVTZSArmv8.3
000111111UNALLOCATED-
001011xUNALLOCATED-
001100000FCVTNS (scalar)half-precision to 32-bitArmv8.2
001100001FCVTNU (scalar)half-precision to 32-bitArmv8.2
001100010SCVTF (scalar, integer)32-bit to half-precisionArmv8.2
001100011UCVTF (scalar, integer)32-bit to half-precisionArmv8.2
001100100FCVTAS (scalar)half-precision to 32-bitArmv8.2
001100101FCVTAU (scalar)half-precision to 32-bitArmv8.2
001100110FMOV (general)half-precision to 32-bitArmv8.2
001100111FMOV (general)32-bit to half-precisionArmv8.2
001101000FCVTPS (scalar)half-precision to 32-bitArmv8.2
001101001FCVTPU (scalar)half-precision to 32-bitArmv8.2
001110000FCVTMS (scalar)half-precision to 32-bitArmv8.2
001110001FCVTMU (scalar)half-precision to 32-bitArmv8.2
001111000FCVTZS (scalar, integer)half-precision to 32-bitArmv8.2
001111001FCVTZU (scalar, integer)half-precision to 32-bitArmv8.2
100011xUNALLOCATED-
100000000FCVTNS (scalar)single-precision to 64-bit-
100000001FCVTNU (scalar)single-precision to 64-bit-
100000010SCVTF (scalar, integer)64-bit to single-precision-
100000011UCVTF (scalar, integer)64-bit to single-precision-
100000100FCVTAS (scalar)single-precision to 64-bit-
100000101FCVTAU (scalar)single-precision to 64-bit-
100001000FCVTPS (scalar)single-precision to 64-bit-
100001001FCVTPU (scalar)single-precision to 64-bit-
100010000FCVTMS (scalar)single-precision to 64-bit-
100010001FCVTMU (scalar)single-precision to 64-bit-
100011000FCVTZS (scalar, integer)single-precision to 64-bit-
100011001FCVTZU (scalar, integer)single-precision to 64-bit-
1001x111xUNALLOCATED-
100100000FCVTNS (scalar)double-precision to 64-bit-
100100001FCVTNU (scalar)double-precision to 64-bit-
100100010SCVTF (scalar, integer)64-bit to double-precision-
100100011UCVTF (scalar, integer)64-bit to double-precision-
100100100FCVTAS (scalar)double-precision to 64-bit-
100100101FCVTAU (scalar)double-precision to 64-bit-
100100110FMOV (general)double-precision to 64-bit-
100100111FMOV (general)64-bit to double-precision-
100101000FCVTPS (scalar)double-precision to 64-bit-
100101001FCVTPU (scalar)double-precision to 64-bit-
10011x11xUNALLOCATED-
100110000FCVTMS (scalar)double-precision to 64-bit-
100110001FCVTMU (scalar)double-precision to 64-bit-
100111000FCVTZS (scalar, integer)double-precision to 64-bit-
100111001FCVTZU (scalar, integer)double-precision to 64-bit-
1010x011xUNALLOCATED-
101001110FMOV (general)top half of 128-bit to 64-bit-
101001111FMOV (general)64-bit to top half of 128-bit-
10101x11xUNALLOCATED-
101100000FCVTNS (scalar)half-precision to 64-bitArmv8.2
101100001FCVTNU (scalar)half-precision to 64-bitArmv8.2
101100010SCVTF (scalar, integer)64-bit to half-precisionArmv8.2
101100011UCVTF (scalar, integer)64-bit to half-precisionArmv8.2
101100100FCVTAS (scalar)half-precision to 64-bitArmv8.2
101100101FCVTAU (scalar)half-precision to 64-bitArmv8.2
101100110FMOV (general)half-precision to 64-bitArmv8.2
101100111FMOV (general)64-bit to half-precisionArmv8.2
101101000FCVTPS (scalar)half-precision to 64-bitArmv8.2
101101001FCVTPU (scalar)half-precision to 64-bitArmv8.2
101110000FCVTMS (scalar)half-precision to 64-bitArmv8.2
101110001FCVTMU (scalar)half-precision to 64-bitArmv8.2
101111000FCVTZS (scalar, integer)half-precision to 64-bitArmv8.2
101111001FCVTZU (scalar, integer)half-precision to 64-bitArmv8.2

Floating-point data-processing (1 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1opcode10000RnRd
Decode fields Instruction Details Architecture Version
MSptypeopcode
1xxxxxUNALLOCATED-
1UNALLOCATED-
0000000000FMOV (register)single-precision-
0000000001FABS (scalar)single-precision-
0000000010FNEG (scalar)single-precision-
0000000011FSQRT (scalar)single-precision-
0000000100UNALLOCATED-
0000000101FCVTsingle-precision to double-precision-
0000000110UNALLOCATED-
0000000111FCVTsingle-precision to half-precision-
0000001000FRINTN (scalar)single-precision-
0000001001FRINTP (scalar)single-precision-
0000001010FRINTM (scalar)single-precision-
0000001011FRINTZ (scalar)single-precision-
0000001100FRINTA (scalar)single-precision-
0000001101UNALLOCATED-
0000001110FRINTX (scalar)single-precision-
0000001111FRINTI (scalar)single-precision-
0000010000FRINT32Z (scalar)single-precisionArmv8.5
0000010001FRINT32X (scalar)single-precisionArmv8.5
0000010010FRINT64Z (scalar)single-precisionArmv8.5
0000010011FRINT64X (scalar)single-precisionArmv8.5
00000101xxUNALLOCATED-
0000011xxxUNALLOCATED-
0001000000FMOV (register)double-precision-
0001000001FABS (scalar)double-precision-
0001000010FNEG (scalar)double-precision-
0001000011FSQRT (scalar)double-precision-
0001000100FCVTdouble-precision to single-precision-
0001000101UNALLOCATED-
0001000111FCVTdouble-precision to half-precision-
0001001000FRINTN (scalar)double-precision-
0001001001FRINTP (scalar)double-precision-
0001001010FRINTM (scalar)double-precision-
0001001011FRINTZ (scalar)double-precision-
0001001100FRINTA (scalar)double-precision-
0001001101UNALLOCATED-
0001001110FRINTX (scalar)double-precision-
0001001111FRINTI (scalar)double-precision-
0001010000FRINT32Z (scalar)double-precisionArmv8.5
0001010001FRINT32X (scalar)double-precisionArmv8.5
0001010010FRINT64Z (scalar)double-precisionArmv8.5
0001010011FRINT64X (scalar)double-precisionArmv8.5
00010101xxUNALLOCATED-
0001011xxxUNALLOCATED-
00100xxxxxUNALLOCATED-
0011000000FMOV (register)half-precisionArmv8.2
0011000001FABS (scalar)half-precisionArmv8.2
0011000010FNEG (scalar)half-precisionArmv8.2
0011000011FSQRT (scalar)half-precisionArmv8.2
0011000100FCVThalf-precision to single-precision-
0011000101FCVThalf-precision to double-precision-
001100011xUNALLOCATED-
0011001000FRINTN (scalar)half-precisionArmv8.2
0011001001FRINTP (scalar)half-precisionArmv8.2
0011001010FRINTM (scalar)half-precisionArmv8.2
0011001011FRINTZ (scalar)half-precisionArmv8.2
0011001100FRINTA (scalar)half-precisionArmv8.2
0011001101UNALLOCATED-
0011001110FRINTX (scalar)half-precisionArmv8.2
0011001111FRINTI (scalar)half-precisionArmv8.2
001101xxxxUNALLOCATED-
1UNALLOCATED-

Floating-point compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1Rmop1000Rnopcode2
Decode fields Instruction Details Architecture Version
MSptypeopopcode2
xxxx1UNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1UNALLOCATED-
1xUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00000000000FCMP-
00000001000FCMP-
00000010000FCMPE-
00000011000FCMPE-
00010000000FCMP-
00010001000FCMP-
00010010000FCMPE-
00010011000FCMPE-
00110000000FCMPArmv8.2
00110001000FCMPArmv8.2
00110010000FCMPEArmv8.2
00110011000FCMPEArmv8.2
1UNALLOCATED-

Floating-point immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1imm8100imm5Rd
Decode fields Instruction Details Architecture Version
MSptypeimm5
xxxx1UNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1xxxUNALLOCATED-
1xxxxUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
000000000FMOV (scalar, immediate)single-precision-
000100000FMOV (scalar, immediate)double-precision-
001100000FMOV (scalar, immediate)half-precisionArmv8.2
1UNALLOCATED-

Floating-point conditional compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1Rmcond01Rnopnzcv
Decode fields Instruction Details Architecture Version
MSptypeop
10UNALLOCATED-
1UNALLOCATED-
00000FCCMPsingle-precision-
00001FCCMPEsingle-precision-
00010FCCMPdouble-precision-
00011FCCMPEdouble-precision-
00110FCCMPhalf-precisionArmv8.2
00111FCCMPEhalf-precisionArmv8.2
1UNALLOCATED-

Floating-point data-processing (2 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1Rmopcode10RnRd
Decode fields Instruction Details Architecture Version
MSptypeopcode
1xx1UNALLOCATED-
1x1xUNALLOCATED-
11xxUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00000000FMUL (scalar)single-precision-
00000001FDIV (scalar)single-precision-
00000010FADD (scalar)single-precision-
00000011FSUB (scalar)single-precision-
00000100FMAX (scalar)single-precision-
00000101FMIN (scalar)single-precision-
00000110FMAXNM (scalar)single-precision-
00000111FMINNM (scalar)single-precision-
00001000FNMUL (scalar)single-precision-
00010000FMUL (scalar)double-precision-
00010001FDIV (scalar)double-precision-
00010010FADD (scalar)double-precision-
00010011FSUB (scalar)double-precision-
00010100FMAX (scalar)double-precision-
00010101FMIN (scalar)double-precision-
00010110FMAXNM (scalar)double-precision-
00010111FMINNM (scalar)double-precision-
00011000FNMUL (scalar)double-precision-
00110000FMUL (scalar)half-precisionArmv8.2
00110001FDIV (scalar)half-precisionArmv8.2
00110010FADD (scalar)half-precisionArmv8.2
00110011FSUB (scalar)half-precisionArmv8.2
00110100FMAX (scalar)half-precisionArmv8.2
00110101FMIN (scalar)half-precisionArmv8.2
00110110FMAXNM (scalar)half-precisionArmv8.2
00110111FMINNM (scalar)half-precisionArmv8.2
00111000FNMUL (scalar)half-precisionArmv8.2
1UNALLOCATED-

Floating-point conditional select

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ptype1Rmcond11RnRd
Decode fields Instruction Details Architecture Version
MSptype
10UNALLOCATED-
1UNALLOCATED-
0000FCSELsingle-precision-
0001FCSELdouble-precision-
0011FCSELhalf-precisionArmv8.2
1UNALLOCATED-

Floating-point data-processing (3 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11111ptypeo1Rmo0RaRnRd
Decode fields Instruction Details Architecture Version
MSptypeo1o0
10UNALLOCATED-
1UNALLOCATED-
000000FMADDsingle-precision-
000001FMSUBsingle-precision-
000010FNMADDsingle-precision-
000011FNMSUBsingle-precision-
000100FMADDdouble-precision-
000101FMSUBdouble-precision-
000110FNMADDdouble-precision-
000111FNMSUBdouble-precision-
001100FMADDhalf-precisionArmv8.2
001101FMSUBhalf-precisionArmv8.2
001110FNMADDhalf-precisionArmv8.2
001111FNMSUBhalf-precisionArmv8.2
1UNALLOCATED-

Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:3004

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