SSRA

Signed shift right and accumulate (immediate).

Shift right by immediate each signed element of the source vector, preserving the sign bit, and add the truncated intermediate result destructively to the corresponding elements of the addend vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm3111000ZnZda

SVE2

SSRA <Zda>.<T>, <Zn>.<T>, #<const>

if !HaveSVE2() then UNDEFINED; bits(4) tsize = tszh:tszl; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer n = UInt(Zn); integer da = UInt(Zda); integer shift = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
00 00 RESERVED
00 01 B
00 1x H
01 xx S
1x xx D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3".

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[da]; bits(VL) result; for e = 0 to elements-1 integer element = SInt(Elem[operand1, e, esize]) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; Z[da] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction that conforms to all of the following requirements, otherwise the behavior of either or both instructions is unpredictable:

The MOVPRFX instructions that can be used with this instruction are as follows:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

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