SVE floating-point arithmetic with immediate (predicated)<const>
Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#2.0.
Where:
<const> |
Is the floating-point immediate value,
encoded in
i1 :
|
SVE floating-point arithmetic with immediate (predicated)<const>
Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#1.0.
Where:
<const> |
Is the floating-point immediate value,
encoded in
i1 :
|
SVE floating-point arithmetic with immediate (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point arithmetic with immediate (predicated)<const>
Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.0 and 1->#1.0.
Where:
<const> |
Is the floating-point immediate value,
encoded in
i1 :
|
SVE floating-point compare with zero<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point serial reduction (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point serial reduction (predicated)<V>
Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
size | <V> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point round to integral value<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point unary operations<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point convert to integer<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point arithmetic (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point reciprocal estimate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point compare vectors<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point multiply-accumulate writing addend<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point multiply-accumulate writing multiplicand<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point arithmetic (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point recursive reduction<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point recursive reduction<V>
Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
size | <V> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point complex add (predicated)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 0->#90 and 1->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
|
SVE floating-point complex add (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point complex multiply-add (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point complex multiply-add (predicated)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE floating-point complex multiply-add (indexed)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE floating-point trig multiply-add coefficient<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 floating-point pairwise operations<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE integer add/subtract immediate (unpredicated)<shift>
Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.
Where:
<shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
sh :
|
SVE integer add/subtract immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer min/max immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer multiply immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer add/subtract vectors (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE address generation<amount>
Original text: Is the index shift amount, encoded in "msz", where 00->[absent], 01->#1, 10->#2 and 11->#3.
Where:
<amount> |
Is the index shift amount,
encoded in
msz :
msz | <amount> |
---|
00 | [absent] | 01 | #1 | 10 | #2 | 11 | #3 |
|
SVE address generation<mod>
Original text: Is the index extend and shift specifier, encoded in "msz", where 00->[absent], 10->LSL and x1->LSL.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
msz :
msz | <mod> |
---|
00 | [absent] | x1 | LSL | 10 | LSL |
|
SVE address generation<T>
Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
sz :
|
SVE floating-point trig select coefficient<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE floating-point exponential accelerator<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE bitwise shift by wide elements (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | B | 01 | H | 10 | S | 11 | RESERVED |
|
SVE bitwise shift by immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
00 | 00 | RESERVED | 00 | 01 | B | 00 | 1x | H | 01 | xx | S | 1x | xx | D |
|
SVE integer add/subtract vectors (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer min/max/difference (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer multiply vectors (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer divide vectors (predicated)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE bitwise logical operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE bitwise shift by immediate (predicated)<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
00 | 00 | RESERVED | 00 | 01 | B | 00 | 1x | H | 01 | xx | S | 1x | xx | D |
|
SVE bitwise shift by vector (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE bitwise shift by wide elements (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | B | 01 | H | 10 | S | 11 | RESERVED |
|
SVE partition break condition<ZM>
Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.
Where:
<ZM> |
Is the predication qualifier,
encoded in
M :
|
SVE integer compare vectors<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer compare vectors<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | B | 01 | H | 10 | S | 11 | RESERVED |
|
SVE integer compare with wide elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | B | 01 | H | 10 | S | 11 | RESERVED |
|
SVE element count<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE inc/dec register by predicate count<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE saturating inc/dec register by predicate count<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE inc/dec vector by predicate count<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE saturating inc/dec vector by predicate count<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE saturating inc/dec vector by element count<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE inc/dec vector by element count<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE conditionally terminate scalars<R>
Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.
Where:
<R> |
Is a width specifier,
encoded in
sz :
|
SVE broadcast floating-point immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE copy floating-point immediate (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE broadcast integer immediate (unpredicated)<shift>
Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.
Where:
<shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
sh :
|
SVE broadcast integer immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE broadcast integer immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE copy integer immediate (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE copy integer immediate (predicated)<shift>
Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.
Where:
<shift> |
Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
encoded in
sh :
|
SVE copy integer immediate (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE broadcast bitmask immediate<T>
Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.
Where:
<T> |
Is the size specifier,
encoded in
imm13<12>:imm13<5:0> :
imm13<12> | imm13<5:0> | <T> |
---|
0 | 0xxxxx | S | 0 | 10xxxx | H | 0 | 110xxx | B | 0 | 1110xx | B | 0 | 11110x | B | 0 | 111110 | RESERVED | 0 | 111111 | RESERVED | 1 | xxxxxx | D |
|
SVE index generation (immediate start, immediate increment)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE index generation (immediate start, register increment)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE index generation (immediate start, register increment)<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE index generation (register start, immediate increment)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE index generation (register start, immediate increment)<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE index generation (register start, register increment)<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE index generation (register start, register increment)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE bitwise logical with immediate (unpredicated)<T>
Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.
Where:
<T> |
Is the size specifier,
encoded in
imm13<12>:imm13<5:0> :
imm13<12> | imm13<5:0> | <T> |
---|
0 | 0xxxxx | S | 0 | 10xxxx | H | 0 | 110xxx | B | 0 | 1110xx | B | 0 | 11110x | B | 0 | 111110 | RESERVED | 0 | 111111 | RESERVED | 1 | xxxxxx | D |
|
SVE integer multiply-add writing multiplicand (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer multiply-accumulate writing addend (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE constructive prefix (predicated)<ZM>
Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.
Where:
<ZM> |
Is the predication qualifier,
encoded in
M :
|
SVE constructive prefix (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer multiply vectors (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE predicate count<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE permute predicate elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE permute vector elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE conditionally extract element to general register<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE conditionally extract element to general register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE conditionally extract element to SIMD&FP scalar<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE conditionally extract element to SIMD&FP scalar<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE conditionally broadcast element to vector<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE compress active elements<T>
Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
sz :
|
SVE copy general register to vector (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE copy general register to vector (predicated)<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE copy SIMD&FP scalar register to vector (predicated)<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE copy SIMD&FP scalar register to vector (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE broadcast indexed element<V>
Original text: Is a width specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.
Where:
<V> |
Is a width specifier,
encoded in
tsz :
tsz | <V> |
---|
00000 | RESERVED | xxxx1 | B | xxx10 | H | xx100 | S | x1000 | D | 10000 | Q |
|
SVE broadcast indexed element<T>
Original text: Is the size specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.
Where:
<T> |
Is the size specifier,
encoded in
tsz :
tsz | <T> |
---|
00000 | RESERVED | xxxx1 | B | xxx10 | H | xx100 | S | x1000 | D | 10000 | Q |
|
SVE broadcast general register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE broadcast general register<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE insert general register<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE insert general register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE insert SIMD&FP scalar register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE insert SIMD&FP scalar register<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE extract element to general register<R>
Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.
Where:
<R> |
Is a width specifier,
encoded in
size :
|
SVE extract element to general register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE extract element to SIMD&FP scalar register<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE extract element to SIMD&FP scalar register<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE reverse within elements<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE reverse within elements<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE reverse within elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE reverse predicate elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE reverse vector elements<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE vector splice (destructive)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE table lookup<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE table lookup (three sources)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE unpack vector elements<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE unpack vector elements<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE predicate next active<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE inc/dec register by element count<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE saturating inc/dec register by element count<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE predicate initialize<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE predicate initialize<pattern>
Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.
Where:
<pattern> |
Is the optional pattern specifier, defaulting to ALL,
encoded in
pattern :
pattern | <pattern> |
---|
00000 | POW2 | 00001 | VL1 | 00010 | VL2 | 00011 | VL3 | 00100 | VL4 | 00101 | VL5 | 00110 | VL6 | 00111 | VL7 | 01000 | VL8 | 01001 | VL16 | 01010 | VL32 | 01011 | VL64 | 01100 | VL128 | 01101 | VL256 | 0111x | #uimm5 | 101x1 | #uimm5 | 10110 | #uimm5 | 1x0x1 | #uimm5 | 1x010 | #uimm5 | 1xx00 | #uimm5 | 11101 | MUL4 | 11110 | MUL3 | 11111 | ALL |
|
SVE integer add reduction (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | B | 01 | H | 10 | S | 11 | RESERVED |
|
SVE integer add reduction (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer min/max reduction (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer min/max reduction (predicated)<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE bitwise logical reduction (predicated)<V>
Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<V> |
Is a width specifier,
encoded in
size :
|
SVE bitwise logical reduction (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
sve_int_rotate_imm<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
00 | 00 | RESERVED | 00 | 01 | B | 00 | 1x | H | 01 | xx | S | 1x | xx | D |
|
SVE integer compare with signed immediate<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE select vector elements (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 signed saturating doubling multiply high (unpredicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer compare with unsigned immediate<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE integer unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE integer unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE integer unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE bitwise unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE bitwise unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE integer compare scalar count and limit<R>
Original text: Is a width specifier, encoded in "sf", where 0->W and 1->X.
Where:
<R> |
Is a width specifier,
encoded in
sf :
|
SVE integer compare scalar count and limit<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE pointer conflict compare<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer absolute difference and accumulate<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer absolute difference and accumulate long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer absolute difference and accumulate long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 integer pairwise add and accumulate long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 integer pairwise add and accumulate long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer add/subtract long with carry<T>
Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
sz :
|
SVE2 integer pairwise arithmetic<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer add/subtract narrow high part<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 integer add/subtract narrow high part<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 saturating/rounding bitwise shift left (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 complex integer add<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 complex integer add<const>
Original text: Is the const specifier, encoded in the "rot" field, where 0->#90 and 1->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
|
SVE2 complex integer dot product<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE2 complex integer dot product<Tb>
Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.
Where:
<Tb> |
Is the size specifier,
encoded in
size<0> :
|
SVE2 complex integer dot product<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE2 complex integer dot product (indexed)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE2 integer add/subtract interleaved long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer add/subtract interleaved long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 complex integer multiply-add<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE2 complex integer multiply-add<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 complex integer multiply-add (indexed)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE2 integer add/subtract long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer add/subtract long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 integer add/subtract wide<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 integer add/subtract wide<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer multiply long<T>
Original text: Is the size specifier, encoded in "size", where 00->Q, 01->H, 10->RESERVED and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | Q | 01 | H | 10 | RESERVED | 11 | D |
|
SVE2 integer multiply long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->D, 01->B, 10->RESERVED and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | D | 01 | B | 10 | RESERVED | 11 | S |
|
SVE2 integer multiply long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer multiply long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE integer dot product (unpredicated)<Tb>
Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.
Where:
<Tb> |
Is the size specifier,
encoded in
size<0> :
|
SVE integer dot product (unpredicated)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE2 bitwise exclusive-or interleaved<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 saturating extract narrow<Tb>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->H, 010->S, 100->D, 101->RESERVED, 110->RESERVED and x11->RESERVED.
Where:
<Tb> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <Tb> |
---|
0 | 00 | RESERVED | 0 | 01 | H | 0 | 10 | S | x | 11 | RESERVED | 1 | 00 | D | 1 | 01 | RESERVED | 1 | 10 | RESERVED |
|
SVE2 saturating extract narrow<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->B, 010->H, 100->S, 101->RESERVED, 110->RESERVED and x11->RESERVED.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
0 | 00 | RESERVED | 0 | 01 | B | 0 | 10 | H | x | 11 | RESERVED | 1 | 00 | S | 1 | 01 | RESERVED | 1 | 10 | RESERVED |
|
SVE2 histogram generation (vector)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE2 character match<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE2 integer multiply-add long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 integer multiply-add long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 bitwise permute<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 vector splice (constructive)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer halving add/subtract (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 saturating add/subtract<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 integer unary operations (predicated)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 saturating multiply-add long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 saturating multiply-add long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 saturating multiply-add interleaved long<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE2 saturating multiply-add interleaved long<Tb>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.
Where:
<Tb> |
Is the size specifier,
encoded in
size :
size | <Tb> |
---|
00 | RESERVED | 01 | B | 10 | H | 11 | S |
|
SVE2 complex saturating multiply-add (indexed)<const>
Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.
Where:
<const> |
Is the const specifier,
encoded in
rot :
rot | <const> |
---|
00 | #0 | 01 | #90 | 10 | #180 | 11 | #270 |
|
SVE2 saturating multiply-add high<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE2 bitwise shift and insert<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
00 | 00 | RESERVED | 00 | 01 | B | 00 | 1x | H | 01 | xx | S | 1x | xx | D |
|
SVE2 bitwise shift left long<Tb>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->B, 01x->H and 1xx->S.
Where:
<Tb> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <Tb> |
---|
0 | 00 | RESERVED | 0 | 01 | B | 0 | 1x | H | 1 | xx | S |
|
SVE2 bitwise shift left long<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->H, 01x->S and 1xx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
0 | 00 | RESERVED | 0 | 01 | H | 0 | 1x | S | 1 | xx | D |
|
SVE2 bitwise shift right narrow<Tb>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->H, 01x->S and 1xx->D.
Where:
<Tb> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <Tb> |
---|
0 | 00 | RESERVED | 0 | 01 | H | 0 | 1x | S | 1 | xx | D |
|
SVE2 bitwise shift right narrow<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 000->RESERVED, 001->B, 01x->H and 1xx->S.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
0 | 00 | RESERVED | 0 | 01 | B | 0 | 1x | H | 1 | xx | S |
|
SVE2 bitwise shift right and accumulate<T>
Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.
Where:
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
00 | 00 | RESERVED | 00 | 01 | B | 00 | 1x | H | 01 | xx | S | 1x | xx | D |
|
SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit gather prefetch (vector plus immediate)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE 64-bit gather prefetch (vector plus immediate)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE contiguous store (scalar plus immediate)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE contiguous store (scalar plus immediate)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE contiguous store (scalar plus immediate)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE contiguous store (scalar plus scalar)<T>
Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
size | <T> |
---|
00 | RESERVED | 01 | H | 10 | S | 11 | D |
|
SVE contiguous store (scalar plus scalar)<T>
Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.
Where:
<T> |
Is the size specifier,
encoded in
size<0> :
|
SVE contiguous store (scalar plus scalar)<T>
Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.
Where:
<T> |
Is the size specifier,
encoded in
size :
|
SVE contiguous prefetch (scalar plus immediate)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE contiguous prefetch (scalar plus scalar)<prfop>
Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.
Where:
<prfop> |
Is the prefetch operation specifier,
encoded in
prfop :
prfop | <prfop> |
---|
0000 | PLDL1KEEP | 0001 | PLDL1STRM | 0010 | PLDL2KEEP | 0011 | PLDL2STRM | 0100 | PLDL3KEEP | 0101 | PLDL3STRM | x11x | #uimm4 | 1000 | PSTL1KEEP | 1001 | PSTL1STRM | 1010 | PSTL2KEEP | 1011 | PSTL2STRM | 1100 | PSTL3KEEP | 1101 | PSTL3STRM |
|
SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)<mod>
Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.
Where:
<mod> |
Is the index extend and shift specifier,
encoded in
xs :
|
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:04
Copyright © 2010-2015 Arm Limited or its affiliates. All rights reserved.
This document is Non-Confidential.