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Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | |||||||||
rmode | opcode |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer intsize = if sf == '1' then 64 else 32;
integer fltsize;
FPConvOp op;
FPRounding rounding;
boolean unsigned;
integer part;
case ftype of
when '00'
fltsize = 32;
when '01'
fltsize = 64;
when '10'
UNDEFINED;
if opcode<2:1>:rmode != '11 01' then UNDEFINED;
fltsize = 128;
when '11'
if HaveFP16Ext() then
fltsize = 16;
else
UNDEFINED;
rounding =case opcode<2:1>:rmode of
when '00 xx' // FCVT[NPMZ][US]
rounding = FPDecodeRounding(rmode);
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_FtoI;
when '01 00' // [US]CVTF
rounding = FPRoundingMode(FPCR);
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_ItoF;
when '10 00' // FCVTA[US]
rounding = FPRounding_TIEAWAY;
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_FtoI;
when '11 00' // FMOV
if fltsize != 16 && fltsize != intsize then UNDEFINED;
op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI;
part = 0;
when '11 01' // FMOV D[1]
if intsize != 64 || fltsize != 128 then UNDEFINED;
op = if opcode<0> == '1' then FPConvOp_MOV_ItoF else FPConvOp_MOV_FtoI;
part = 1;
fltsize = 64; // size of D[1] is 64
when '11 11' // FJCVTZS
if !HaveFJCVTZSExt() then UNDEFINED;
rounding = FPRounding_ZERO;
unsigned = (opcode<0> == '1');
op = FPConvOp_CVT_FtoI_JS(rmode);;
otherwise
UNDEFINED;
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Hn> | Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Dn> | Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64();
bits(fltsize) fltval;
bits(intsize) intval;
fltval =case op of
when FPConvOp_CVT_FtoI
fltval = V[n];
intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding);
X[d] = intval;
when FPConvOp_CVT_ItoF
intval = X[n];
fltval = FixedToFP(intval, 0, unsigned, FPCR, rounding);
V[d] = fltval;
when FPConvOp_MOV_FtoI
fltval = Vpart[n,part];
intval = ZeroExtend(fltval, intsize);
X[d] = intval;
when FPConvOp_MOV_ItoF
intval = X[n];
fltval = intval<fltsize-1:0>;
Vpart[d,part] = fltval;
when FPConvOp_CVT_FtoI_JS
bit Z;
fltval = V[n];
(intval, Z) = FPToFixedJS(fltval, 0, TRUE, FPCR, rounding);(fltval, FPCR, TRUE);
PSTATE.<N,Z,C,V> = '0':Z:'00';
X[d] = intval;
Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4
; Build timestamp: 2019-06-26T22:3004
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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