TLBI
TLB Invalidate operation. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
This is an alias of
SYS.
This means:
-
The encodings in this description are named to match the encodings of
SYS.
-
The description of
SYS
gives the operational pseudocode for this instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | op1 | 1 | 0 | 0 | 0 | CRm | op2 | Rt |
| L | | | CRn | | | |
Assembler Symbols
<op1> | Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field. |
<Cm> | Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field. |
<op2> | Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field. |
<tlbi_op> |
Is a TLBI instruction name, as listed for the TLBI system instruction group,
encoded in
op1:CRm:op2 :
op1 | CRm | op2 | <tlbi_op> | Architectural Feature |
---|
000 | 0001 | 000 | VMALLE1OS |
ARMv8.4-TLBI
| 000 | 0001 | 001 | VAE1OS |
ARMv8.4-TLBI
| 000 | 0001 | 010 | ASIDE1OS |
ARMv8.4-TLBI
| 000 | 0001 | 011 | VAAE1OS |
ARMv8.4-TLBI
| 000 | 0001 | 101 | VALE1OS |
ARMv8.4-TLBI
| 000 | 0001 | 111 | VAALE1OS |
ARMv8.4-TLBI
| 000 | 0010 | 001 | RVAE1IS |
ARMv8.4-TLBI
| 000 | 0010 | 011 | RVAAE1IS |
ARMv8.4-TLBI
| 000 | 0010 | 101 | RVALE1IS |
ARMv8.4-TLBI
| 000 | 0010 | 111 | RVAALE1IS |
ARMv8.4-TLBI
| 000 | 0011 | 000 | VMALLE1IS |
-
| 000 | 0011 | 001 | VAE1IS |
-
| 000 | 0011 | 010 | ASIDE1IS |
-
| 000 | 0011 | 011 | VAAE1IS |
-
| 000 | 0011 | 101 | VALE1IS |
-
| 000 | 0011 | 111 | VAALE1IS |
-
| 000 | 0101 | 001 | RVAE1OS |
ARMv8.4-TLBI
| 000 | 0101 | 011 | RVAAE1OS |
ARMv8.4-TLBI
| 000 | 0101 | 101 | RVALE1OS |
ARMv8.4-TLBI
| 000 | 0101 | 111 | RVAALE1OS |
ARMv8.4-TLBI
| 000 | 0110 | 001 | RVAE1 |
ARMv8.4-TLBI
| 000 | 0110 | 011 | RVAAE1 |
ARMv8.4-TLBI
| 000 | 0110 | 101 | RVALE1 |
ARMv8.4-TLBI
| 000 | 0110 | 111 | RVAALE1 |
ARMv8.4-TLBI
| 000 | 0111 | 000 | VMALLE1 |
-
| 000 | 0111 | 001 | VAE1 |
-
| 000 | 0111 | 010 | ASIDE1 |
-
| 000 | 0111 | 011 | VAAE1 |
-
| 000 | 0111 | 101 | VALE1 |
-
| 000 | 0111 | 111 | VAALE1 |
-
| 100 | 0000 | 001 | IPAS2E1IS |
-
| 100 | 0000 | 010 | RIPAS2E1IS |
ARMv8.4-TLBI
| 100 | 0000 | 101 | IPAS2LE1IS |
-
| 100 | 0000 | 110 | RIPAS2LE1IS |
ARMv8.4-TLBI
| 100 | 0001 | 000 | ALLE2OS |
ARMv8.4-TLBI
| 100 | 0001 | 001 | VAE2OS |
ARMv8.4-TLBI
| 100 | 0001 | 100 | ALLE1OS |
ARMv8.4-TLBI
| 100 | 0001 | 101 | VALE2OS |
ARMv8.4-TLBI
| 100 | 0001 | 110 | VMALLS12E1OS |
ARMv8.4-TLBI
| 100 | 0010 | 001 | RVAE2IS |
ARMv8.4-TLBI
| 100 | 0010 | 101 | RVALE2IS |
ARMv8.4-TLBI
| 100 | 0011 | 000 | ALLE2IS |
-
| 100 | 0011 | 001 | VAE2IS |
-
| 100 | 0011 | 100 | ALLE1IS |
-
| 100 | 0011 | 101 | VALE2IS |
-
| 100 | 0011 | 110 | VMALLS12E1IS |
-
| 100 | 0100 | 000 | IPAS2E1OS |
ARMv8.4-TLBI
| 100 | 0100 | 001 | IPAS2E1 |
-
| 100 | 0100 | 010 | RIPAS2E1 |
ARMv8.4-TLBI
| 100 | 0100 | 011 | RIPAS2E1OS |
ARMv8.4-TLBI
| 100 | 0100 | 100 | IPAS2LE1OS |
ARMv8.4-TLBI
| 100 | 0100 | 101 | IPAS2LE1 |
-
| 100 | 0100 | 110 | RIPAS2LE1 |
ARMv8.4-TLBI
| 100 | 0100 | 111 | RIPAS2LE1OS |
ARMv8.4-TLBI
| 100 | 0101 | 001 | RVAE2OS |
ARMv8.4-TLBI
| 100 | 0101 | 101 | RVALE2OS |
ARMv8.4-TLBI
| 100 | 0110 | 001 | RVAE2 |
ARMv8.4-TLBI
| 100 | 0110 | 101 | RVALE2 |
ARMv8.4-TLBI
| 100 | 0111 | 000 | ALLE2 |
-
| 100 | 0111 | 001 | VAE2 |
-
| 100 | 0111 | 100 | ALLE1 |
-
| 100 | 0111 | 101 | VALE2 |
-
| 100 | 0111 | 110 | VMALLS12E1 |
-
| 110 | 0001 | 000 | ALLE3OS |
ARMv8.4-TLBI
| 110 | 0001 | 001 | VAE3OS |
ARMv8.4-TLBI
| 110 | 0001 | 101 | VALE3OS |
ARMv8.4-TLBI
| 110 | 0010 | 001 | RVAE3IS |
ARMv8.4-TLBI
| 110 | 0010 | 101 | RVALE3IS |
ARMv8.4-TLBI
| 110 | 0011 | 000 | ALLE3IS |
-
| 110 | 0011 | 001 | VAE3IS |
-
| 110 | 0011 | 101 | VALE3IS |
-
| 110 | 0101 | 001 | RVAE3OS |
ARMv8.4-TLBI
| 110 | 0101 | 101 | RVALE3OS |
ARMv8.4-TLBI
| 110 | 0110 | 001 | RVAE3 |
ARMv8.4-TLBI
| 110 | 0110 | 101 | RVALE3 |
ARMv8.4-TLBI
| 110 | 0111 | 000 | ALLE3 |
-
| 110 | 0111 | 001 | VAE3 |
-
| 110 | 0111 | 101 | VALE3 |
-
|
|
<Xt> | Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field. |
Operation
The description of
SYS
gives the operational pseudocode for this instruction.
Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5
; Build timestamp: 2019-06-26T222019-04-17T09:0458
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