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UQINCP (scalar)

Unsigned saturating increment scalar by countactive ofpredicate trueelement predicate elements.count.

Counts the number of trueactive elements in the source predicate and then uses the result to increment the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit

313029282726252423222120191817161514131211109876543210
00100101size1010011000100PmPgRdn

32-bit

UQINCP <Wdn>, <Pm><Pg>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m =integer g = UInt(Pm); (Pg); integer dn = UInt(Rdn); boolean unsigned = TRUE; integer ssize = 32;

64-bit

313029282726252423222120191817161514131211109876543210
00100101size1010011000110PmPgRdn

64-bit

UQINCP <Xdn>, <Pm><Pg>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m =integer g = UInt(Pm); (Pg); integer dn = UInt(Rdn); boolean unsigned = TRUE; integer ssize = 64;

Assembler Symbols

<Wdn>

Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<PmPg>

Is the name of the sourcegoverning scalable predicate register, encoded in the "PmPg" field.

<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(ssize) operand1 =bits(PL) mask = P[g]; bits(ssize) operand = X[dn]; bits(PL) operand2 = P[m]; [dn]; bits(ssize) result; integer count = 0; for e = 0 to elements-1 if ElemP[operand2, e, esize] == '1' then [mask, e, esize] == '1' then count = count + 1; integer element = Int(operand1, unsigned); (operand, unsigned); (result, -) = SatQ(element + count, ssize, unsigned); X[dn] = Extend(result, 64, unsigned);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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