A64 ISA XML for Future Architecture Technologies
(2019-06)
27 June 2019
1. Introduction
This is the 2019-06
release of the A64 ISA XML for Future Architecture Technologies.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
2. Contents
3. Release Notes
Change history
This is the A64 ISA XML for Future Architecture Technologies (2019-06).
-
SVE instructions that may be prefixed by a MOVPRFX
instruction now contain Operational information that
describes which variants of MOVPRFX can be used and the
register constraints to be honored to guarantee
predictable behavior.
-
SVE instructions whose timing properties are affected by
PSTATE.DIT now contain Operational information that
describes the effects on their execution timing when
PSTATE.DIT is 1.
-
Many simple clarifications and corrections are also present,
but are too small to be listed here. These can be seen in the
Change Markup PDF provided.
Known issues
-
The Programmable table lookup (TBL) instruction is currently listed
in the Base instructions index. TBL is an SVE and SVE2 instruction,
with encodings from both the SVE and SVE2 classes. The correct
grouping for TBL is under 'SVE instructions'.
-
The SVE MOV(S) aliases of AND(S) (predicates), ORR(S) (predicates)
and SEL (predicates) are missing a qualifier to differentiate the
different types of instructions.
-
The SVE CLASTA (vectors), CLASTB (vectors), COMPACT, LASTA
(vectors), LASTB (vectors), and SPLICE instructions incorrectly
state that they can be used with a predicated MOVPRFX
instruction.