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SQXTUNT

Signed saturating unsigned extract narrow (top).

Saturate the signed integer value in each source element to an unsigned integer value that is half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010101ZnZd

SVE2

SQXTUNT <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE2() then UNDEFINED; bits(3) tsize = tszh:tszl; case tsize of when '001' esize = 16; when '010' esize = 32; when '100' esize = 64; otherwise UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszhtszl<T>
000RESERVED
001B
010H
x11RESERVED
100S
101RESERVED
110RESERVED
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in tszh:tszl:
tszhtszl<Tb>
000RESERVED
001H
010S
x11RESERVED
100D
101RESERVED
110RESERVED

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) result = Z[d]; integer halfesize = esize DIV 2; for e = 0 to elements-1 integer element1 = SInt(Elem[operand1, e, esize]); bits(halfesize) res = UnsignedSat(element1, halfesize); Elem[result, 2*e + 1, halfesize] = res; Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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