RDVL

Read multiple of vector register size to scalar register.

Multiply the current vector register size in bytes by an immediate in the range -32 to 31 and place the result in the 64-bit destination general-purpose register.

313029282726252423222120191817161514131211109876543210
000001001011111101010imm6Rd

SVE

RDVL <Xd>, #<imm>

if !HaveSVE() then UNDEFINED; integer d = UInt(Rd); integer imm = SInt(imm6);

Assembler Symbols

<Xd>

Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.

<imm>

Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.

Operation

CheckSVEEnabled(); integer len = imm * (VL DIV 8); X[d] = len<63:0>;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:30

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.