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SUBS (extended register)

Subtract (extended register), setting flags, subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.

This instruction is used by the alias CMP (extended register).

313029282726252423222120191817161514131211109876543210
sf1101011001Rmoptionimm3RnRd
opS

32-bit (sf == 0)

SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}

64-bit (sf == 1)

SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if sf == '1' then 64 else 32;integer datasize = if sf == '1' then 64 else 32; boolean sub_op = (op == '1'); boolean setflags = (S == '1'); ExtendType extend_type = DecodeRegExtend(option); integer shift = UInt(imm3); if shift > 4 then UNDEFINED;

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn|WSP>

Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.

<Wm>

Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn|SP>

Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.

<R> Is a width specifier, encoded in option:
option<R>
00xW
010W
x11X
10xW
110W
<m>

Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

<extend> For the 32-bit variant: is the extension to be applied to the second source operand, encoded in option:
option<extend>
000UXTB
001UXTH
010LSL|UXTW
011UXTX
100SXTB
101SXTH
110SXTW
111SXTX
If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
For the 64-bit variant: is the extension to be applied to the second source operand, encoded in option:
option<extend>
000UXTB
001UXTH
010UXTW
011LSL|UXTX
100SXTB
101SXTH
110SXTW
111SXTX
If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.
<amount>

Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.

Alias Conditions

AliasIs preferred when
CMP (extended register)Rd == '11111'

Operation

bits(datasize) result; bits(datasize) operand1 = if n == 31 then SP[] else X[n]; bits(datasize) operand2 = ExtendReg(m, extend_type, shift); bits(4) nzcv; bit carry_in; operand2 = NOT(operand2); if sub_op then operand2 = NOT(operand2); carry_in = '1'; else carry_in = '0'; (result, nzcv) = AddWithCarry(operand1, operand2, '1'); (operand1, operand2, carry_in); PSTATE.<N,Z,C,V> = nzcv;if setflags then PSTATE.<N,Z,C,V> = nzcv; if d == 31 && !setflags then SP[] = result; else X[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2, sve v2019-06_rc4 ; Build timestamp: 2019-06-26T22:3004

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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