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UZP1, UZP2 (predicates)

Concatenate even or odd elements from two predicates.

Concatenate adjacent even or odd-numbered elements from the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

It has encodings from 2 classes: Even and Odd

Even

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100100Pn0Pd

Even

UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 0;

Odd

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100110Pn0Pd

Odd

UZP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 1;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D
<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) operand1 = P[n]; bits(PL) operand2 = P[m]; bits(PL) result; bits(PL*2) zipped = operand2:operand1; for e = 0 to elements-1 Elem[result, e, esize DIV 8] = Elem[zipped, 2*e+part, esize DIV 8]; P[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.44v30.42, AdvSIMD v27.08, pseudocode v8.5-2019-06_rc2-5-g22901f2future-20190403, sve v2019-06_rc4v8.5-00bet10_rc5 ; Build timestamp: 2019-06-26T222019-04-17T09:0458

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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