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# GICR_VPENDBASER, Virtual Redistributor LPI Pending Table Base Address Register

The GICR_VPENDBASER characteristics are:

## Purpose

Specifies the base address of the memory that holds the virtual LPI Pending table for the currently scheduled virtual machine.

## Configuration

Some or all RW fields of this register have defined reset values.

This register is provided only in GICv4 implementations.

## Attributes

GICR_VPENDBASER is a 64-bit register.

## Field descriptions

The GICR_VPENDBASER bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
Valid | IDAI | PendingLast | Dirty | RES0 | OuterCache | RES0 | Physical_Address
Physical_Address | RES0 | Shareability | InnerCache | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Valid, bit [63]

This bit controls whether the virtual LPI Pending table is valid:

Valid | Meaning
--- | ---
0b0 | The virtual LPI Pending table is not valid. No vPE is scheduled.
0b1 | The virtual LPI Pending table is valid. A vPE is scheduled.

Setting GICR_VPENDBASER.Valid == 1 when the associated CPU interface does not implement GICv4 is UNPREDICTABLE.

Note

Software can determine whether a PE supports GICv3 or GICv4 by reading ID_AA64PFR0_EL1.

Writing a new value to any bit of GICR_VPENDBASER, other than GICR_VPENDBASER.Valid, when GICR_VPENDBASER.Valid==1 is UNPREDICTABLE.

This field resets to 0.

#### IDAI, bit [62]

Implementation Defined Area Invalid. Indicates whether the IMPLEMENTATION DEFINED area in the virtual LPI Pending table is valid:

IDAI | Meaning
--- | ---
0b0 | The IMPLEMENTATION DEFINED area is valid.
0b1 | The IMPLEMENTATION DEFINED area is invalid and all pending interrupt information is held in the architecturally defined part of the virtual LPI Pending table.

For more information, see LPI Pending tables and Virtual LPI Configuration tables and virtual LPI Pending tables.

This field resets to an architecturally UNKNOWN value.

#### PendingLast, bit [61]

Indicates whether there are pending and enabled interrupts for the last scheduled vPE.

This value is set by the implementation when GICR_VPENDBASER.Valid has been written from 1 to 0 and is otherwise UNKNOWN.

PendingLast | Meaning
--- | ---
0b0 | There are no pending and enabled interrupts for the last scheduled vPE.
0b1 | There is at least one pending interrupt for the last scheduled vPE. It is IMPLEMENTATION DEFINED whether this bit is set when the only pending interrupts for the last scheduled vPE are not enabled. Arm deprecates setting PendingLast to 1 when the only pending interrupts for the last scheduled virtual machine are not enabled.

When the GICR_VPENDBASER.Valid bit is written from 0 to 1, then the state of this bit indicates to the hardware whether the virtual LPI Pending table contains no pending interrupts:

- 0b0: The virtual LPI Pending table is known to be zero, and so the virtual LPI Pending table does not need to be read by hardware to determine which pending interrupts are present.
- 0b1: The virtual LPI Pending table is not known to be zero, and so the hardware must read the virtual LPI Pending table to determine which pending interrupts are present.

This field resets to 0.

#### Dirty, bit [60]
When GICR_VPENDBASER.Valid == 0:

Indicates whether there are any virtual LPIs for the last scheduled vPE that have not completed.

Dirty | Meaning
--- | ---
0b0 | There are no uncompleted virtual LPIs for the last scheduled vPE.
0b1 | There is at least one uncompleted virtual LPI for the last scheduled vPE

This field resets to 0.

####
When GICR_VPENDBASER.Valid == 1, GICR_VPENDBASER.PendingLast == 1 and GICR_TYPER.Dirty == 1:

Reports whether the Virtual Pending table has be parsed.

Dirty | Meaning
--- | ---
0b0 | Parsing of the Virtual Pending Table has completed.
0b1 | Parsing of the Virtual Pending Table has not completed.

This field resets to 0.

####
Otherwise:

Reserved, UNKNOWN.

#### Bit [59]

Reserved, RES0.

#### OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to virtual LPI Pending tables of vPEs targeting this Redistributor. The possible values of this field are:

OuterCache | Meaning
--- | ---
0b000 | Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.
0b001 | Normal Outer Non-cacheable.
0b010 | Normal Outer Cacheable Read-allocate, Write-through.
0b011 | Normal Outer Cacheable Read-allocate, Write-back.
0b100 | Normal Outer Cacheable Write-allocate, Write-through.
0b101 | Normal Outer Cacheable Write-allocate, Write-back.
0b110 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the OuterCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

This field resets to an architecturally UNKNOWN value.

#### Bits [55:52]

Reserved, RES0.

#### Physical_Address, bits [51:16]

Bits [51:16] of the physical address containing the virtual LPI Pending table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

This field resets to an architecturally UNKNOWN value.

#### Bits [15:12]

Reserved, RES0.

#### Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the virtual LPI Pending table. The possible values of this field are:

Shareability | Meaning
--- | ---
0b00 | Non-shareable.
0b01 | Inner Shareable.
0b10 | Outer Shareable.
0b11 | Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the Shareability attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

This field resets to an architecturally UNKNOWN value.

#### InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the virtual LPI Pending table. The possible values of this field are:

InnerCache | Meaning
--- | ---
0b000 | Device-nGnRnE.
0b001 | Normal Inner Non-cacheable.
0b010 | Normal Inner Cacheable Read-allocate, Write-through.
0b011 | Normal Inner Cacheable Read-allocate, Write-back.
0b100 | Normal Inner Cacheable Write-allocate, Write-through.
0b101 | Normal Inner Cacheable Write-allocate, Write-back.
0b110 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the InnerCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

This field resets to an architecturally UNKNOWN value.

#### Bits [6:0]

Reserved, RES0.

## Accessing the GICR_VPENDBASER

The effect of a write to this register is not guaranteed to be visible throughout the affinity hierarchy, as indicated by GICR_CTLR.RWP == 0.

#### GICR_VPENDBASER can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | VLPI_base | 0x0078 | GICR_VPENDBASER

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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