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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0

The ID_AA64DFR0_EL1 characteristics are:

## Purpose

Provides top level information about the debug system in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

The external register EDDFR gives information from this register.

## Attributes

ID_AA64DFR0_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64DFR0_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | TraceBuffer TraceFilt | TraceFilt DoubleLock | DoubleLock PMSVer | PMSVer
CTX_CMPs | RES0 | WRPs | RES0 | BRPs | PMUVer | TraceVer | DebugVer
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:48 44]

Reserved, RES0.

#### TraceBuffer, bits [47:44]
When TRBE is implemented:

Trace Buffer Extension version. Defined values are:

TraceBuffer | Meaning
--- | ---
0b0000 | Trace Buffer Extension not implemented.
0b0001 | Trace Buffer Extension implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### TraceFilt, bits [43:40]
From Armv8.4:

Armv8.4 Self-hosted Trace Extension version. Defined values are:

TraceFilt | Meaning
--- | ---
0b0000 | Armv8.4 Self-hosted Trace Extension not implemented.
0b0001 | Armv8.4 Self-hosted Trace Extension implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### DoubleLock, bits [39:36]

OS Double Lock implemented. Defined values are:

DoubleLock | Meaning
--- | ---
0b0000 | OS Double Lock implemented. OSDLR_EL1 is read/write.
0b1111 | OS Double Lock not implemented. OSDLR_EL1 is RAZ/WI.

ARMv8.0-DoubleLock implements the functionality added by the value 0b0000.

All other values are reserved.

#### PMSVer, bits [35:32]
From Armv8.2:

Statistical Profiling Extension version. Defined values are:

PMSVer | Meaning
--- | ---
0b0000 | Statistical Profiling Extension not implemented.
0b0001 | Statistical Profiling Extension implemented.
0b0010 | As 0b0001 and also includes support for: The Event packet Alignment flag. If SVE is implemented, the Scalable Vector extensions to Statistical Profiling.

SPE implements the functionality added by the value 0b0001.

ARMv8.3-SPE implements the functionality added by the value 0b0010. If ARMv8.3-SPE is implemented, then ID_AA64DFR0_EL1.PMSVer is not permitted to read as 0b0000 or 0b0001.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### CTX_CMPs, bits [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

#### Bits [27:24]

Reserved, RES0.

#### WRPs, bits [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

#### Bits [19:16]

Reserved, RES0.

#### BRPs, bits [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

#### PMUVer, bits [11:8]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the Alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Defined values are:

PMUVer | Meaning
--- | ---
0b0000 | Performance Monitors Extension not implemented.
0b0001 | Performance Monitors Extension implemented, PMUv3.
0b0100 | PMUv3 for Armv8.1. As 0b0001, and also includes support for: Extended 16-bit PMEVTYPER<n>_EL0.evtCount field. If EL2 is implemented, the MDCR_EL2.HPMD control bit.
0b0101 | PMUv3 for Armv8.4. As 0b0100 and also includes support for the PMMIR_EL1 register.
0b0110 | PMUv3 for Armv8.5. As 0b0101 and also includes support for: 64-bit event counters. If EL2 is implemented, the MDCR_EL2.HCCD control bit. If EL3 is implemented, the MDCR_EL3.SCCD control bit.
0b1111 | IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value in new implementations.

ARMv8.1-PMU implements the functionality added by the value 0b0100.

ARMv8.4-PMU implements the functionality added by the value 0b0101.

ARMv8.5-PMU implements the functionality added by the value 0b0110.

All other values are reserved.

From Armv8.1, the value 0b0001 is not permitted.

From Armv8.4, the value 0b0100 is not permitted.

From Armv8.5, the value 0b0101 is not permitted.

#### TraceVer, bits [7:4]

Trace support. Indicates whether System register interface to a PE trace unit is implemented. Defined values are:

TraceVer | Meaning
--- | ---
0b0000 | PE trace unit System registers not implemented.
0b0001 | PE trace unit System registers implemented.

All other values are reserved.

A value of 0b0000 only indicates that no System register interface to a PE trace unit is implemented. A PE trace unit might nevertheless be implemented without a System register interface.

See the ETM Architecture Specification for more information.

#### DebugVer, bits [3:0]

Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:

DebugVer | Meaning
--- | ---
0b0110 | Armv8 debug architecture.
0b0111 | Armv8 debug architecture with Virtualization Host Extensions.
0b1000 | Armv8.2 debug architecture
0b1001 | Armv8.4 debug architecture

All other values are reserved.

ARMv8.2-Debug adds the functionality indicated by the value 0b1000.

- If ARMv8.1-VHE is not implemented the only permitted value is 0b0110.
- In an Armv8.0 implementation the value 0b1000 is not permitted.

## Accessing the ID_AA64DFR0_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64DFR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0101 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64DFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64DFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64DFR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

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