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# ERR<n>MISC0, Error Record Miscellaneous Register 0

The ERR<n>MISC0 characteristics are:

## Purpose

IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:

- A Corrected error counter or counters.

- Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.

- Other state information not present in the corresponding status and address registers.

If the node <q> that owns error record <n> implements architecturally-defined error counters, so that ERR<q>FR.CEC != 0b000, and error record <n> can record countable errors, then ERR<n>MISC0 implements the architecturally-defined error counter or counters.

## Configuration

Some or all RW fields of this register have defined reset values.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, ERR<n>MISC0 is RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

## Attributes

ERR<n>MISC0 is a 64-bit register.

## Field descriptions

The ERR<n>MISC0 bit assignments are:

### When ERR<q>FR.CEC == 0b000:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

### When ERR<q>FR.CEC == 0b100 and ERR<q>FR.RP == 0:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED | OF | CEC
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:48]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

#### OF, bit [47]

Sticky overflow bit.

Set to 1 when the Corrected error count field is incremented and wraps through zero.

OF | Meaning
--- | ---
0b0 | Counter has not overflowed.
0b1 | Counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CEC, bits [46:32]

Corrected error count.

Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

### When ERR<q>FR.CEC == 0b010 and ERR<q>FR.RP == 0:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED | OF | CEC
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:40]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

#### OF, bit [39]

Sticky overflow bit.

Set to 1 when the Corrected error count field is incremented and wraps through zero.

OF | Meaning
--- | ---
0b0 | Counter has not overflowed.
0b1 | Counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CEC, bits [38:32]

Corrected error count.

Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

### When ERR<q>FR.CEC == 0b100 and ERR<q>FR.RP == 1:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
OFO | CECO | OFR | CECR
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### OFO, bit [63]

Sticky overflow bit, other.

Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

OFO | Meaning
--- | ---
0b0 | Other counter has not overflowed.
0b1 | Other counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CECO, bits [62:48]

Corrected error count, other.

Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### OFR, bit [47]

Sticky overflow bit, repeat.

Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

OFR | Meaning
--- | ---
0b0 | Repeat counter has not overflowed.
0b1 | Repeat counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CECR, bits [46:32]

Corrected error count, repeat.

Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

### When ERR<q>FR.CEC == 0b010 and ERR<q>FR.RP == 1:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED | OFO | CECO | OFR | CECR
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:48]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

#### OFO, bit [47]

Sticky overflow bit, other.

Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

OFO | Meaning
--- | ---
0b0 | Other counter has not overflowed.
0b1 | Other counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CECO, bits [46:40]

Corrected error count, other.

Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### OFR, bit [39]

Sticky overflow bit, repeat.

Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

OFR | Meaning
--- | ---
0b0 | Repeat counter has not overflowed.
0b1 | Repeat counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

- This bit is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CECR, bits [38:32]

Corrected error count, repeat.

Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way.

The following resets apply:

- This field is preserved on an Error Recovery reset.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

## Accessing the ERR<n>MISC0

Arm recommends that a miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.

When ERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.

#### ERR<n>MISC0 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0x020 + 64n | ERR<n>MISC0

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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