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# ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2

The ID_AA64MMFR2_EL1 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch64 state.

For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers.

## Configuration

This register is present only from Armv8.2. Otherwise, direct accesses to ID_AA64MMFR2_EL1 are RES0.

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ID_AA64MMFR2_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64MMFR2_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
E0PD | EVT | BBM | TTL | RES0 | FWB | IDS | AT
ST | NV | CCIDX | VARange | IESB | LSM | UAO | CnP
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### E0PD, bits [63:60]
From Armv8.5:

Indicates support for the ARMv8.5-E0PD mechanism. Defined values are:

E0PD | Meaning
--- | ---
0b0000 | E0PDx mechanism is not implemented.
0b0001 | E0PDx mechanism is implemented.

All other values are reserved.

In Armv8.4, the only permitted value is 0b0000.

From Armv8.5, the only permitted values is 0b0001.

####
Otherwise:

Reserved, RES0.

#### EVT, bits [59:56]
When ARMv8.2-EVT is implemented:

Enhanced Virtualization Traps. If EL2 is implemented, indicates support for the HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps. Defined values are:

EVT | Meaning
--- | ---
0b0000 | HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps are not supported.
0b0001 | HCR_EL2.{TOCU, TICAB, TID4} traps are supported. HCR_EL2.{TTLBOS, TTLBIS} traps are not supported.
0b0010 | HCR_EL2.{TTLBOS, TTLBIS, TOCU, TICAB, TID4} traps are supported.

All other values are reserved.

In Armv8.0, the only permitted value is 0b0000.

From Armv8.1, the permitted values are 0b0000, 0b0001, and 0b0010.

From Armv8.5, the permitted values are:

- 0b0000 when EL2 is not implemented.
- 0b0010 when EL2 is implemented. This feature is identified as ARMv8.2-EVT.

####
Otherwise:

Reserved, RES0.

#### BBM, bits [55:52]
From Armv8.4:

Allows identification of the requirements of the hardware to have break-before-make sequences when changing block size for a translation.

BBM | Meaning
--- | ---
0b0000 | Level 0 support for changing block size is supported.
0b0001 | Level 1 support for changing block size is supported.
0b0010 | Level 2 support for changing block size is supported.

All other values are reserved.

ARMv8.4-TTRem implements the functionality identified by the values 0b0000, 0b0001, and 0b0010.

From Armv8.4, the permitted values are 0b0000, 0b0001, and 0b0010.

####
Otherwise:

Reserved, RES0.

#### TTL, bits [51:48]
From Armv8.4:

Indicates support for TTL field in address operations. Defined values are:

TTL | Meaning
--- | ---
0b0000 | TLB maintenance instructions by address have bits[47:44] as RES0.
0b0001 | TLB maintenance instructions by address have bits[47:44] holding the TTL field.

All other values are reserved.

ARMv8.4-TTL implements the functionality identified by the value 0b0001.

This field affects TLBI IPAS2E1, TLBI IPAS2E1IS, TLBI IPAS2E1OS, TLBI IPAS2LE1, TLBI IPAS2LE1IS, TLBI IPAS2LE1OS, TLBI VAAE1, TLBI VAAE1IS, TLBI VAAE1OS, TLBI VAALE1, TLBI VAALE1IS, TLBI VAALE1OS, TLBI VAE1, TLBI VAE1IS, TLBI VAE1OS, TLBI VAE2, TLBI VAE2IS, TLBI VAE2OS, TLBI VAE3, TLBI VAE3IS, TLBI VAE3OS,TLBI VALE1, TLBI VALE1IS, TLBI VALE1OS, TLBI VALE2, TLBI VALE2IS, TLBI VALE2OS, TLBI VALE3, TLBI VALE3IS, TLBI VALE3OS.

From Armv8.4, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### Bits [47:44]

Reserved, RES0.

#### FWB, bits [43:40]
From Armv8.4:

Indicates support for HCR_EL2.FWB

FWB | Meaning
--- | ---
0b0000 | HCR_EL2.FWB bit is not supported and the field is RES0
0b0001 | HCR_EL2.FWB is supported.

If ARMv8.4-SecEL2 is implemented the only permitted value is 0b0001

All other values reserved.

This field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### IDS, bits [39:36]
From Armv8.4:

Indicates the value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. Defined values are:

IDS | Meaning
--- | ---
0b0000 | An exception, other than a trap caused by HCR_EL2.TID3, generated by a read access to the feature ID space is reported by ESR_ELx.EC == 0x0.
0b0001 | All exceptions generated by an AArch64 read access to the feature ID space are reported by ESR_ELx.EC == 0x18.

All other values are reserved.

The Feature ID space is defined as the System register space in AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}.

ARMv8.4-IDST implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### AT, bits [35:32]
From Armv8.4:

Identifies support for unaligned single-copy atomicity and atomic functions. Defined values are:

AT | Meaning
--- | ---
0b0000 | Unaligned single-copy atomicity and atomic functions are not supported.
0b0001 | Unaligned single-copy atomicity and atomic functions with a 16-byte address range aligned to 16-bytes are supported.

All other values are reserved.

ARMv8.4-LSE implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### ST, bits [31:28]
From Armv8.4:

Identifies support for small translation tables. Defined values are:

ST | Meaning
--- | ---
0b0000 | The maximum value of the TCR_ELx.{T0SZ,T1SZ} and VTCR_EL2.T0SZ fields is 39.
0b0001 | The maximum value of the TCR_ELx.{T0SZ,T1SZ} and VTCR_EL2.T0SZ fields is 48 for 4KB and 16KB granules, and 47 for 64KB granules.

All other values are reserved.

ARMv8.4-TTST implements the functionality identified by the value 0b0001.

If ARMv8.4-SecEL2 is implemented the only permitted value is 0b0001.

In an implementation which does not support Secure EL2, the permitted values are 0b0000 and 0b0001.

####
Otherwise:

Reserved, RES0.

#### NV, bits [27:24]
From Armv8.4:

Nested Virtualization. If EL2 is implemented, indicates support for the use of nested virtualization. Defined values are:

NV | Meaning
--- | ---
0b0000 | Nested virtualization is not supported.
0b0001 | The HCR_EL2.NV, HCR_EL2.NV1, HCR_EL2.AT bits are implemented.
0b0010 | The VNCR_EL2 register and the HCR_EL2.{AT, NV, NV1, NV2} bits are implemented.

All other values are reserved.

In Armv8.2, the only permitted value is 0b0000.

In Armv8.3, the permitted values are:

- When EL2 is not implemented, 0b0000.
- When EL2 is implemented, 0b0001.

The feature ARMv8.3-NV implements the functionality identified by the value 0b0001.

In Armv8.4, the permitted values are:

- When EL2 is not implemented, 0b0000.
- When EL2 is implemented, 0b0010.

The feature ARMv8.4-NV implements the functionality identified by the value 0b0010.

####
From Armv8.3:

Nested Virtualization. If EL2 is implemented, indicates support for the use of nested virtualization. Defined values are:

NV | Meaning
--- | ---
0b0000 | Nested virtualization is not supported.
0b0001 | The HCR_EL2.NV, HCR_EL2.NV1, HCR_EL2.AT bits are implemented.

All other values are reserved.

In Armv8.2, the only permitted value is 0b0000.

From Armv8.3, the permitted values are:

- When EL2 is not implemented, 0b0000.
- When EL2 is implemented, 0b0001.

The feature ARMv8.3-NV implements the functionality identified by this value.

####
Otherwise:

Reserved, RES0.

#### CCIDX, bits [23:20]
From Armv8.3:

Support for the use of revised CCSIDR_EL1 register format. Defined values are:

CCIDX | Meaning
--- | ---
0b0000 | 32-bit format implemented for all levels of the CCSIDR_EL1.
0b0001 | 64-bit format implemented for all levels of the CCSIDR_EL1.

All other values are reserved.

This feature is identified as ARMv8.3-CCIDX.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

####
Otherwise:

Reserved, RES0.

#### VARange, bits [19:16]
From Armv8.2:

Indicates support for a larger virtual address. Defined values are:

VARange | Meaning
--- | ---
0b0000 | VMSAv8-64 supports 48-bit VAs.
0b0001 | VMSAv8-64 supports 52-bit VAs when using the 64KB translation granule. The other translation granules support 48-bit VAs.

All other values are reserved.

ARMv8.2-LVA implements the functionality identified by the value 0b0001.

From Armv8.2, the permitted values are 0b0000 and 0b0001.

####
Otherwise:

Reserved, RES0.

#### IESB, bits [15:12]
From Armv8.2:

Indicates support for the IESB bit in the SCTLR_ELx registers. Defined values are:

IESB | Meaning
--- | ---
0b0000 | IESB bit in the SCTLR_ELx registers is not supported.
0b0001 | IESB bit in the SCTLR_ELx registers is supported.

All other values are reserved.

ARMv8.2-IESB implements the functionality identified by the value 0b0001.

From Armv8.2, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### LSM, bits [11:8]
From Armv8.2:

Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. Defined values are:

LSM | Meaning
--- | ---
0b0000 | LSMAOE and nTLSMD bits not supported.
0b0001 | LSMAOE and nTLSMD bits supported.

All other values are reserved.

ARMv8.2-LSMAOC implements the functionality identified by the value 0b0001.

####
Otherwise:

Reserved, RES0.

#### UAO, bits [7:4]
From Armv8.2:

User Access Override. Defined values are:

UAO | Meaning
--- | ---
0b0000 | UAO not supported.
0b0001 | UAO supported.

All other values are reserved.

ARMv8.2-UAO implements the functionality identified by the value 0b0001.

From Armv8.2, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### CnP, bits [3:0]
From Armv8.2:

Common not Private translations. Defined values are:

CnP | Meaning
--- | ---
0b0000 | Common not Private translations not supported.
0b0001 | Common not Private translations supported.

All other values are reserved.

ARMv8.2-TTCNP implements the functionality identified by the value 0b0001.

From Armv8.2, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_AA64MMFR2_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64MMFR2_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0111 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64MMFR2_EL1; elsif PSTATE.EL == EL2 then return ID_AA64MMFR2_EL1; elsif PSTATE.EL == EL3 then return ID_AA64MMFR2_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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