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# SPSel, Stack Pointer Select

The SPSel characteristics are:

## Purpose

Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx.

## Configuration

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

SPSel is a 64-bit register.

## Field descriptions

The SPSel bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | SP
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:1]

Reserved, RES0.

#### SP, bit [0]

Stack pointer to use. Possible values of this bit are:

SP | Meaning
--- | ---
0b0 | Use SP_EL0 at all Exception levels.
0b1 | Use SP_ELx for Exception level ELx.

This field resets to 1.

## Accessing the SPSel

For details on the operation of the MSR (immediate) accessor, see MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Accesses to this register use the following encodings:

#### MRS <Xt>, SPSel

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0100 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return Zeros(63):PSTATE.SP; elsif PSTATE.EL == EL2 then return Zeros(63):PSTATE.SP; elsif PSTATE.EL == EL3 then return Zeros(63):PSTATE.SP;

#### MSR SPSel, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0100 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.SP = X[t]<0>; elsif PSTATE.EL == EL2 then PSTATE.SP = X[t]<0>; elsif PSTATE.EL == EL3 then PSTATE.SP = X[t]<0>;

#### MSR SPSel, #<imm>

op0 | op1 | CRn | op2
--- | --- | --- | ---
0b00 | 0b000 | 0b0100 | 0b101

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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