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# ID_MMFR2, Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR3, and ID_MMFR4.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register ID_MMFR2 bits [31:0] are architecturally mapped to AArch64 System register ID_MMFR2_EL1[31:0] .

## Attributes

ID_MMFR2 is a 32-bit register.

## Field descriptions

The ID_MMFR2 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
HWAccFlg | WFIStall | MemBarr | UniTLB | HvdTLB | L1HvdRng | L1HvdBG | L1HvdFG

#### HWAccFlg, bits [31:28]

Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:

HWAccFlg | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for VMSAv7 Access flag, updated in hardware.

All other values are reserved.

In Armv8 the only permitted value is 0b000.

#### WFIStall, bits [27:24]

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:

WFIStall | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for WFI stalling.

All other values are reserved.

In Armv8 the permitted values are 0b000 and 0b001.

#### MemBarr, bits [23:20]

Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==1111) encoding space:

MemBarr | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported memory barrier System instructions are: Data Synchronization Barrier (DSB).
0b0010 | As for 0b001, and adds: Instruction Synchronization Barrier (ISB). Data Memory Barrier (DMB).

All other values are reserved.

In Armv8 the only permitted value is 0b010.

Arm deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.

#### UniTLB, bits [19:16]

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:

UniTLB | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Supported unified TLB maintenance operations are: Invalidate all entries in the TLB. Invalidate TLB entry by VA.
0b0010 | As for 0b001, and adds: Invalidate TLB entries by ASID match.
0b0011 | As for 0b010, and adds: Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation
0b0100 | As for 0b011, and adds: Invalidate Hyp mode unified TLB entry by VA. Invalidate entire Non-secure PL1&0 unified TLB. Invalidate entire Hyp mode unified TLB.
0b0101 | As for 0b100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL,TLBIMVALH.
0b0110 | As for 0b101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L.

All other values are reserved.

In Armv8-A the only permitted value is 0b110.

#### HvdTLB, bits [15:12]

If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. Arm deprecates the use of this field by software.

#### L1HvdRng, bits [11:8]

Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:

L1HvdRng | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Supported Level 1 Harvard cache maintenance range operations are: Invalidate data cache range by VA. Invalidate instruction cache range by VA. Clean data cache range by VA. Clean and invalidate data cache range by VA.

All other values are reserved.

In Armv8 the only permitted value is 0b0000.

#### L1HvdBG, bits [7:4]

Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:

L1HvdBG | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Supported Level 1 Harvard cache background fetch operations are: Fetch instruction cache range by VA. Fetch data cache range by VA.

All other values are reserved.

In Armv8 the only permitted value is 0b0000.

#### L1HvdFG, bits [3:0]

Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:

L1HvdFG | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Supported Level 1 Harvard cache foreground fetch operations are: Fetch instruction cache range by VA. Fetch data cache range by VA.

All other values are reserved.

In Armv8 the only permitted value is 0b0000.

## Accessing the ID_MMFR2

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_MMFR2; elsif PSTATE.EL == EL2 then return ID_MMFR2; elsif PSTATE.EL == EL3 then return ID_MMFR2;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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