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# SDER32_EL2, AArch32 Secure Debug Enable Register

The SDER32_EL2 characteristics are:

## Purpose

Allows access to the AArch32 register SDER from Secure EL2 and EL3 only.

## Configuration

This register has no effect if EL2 is not enabled in the current Security state.

If EL1 is AArch64 only, this register is UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

SDER32_EL2 is a 64-bit register.

## Field descriptions

The SDER32_EL2 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | SUNIDEN | SUIDEN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:2]

Reserved, RES0.

#### SUNIDEN, bit [1]

Secure User Non-Invasive Debug Enable:

SUNIDEN | Meaning
--- | ---
0b0 | Performance Monitors event counting prohibited in Secure EL0 unless allowed by MDCR_EL3.SPME or the IMPLEMENTATION DEFINED authentication interface ExternalSecureNoninvasiveDebugEnabled().
0b1 | Performance Monitors event counting allowed in Secure EL0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### SUIDEN, bit [0]

Secure User Invasive Debug Enable:

SUIDEN | Meaning
--- | ---
0b0 | Debug exceptions other than Breakpoint Instruction exceptions from Secure EL0 are disabled, unless enabled by MDCR_EL3.SPD32.
0b1 | Debug exceptions from Secure EL0 are enabled.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing the SDER32_EL2

Accesses to this register use the following encodings:

#### MRS <Xt>, SDER32_EL2

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0001 | 0b0011 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return SDER32_EL2; elsif PSTATE.EL == EL3 then return SDER32_EL2;

#### MSR SDER32_EL2, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0001 | 0b0011 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then SDER32_EL2 = X[t]; elsif PSTATE.EL == EL3 then SDER32_EL2 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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