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# MPAMCFG_CPBM, MPAM Cache Portion Bitmap Partition Configuration Register

The MPAMCFG_CPBM characteristics are:

## Purpose

The MPAMCFG_CPBM register is a read-write register that configures the cache portions that a PARTID is allowed to allocate. After setting MPAMCFG_PART_SEL with a PARTID, software (usually a hypervisor) writes to the MPAMCFG_CPBM register to configure which cache portions the PARTID is allowed to allocate.

## Configuration

The power domain of MPAMCFG_CPBM is IMPLEMENTATION DEFINED.

This register is present only when MPAMF_IDR.HAS_CPOR == 1. Otherwise, direct accesses to MPAMCFG_CPBM are IMPLEMENTATION DEFINED.

## Attributes

MPAMCFG_CPBM is a 32768-bit register.

## Field descriptions

The MPAMCFG_CPBM bit assignments are:

#### CPBM<n>, bit [n], for n = 0 to 32767

Each bit, CPBM<n>, grants permission to the PARTID to allocate cache lines within cache portion n.

CPBM<n> | Meaning
--- | ---
0b0 | The PARTID is not permitted to allocate into cache portion n.
0b1 | The PARTID is permitted to allocate within cache portion n.

The number of bits in the cache portion partitioning bit map of this component is given in MPAMF_CPOR_IDR.CPBM_WD. CPBM_WD contains a value from 1 to 215, inclusive. Values of CPBM_WD greater than 32 require a group of 32-bit registers to access the CPBM, up to 1024 registers.

Bits CPBM<n>, where n is greater than CPBM_WD, are not required to be implemented.

## Accessing the MPAMCFG_CPBM

This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.

MPAMCFG_CPBM must be accessible from the Non-secure and Secure address maps.

MPAMCFG_CPBM must be banked for the Secure and Non-secure address maps. The Secure instance accesses the cache portion bitmaps used for Secure PARTIDs, and the Non-secure instance accesses the cache portion bitmaps used for Non-secure PARTIDs.

#### MPAMCFG_CPBM can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_s | 0x1000 | MPAMCFG_CPBM_s

Access on this interface is RW.

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_ns | 0x1000 | MPAMCFG_CPBM_ns

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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