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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCCIDCCTLR0, Context Identifier Comparator Control Register 0

The TRCCIDCCTLR0 characteristics are:

## Purpose

Contains Context identifier mask values for the TRCCIDCVR<n> registers, for n = 0 to 3.

## Configuration

External register TRCCIDCCTLR0 bits [31:0] are architecturally mapped to AArch64 System register TRCCIDCCTLR0[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMCIDC > 0x0, TRCIDR2.CIDSIZE > 0b00000 and ETE is implemented. Otherwise, direct accesses to TRCCIDCCTLR0 are RES0.

## Attributes

TRCCIDCCTLR0 is a 32-bit register.

## Field descriptions

The TRCCIDCCTLR0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
COMP3<m>, bit [m+24] | COMP2<m>, bit [m+16] | COMP1<m>, bit [m+8] | COMP0<m>, bit [m]

#### COMP3<m>, bit [m+24], for m = 0 to 7
When TRCIDR4.NUMCIDC > 3:

TRCCIDCVR3 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR3. Each bit in this field corresponds to a byte in TRCCIDCVR3.

COMP3<m> | Meaning
--- | ---
0b0 | The trace unit includes TRCCIDCVR3[(m×8+7):(m×8)] when it performs the Context identifier comparison.
0b1 | The trace unit ignores TRCCIDCVR3[(m×8+7):(m×8)] when it performs the Context identifier comparison.

This bit is RES0 if m >= TRCIDR2.CIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### COMP2<m>, bit [m+16], for m = 0 to 7
When TRCIDR4.NUMCIDC > 2:

TRCCIDCVR2 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR2. Each bit in this field corresponds to a byte in TRCCIDCVR2.

COMP2<m> | Meaning
--- | ---
0b0 | The trace unit includes TRCCIDCVR2[(m×8+7):(m×8)] when it performs the Context identifier comparison.
0b1 | The trace unit ignores TRCCIDCVR2[(m×8+7):(m×8)] when it performs the Context identifier comparison.

This bit is RES0 if m >= TRCIDR2.CIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### COMP1<m>, bit [m+8], for m = 0 to 7
When TRCIDR4.NUMCIDC > 1:

TRCCIDCVR1 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR1. Each bit in this field corresponds to a byte in TRCCIDCVR1.

COMP1<m> | Meaning
--- | ---
0b0 | The trace unit includes TRCCIDCVR1[(m×8+7):(m×8)] when it performs the Context identifier comparison.
0b1 | The trace unit ignores TRCCIDCVR1[(m×8+7):(m×8)] when it performs the Context identifier comparison.

This bit is RES0 if m >= TRCIDR2.CIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### COMP0<m>, bit [m], for m = 0 to 7
When TRCIDR4.NUMCIDC > 0:

TRCCIDCVR0 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR0. Each bit in this field corresponds to a byte in TRCCIDCVR0.

COMP0<m> | Meaning
--- | ---
0b0 | The trace unit includes TRCCIDCVR0[(m×8+7):(m×8)] when it performs the Context identifier comparison.
0b1 | The trace unit ignores TRCCIDCVR0[(m×8+7):(m×8)] when it performs the Context identifier comparison.

This bit is RES0 if m >= TRCIDR2.CIDSIZE.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

## Accessing the TRCCIDCCTLR0

If software uses the TRCCIDCVR<n> registers, for n = 0 to 3, then it must program this register.

If software sets a mask bit to 0b1 then it must program the relevant byte in TRCCIDCVR<n> to 0x00.

If any bit is 0b1 and the relevant byte in TRCCIDCVR<n> is not 0x00, the behavior of the Context Identifier Comparator is CONSTRAINED UNPREDICTABLE. In this scenario the comparator might match unexpectedly or might not match.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCCIDCCTLR0 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x680

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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