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# ICH_VTR, Interrupt Controller VGIC Type Register

The ICH_VTR characteristics are:

## Purpose

Reports supported GIC virtualisartion features.

## Configuration

AArch32 System register ICH_VTR bits [31:0] are architecturally mapped to AArch64 System register ICH_VTR_EL2[31:0] .

If EL2 is not implemented, all bits in this register are RES0 from EL3, except for nV4, which is RES1 from EL3.

## Attributes

ICH_VTR is a 32-bit register.

## Field descriptions

The ICH_VTR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRIbits | PREbits | IDbits | SEIS | A3V | nV4 | TDS | RES0 | ListRegs

#### PRIbits, bits [31:29]

Priority bits. The number of virtual priority bits implemented, minus one.

An implementation must implement at least 32 levels of virtual priority (5 priority bits).

This field is an alias of ICV_CTLR.PRIbits.

#### PREbits, bits [28:26]

The number of virtual preemption bits implemented, minus one.

An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).

The value of this field must be less than or equal to the value of ICH_VTR.PRIbits.

#### IDbits, bits [25:23]

The number of virtual interrupt identifier bits supported:

IDbits | Meaning
--- | ---
0b000 | 16 bits.
0b001 | 24 bits.

All other values are reserved.

This field is an alias of ICV_CTLR.IDbits.

#### SEIS, bit [22]

SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs:

SEIS | Meaning
--- | ---
0b0 | The virtual CPU interface logic does not support generation of SEIs.
0b1 | The virtual CPU interface logic supports generation of SEIs.

This bit is an alias of ICV_CTLR.SEIS.

#### A3V, bit [21]

Affinity 3 Valid. Possible values are:

A3V | Meaning
--- | ---
0b0 | The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.
0b1 | The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

This bit is an alias of ICV_CTLR.A3V.

#### nV4, bit [20]

Direct injection of virtual interrupts not supported. Possible values are:

nV4 | Meaning
--- | ---
0b0 | The CPU interface logic supports direct injection of virtual interrupts.
0b1 | The CPU interface logic does not support direct injection of virtual interrupts.

In GICv3 this bit is RES1.

#### TDS, bit [19]

Separate trapping of Non-secure EL1 writes to ICV_DIR supported.

TDS | Meaning
--- | ---
0b0 | Implementation does not support ICH_HCR.TDIR.
0b1 | Implementation supports ICH_HCR.TDIR.

#### Bits [18:5]

Reserved, RES0.

#### ListRegs, bits [4:0]

The number of implemented List registers, minus one. For example, a value of 0b01111 indicates that the maximum of 16 List registers are implemented.

## Accessing the ICH_VTR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_VTR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_VTR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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