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# ID_PFR0_EL1, AArch32 Processor Feature Register 0

The ID_PFR0_EL1 characteristics are:

## Purpose

Gives top-level information about the instruction sets supported by the PE in AArch32 state.

Must be interpreted with ID_PFR1_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

AArch64 System register ID_PFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR0[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_PFR0_EL1 is a 64-bit register.

## Field descriptions

The ID_PFR0_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RAS | DIT | AMU | CSV2 | State3 | State2 | State1 | State0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### RAS, bits [31:28]

RAS Extension version.

RAS | Meaning
--- | ---
0b0000 | No RAS Extension.
0b0001 | RAS Extension present.
0b0010 | ARMv8.4-RAS present. As 0b0001, and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp Extension.

All other values are reserved.

From Armv8.4, when ARMv8.4-DFE is not implemented, and ERRIDR.NUM is zero, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010. Otherwise from Armv8.4 the only permitted value is 0b0010.

ARMv8.4-RAS implements the functionality identified by the value 0b0010.

In Armv8.2, the only permitted value is 0b0001.

In Armv8.1 and Armv8.0, the permitted values are 0b0000 and 0b0001.

#### DIT, bits [27:24]
From Armv8.4:

Data Independent Timing. Defined values are:

DIT | Meaning
--- | ---
0b0000 | AArch32 does not guarantee constant execution time of any instructions.
0b0001 | AArch32 provides the CPSR.DIT mechanism to guarantee constant execution time of certain instructions.

All other values are reserved.

ARMv8.4-DIT implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### AMU, bits [23:20]
From Armv8.4:

Activity Monitors Extension. Defined values are:

AMU | Meaning
--- | ---
0b0000 | Activity Monitors Extension is not implemented.
0b0001 | Activity Monitors Extension Version 1 is implemented.

All other values are reserved.

AMUv1 implements the functionality identified by the value 0b0001.

In Armv8.0, Armv8.1, Armv8.2, and Armv8.3, the only permitted value is 0b0000.

From Armv8.4, the permitted values are 0b0000 and 0b0001.

####
Otherwise:

Reserved, RES0.

#### CSV2, bits [19:16]
From Armv8.5:

Speculative use of out of context branch targets. Defined values are:

CSV2 | Meaning
--- | ---
0b0000 | This Device does not disclose whether branch targets trained in one hardware described context can affect speculative execution in a different hardware described context.
0b0001 | Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way.

From Armv8.5 the only permitted value is 0b0001.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### State3, bits [15:12]

T32EE instruction set support. Defined values are:

State3 | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | T32EE instruction set implemented.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### State2, bits [11:8]

Jazelle extension support. Defined values are:

State2 | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | Jazelle extension implemented, without clearing of JOSCR.CV on exception entry.
0b0010 | Jazelle extension implemented, with clearing of JOSCR.CV on exception entry.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

#### State1, bits [7:4]

T32 instruction set support. Defined values are:

State1 | Meaning
--- | ---
0b0000 | T32 instruction set not implemented.
0b0001 | T32 encodings before the introduction of Thumb-2 technology implemented: All instructions are 16-bit. A BL or BLX is a pair of 16-bit instructions. 32-bit instructions other than BL and BLX cannot be encoded.
0b0011 | T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions.

All other values are reserved.

In Armv8-A the only permitted value is 0b0011.

#### State0, bits [3:0]

A32 instruction set support. Defined values are:

State0 | Meaning
--- | ---
0b0000 | A32 instruction set not implemented.
0b0001 | A32 instruction set implemented.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

## Accessing the ID_PFR0_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_PFR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0001 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_PFR0_EL1; elsif PSTATE.EL == EL2 then return ID_PFR0_EL1; elsif PSTATE.EL == EL3 then return ID_PFR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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