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# DAIF, Interrupt Mask Bits

The DAIF characteristics are:

## Purpose

Allows access to the interrupt mask bits.

## Configuration

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

DAIF is a 64-bit register.

## Field descriptions

The DAIF bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | D | A | I | F | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:10]

Reserved, RES0.

#### D, bit [9]

Process state D mask. The possible values of this bit are:

D | Meaning
--- | ---
0b0 | Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked.
0b1 | Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked.

When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.

This field resets to 1.

#### A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

A | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

This field resets to 1.

#### I, bit [7]

IRQ mask bit. The possible values of this bit are:

I | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

This field resets to 1.

#### F, bit [6]

FIQ mask bit. The possible values of this bit are:

F | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

This field resets to 1.

#### Bits [5:0]

Reserved, RES0.

## Accessing the DAIF

For details on the operation of the MSR (immediate) accessor, see MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Accesses to this register use the following encodings:

#### MRS <Xt>, DAIF

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0010 | 0b001

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && ((EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') || SCTLR_EL1.UMA == '0') then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL1 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL2 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL3 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6);

#### MSR DAIF, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0010 | 0b001

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && ((EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') || SCTLR_EL1.UMA == '0') then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL1 then PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL2 then PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL3 then PSTATE.<D,A,I,F> = X[t]<9:6>;

#### MSR DAIFSet, #<imm>

op0 | op1 | CRn | op2
--- | --- | --- | ---
0b00 | 0b011 | 0b0100 | 0b110

#### MSR DAIFClr, #<imm>

op0 | op1 | CRn | op2
--- | --- | --- | ---
0b00 | 0b011 | 0b0100 | 0b111

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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