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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCPIDR4, Peripheral Identification Register 4

The TRCPIDR4 characteristics are:

## Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

## Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR4 are RES0.

There are no configuration notes.

## Attributes

TRCPIDR4 is a 32-bit register.

## Field descriptions

The TRCPIDR4 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SIZE | DES_2

#### Bits [31:8]

Reserved, RES0.

#### SIZE, bits [7:4]

IMPLEMENTATION DEFINED.

Size of the component.

The distance from the start of the address space used by this component to the end of the component identification registers.

A value of 0b0000 means one of the following is true:

- The component uses a single 4KB block.
- The component uses an IMPLEMENTATION DEFINED number of 4KB blocks.

Any other value means the component occupies 2SIZE 4KB blocks.

Using this field to indicate the size of the component is deprecated. This field might not correctly indicate the size of the component. ARM recommends that software determine the size of the component from the Unique Component Identifier fields, and other IMPLEMENTATION DEFINED registers in the component.

This field reads as an IMPLEMENTATION DEFINED value.

#### DES_2, bits [3:0]

IMPLEMENTATION DEFINED.

Designer, JEP106 continuation code. This is the JEDEC-assigned JEP106 bank identifier for the designer of the component, minus 1. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

Note that for a component designed by ARM Limited, the JEP106 bank is 5, meaning this field has the value 0x4.

This field reads as an IMPLEMENTATION DEFINED value.

## Accessing the TRCPIDR4

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCPIDR4 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xFD0

This interface is accessible as follows:

- When !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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