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# TRCPDCR, PowerDown Control Register

The TRCPDCR characteristics are:

## Purpose

Requests the system to provide power to the trace unit.

## Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPDCR are RES0.

There are no configuration notes.

## Attributes

TRCPDCR is a 32-bit register.

## Field descriptions

The TRCPDCR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PU | RES0

#### Bits [31:4]

Reserved, RES0.

#### PU, bit [3]

Power Up Request.

PU | Meaning
--- | ---
0b0 | The system can remove power from the trace unit core power domain, or requests for power to the trace unit core power domain are implemented outside of the trace unit.
0b1 | The system must provide power to the trace unit core power domain.

This bit is RES0.

#### Bits [2:0]

Reserved, RES0.

## Accessing the TRCPDCR

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCPDCR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x310

This interface is accessible as follows:

- When !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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