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# VPIDR_EL2, Virtualization Processor ID Register

The VPIDR_EL2 characteristics are:

## Purpose

Holds the value of the Virtualization Processor ID. This is the value returned by EL1 reads of MIDR_EL1.

## Configuration

AArch64 System register VPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VPIDR[31:0] .

If EL2 is not implemented, reads of this register return the value of the MIDR_EL1, and writes to the register are ignored.

This register has no effect if EL2 is not enabled in the current Security state.

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

VPIDR_EL2 is a 64-bit register.

## Field descriptions

The VPIDR_EL2 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
Implementer | Variant | Architecture | PartNum | Revision
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:

Hex representation | ASCII representation | Implementer
--- | --- | ---
0x41 | A | Arm Limited
0x42 | B | Broadcom Corporation
0x43 | C | Cavium Inc.
0x44 | D | Digital Equipment Corporation
0x49 | I | Infineon Technologies AG
0x4D | M | Motorola or Freescale Semiconductor Inc.
0x4E | N | NVIDIA Corporation
0x50 | P | Applied Micro Circuits Corporation
0x51 | Q | Qualcomm Inc.
0x56 | V | Marvell International Ltd.
0x69 | i | Intel Corporation

Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.

This field resets to an architecturally UNKNOWN value.

#### Variant, bits [23:20]

An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

This field resets to an architecturally UNKNOWN value.

#### Architecture, bits [19:16]

The permitted values of this field are:

Architecture | Meaning
--- | ---
0b0001 | Armv4.
0b0010 | Armv4T.
0b0011 | Armv5 (obsolete).
0b0100 | Armv5T.
0b0101 | Armv5TE.
0b0110 | Armv5TEJ.
0b0111 | Armv6.
0b1111 | Architectural features are individually identified in the ID_* registers, see 'ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K12.3.3.

All other values are reserved.

This field resets to an architecturally UNKNOWN value.

#### PartNum, bits [15:4]

An IMPLEMENTATION DEFINED primary part number for the device.

On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

This field resets to an architecturally UNKNOWN value.

#### Revision, bits [3:0]

An IMPLEMENTATION DEFINED revision number for the device.

This field resets to an architecturally UNKNOWN value.

## Accessing the VPIDR_EL2

Accesses to this register use the following encodings:

#### MRS <Xt>, VPIDR_EL2

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x088]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return VPIDR_EL2; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return MIDR_EL1; else return VPIDR_EL2;

#### MSR VPIDR_EL2, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x088] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VPIDR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then //no operation else VPIDR_EL2 = X[t];

#### MRS <Xt>, MIDR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) then return VPIDR_EL2; else return MIDR_EL1; elsif PSTATE.EL == EL2 then return MIDR_EL1; elsif PSTATE.EL == EL3 then return MIDR_EL1;

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) then return VPIDR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) then return VPIDR<31:0>; else return MIDR<31:0>; elsif PSTATE.EL == EL2 then return MIDR<31:0>; elsif PSTATE.EL == EL3 then return MIDR<31:0>;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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