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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCDEVAFF, Device Affinity Register

The TRCDEVAFF characteristics are:

## Purpose

For additional information see the CoreSight Architecture Specification.

Reads the same value as the MPIDR_EL1 register for the PE this trace unit has affinity with.

## Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCDEVAFF are RES0.

There are no configuration notes.

## Attributes

TRCDEVAFF is a 64-bit register.

## Field descriptions

The TRCDEVAFF bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
MPIDR_EL1
MPIDR_EL1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### MPIDR_EL1, bits [63:0]

Read-only copy of MPIDR_EL1, as seen from the highest implemented Exception level.

## Accessing the TRCDEVAFF

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCDEVAFF can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xFA8

This interface is accessible as follows:

- When !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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