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# MPAMF_AIDR, MPAM Architecture Identification Register

The MPAMF_AIDR characteristics are:

## Purpose

The MPAMF_AIDR is a 32-bit read-only register that identifies the version of the MPAM architecture that this MSC implements.

Note: The following values are defined for bits [7:0]:

- 0x10 == MPAM architecture v1.0

## Configuration

The power domain of MPAMF_AIDR is IMPLEMENTATION DEFINED.

## Attributes

MPAMF_AIDR is a 32-bit register.

## Field descriptions

The MPAMF_AIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | ArchMajorRev | ArchMinorRev

#### Bits [31:8]

Reserved, RES0.

#### ArchMajorRev, bits [7:4]

Major revision of the MPAM architecture implemented by the MSC.

#### ArchMinorRev, bits [3:0]

Minor revision of the MPAM architecture implemented by the MSC.

## Accessing the MPAMF_AIDR

This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.

MPAMF_AIDR must be accessible from the Non-secure and Secure address maps.

MPAMF_AIDR must be shared between the Secure and Non-secure address maps.

#### MPAMF_AIDR can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_s | 0x0020 | MPAMF_AIDR_s

Access on this interface is RO.

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_ns | 0x0020 | MPAMF_AIDR_ns

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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