no old file | htmldiff from- | (new)

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCITCTRL, Integration Mode Control Register

The TRCITCTRL characteristics are:

## Purpose

A component can use TRCITCTRL to dynamically switch between functional mode and integration mode. In integration mode, topology detection is enabled. After switching to integration mode and performing integration tests or topology detection, reset the system to ensure correct behavior of CoreSight and other connected system components.

For additional information see the CoreSight Architecture Specification.

## Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCITCTRL are RES0.

There are no configuration notes.

## Attributes

TRCITCTRL is a 32-bit register.

## Field descriptions

The TRCITCTRL bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | IME

#### Bits [31:1]

Reserved, RES0.

#### IME, bit [0]

Integration Mode Enable.

IME | Meaning
--- | ---
0b0 | The component must enter functional mode.
0b1 | The component must enter integration mode, and enable support for topology detection and integration testing.

This bit is RES0 if no topology detection or integration functionality is implemented.

## Accessing the TRCITCTRL

External debugger accesses to this register are IMPLEMENTATION DEFINED when the trace unit is not in the Idle state.

#### TRCITCTRL can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xF00

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

no old file | htmldiff from- | (new)