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# MAIR_EL3, Memory Attribute Indirection Register (EL3)

The MAIR_EL3 characteristics are:

## Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL3.

## Configuration

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

MAIR_EL3 is a 64-bit register.

## Field descriptions

The MAIR_EL3 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
Attr7 | Attr6 | Attr5 | Attr4
Attr3 | Attr2 | Attr1 | Attr0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

MAIR_EL3 is permitted to be cached in a TLB.

#### Attr<n>, bits [8n+7:8n], for n = 0 to 7

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.

Attr is encoded as follows:

Attr | Meaning
--- | ---
0b0000dd00 | Device memory. See encoding of 'dd' for the type of Device memory.
0b0000ddxx, (xx != 00) | UNPREDICTABLE
0booooiiii, (oooo != 0000 and iiii != 0000) | Normal memory. See encoding of 'oooo' and 'iiii' for the type of Normal Memory.
0b11110000 | Tagged Normal Memory. Inner+Outer Write-Back Non-Transient memory, Inner+Outer Read-Allocate, Inner+Outer Write-Allocate.
0bxxxx0000, (xxxx != 0000 and xxxx != 1111) | UNPREDICTABLE

'dd' is encoded as follows:

dd | Meaning
0b00 | Device-nGnRnE memory
0b01 | Device-nGnRE memory
0b10 | Device-nGRE memory
0b11 | Device-GRE memory

'oooo' is encoded as follows:

'oooo' | Meaning
--- | ---
0b0000 | See encoding of Attr
0b00RW, RW not 0b00 | Normal memory, Outer Write-Through Transient
0b0100 | Normal memory, Outer Non-cacheable
0b01RW, RW not 0b00 | Normal memory, Outer Write-Back Transient
0b10RW | Normal memory, Outer Write-Through Non-transient
0b11RW | Normal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

'iiii' is encoded as follows:

'iiii' | Meaning
--- | ---
0b0000 | See encoding of Attr
0b00RW, RW not 0b00 | Normal memory, Inner Write-Through Transient
0b0100 | Normal memory, Inner Non-cacheable
0b01RW, RW not 0b00 | Normal memory, Inner Write-Back Transient
0b10RW | Normal memory, Inner Write-Through Non-transient
0b11RW | Normal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in 'oooo' and 'iiii' fields have the following meanings:

R or W | Meaning
--- | ---
0b0 | No Allocate
0b1 | Allocate

This field resets to an architecturally UNKNOWN value.

## Accessing the MAIR_EL3

Accesses to this register use the following encodings:

#### MRS <Xt>, MAIR_EL3

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b1010 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return MAIR_EL3;

#### MSR MAIR_EL3, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b1010 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then MAIR_EL3 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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