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# ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0

The ID_ISAR0_EL1 characteristics are:

## Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D7.1.3.

## Configuration

AArch64 System register ID_ISAR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR0[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_ISAR0_EL1 is a 64-bit register.

## Field descriptions

The ID_ISAR0_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | Divide | Debug | Coproc | CmpBranch | BitField | BitCount | Swap
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:28]

Reserved, RES0.

#### Divide, bits [27:24]

Indicates the implemented Divide instructions. Defined values are:

Divide | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds SDIV and UDIV in the T32 instruction set.
0b0010 | As for 0b0001, and adds SDIV and UDIV in the A32 instruction set.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0010.

#### Debug, bits [23:20]

Indicates the implemented Debug instructions. Defined values are:

Debug | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds BKPT.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0001.

#### Coproc, bits [19:16]

Indicates the implemented System register access instructions. Defined values are:

Coproc | Meaning
--- | ---
0b0000 | None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions.
0b0001 | Adds generic CDP, LDC, MCR, MRC, and STC.
0b0010 | As for 0b0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2.
0b0011 | As for 0b0010, and adds generic MCRR and MRRC.
0b0100 | As for 0b0011, and adds generic MCRR2 and MRRC2.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

#### CmpBranch, bits [15:12]

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set. Defined values are:

CmpBranch | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds CBNZ and CBZ.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0001.

#### BitField, bits [11:8]

Indicates the implemented BitField instructions. Defined values are:

BitField | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds BFC, BFI, SBFX, and UBFX.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0001.

#### BitCount, bits [7:4]

Indicates the implemented Bit Counting instructions. Defined values are:

BitCount | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds CLZ.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0001.

#### Swap, bits [3:0]

Indicates the implemented Swap instructions in the A32 instruction set. Defined values are:

Swap | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds SWP and SWPB.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

## Accessing the ID_ISAR0_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_ISAR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_ISAR0_EL1; elsif PSTATE.EL == EL2 then return ID_ISAR0_EL1; elsif PSTATE.EL == EL3 then return ID_ISAR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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