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# GICR_VPROPBASER, Virtual Redistributor Properties Base Address Register

The GICR_VPROPBASER characteristics are:

## Purpose

Specifies the base address of the memory that holds the virtual LPI Configuration table for the currently scheduled virtual machine.

## Configuration

RW fields in this register reset to architecturally UNKNOWN values.

This register is provided in GICv4 implementations only.

## Attributes

GICR_VPROPBASER is a 64-bit register.

## Field descriptions

The GICR_VPROPBASER bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | OuterCache | RES0 | Physical_Address
Physical_Address | Shareability | InnerCache | RES0 | IDbits
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:59]

Reserved, RES0.

#### OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table. The possible values of this field are:

OuterCache | Meaning
--- | ---
0b000 | Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.
0b001 | Normal Outer Non-cacheable.
0b010 | Normal Outer Cacheable Read-allocate, Write-through.
0b011 | Normal Outer Cacheable Read-allocate, Write-back.
0b100 | Normal Outer Cacheable Write-allocate, Write-through.
0b101 | Normal Outer Cacheable Write-allocate, Write-back.
0b110 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

#### Bits [55:52]

Reserved, RES0.

#### Physical_Address, bits [51:12]

Bits [51:12] of the physical address containing the virtual LPI Configuration table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

This field resets to an architecturally UNKNOWN value.

#### Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the LPI Configuration table. The possible values of this field are:

Shareability | Meaning
--- | ---
0b00 | Non-shareable.
0b01 | Inner Shareable.
0b10 | Outer Shareable.
0b11 | Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

#### InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table. The possible values of this field are:

InnerCache | Meaning
--- | ---
0b000 | Device-nGnRnE.
0b001 | Normal Inner Non-cacheable.
0b010 | Normal Inner Cacheable Read-allocate, Write-through.
0b011 | Normal Inner Cacheable Read-allocate, Write-back.
0b100 | Normal Inner Cacheable Write-allocate, Write-through.
0b101 | Normal Inner Cacheable Write-allocate, Write-back.
0b110 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

This field resets to an architecturally UNKNOWN value.

#### Bits [6:5]

Reserved, RES0.

#### IDbits, bits [4:0]

The number of bits of virtual LPI INTID supported, minus one.

If the value of this field is less than 0b1101, indicating that the largest INTID is less than 8192 (the smallest LPI interrupt ID), the GIC will behave as if all virtual LPIs are out of range.

This field resets to an architecturally UNKNOWN value.

## Accessing the GICR_VPROPBASER

#### GICR_VPROPBASER can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | VLPI_base | 0x0070 | GICR_VPROPBASER

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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