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# PMSFCR_EL1, Sampling Filter Control Register

The PMSFCR_EL1 characteristics are:

## Purpose

Controls sample filtering. The filter is the logical AND of the FL, FT and FE bits. For example, if FE == 1 and FT == 1 only samples including the selected operation types and the selected events will be recorded

## Configuration

This register is present only when SPE is implemented. Otherwise, direct accesses to PMSFCR_EL1 are UNDEFINED.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

PMSFCR_EL1 is a 64-bit register.

## Field descriptions

The PMSFCR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | ST | LD | B | RES0 | FL | FT | FE
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:19]

Reserved, RES0.

#### ST, bit [18]

Store filter enable

ST | Meaning
--- | ---
0b0 | Do not record store operations
0b1 | Record all store operations, including vector stores and all atomic operations

This bit is ignored by the PE when PMSFCR_EL1.FT == 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### LD, bit [17]

Load filter enable

LD | Meaning
--- | ---
0b0 | Do not record load operations
0b1 | Record all load operations, including vector loads and atomic operations that return data

This bit is ignored by the PE when PMSFCR_EL1.FT == 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### B, bit [16]

Branch filter enable

B | Meaning
--- | ---
0b0 | Do not record branch and exception return operations
0b1 | Record all branch and exception return operations

This bit is ignored by the PE when PMSFCR_EL1.FT == 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### Bits [15:3]

Reserved, RES0.

#### FL, bit [2]

Filter by latency

FL | Meaning
--- | ---
0b0 | Latency filtering disabled
0b1 | Latency filtering enabled. Samples with a total latency less than PMSLATFR_EL1.MINLAT will not be recorded

If this field is set to 1 and PMSLATFR_EL1.MINLAT is set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FL is set to 0

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### FT, bit [1]

Filter by operation type. The filter is the logical OR of the ST, LD and B bits. For example, if LD and ST are both set, both load and store operations are recorded

FT | Meaning
--- | ---
0b0 | Type filtering disabled
0b1 | Type filtering enabled. Samples not one of the selected operation types will not be recorded

If this field is set to 1 and the PMSFCR_EL1.{ST, LD, B} bits are all set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FT is set to 0

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### FE, bit [0]

Filter by event

FE | Meaning
--- | ---
0b0 | Event filtering disabled
0b1 | Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1 will not be recorded

If this field is set to 1 and PMSEVFR_EL1 is set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FE is set to 0

On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing the PMSFCR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, PMSFCR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1001 | 0b1001 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMSFCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return PMSFCR_EL1; elsif PSTATE.EL == EL3 then return PMSFCR_EL1;

#### MSR PMSFCR_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1001 | 0b1001 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSFCR_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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