AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# System Register index by instruction and encoding

Below are indexes for registers and operations accessed in the following ways:

For AArch32

- MCR/MRC
- MCRR/MRRC
- MRS/MSR
- VMRS/VMSR

For AArch64

- AT
- CFP
- CPP
- DC
- DVP
- IC
- MRS/MSR
- TLBI

## Registers and operations in AArch32

## Accessed using MCR/MRC:

Register selectors | Name | Description
--- | --- | ---
coproc | opc1 | CRn | CRm | opc2
0b1110 | 0b000 | 0b0000 | 0b0000 | 0b000 | DBGDIDR | Debug ID Register
0b1110 | 0b000 | 0b0000 | 0b0000 | 0b010 | DBGDTRRXext | Debug OS Lock Data Transfer Register, Receive, External View
0b1110 | 0b000 | 0b0000 | 0b0001 | 0b000 | DBGDSCRint | Debug Status and Control Register, Internal View
0b1110 | 0b000 | 0b0000 | 0b0010 | 0b000 | DBGDCCINT | DCC Interrupt Enable Register
0b1110 | 0b000 | 0b0000 | 0b0010 | 0b010 | DBGDSCRext | Debug Status and Control Register, External View
0b1110 | 0b000 | 0b0000 | 0b0011 | 0b010 | DBGDTRTXext | Debug OS Lock Data Transfer Register, Transmit
0b1110 | 0b000 | 0b0000 | 0b0101 | 0b000 | DBGDTRRXint | Debug Data Transfer Register, Receive
0b1110 | 0b000 | 0b0000 | 0b0101 | 0b000 | DBGDTRTXint | Debug Data Transfer Register, Transmit
0b1110 | 0b000 | 0b0000 | 0b0110 | 0b000 | DBGWFAR | Debug Watchpoint Fault Address Register
0b1110 | 0b000 | 0b0000 | 0b0110 | 0b010 | DBGOSECCR | Debug OS Lock Exception Catch Control Register
0b1110 | 0b000 | 0b0000 | 0b0111 | 0b000 | DBGVCR | Debug Vector Catch Register
0b1110 | 0b000 | 0b0000 | 0bnnnn | 0b100 | DBGBVR<n> | Debug Breakpoint Value Registers
0b1110 | 0b000 | 0b0000 | 0bnnnn | 0b101 | DBGBCR<n> | Debug Breakpoint Control Registers
0b1110 | 0b000 | 0b0000 | 0bnnnn | 0b110 | DBGWVR<n> | Debug Watchpoint Value Registers
0b1110 | 0b000 | 0b0000 | 0bnnnn | 0b111 | DBGWCR<n> | Debug Watchpoint Control Registers
0b1110 | 0b000 | 0b0001 | 0b0000 | 0b000 | DBGDRAR | Debug ROM Address Register
0b1110 | 0b000 | 0b0001 | 0b0000 | 0b100 | DBGOSLAR | Debug OS Lock Access Register
0b1110 | 0b000 | 0b0001 | 0b0001 | 0b100 | DBGOSLSR | Debug OS Lock Status Register
0b1110 | 0b000 | 0b0001 | 0b0011 | 0b100 | DBGOSDLR | Debug OS Double Lock Register
0b1110 | 0b000 | 0b0001 | 0b0100 | 0b100 | DBGPRCR | Debug Power Control Register
0b1110 | 0b000 | 0b0001 | 0bnnnn | 0b001 | DBGBXVR<n> | Debug Breakpoint Extended Value Registers
0b1110 | 0b000 | 0b0010 | 0b0000 | 0b000 | DBGDSAR | Debug Self Address Register
0b1110 | 0b000 | 0b0111 | 0b0000 | 0b111 | DBGDEVID2 | Debug Device ID register 2
0b1110 | 0b000 | 0b0111 | 0b0001 | 0b111 | DBGDEVID1 | Debug Device ID register 1
0b1110 | 0b000 | 0b0111 | 0b0010 | 0b111 | DBGDEVID | Debug Device ID register 0
0b1110 | 0b000 | 0b0111 | 0b1000 | 0b110 | DBGCLAIMSET | Debug Claim Tag Set register
0b1110 | 0b000 | 0b0111 | 0b1001 | 0b110 | DBGCLAIMCLR | Debug Claim Tag Clear register
0b1110 | 0b000 | 0b0111 | 0b1110 | 0b110 | DBGAUTHSTATUS | Debug Authentication Status register
0b1110 | 0b111 | 0b0000 | 0b0000 | 0b000 | JIDR | Jazelle ID Register
0b1110 | 0b111 | 0b0001 | 0b0000 | 0b000 | JOSCR | Jazelle OS Control Register
0b1110 | 0b111 | 0b0010 | 0b0000 | 0b000 | JMCR | Jazelle Main Configuration Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b000 | MIDR | Main ID Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b001 | CTR | Cache Type Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b010 | TCMTR | TCM Type Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b011 | TLBTR | TLB Type Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b101 | MPIDR | Multiprocessor Affinity Register
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b110 | REVIDR | Revision ID Register
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b000 | ID_PFR0 | Processor Feature Register 0
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b001 | ID_PFR1 | Processor Feature Register 1
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b010 | ID_DFR0 | Debug Feature Register 0
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b011 | ID_AFR0 | Auxiliary Feature Register 0
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b100 | ID_MMFR0 | Memory Model Feature Register 0
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b101 | ID_MMFR1 | Memory Model Feature Register 1
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b110 | ID_MMFR2 | Memory Model Feature Register 2
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b111 | ID_MMFR3 | Memory Model Feature Register 3
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b000 | ID_ISAR0 | Instruction Set Attribute Register 0
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b001 | ID_ISAR1 | Instruction Set Attribute Register 1
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b010 | ID_ISAR2 | Instruction Set Attribute Register 2
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b011 | ID_ISAR3 | Instruction Set Attribute Register 3
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b100 | ID_ISAR4 | Instruction Set Attribute Register 4
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b101 | ID_ISAR5 | Instruction Set Attribute Register 5
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b110 | ID_MMFR4 | Memory Model Feature Register 4
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b111 | ID_ISAR6 | Instruction Set Attribute Register 6
0b1111 | 0b000 | 0b0000 | 0b0011 | 0b100 | ID_PFR2 | Processor Feature Register 2
0b1111 | 0b000 | 0b0001 | 0b0000 | 0b000 | SCTLR | System Control Register
0b1111 | 0b000 | 0b0001 | 0b0000 | 0b001 | ACTLR | Auxiliary Control Register
0b1111 | 0b000 | 0b0001 | 0b0000 | 0b010 | CPACR | Architectural Feature Access Control Register
0b1111 | 0b000 | 0b0001 | 0b0000 | 0b011 | ACTLR2 | Auxiliary Control Register 2
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b000 | SCR | Secure Configuration Register
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b001 | SDER | Secure Debug Enable Register
0b1111 | 0b000 | 0b0001 | 0b0001 | 0b010 | NSACR | Non-Secure Access Control Register
0b1111 | 0b000 | 0b0001 | 0b0010 | 0b001 | TRFCR | Trace Filter Control Register
0b1111 | 0b000 | 0b0001 | 0b0011 | 0b001 | SDCR | Secure Debug Control Register
0b1111 | 0b000 | 0b0010 | 0b0000 | 0b000 | TTBR0 | Translation Table Base Register 0
0b1111 | 0b000 | 0b0010 | 0b0000 | 0b001 | TTBR1 | Translation Table Base Register 1
0b1111 | 0b000 | 0b0010 | 0b0000 | 0b010 | TTBCR | Translation Table Base Control Register
0b1111 | 0b000 | 0b0010 | 0b0000 | 0b011 | TTBCR2 | Translation Table Base Control Register 2
0b1111 | 0b000 | 0b0011 | 0b0000 | 0b000 | DACR | Domain Access Control Register
0b1111 | 0b000 | 0b0100 | 0b0110 | 0b000 | ICC_PMR | Interrupt Controller Interrupt Priority Mask Register
0b1111 | 0b000 | 0b0101 | 0b0000 | 0b000 | DFSR | Data Fault Status Register
0b1111 | 0b000 | 0b0101 | 0b0000 | 0b001 | IFSR | Instruction Fault Status Register
0b1111 | 0b000 | 0b0101 | 0b0001 | 0b000 | ADFSR | Auxiliary Data Fault Status Register
0b1111 | 0b000 | 0b0101 | 0b0001 | 0b001 | AIFSR | Auxiliary Instruction Fault Status Register
0b1111 | 0b000 | 0b0101 | 0b0011 | 0b000 | ERRIDR | Error Record ID Register
0b1111 | 0b000 | 0b0101 | 0b0011 | 0b001 | ERRSELR | Error Record Select Register
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b000 | ERXFR | Selected Error Record Feature Register
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b001 | ERXCTLR | Selected Error Record Control Register
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b010 | ERXSTATUS | Selected Error Record Primary Status Register
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b011 | ERXADDR | Selected Error Record Address Register
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b100 | ERXFR2 | Selected Error Record Feature Register 2
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b101 | ERXCTLR2 | Selected Error Record Control Register 2
0b1111 | 0b000 | 0b0101 | 0b0100 | 0b111 | ERXADDR2 | Selected Error Record Address Register 2
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b000 | ERXMISC0 | Selected Error Record Miscellaneous Register 0
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b001 | ERXMISC1 | Selected Error Record Miscellaneous Register 1
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b010 | ERXMISC4 | Selected Error Record Miscellaneous Register 4
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b011 | ERXMISC5 | Selected Error Record Miscellaneous Register 5
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b100 | ERXMISC2 | Selected Error Record Miscellaneous Register 2
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b101 | ERXMISC3 | Selected Error Record Miscellaneous Register 3
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b110 | ERXMISC6 | Selected Error Record Miscellaneous Register 6
0b1111 | 0b000 | 0b0101 | 0b0101 | 0b111 | ERXMISC7 | Selected Error Record Miscellaneous Register 7
0b1111 | 0b000 | 0b0110 | 0b0000 | 0b000 | DFAR | Data Fault Address Register
0b1111 | 0b000 | 0b0110 | 0b0000 | 0b010 | IFAR | Instruction Fault Address Register
0b1111 | 0b000 | 0b0111 | 0b0001 | 0b000 | ICIALLUIS | Instruction Cache Invalidate All to PoU, Inner Shareable
0b1111 | 0b000 | 0b0111 | 0b0001 | 0b110 | BPIALLIS | Branch Predictor Invalidate All, Inner Shareable
0b1111 | 0b000 | 0b0111 | 0b0011 | 0b100 | CFPRCTX | Control Flow Prediction Restriction by Context
0b1111 | 0b000 | 0b0111 | 0b0011 | 0b101 | DVPRCTX | Data Value Prediction Restriction by Context
0b1111 | 0b000 | 0b0111 | 0b0011 | 0b111 | CPPRCTX | Cache Prefetch Prediction Restriction by Context
0b1111 | 0b000 | 0b0111 | 0b0100 | 0b000 | PAR | Physical Address Register
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b000 | ICIALLU | Instruction Cache Invalidate All to PoU
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b001 | ICIMVAU | Instruction Cache line Invalidate by VA to PoU
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b100 | CP15ISB | Instruction Synchronization Barrier System instruction
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b110 | BPIALL | Branch Predictor Invalidate All
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b111 | BPIMVA | Branch Predictor Invalidate by VA
0b1111 | 0b000 | 0b0111 | 0b0110 | 0b001 | DCIMVAC | Data Cache line Invalidate by VA to PoC
0b1111 | 0b000 | 0b0111 | 0b0110 | 0b010 | DCISW | Data Cache line Invalidate by Set/Way
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b000 | ATS1CPR | Address Translate Stage 1 Current state PL1 Read
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b001 | ATS1CPW | Address Translate Stage 1 Current state PL1 Write
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b010 | ATS1CUR | Address Translate Stage 1 Current state Unprivileged Read
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b011 | ATS1CUW | Address Translate Stage 1 Current state Unprivileged Write
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b100 | ATS12NSOPR | Address Translate Stages 1 and 2 Non-secure Only PL1 Read
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b101 | ATS12NSOPW | Address Translate Stages 1 and 2 Non-secure Only PL1 Write
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b110 | ATS12NSOUR | Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b111 | ATS12NSOUW | Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
0b1111 | 0b000 | 0b0111 | 0b1001 | 0b000 | ATS1CPRP | Address Translate Stage 1 Current state PL1 Read PAN
0b1111 | 0b000 | 0b0111 | 0b1001 | 0b001 | ATS1CPWP | Address Translate Stage 1 Current state PL1 Write PAN
0b1111 | 0b000 | 0b0111 | 0b1010 | 0b001 | DCCMVAC | Data Cache line Clean by VA to PoC
0b1111 | 0b000 | 0b0111 | 0b1010 | 0b010 | DCCSW | Data Cache line Clean by Set/Way
0b1111 | 0b000 | 0b0111 | 0b1010 | 0b100 | CP15DSB | Data Synchronization Barrier System instruction
0b1111 | 0b000 | 0b0111 | 0b1010 | 0b101 | CP15DMB | Data Memory Barrier System instruction
0b1111 | 0b000 | 0b0111 | 0b1011 | 0b001 | DCCMVAU | Data Cache line Clean by VA to PoU
0b1111 | 0b000 | 0b0111 | 0b1110 | 0b001 | DCCIMVAC | Data Cache line Clean and Invalidate by VA to PoC
0b1111 | 0b000 | 0b0111 | 0b1110 | 0b010 | DCCISW | Data Cache line Clean and Invalidate by Set/Way
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b000 | TLBIALLIS | TLB Invalidate All, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b001 | TLBIMVAIS | TLB Invalidate by VA, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b010 | TLBIASIDIS | TLB Invalidate by ASID match, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b011 | TLBIMVAAIS | TLB Invalidate by VA, All ASID, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b101 | TLBIMVALIS | TLB Invalidate by VA, Last level, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b111 | TLBIMVAALIS | TLB Invalidate by VA, All ASID, Last level, Inner Shareable
0b1111 | 0b000 | 0b1000 | 0b0101 | 0b000 | ITLBIALL | Instruction TLB Invalidate All
0b1111 | 0b000 | 0b1000 | 0b0101 | 0b001 | ITLBIMVA | Instruction TLB Invalidate by VA
0b1111 | 0b000 | 0b1000 | 0b0101 | 0b010 | ITLBIASID | Instruction TLB Invalidate by ASID match
0b1111 | 0b000 | 0b1000 | 0b0110 | 0b000 | DTLBIALL | Data TLB Invalidate All
0b1111 | 0b000 | 0b1000 | 0b0110 | 0b001 | DTLBIMVA | Data TLB Invalidate by VA
0b1111 | 0b000 | 0b1000 | 0b0110 | 0b010 | DTLBIASID | Data TLB Invalidate by ASID match
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b000 | TLBIALL | TLB Invalidate All
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b001 | TLBIMVA | TLB Invalidate by VA
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b010 | TLBIASID | TLB Invalidate by ASID match
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b011 | TLBIMVAA | TLB Invalidate by VA, All ASID
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b101 | TLBIMVAL | TLB Invalidate by VA, Last level
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b111 | TLBIMVAAL | TLB Invalidate by VA, All ASID, Last level
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b000 | PMCR | Performance Monitors Control Register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b001 | PMCNTENSET | Performance Monitors Count Enable Set register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b010 | PMCNTENCLR | Performance Monitors Count Enable Clear register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b011 | PMOVSR | Performance Monitors Overflow Flag Status Register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b100 | PMSWINC | Performance Monitors Software Increment register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b101 | PMSELR | Performance Monitors Event Counter Selection Register
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b110 | PMCEID0 | Performance Monitors Common Event Identification register 0
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b111 | PMCEID1 | Performance Monitors Common Event Identification register 1
0b1111 | 0b000 | 0b1001 | 0b1101 | 0b000 | PMCCNTR | Performance Monitors Cycle Count Register
0b1111 | 0b000 | 0b1001 | 0b1101 | 0b001 | PMXEVTYPER | Performance Monitors Selected Event Type Register
0b1111 | 0b000 | 0b1001 | 0b1101 | 0b010 | PMXEVCNTR | Performance Monitors Selected Event Count Register
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b000 | PMUSERENR | Performance Monitors User Enable Register
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b001 | PMINTENSET | Performance Monitors Interrupt Enable Set register
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b010 | PMINTENCLR | Performance Monitors Interrupt Enable Clear register
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b011 | PMOVSSET | Performance Monitors Overflow Flag Status Set register
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b100 | PMCEID2 | Performance Monitors Common Event Identification register 2
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b101 | PMCEID3 | Performance Monitors Common Event Identification register 3
0b1111 | 0b000 | 0b1001 | 0b1110 | 0b110 | PMMIR | Performance Monitors Machine Identification Register
0b1111 | 0b000 | 0b1010 | 0b0011 | 0b000 | AMAIR0 | Auxiliary Memory Attribute Indirection Register 0
0b1111 | 0b000 | 0b1010 | 0b0011 | 0b001 | AMAIR1 | Auxiliary Memory Attribute Indirection Register 1
0b1111 | 0b000 | 0b1100 | 0b0000 | 0b000 | VBAR | Vector Base Address Register
0b1111 | 0b000 | 0b1100 | 0b0000 | 0b010 | RMR | Reset Management Register
0b1111 | 0b000 | 0b1100 | 0b0001 | 0b000 | ISR | Interrupt Status Register
0b1111 | 0b000 | 0b1100 | 0b0001 | 0b001 | DISR | Deferred Interrupt Status Register
0b1111 | 0b000 | 0b1100 | 0b1000 | 0b000 | ICC_IAR0 | Interrupt Controller Interrupt Acknowledge Register 0
0b1111 | 0b000 | 0b1100 | 0b1000 | 0b001 | ICC_EOIR0 | Interrupt Controller End Of Interrupt Register 0
0b1111 | 0b000 | 0b1100 | 0b1000 | 0b010 | ICC_HPPIR0 | Interrupt Controller Highest Priority Pending Interrupt Register 0
0b1111 | 0b000 | 0b1100 | 0b1000 | 0b011 | ICC_BPR0 | Interrupt Controller Binary Point Register 0
0b1111 | 0b000 | 0b1100 | 0b1000 | 0b1[n:1:0] | ICC_AP0R<n> | Interrupt Controller Active Priorities Group 0 Registers
0b1111 | 0b000 | 0b1100 | 0b1001 | 0b0[n:1:0] | ICC_AP1R<n> | Interrupt Controller Active Priorities Group 1 Registers
0b1111 | 0b000 | 0b1100 | 0b1011 | 0b001 | ICC_DIR | Interrupt Controller Deactivate Interrupt Register
0b1111 | 0b000 | 0b1100 | 0b1011 | 0b011 | ICC_RPR | Interrupt Controller Running Priority Register
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b000 | ICC_IAR1 | Interrupt Controller Interrupt Acknowledge Register 1
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b001 | ICC_EOIR1 | Interrupt Controller End Of Interrupt Register 1
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b010 | ICC_HPPIR1 | Interrupt Controller Highest Priority Pending Interrupt Register 1
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b011 | ICC_BPR1 | Interrupt Controller Binary Point Register 1
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b100 | ICC_CTLR | Interrupt Controller Control Register
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b101 | ICC_SRE | Interrupt Controller System Register Enable register
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b110 | ICC_IGRPEN0 | Interrupt Controller Interrupt Group 0 Enable register
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b111 | ICC_IGRPEN1 | Interrupt Controller Interrupt Group 1 Enable register
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b000 | FCSEIDR | FCSE Process ID register
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b001 | CONTEXTIDR | Context ID Register
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b010 | TPIDRURW | PL0 Read/Write Software Thread ID Register
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b011 | TPIDRURO | PL0 Read-Only Software Thread ID Register
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b100 | TPIDRPRW | PL1 Software Thread ID Register
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b000 | AMCR | Activity Monitors Control Register
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b001 | AMCFGR | Activity Monitors Configuration Register
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b010 | AMCGCR | Activity Monitors Counter Group Configuration Register
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b011 | AMUSERENR | Activity Monitors User Enable Register
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b100 | AMCNTENCLR0 | Activity Monitors Count Enable Clear Register 0
0b1111 | 0b000 | 0b1101 | 0b0010 | 0b101 | AMCNTENSET0 | Activity Monitors Count Enable Set Register 0
0b1111 | 0b000 | 0b1101 | 0b0011 | 0b000 | AMCNTENCLR1 | Activity Monitors Count Enable Clear Register 1
0b1111 | 0b000 | 0b1101 | 0b0011 | 0b001 | AMCNTENSET1 | Activity Monitors Count Enable Set Register 1
0b1111 | 0b000 | 0b1101 | 0b011[n:3] | 0b[n:2:0] | AMEVTYPER0<n> | Activity Monitors Event Type Registers 0
0b1111 | 0b000 | 0b1101 | 0b111[n:3] | 0b[n:2:0] | AMEVTYPER1<n> | Activity Monitors Event Type Registers 1
0b1111 | 0b000 | 0b1110 | 0b0000 | 0b000 | CNTFRQ | Counter-timer Frequency register
0b1111 | 0b000 | 0b1110 | 0b0001 | 0b000 | CNTKCTL | Counter-timer Kernel Control register
0b1111 | 0b000 | 0b1110 | 0b0010 | 0b000 | CNTP_TVAL | Counter-timer Physical Timer TimerValue register
0b1111 | 0b000 | 0b1110 | 0b0010 | 0b001 | CNTP_CTL | Counter-timer Physical Timer Control register
0b1111 | 0b000 | 0b1110 | 0b0011 | 0b000 | CNTV_TVAL | Counter-timer Virtual Timer TimerValue register
0b1111 | 0b000 | 0b1110 | 0b0011 | 0b001 | CNTV_CTL | Counter-timer Virtual Timer Control register
0b1111 | 0b000 | 0b1110 | 0b10[n:4:3] | 0b[n:2:0] | PMEVCNTR<n> | Performance Monitors Event Count Registers
0b1111 | 0b000 | 0b1110 | 0b1111 | 0b111 | PMCCFILTR | Performance Monitors Cycle Count Filter Register
0b1111 | 0b000 | 0b1110 | 0b11[n:4:3] | 0b[n:2:0] | PMEVTYPER<n> | Performance Monitors Event Type Registers
0b1111 | 0b001 | 0b0000 | 0b0000 | 0b000 | CCSIDR | Current Cache Size ID Register
0b1111 | 0b001 | 0b0000 | 0b0000 | 0b001 | CLIDR | Cache Level ID Register
0b1111 | 0b001 | 0b0000 | 0b0000 | 0b010 | CCSIDR2 | Current Cache Size ID Register 2
0b1111 | 0b001 | 0b0000 | 0b0000 | 0b111 | AIDR | Auxiliary ID Register
0b1111 | 0b010 | 0b0000 | 0b0000 | 0b000 | CSSELR | Cache Size Selection Register
0b1111 | 0b011 | 0b0100 | 0b0101 | 0b000 | DSPSR | Debug Saved Program Status Register
0b1111 | 0b011 | 0b0100 | 0b0101 | 0b001 | DLR | Debug Link Register
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b000 | VPIDR | Virtualization Processor ID Register
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b101 | VMPIDR | Virtualization Multiprocessor ID Register
0b1111 | 0b100 | 0b0001 | 0b0000 | 0b000 | HSCTLR | Hyp System Control Register
0b1111 | 0b100 | 0b0001 | 0b0000 | 0b001 | HACTLR | Hyp Auxiliary Control Register
0b1111 | 0b100 | 0b0001 | 0b0000 | 0b011 | HACTLR2 | Hyp Auxiliary Control Register 2
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b000 | HCR | Hyp Configuration Register
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b001 | HDCR | Hyp Debug Control Register
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b010 | HCPTR | Hyp Architectural Feature Trap Register
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b011 | HSTR | Hyp System Trap Register
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b100 | HCR2 | Hyp Configuration Register 2
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b111 | HACR | Hyp Auxiliary Configuration Register
0b1111 | 0b100 | 0b0001 | 0b0010 | 0b001 | HTRFCR | Hyp Trace Filter Control Register
0b1111 | 0b100 | 0b0010 | 0b0000 | 0b010 | HTCR | Hyp Translation Control Register
0b1111 | 0b100 | 0b0010 | 0b0001 | 0b010 | VTCR | Virtualization Translation Control Register
0b1111 | 0b100 | 0b0101 | 0b0001 | 0b000 | HADFSR | Hyp Auxiliary Data Fault Status Register
0b1111 | 0b100 | 0b0101 | 0b0001 | 0b001 | HAIFSR | Hyp Auxiliary Instruction Fault Status Register
0b1111 | 0b100 | 0b0101 | 0b0010 | 0b000 | HSR | Hyp Syndrome Register
0b1111 | 0b100 | 0b0101 | 0b0010 | 0b011 | VDFSR | Virtual SError Exception Syndrome Register
0b1111 | 0b100 | 0b0110 | 0b0000 | 0b000 | HDFAR | Hyp Data Fault Address Register
0b1111 | 0b100 | 0b0110 | 0b0000 | 0b010 | HIFAR | Hyp Instruction Fault Address Register
0b1111 | 0b100 | 0b0110 | 0b0000 | 0b100 | HPFAR | Hyp IPA Fault Address Register
0b1111 | 0b100 | 0b0111 | 0b1000 | 0b000 | ATS1HR | Address Translate Stage 1 Hyp mode Read
0b1111 | 0b100 | 0b0111 | 0b1000 | 0b001 | ATS1HW | Address Translate Stage 1 Hyp mode Write
0b1111 | 0b100 | 0b1000 | 0b0000 | 0b001 | TLBIIPAS2IS | TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0000 | 0b101 | TLBIIPAS2LIS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0011 | 0b000 | TLBIALLHIS | TLB Invalidate All, Hyp mode, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0011 | 0b001 | TLBIMVAHIS | TLB Invalidate by VA, Hyp mode, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0011 | 0b100 | TLBIALLNSNHIS | TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0011 | 0b101 | TLBIMVALHIS | TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
0b1111 | 0b100 | 0b1000 | 0b0100 | 0b001 | TLBIIPAS2 | TLB Invalidate by Intermediate Physical Address, Stage 2
0b1111 | 0b100 | 0b1000 | 0b0100 | 0b101 | TLBIIPAS2L | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level
0b1111 | 0b100 | 0b1000 | 0b0111 | 0b000 | TLBIALLH | TLB Invalidate All, Hyp mode
0b1111 | 0b100 | 0b1000 | 0b0111 | 0b001 | TLBIMVAH | TLB Invalidate by VA, Hyp mode
0b1111 | 0b100 | 0b1000 | 0b0111 | 0b100 | TLBIALLNSNH | TLB Invalidate All, Non-Secure Non-Hyp
0b1111 | 0b100 | 0b1000 | 0b0111 | 0b101 | TLBIMVALH | TLB Invalidate by VA, Last level, Hyp mode
0b1111 | 0b100 | 0b1010 | 0b0010 | 0b000 | HMAIR0 | Hyp Memory Attribute Indirection Register 0
0b1111 | 0b100 | 0b1010 | 0b0010 | 0b001 | HMAIR1 | Hyp Memory Attribute Indirection Register 1
0b1111 | 0b100 | 0b1010 | 0b0011 | 0b000 | HAMAIR0 | Hyp Auxiliary Memory Attribute Indirection Register 0
0b1111 | 0b100 | 0b1010 | 0b0011 | 0b001 | HAMAIR1 | Hyp Auxiliary Memory Attribute Indirection Register 1
0b1111 | 0b100 | 0b1100 | 0b0000 | 0b000 | HVBAR | Hyp Vector Base Address Register
0b1111 | 0b100 | 0b1100 | 0b0000 | 0b010 | HRMR | Hyp Reset Management Register
0b1111 | 0b100 | 0b1100 | 0b0001 | 0b001 | VDISR | Virtual Deferred Interrupt Status Register
0b1111 | 0b100 | 0b1100 | 0b1000 | 0b0[n:1:0] | ICH_AP0R<n> | Interrupt Controller Hyp Active Priorities Group 0 Registers
0b1111 | 0b100 | 0b1100 | 0b1001 | 0b0[n:1:0] | ICH_AP1R<n> | Interrupt Controller Hyp Active Priorities Group 1 Registers
0b1111 | 0b100 | 0b1100 | 0b1001 | 0b101 | ICC_HSRE | Interrupt Controller Hyp System Register Enable register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b000 | ICH_HCR | Interrupt Controller Hyp Control Register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b001 | ICH_VTR | Interrupt Controller VGIC Type Register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b010 | ICH_MISR | Interrupt Controller Maintenance Interrupt State Register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b011 | ICH_EISR | Interrupt Controller End of Interrupt Status Register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b101 | ICH_ELRSR | Interrupt Controller Empty List Register Status Register
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b111 | ICH_VMCR | Interrupt Controller Virtual Machine Control Register
0b1111 | 0b100 | 0b1100 | 0b110[n:3] | 0b[n:2:0] | ICH_LR<n> | Interrupt Controller List Registers
0b1111 | 0b100 | 0b1100 | 0b111[n:3] | 0b[n:2:0] | ICH_LRC<n> | Interrupt Controller List Registers
0b1111 | 0b100 | 0b1101 | 0b0000 | 0b010 | HTPIDR | Hyp Software Thread ID Register
0b1111 | 0b100 | 0b1110 | 0b0001 | 0b000 | CNTHCTL | Counter-timer Hyp Control register
0b1111 | 0b100 | 0b1110 | 0b0010 | 0b000 | CNTHP_TVAL | Counter-timer Hyp Physical Timer TimerValue register
0b1111 | 0b100 | 0b1110 | 0b0010 | 0b001 | CNTHP_CTL | Counter-timer Hyp Physical Timer Control register
0b1111 | 0b110 | 0b1100 | 0b1100 | 0b100 | ICC_MCTLR | Interrupt Controller Monitor Control Register
0b1111 | 0b110 | 0b1100 | 0b1100 | 0b101 | ICC_MSRE | Interrupt Controller Monitor System Register Enable register
0b1111 | 0b110 | 0b1100 | 0b1100 | 0b111 | ICC_MGRPEN1 | Interrupt Controller Monitor Interrupt Group 1 Enable register

## Accessed using MCRR/MRRC:

Register selectors | Name | Description
--- | --- | ---
coproc | CRm | opc1
0b1110 | 0b0001 | 0b0000 | DBGDRAR | Debug ROM Address Register
0b1110 | 0b0010 | 0b0000 | DBGDSAR | Debug Self Address Register
0b1111 | 0b000[n:3] | 0b0[n:2:0] | AMEVCNTR0<n> | Activity Monitors Event Counter Registers 0
0b1111 | 0b0010 | 0b0000 | TTBR0 | Translation Table Base Register 0
0b1111 | 0b0010 | 0b0001 | TTBR1 | Translation Table Base Register 1
0b1111 | 0b0010 | 0b0100 | HTTBR | Hyp Translation Table Base Register
0b1111 | 0b0010 | 0b0110 | VTTBR | Virtualization Translation Table Base Register
0b1111 | 0b010[n:3] | 0b0[n:2:0] | AMEVCNTR1<n> | Activity Monitors Event Counter Registers 1
0b1111 | 0b0111 | 0b0000 | PAR | Physical Address Register
0b1111 | 0b1001 | 0b0000 | PMCCNTR | Performance Monitors Cycle Count Register
0b1111 | 0b1100 | 0b0000 | ICC_SGI1R | Interrupt Controller Software Generated Interrupt Group 1 Register
0b1111 | 0b1100 | 0b0001 | ICC_ASGI1R | Interrupt Controller Alias Software Generated Interrupt Group 1 Register
0b1111 | 0b1100 | 0b0010 | ICC_SGI0R | Interrupt Controller Software Generated Interrupt Group 0 Register
0b1111 | 0b1110 | 0b0000 | CNTPCT | Counter-timer Physical Count register
0b1111 | 0b1110 | 0b0001 | CNTVCT | Counter-timer Virtual Count register
0b1111 | 0b1110 | 0b0010 | CNTP_CVAL | Counter-timer Physical Timer CompareValue register
0b1111 | 0b1110 | 0b0011 | CNTV_CVAL | Counter-timer Virtual Timer CompareValue register
0b1111 | 0b1110 | 0b0100 | CNTVOFF | Counter-timer Virtual Offset register
0b1111 | 0b1110 | 0b0110 | CNTHP_CVAL | Counter-timer Hyp Physical CompareValue register

## Accessed using MRS/MSR:

Register selectors | Name | Description
--- | --- | ---
R | M | M1
0b0 | 0b1 | 0b1110 | ELR_hyp | Exception Link Register (Hyp mode)
0b1 | 0b0 | 0b1110 | SPSR_fiq | Saved Program Status Register (FIQ mode)
0b1 | 0b1 | 0b0000 | SPSR_irq | Saved Program Status Register (IRQ mode)
0b1 | 0b1 | 0b0010 | SPSR_svc | Saved Program Status Register (Supervisor mode)
0b1 | 0b1 | 0b0100 | SPSR_abt | Saved Program Status Register (Abort mode)
0b1 | 0b1 | 0b0110 | SPSR_und | Saved Program Status Register (Undefined mode)
0b1 | 0b1 | 0b1100 | SPSR_mon | Saved Program Status Register (Monitor mode)
0b1 | 0b1 | 0b1110 | SPSR_hyp | Saved Program Status Register (Hyp mode)

## Accessed using VMRS/VMSR:

Register selectors | Name | Description
--- | --- | ---
reg
0b0000 | FPSID | Floating-Point System ID register
0b0001 | FPSCR | Floating-Point Status and Control Register
0b0101 | MVFR2 | Media and VFP Feature Register 2
0b0110 | MVFR1 | Media and VFP Feature Register 1
0b0111 | MVFR0 | Media and VFP Feature Register 0
0b1000 | FPEXC | Floating-Point Exception Control register

## Registers and operations in AArch64

## Accessed using AT:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b01 | 0b000 | 0b0111 | 0b1000 | 0b000 | AT S1E1R | Address Translate Stage 1 EL1 Read
0b01 | 0b000 | 0b0111 | 0b1000 | 0b001 | AT S1E1W | Address Translate Stage 1 EL1 Write
0b01 | 0b000 | 0b0111 | 0b1000 | 0b010 | AT S1E0R | Address Translate Stage 1 EL0 Read
0b01 | 0b000 | 0b0111 | 0b1000 | 0b011 | AT S1E0W | Address Translate Stage 1 EL0 Write
0b01 | 0b000 | 0b0111 | 0b1001 | 0b000 | AT S1E1RP | Address Translate Stage 1 EL1 Read PAN
0b01 | 0b000 | 0b0111 | 0b1001 | 0b001 | AT S1E1WP | Address Translate Stage 1 EL1 Write PAN
0b01 | 0b100 | 0b0111 | 0b1000 | 0b000 | AT S1E2R | Address Translate Stage 1 EL2 Read
0b01 | 0b100 | 0b0111 | 0b1000 | 0b001 | AT S1E2W | Address Translate Stage 1 EL2 Write
0b01 | 0b100 | 0b0111 | 0b1000 | 0b100 | AT S12E1R | Address Translate Stages 1 and 2 EL1 Read
0b01 | 0b100 | 0b0111 | 0b1000 | 0b101 | AT S12E1W | Address Translate Stages 1 and 2 EL1 Write
0b01 | 0b100 | 0b0111 | 0b1000 | 0b110 | AT S12E0R | Address Translate Stages 1 and 2 EL0 Read
0b01 | 0b100 | 0b0111 | 0b1000 | 0b111 | AT S12E0W | Address Translate Stages 1 and 2 EL0 Write
0b01 | 0b110 | 0b0111 | 0b1000 | 0b000 | AT S1E3R | Address Translate Stage 1 EL3 Read
0b01 | 0b110 | 0b0111 | 0b1000 | 0b001 | AT S1E3W | Address Translate Stage 1 EL3 Write

## Accessed using CFP:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b01 | 0b011 | 0b0111 | 0b0011 | 0b100 | CFP RCTX | Control Flow Prediction Restriction by Context

## Accessed using CPP:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b01 | 0b011 | 0b0111 | 0b0011 | 0b111 | CPP RCTX | Cache Prefetch Prediction Restriction by Context

## Accessed using DC:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b01 | 0b000 | 0b0111 | 0b0110 | 0b001 | DC IVAC | Data or unified Cache line Invalidate by VA to PoC
0b01 | 0b000 | 0b0111 | 0b0110 | 0b010 | DC ISW | Data or unified Cache line Invalidate by Set/Way
0b01 | 0b000 | 0b0111 | 0b0110 | 0b011 | DC IGVAC | Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC
0b01 | 0b000 | 0b0111 | 0b0110 | 0b100 | DC IGSW | Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way
0b01 | 0b000 | 0b0111 | 0b0110 | 0b101 | DC IGDVAC | Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC
0b01 | 0b000 | 0b0111 | 0b0110 | 0b110 | DC IGDSW | Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way
0b01 | 0b000 | 0b0111 | 0b1010 | 0b010 | DC CSW | Data or unified Cache line Clean by Set/Way
0b01 | 0b000 | 0b0111 | 0b1010 | 0b100 | DC CGSW | Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way
0b01 | 0b000 | 0b0111 | 0b1010 | 0b110 | DC CGDSW | Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way
0b01 | 0b000 | 0b0111 | 0b1110 | 0b010 | DC CISW | Data or unified Cache line Clean and Invalidate by Set/Way
0b01 | 0b000 | 0b0111 | 0b1110 | 0b100 | DC CIGSW | Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way
0b01 | 0b000 | 0b0111 | 0b1110 | 0b110 | DC CIGDSW | Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way
0b01 | 0b011 | 0b0111 | 0b0100 | 0b001 | DC ZVA | Data Cache Zero by VA
0b01 | 0b011 | 0b0111 | 0b0100 | 0b011 | DC GVA | Data Cache set Allocation Tag by VA
0b01 | 0b011 | 0b0111 | 0b0100 | 0b100 | DC GZVA | Data Cache set Allocation Tags and Zero by VA
0b01 | 0b011 | 0b0111 | 0b1010 | 0b001 | DC CVAC | Data or unified Cache line Clean by VA to PoC
0b01 | 0b011 | 0b0111 | 0b1010 | 0b011 | DC CGVAC | Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC
0b01 | 0b011 | 0b0111 | 0b1010 | 0b101 | DC CGDVAC | Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC
0b01 | 0b011 | 0b0111 | 0b1011 | 0b001 | DC CVAU | Data or unified Cache line Clean by VA to PoU
0b01 | 0b011 | 0b0111 | 0b1100 | 0b001 | DC CVAP | Data or unified Cache line Clean by VA to PoP
0b01 | 0b011 | 0b0111 | 0b1100 | 0b011 | DC CGVAP | Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP
0b01 | 0b011 | 0b0111 | 0b1100 | 0b101 | DC CGDVAP | Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP
0b01 | 0b011 | 0b0111 | 0b1101 | 0b001 | DC CVADP | Data or unified Cache line Clean by VA to PoDP
0b01 | 0b011 | 0b0111 | 0b1101 | 0b011 | DC CGVADP | Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoDP
0b01 | 0b011 | 0b0111 | 0b1101 | 0b101 | DC CGDVADP | Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP
0b01 | 0b011 | 0b0111 | 0b1110 | 0b001 | DC CIVAC | Data or unified Cache line Clean and Invalidate by VA to PoC
0b01 | 0b011 | 0b0111 | 0b1110 | 0b011 | DC CIGVAC | Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC
0b01 | 0b011 | 0b0111 | 0b1110 | 0b101 | DC CIGDVAC | Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC

## Accessed using DVP:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b01 | 0b011 | 0b0111 | 0b0011 | 0b101 | DVP RCTX | Data Value Prediction Restriction by Context

## Accessed using IC:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2 | Rt
0b01 | 0b000 | 0b0111 | 0b0001 | 0b000 | 0b11111 | IC IALLUIS | Instruction Cache Invalidate All to PoU, Inner Shareable
0b01 | 0b000 | 0b0111 | 0b0101 | 0b000 | 0b11111 | IC IALLU | Instruction Cache Invalidate All to PoU
0b01 | 0b011 | 0b0111 | 0b0101 | 0b001 | - | IC IVAU | Instruction Cache line Invalidate by VA to PoU

## Accessed using MRS/MSR:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2
0b10 | 0b000 | 0b0000 | 0b0000 | 0b010 | OSDTRRX_EL1 | OS Lock Data Transfer Register, Receive
0b10 | 0b000 | 0b0000 | 0b0010 | 0b000 | MDCCINT_EL1 | Monitor DCC Interrupt Enable Register
0b10 | 0b000 | 0b0000 | 0b0010 | 0b010 | MDSCR_EL1 | Monitor Debug System Control Register
0b10 | 0b000 | 0b0000 | 0b0011 | 0b010 | OSDTRTX_EL1 | OS Lock Data Transfer Register, Transmit
0b10 | 0b000 | 0b0000 | 0b0110 | 0b010 | OSECCR_EL1 | OS Lock Exception Catch Control Register
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b100 | DBGBVR<n>_EL1 | Debug Breakpoint Value Registers
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b101 | DBGBCR<n>_EL1 | Debug Breakpoint Control Registers
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b110 | DBGWVR<n>_EL1 | Debug Watchpoint Value Registers
0b10 | 0b000 | 0b0000 | 0bnnnn | 0b111 | DBGWCR<n>_EL1 | Debug Watchpoint Control Registers
0b10 | 0b000 | 0b0001 | 0b0000 | 0b000 | MDRAR_EL1 | Monitor Debug ROM Address Register
0b10 | 0b000 | 0b0001 | 0b0000 | 0b100 | OSLAR_EL1 | OS Lock Access Register
0b10 | 0b000 | 0b0001 | 0b0001 | 0b100 | OSLSR_EL1 | OS Lock Status Register
0b10 | 0b000 | 0b0001 | 0b0011 | 0b100 | OSDLR_EL1 | OS Double Lock Register
0b10 | 0b000 | 0b0001 | 0b0100 | 0b100 | DBGPRCR_EL1 | Debug Power Control Register
0b10 | 0b000 | 0b0111 | 0b1000 | 0b110 | DBGCLAIMSET_EL1 | Debug Claim Tag Set register
0b10 | 0b000 | 0b0111 | 0b1001 | 0b110 | DBGCLAIMCLR_EL1 | Debug Claim Tag Clear register
0b10 | 0b000 | 0b0111 | 0b1110 | 0b110 | DBGAUTHSTATUS_EL1 | Debug Authentication Status register
0b10 | 0b001 | 0b0000 | 0b0000 | 0b001 | TRCTRACEIDR | Trace ID Register
0b10 | 0b001 | 0b0000 | 0b0000 | 0b010 | TRCVICTLR | ViewInst Main Control Register
0b10 | 0b001 | 0b0000 | 0b0000 | 0b110 | TRCIDR8 | ID Register 8
0b10 | 0b001 | 0b0000 | 0b0000 | 0b111 | TRCIMSPEC0 | IMP DEF Register 0
0b10 | 0b001 | 0b0000 | 0b0001 | 0b000 | TRCPRGCTLR | Programming Control Register
0b10 | 0b001 | 0b0000 | 0b0001 | 0b001 | TRCQCTLR | Q Element Control Register
0b10 | 0b001 | 0b0000 | 0b0001 | 0b010 | TRCVIIECTLR | ViewInst Include/Exclude Control Register
0b10 | 0b001 | 0b0000 | 0b0001 | 0b110 | TRCIDR9 | ID Register 9
0b10 | 0b001 | 0b0000 | 0b0010 | 0b010 | TRCVISSCTLR | ViewInst Start/Stop Control Register
0b10 | 0b001 | 0b0000 | 0b0010 | 0b110 | TRCIDR10 | ID Register 10
0b10 | 0b001 | 0b0000 | 0b0011 | 0b000 | TRCSTATR | Trace Status Register
0b10 | 0b001 | 0b0000 | 0b0011 | 0b010 | TRCVIPCSSCTLR | ViewInst Start/Stop PE Comparator Control Register
0b10 | 0b001 | 0b0000 | 0b0011 | 0b110 | TRCIDR11 | ID Register 11
0b10 | 0b001 | 0b0000 | 0b00[n:1:0] | 0b100 | TRCSEQEVR<n> | Sequencer State Transition Control Register <n>
0b10 | 0b001 | 0b0000 | 0b00[n:1:0] | 0b101 | TRCCNTRLDVR<n> | Counter Reload Value Register <n>
0b10 | 0b001 | 0b0000 | 0b0100 | 0b000 | TRCCONFIGR | Trace Configuration Register
0b10 | 0b001 | 0b0000 | 0b0100 | 0b110 | TRCIDR12 | ID Register 12
0b10 | 0b001 | 0b0000 | 0b0101 | 0b110 | TRCIDR13 | ID Register 13
0b10 | 0b001 | 0b0000 | 0b0110 | 0b000 | TRCAUXCTLR | Auxillary Control Register
0b10 | 0b001 | 0b0000 | 0b0110 | 0b100 | TRCSEQRSTEVR | Sequencer Reset Control Register
0b10 | 0b001 | 0b0000 | 0b0111 | 0b100 | TRCSEQSTR | Sequencer State Register
0b10 | 0b001 | 0b0000 | 0b01[n:1:0] | 0b101 | TRCCNTCTLR<n> | Counter Control Register <n>
0b10 | 0b001 | 0b0000 | 0b0[n:2:0] | 0b111 | TRCIMSPEC<n> | IMP DEF Register <n>
0b10 | 0b001 | 0b0000 | 0b1000 | 0b000 | TRCEVENTCTL0R | Event Control 0 Register
0b10 | 0b001 | 0b0000 | 0b1000 | 0b111 | TRCIDR0 | ID Register 0
0b10 | 0b001 | 0b0000 | 0b1001 | 0b000 | TRCEVENTCTL1R | Event Control 1 Register
0b10 | 0b001 | 0b0000 | 0b1001 | 0b111 | TRCIDR1 | ID Register 1
0b10 | 0b001 | 0b0000 | 0b1010 | 0b000 | TRCRSR | Resources Status Register
0b10 | 0b001 | 0b0000 | 0b1010 | 0b111 | TRCIDR2 | ID Register 2
0b10 | 0b001 | 0b0000 | 0b1011 | 0b000 | TRCSTALLCTLR | Stall Control Register
0b10 | 0b001 | 0b0000 | 0b1011 | 0b111 | TRCIDR3 | ID Register 3
0b10 | 0b001 | 0b0000 | 0b10[n:1:0] | 0b100 | TRCEXTINSELR<n> | External Input Select Register <n>
0b10 | 0b001 | 0b0000 | 0b10[n:1:0] | 0b101 | TRCCNTVR<n> | Counter Value Register <n>
0b10 | 0b001 | 0b0000 | 0b1100 | 0b000 | TRCTSCTLR | Timestamp Control Register
0b10 | 0b001 | 0b0000 | 0b1100 | 0b111 | TRCIDR4 | ID Register 4
0b10 | 0b001 | 0b0000 | 0b1101 | 0b000 | TRCSYNCPR | Synchronization Period Register
0b10 | 0b001 | 0b0000 | 0b1101 | 0b111 | TRCIDR5 | ID Register 5
0b10 | 0b001 | 0b0000 | 0b1110 | 0b000 | TRCCCCTLR | Cycle Count Control Register
0b10 | 0b001 | 0b0000 | 0b1110 | 0b111 | TRCIDR6 | ID Register 6
0b10 | 0b001 | 0b0000 | 0b1111 | 0b000 | TRCBBCTLR | Branch Broadcast Control Register
0b10 | 0b001 | 0b0000 | 0b1111 | 0b111 | TRCIDR7 | ID Register 7
0b10 | 0b001 | 0b0001 | 0b0001 | 0b100 | TRCOSLSR | Trace OS Lock Status Register
0b10 | 0b001 | 0b0001 | 0b0[n:2:0] | 0b010 | TRCSSCCR<n> | Single-shot Comparator Control Register <n>
0b10 | 0b001 | 0b0001 | 0b0[n:2:0] | 0b011 | TRCSSPCICR<n> | Single-shot Processing Element Comparator Input Control Register <n>
0b10 | 0b001 | 0b0001 | 0b1[n:2:0] | 0b010 | TRCSSCSR<n> | Single-shot Comparator Control Status Register <n>
0b10 | 0b001 | 0b0001 | 0b[n:3:0] | 0b00[n:4] | TRCRSCTLR<n> | Resource Selection Control Register <n>
0b10 | 0b001 | 0b0010 | 0b[n:2:0]0 | 0b00[n:3] | TRCACVR<n> | Address Comparator Value Register <n>
0b10 | 0b001 | 0b0010 | 0b[n:2:0]0 | 0b01[n:3] | TRCACATR<n> | Address Comparator Access Type Register <n>
0b10 | 0b001 | 0b0011 | 0b0000 | 0b010 | TRCCIDCCTLR0 | Context Identifier Comparator Control Register 0
0b10 | 0b001 | 0b0011 | 0b0001 | 0b010 | TRCCIDCCTLR1 | Context Identifier Comparator Control Register 1
0b10 | 0b001 | 0b0011 | 0b0010 | 0b010 | TRCVMIDCCTLR0 | Virtual Context Identifier Comparator Control Register 0
0b10 | 0b001 | 0b0011 | 0b0011 | 0b010 | TRCVMIDCCTLR1 | Virtual Context Identifier Comparator Control Register 1
0b10 | 0b001 | 0b0011 | 0b[n:2:0]0 | 0b000 | TRCCIDCVR<n> | Context Identifier Comparator Value Registers <n>
0b10 | 0b001 | 0b0011 | 0b[n:2:0]0 | 0b001 | TRCVMIDCVR<n> | Virtual Context Identifier Comparator Value Register <n>
0b10 | 0b001 | 0b0111 | 0b0010 | 0b111 | TRCDEVID | Device Configuration Register
0b10 | 0b001 | 0b0111 | 0b1000 | 0b110 | TRCCLAIMSET | Claim Tag Set Register
0b10 | 0b001 | 0b0111 | 0b1001 | 0b110 | TRCCLAIMCLR | Claim Tag Clear Register
0b10 | 0b001 | 0b0111 | 0b1110 | 0b110 | TRCAUTHSTATUS | Authentication Status Register
0b10 | 0b001 | 0b0111 | 0b1111 | 0b110 | TRCDEVARCH | Device Architecture Register
0b10 | 0b011 | 0b0000 | 0b0001 | 0b000 | MDCCSR_EL0 | Monitor DCC Status Register
0b10 | 0b011 | 0b0000 | 0b0100 | 0b000 | DBGDTR_EL0 | Debug Data Transfer Register, half-duplex
0b10 | 0b011 | 0b0000 | 0b0101 | 0b000 | DBGDTRRX_EL0 | Debug Data Transfer Register, Receive
0b10 | 0b011 | 0b0000 | 0b0101 | 0b000 | DBGDTRTX_EL0 | Debug Data Transfer Register, Transmit
0b10 | 0b100 | 0b0000 | 0b0111 | 0b000 | DBGVCR32_EL2 | Debug Vector Catch Register
0b11 | 0b000 | 0b0000 | 0b0000 | 0b000 | MIDR_EL1 | Main ID Register
0b11 | 0b000 | 0b0000 | 0b0000 | 0b101 | MPIDR_EL1 | Multiprocessor Affinity Register
0b11 | 0b000 | 0b0000 | 0b0000 | 0b110 | REVIDR_EL1 | Revision ID Register
0b11 | 0b000 | 0b0000 | 0b0001 | 0b000 | ID_PFR0_EL1 | AArch32 Processor Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0001 | 0b001 | ID_PFR1_EL1 | AArch32 Processor Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0001 | 0b010 | ID_DFR0_EL1 | AArch32 Debug Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0001 | 0b011 | ID_AFR0_EL1 | AArch32 Auxiliary Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0001 | 0b100 | ID_MMFR0_EL1 | AArch32 Memory Model Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0001 | 0b101 | ID_MMFR1_EL1 | AArch32 Memory Model Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0001 | 0b110 | ID_MMFR2_EL1 | AArch32 Memory Model Feature Register 2
0b11 | 0b000 | 0b0000 | 0b0001 | 0b111 | ID_MMFR3_EL1 | AArch32 Memory Model Feature Register 3
0b11 | 0b000 | 0b0000 | 0b0010 | 0b000 | ID_ISAR0_EL1 | AArch32 Instruction Set Attribute Register 0
0b11 | 0b000 | 0b0000 | 0b0010 | 0b001 | ID_ISAR1_EL1 | AArch32 Instruction Set Attribute Register 1
0b11 | 0b000 | 0b0000 | 0b0010 | 0b010 | ID_ISAR2_EL1 | AArch32 Instruction Set Attribute Register 2
0b11 | 0b000 | 0b0000 | 0b0010 | 0b011 | ID_ISAR3_EL1 | AArch32 Instruction Set Attribute Register 3
0b11 | 0b000 | 0b0000 | 0b0010 | 0b100 | ID_ISAR4_EL1 | AArch32 Instruction Set Attribute Register 4
0b11 | 0b000 | 0b0000 | 0b0010 | 0b101 | ID_ISAR5_EL1 | AArch32 Instruction Set Attribute Register 5
0b11 | 0b000 | 0b0000 | 0b0010 | 0b110 | ID_MMFR4_EL1 | AArch32 Memory Model Feature Register 4
0b11 | 0b000 | 0b0000 | 0b0010 | 0b111 | ID_ISAR6_EL1 | AArch32 Instruction Set Attribute Register 6
0b11 | 0b000 | 0b0000 | 0b0011 | 0b000 | MVFR0_EL1 | AArch32 Media and VFP Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0011 | 0b001 | MVFR1_EL1 | AArch32 Media and VFP Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0011 | 0b010 | MVFR2_EL1 | AArch32 Media and VFP Feature Register 2
0b11 | 0b000 | 0b0000 | 0b0011 | 0b100 | ID_PFR2_EL1 | AArch32 Processor Feature Register 2
0b11 | 0b000 | 0b0000 | 0b0100 | 0b000 | ID_AA64PFR0_EL1 | AArch64 Processor Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0100 | 0b001 | ID_AA64PFR1_EL1 | AArch64 Processor Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0100 | 0b100 | ID_AA64ZFR0_EL1 | SVE Feature ID register 0
0b11 | 0b000 | 0b0000 | 0b0101 | 0b000 | ID_AA64DFR0_EL1 | AArch64 Debug Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0101 | 0b001 | ID_AA64DFR1_EL1 | AArch64 Debug Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0101 | 0b100 | ID_AA64AFR0_EL1 | AArch64 Auxiliary Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0101 | 0b101 | ID_AA64AFR1_EL1 | AArch64 Auxiliary Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0110 | 0b000 | ID_AA64ISAR0_EL1 | AArch64 Instruction Set Attribute Register 0
0b11 | 0b000 | 0b0000 | 0b0110 | 0b001 | ID_AA64ISAR1_EL1 | AArch64 Instruction Set Attribute Register 1
0b11 | 0b000 | 0b0000 | 0b0111 | 0b000 | ID_AA64MMFR0_EL1 | AArch64 Memory Model Feature Register 0
0b11 | 0b000 | 0b0000 | 0b0111 | 0b001 | ID_AA64MMFR1_EL1 | AArch64 Memory Model Feature Register 1
0b11 | 0b000 | 0b0000 | 0b0111 | 0b010 | ID_AA64MMFR2_EL1 | AArch64 Memory Model Feature Register 2
0b11 | 0b000 | 0b0001 | 0b0000 | 0b000 | SCTLR_EL1 | System Control Register (EL1)
0b11 | 0b000 | 0b0001 | 0b0000 | 0b001 | ACTLR_EL1 | Auxiliary Control Register (EL1)
0b11 | 0b000 | 0b0001 | 0b0000 | 0b010 | CPACR_EL1 | Architectural Feature Access Control Register
0b11 | 0b000 | 0b0001 | 0b0000 | 0b101 | RGSR_EL1 | Random Allocation Tag Seed Register.
0b11 | 0b000 | 0b0001 | 0b0000 | 0b110 | GCR_EL1 | Tag Control Register.
0b11 | 0b000 | 0b0001 | 0b0010 | 0b000 | ZCR_EL1 | SVE Control Register for EL1
0b11 | 0b000 | 0b0001 | 0b0010 | 0b001 | TRFCR_EL1 | Trace Filter Control Register (EL1)
0b11 | 0b000 | 0b0010 | 0b0000 | 0b000 | TTBR0_EL1 | Translation Table Base Register 0 (EL1)
0b11 | 0b000 | 0b0010 | 0b0000 | 0b001 | TTBR1_EL1 | Translation Table Base Register 1 (EL1)
0b11 | 0b000 | 0b0010 | 0b0000 | 0b010 | TCR_EL1 | Translation Control Register (EL1)
0b11 | 0b000 | 0b0010 | 0b0001 | 0b000 | APIAKeyLo_EL1 | Pointer Authentication Key A for Instruction (bits[63:0])
0b11 | 0b000 | 0b0010 | 0b0001 | 0b001 | APIAKeyHi_EL1 | Pointer Authentication Key A for Instruction (bits[127:64])
0b11 | 0b000 | 0b0010 | 0b0001 | 0b010 | APIBKeyLo_EL1 | Pointer Authentication Key B for Instruction (bits[63:0])
0b11 | 0b000 | 0b0010 | 0b0001 | 0b011 | APIBKeyHi_EL1 | Pointer Authentication Key B for Instruction (bits[127:64])
0b11 | 0b000 | 0b0010 | 0b0010 | 0b000 | APDAKeyLo_EL1 | Pointer Authentication Key A for Data (bits[63:0])
0b11 | 0b000 | 0b0010 | 0b0010 | 0b001 | APDAKeyHi_EL1 | Pointer Authentication Key A for Data (bits[127:64])
0b11 | 0b000 | 0b0010 | 0b0010 | 0b010 | APDBKeyLo_EL1 | Pointer Authentication Key B for Data (bits[63:0])
0b11 | 0b000 | 0b0010 | 0b0010 | 0b011 | APDBKeyHi_EL1 | Pointer Authentication Key B for Data (bits[127:64])
0b11 | 0b000 | 0b0010 | 0b0011 | 0b000 | APGAKeyLo_EL1 | Pointer Authentication Key A for Code (bits[63:0])
0b11 | 0b000 | 0b0010 | 0b0011 | 0b001 | APGAKeyHi_EL1 | Pointer Authentication Key A for Code (bits[127:64])
0b11 | 0b000 | 0b0100 | 0b0000 | 0b000 | SPSR_EL1 | Saved Program Status Register (EL1)
0b11 | 0b000 | 0b0100 | 0b0000 | 0b001 | ELR_EL1 | Exception Link Register (EL1)
0b11 | 0b000 | 0b0100 | 0b0001 | 0b000 | SP_EL0 | Stack Pointer (EL0)
0b11 | 0b000 | 0b0100 | 0b0010 | 0b000 | SPSel | Stack Pointer Select
0b11 | 0b000 | 0b0100 | 0b0010 | 0b010 | CurrentEL | Current Exception Level
0b11 | 0b000 | 0b0100 | 0b0010 | 0b011 | PAN | Privileged Access Never
0b11 | 0b000 | 0b0100 | 0b0010 | 0b100 | UAO | User Access Override
0b11 | 0b000 | 0b0100 | 0b0110 | 0b000 | ICC_PMR_EL1 | Interrupt Controller Interrupt Priority Mask Register
0b11 | 0b000 | 0b0101 | 0b0001 | 0b000 | AFSR0_EL1 | Auxiliary Fault Status Register 0 (EL1)
0b11 | 0b000 | 0b0101 | 0b0001 | 0b001 | AFSR1_EL1 | Auxiliary Fault Status Register 1 (EL1)
0b11 | 0b000 | 0b0101 | 0b0010 | 0b000 | ESR_EL1 | Exception Syndrome Register (EL1)
0b11 | 0b000 | 0b0101 | 0b0011 | 0b000 | ERRIDR_EL1 | Error Record ID Register
0b11 | 0b000 | 0b0101 | 0b0011 | 0b001 | ERRSELR_EL1 | Error Record Select Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b000 | ERXFR_EL1 | Selected Error Record Feature Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b001 | ERXCTLR_EL1 | Selected Error Record Control Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b010 | ERXSTATUS_EL1 | Selected Error Record Primary Status Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b011 | ERXADDR_EL1 | Selected Error Record Address Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b100 | ERXPFGF_EL1 | Selected Pseudo-fault Generation Feature Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b101 | ERXPFGCTL_EL1 | Selected Pseudo-fault Generation Control Register
0b11 | 0b000 | 0b0101 | 0b0100 | 0b110 | ERXPFGCDN_EL1 | Selected Pseudo-fault Generation Countdown Register
0b11 | 0b000 | 0b0101 | 0b0101 | 0b000 | ERXMISC0_EL1 | Selected Error Record Miscellaneous Register 0
0b11 | 0b000 | 0b0101 | 0b0101 | 0b001 | ERXMISC1_EL1 | Selected Error Record Miscellaneous Register 1
0b11 | 0b000 | 0b0101 | 0b0101 | 0b010 | ERXMISC2_EL1 | Selected Error Record Miscellaneous Register 2
0b11 | 0b000 | 0b0101 | 0b0101 | 0b011 | ERXMISC3_EL1 | Selected Error Record Miscellaneous Register 3
0b11 | 0b000 | 0b0110 | 0b0000 | 0b000 | FAR_EL1 | Fault Address Register (EL1)
0b11 | 0b000 | 0b0110 | 0b0101 | 0b000 | TFSR_EL1 | Tag Fail Status Register (EL1).
0b11 | 0b000 | 0b0110 | 0b0110 | 0b001 | TFSRE0_EL1 | Tag Fail Status Register (EL0).
0b11 | 0b000 | 0b0111 | 0b0100 | 0b000 | PAR_EL1 | Physical Address Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b000 | PMSCR_EL1 | Statistical Profiling Control Register (EL1)
0b11 | 0b000 | 0b1001 | 0b1001 | 0b010 | PMSICR_EL1 | Sampling Interval Counter Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b011 | PMSIRR_EL1 | Sampling Interval Reload Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b100 | PMSFCR_EL1 | Sampling Filter Control Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b101 | PMSEVFR_EL1 | Sampling Event Filter Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b110 | PMSLATFR_EL1 | Sampling Latency Filter Register
0b11 | 0b000 | 0b1001 | 0b1001 | 0b111 | PMSIDR_EL1 | Sampling Profiling ID Register
0b11 | 0b000 | 0b1001 | 0b1010 | 0b000 | PMBLIMITR_EL1 | Profiling Buffer Limit Address Register
0b11 | 0b000 | 0b1001 | 0b1010 | 0b001 | PMBPTR_EL1 | Profiling Buffer Write Pointer Register
0b11 | 0b000 | 0b1001 | 0b1010 | 0b011 | PMBSR_EL1 | Profiling Buffer Status/syndrome Register
0b11 | 0b000 | 0b1001 | 0b1010 | 0b111 | PMBIDR_EL1 | Profiling Buffer ID Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b000 | TRBLIMITR_EL1 | Trace Buffer Limit Address Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b001 | TRBPTR_EL1 | Trace Buffer Write Pointer Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b010 | TRBBASER_EL1 | Trace Buffer Base Address Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b011 | TRBSR_EL1 | Trace Buffer Status/syndrome Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b100 | TRBMAR_EL1 | Trace Buffer Memory Attribute Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b110 | TRBTRG_EL1 | Trace Buffer Trigger Counter Register
0b11 | 0b000 | 0b1001 | 0b1011 | 0b111 | TRBIDR_EL1 | Trace Buffer ID Register
0b11 | 0b000 | 0b1001 | 0b1110 | 0b001 | PMINTENSET_EL1 | Performance Monitors Interrupt Enable Set register
0b11 | 0b000 | 0b1001 | 0b1110 | 0b010 | PMINTENCLR_EL1 | Performance Monitors Interrupt Enable Clear register
0b11 | 0b000 | 0b1001 | 0b1110 | 0b110 | PMMIR_EL1 | Performance Monitors Machine Identification Register
0b11 | 0b000 | 0b1010 | 0b0010 | 0b000 | MAIR_EL1 | Memory Attribute Indirection Register (EL1)
0b11 | 0b000 | 0b1010 | 0b0011 | 0b000 | AMAIR_EL1 | Auxiliary Memory Attribute Indirection Register (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b000 | LORSA_EL1 | LORegion Start Address (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b001 | LOREA_EL1 | LORegion End Address (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b010 | LORN_EL1 | LORegion Number (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b011 | LORC_EL1 | LORegion Control (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b100 | MPAMIDR_EL1 | MPAM ID Register (EL1)
0b11 | 0b000 | 0b1010 | 0b0100 | 0b111 | LORID_EL1 | LORegionID (EL1)
0b11 | 0b000 | 0b1010 | 0b0101 | 0b000 | MPAM1_EL1 | MPAM1 Register (EL1)
0b11 | 0b000 | 0b1010 | 0b0101 | 0b001 | MPAM0_EL1 | MPAM0 Register (EL1)
0b11 | 0b000 | 0b1100 | 0b0000 | 0b000 | VBAR_EL1 | Vector Base Address Register (EL1)
0b11 | 0b000 | 0b1100 | 0b0000 | 0b001 | RVBAR_EL1 | Reset Vector Base Address Register (if EL2 and EL3 not implemented)
0b11 | 0b000 | 0b1100 | 0b0000 | 0b010 | RMR_EL1 | Reset Management Register (EL1)
0b11 | 0b000 | 0b1100 | 0b0001 | 0b000 | ISR_EL1 | Interrupt Status Register
0b11 | 0b000 | 0b1100 | 0b0001 | 0b001 | DISR_EL1 | Deferred Interrupt Status Register
0b11 | 0b000 | 0b1100 | 0b1000 | 0b000 | ICC_IAR0_EL1 | Interrupt Controller Interrupt Acknowledge Register 0
0b11 | 0b000 | 0b1100 | 0b1000 | 0b001 | ICC_EOIR0_EL1 | Interrupt Controller End Of Interrupt Register 0
0b11 | 0b000 | 0b1100 | 0b1000 | 0b010 | ICC_HPPIR0_EL1 | Interrupt Controller Highest Priority Pending Interrupt Register 0
0b11 | 0b000 | 0b1100 | 0b1000 | 0b011 | ICC_BPR0_EL1 | Interrupt Controller Binary Point Register 0
0b11 | 0b000 | 0b1100 | 0b1000 | 0b1[n:1:0] | ICC_AP0R<n>_EL1 | Interrupt Controller Active Priorities Group 0 Registers
0b11 | 0b000 | 0b1100 | 0b1001 | 0b0[n:1:0] | ICC_AP1R<n>_EL1 | Interrupt Controller Active Priorities Group 1 Registers
0b11 | 0b000 | 0b1100 | 0b1011 | 0b001 | ICC_DIR_EL1 | Interrupt Controller Deactivate Interrupt Register
0b11 | 0b000 | 0b1100 | 0b1011 | 0b011 | ICC_RPR_EL1 | Interrupt Controller Running Priority Register
0b11 | 0b000 | 0b1100 | 0b1011 | 0b101 | ICC_SGI1R_EL1 | Interrupt Controller Software Generated Interrupt Group 1 Register
0b11 | 0b000 | 0b1100 | 0b1011 | 0b110 | ICC_ASGI1R_EL1 | Interrupt Controller Alias Software Generated Interrupt Group 1 Register
0b11 | 0b000 | 0b1100 | 0b1011 | 0b111 | ICC_SGI0R_EL1 | Interrupt Controller Software Generated Interrupt Group 0 Register
0b11 | 0b000 | 0b1100 | 0b1100 | 0b000 | ICC_IAR1_EL1 | Interrupt Controller Interrupt Acknowledge Register 1
0b11 | 0b000 | 0b1100 | 0b1100 | 0b001 | ICC_EOIR1_EL1 | Interrupt Controller End Of Interrupt Register 1
0b11 | 0b000 | 0b1100 | 0b1100 | 0b010 | ICC_HPPIR1_EL1 | Interrupt Controller Highest Priority Pending Interrupt Register 1
0b11 | 0b000 | 0b1100 | 0b1100 | 0b011 | ICC_BPR1_EL1 | Interrupt Controller Binary Point Register 1
0b11 | 0b000 | 0b1100 | 0b1100 | 0b100 | ICC_CTLR_EL1 | Interrupt Controller Control Register (EL1)
0b11 | 0b000 | 0b1100 | 0b1100 | 0b101 | ICC_SRE_EL1 | Interrupt Controller System Register Enable register (EL1)
0b11 | 0b000 | 0b1100 | 0b1100 | 0b110 | ICC_IGRPEN0_EL1 | Interrupt Controller Interrupt Group 0 Enable register
0b11 | 0b000 | 0b1100 | 0b1100 | 0b111 | ICC_IGRPEN1_EL1 | Interrupt Controller Interrupt Group 1 Enable register
0b11 | 0b000 | 0b1101 | 0b0000 | 0b001 | CONTEXTIDR_EL1 | Context ID Register (EL1)
0b11 | 0b000 | 0b1101 | 0b0000 | 0b100 | TPIDR_EL1 | EL1 Software Thread ID Register
0b11 | 0b000 | 0b1101 | 0b0000 | 0b111 | SCXTNUM_EL1 | EL1 Read/Write Software Context Number
0b11 | 0b000 | 0b1110 | 0b0001 | 0b000 | CNTKCTL_EL1 | Counter-timer Kernel Control register
0b11 | 0b001 | 0b0000 | 0b0000 | 0b000 | CCSIDR_EL1 | Current Cache Size ID Register
0b11 | 0b001 | 0b0000 | 0b0000 | 0b001 | CLIDR_EL1 | Cache Level ID Register
0b11 | 0b001 | 0b0000 | 0b0000 | 0b010 | CCSIDR2_EL1 | Current Cache Size ID Register 2
0b11 | 0b001 | 0b0000 | 0b0000 | 0b100 | GMID_EL1 | Multiple tag transfer ID register
0b11 | 0b001 | 0b0000 | 0b0000 | 0b111 | AIDR_EL1 | Auxiliary ID Register
0b11 | 0b010 | 0b0000 | 0b0000 | 0b000 | CSSELR_EL1 | Cache Size Selection Register
0b11 | 0b011 | 0b0000 | 0b0000 | 0b001 | CTR_EL0 | Cache Type Register
0b11 | 0b011 | 0b0000 | 0b0000 | 0b111 | DCZID_EL0 | Data Cache Zero ID register
0b11 | 0b011 | 0b0010 | 0b0100 | 0b000 | RNDR | Random Number
0b11 | 0b011 | 0b0010 | 0b0100 | 0b001 | RNDRRS | Reseeded Random Number
0b11 | 0b011 | 0b0100 | 0b0010 | 0b000 | NZCV | Condition Flags
0b11 | 0b011 | 0b0100 | 0b0010 | 0b001 | DAIF | Interrupt Mask Bits
0b11 | 0b011 | 0b0100 | 0b0010 | 0b101 | DIT | Data Independent Timing
0b11 | 0b011 | 0b0100 | 0b0010 | 0b110 | SSBS | Speculative Store Bypass Safe
0b11 | 0b011 | 0b0100 | 0b0010 | 0b111 | TCO | Tag Check Override
0b11 | 0b011 | 0b0100 | 0b0100 | 0b000 | FPCR | Floating-point Control Register
0b11 | 0b011 | 0b0100 | 0b0100 | 0b001 | FPSR | Floating-point Status Register
0b11 | 0b011 | 0b0100 | 0b0101 | 0b000 | DSPSR_EL0 | Debug Saved Program Status Register
0b11 | 0b011 | 0b0100 | 0b0101 | 0b001 | DLR_EL0 | Debug Link Register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b000 | PMCR_EL0 | Performance Monitors Control Register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b001 | PMCNTENSET_EL0 | Performance Monitors Count Enable Set register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b010 | PMCNTENCLR_EL0 | Performance Monitors Count Enable Clear register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b011 | PMOVSCLR_EL0 | Performance Monitors Overflow Flag Status Clear Register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b100 | PMSWINC_EL0 | Performance Monitors Software Increment register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b101 | PMSELR_EL0 | Performance Monitors Event Counter Selection Register
0b11 | 0b011 | 0b1001 | 0b1100 | 0b110 | PMCEID0_EL0 | Performance Monitors Common Event Identification register 0
0b11 | 0b011 | 0b1001 | 0b1100 | 0b111 | PMCEID1_EL0 | Performance Monitors Common Event Identification register 1
0b11 | 0b011 | 0b1001 | 0b1101 | 0b000 | PMCCNTR_EL0 | Performance Monitors Cycle Count Register
0b11 | 0b011 | 0b1001 | 0b1101 | 0b001 | PMXEVTYPER_EL0 | Performance Monitors Selected Event Type Register
0b11 | 0b011 | 0b1001 | 0b1101 | 0b010 | PMXEVCNTR_EL0 | Performance Monitors Selected Event Count Register
0b11 | 0b011 | 0b1001 | 0b1110 | 0b000 | PMUSERENR_EL0 | Performance Monitors User Enable Register
0b11 | 0b011 | 0b1001 | 0b1110 | 0b011 | PMOVSSET_EL0 | Performance Monitors Overflow Flag Status Set register
0b11 | 0b011 | 0b1101 | 0b0000 | 0b010 | TPIDR_EL0 | EL0 Read/Write Software Thread ID Register
0b11 | 0b011 | 0b1101 | 0b0000 | 0b011 | TPIDRRO_EL0 | EL0 Read-Only Software Thread ID Register
0b11 | 0b011 | 0b1101 | 0b0000 | 0b111 | SCXTNUM_EL0 | EL0 Read/Write Software Context Number
0b11 | 0b011 | 0b1101 | 0b0010 | 0b000 | AMCR_EL0 | Activity Monitors Control Register
0b11 | 0b011 | 0b1101 | 0b0010 | 0b001 | AMCFGR_EL0 | Activity Monitors Configuration Register
0b11 | 0b011 | 0b1101 | 0b0010 | 0b010 | AMCGCR_EL0 | Activity Monitors Counter Group Configuration Register
0b11 | 0b011 | 0b1101 | 0b0010 | 0b011 | AMUSERENR_EL0 | Activity Monitors User Enable Register
0b11 | 0b011 | 0b1101 | 0b0010 | 0b100 | AMCNTENCLR0_EL0 | Activity Monitors Count Enable Clear Register 0
0b11 | 0b011 | 0b1101 | 0b0010 | 0b101 | AMCNTENSET0_EL0 | Activity Monitors Count Enable Set Register 0
0b11 | 0b011 | 0b1101 | 0b0011 | 0b000 | AMCNTENCLR1_EL0 | Activity Monitors Count Enable Clear Register 1
0b11 | 0b011 | 0b1101 | 0b0011 | 0b001 | AMCNTENSET1_EL0 | Activity Monitors Count Enable Set Register 1
0b11 | 0b011 | 0b1101 | 0b010[n:3] | 0b[n:2:0] | AMEVCNTR0<n>_EL0 | Activity Monitors Event Counter Registers 0
0b11 | 0b011 | 0b1101 | 0b011[n:3] | 0b[n:2:0] | AMEVTYPER0<n>_EL0 | Activity Monitors Event Type Registers 0
0b11 | 0b011 | 0b1101 | 0b110[n:3] | 0b[n:2:0] | AMEVCNTR1<n>_EL0 | Activity Monitors Event Counter Registers 1
0b11 | 0b011 | 0b1101 | 0b111[n:3] | 0b[n:2:0] | AMEVTYPER1<n>_EL0 | Activity Monitors Event Type Registers 1
0b11 | 0b011 | 0b1110 | 0b0000 | 0b000 | CNTFRQ_EL0 | Counter-timer Frequency register
0b11 | 0b011 | 0b1110 | 0b0000 | 0b001 | CNTPCT_EL0 | Counter-timer Physical Count register
0b11 | 0b011 | 0b1110 | 0b0000 | 0b010 | CNTVCT_EL0 | Counter-timer Virtual Count register
0b11 | 0b011 | 0b1110 | 0b0010 | 0b000 | CNTP_TVAL_EL0 | Counter-timer Physical Timer TimerValue register
0b11 | 0b011 | 0b1110 | 0b0010 | 0b001 | CNTP_CTL_EL0 | Counter-timer Physical Timer Control register
0b11 | 0b011 | 0b1110 | 0b0010 | 0b010 | CNTP_CVAL_EL0 | Counter-timer Physical Timer CompareValue register
0b11 | 0b011 | 0b1110 | 0b0011 | 0b000 | CNTV_TVAL_EL0 | Counter-timer Virtual Timer TimerValue register
0b11 | 0b011 | 0b1110 | 0b0011 | 0b001 | CNTV_CTL_EL0 | Counter-timer Virtual Timer Control register
0b11 | 0b011 | 0b1110 | 0b0011 | 0b010 | CNTV_CVAL_EL0 | Counter-timer Virtual Timer CompareValue register
0b11 | 0b011 | 0b1110 | 0b10[n:4:3] | 0b[n:2:0] | PMEVCNTR<n>_EL0 | Performance Monitors Event Count Registers
0b11 | 0b011 | 0b1110 | 0b1111 | 0b111 | PMCCFILTR_EL0 | Performance Monitors Cycle Count Filter Register
0b11 | 0b011 | 0b1110 | 0b11[n:4:3] | 0b[n:2:0] | PMEVTYPER<n>_EL0 | Performance Monitors Event Type Registers
0b11 | 0b100 | 0b0000 | 0b0000 | 0b000 | VPIDR_EL2 | Virtualization Processor ID Register
0b11 | 0b100 | 0b0000 | 0b0000 | 0b101 | VMPIDR_EL2 | Virtualization Multiprocessor ID Register
0b11 | 0b100 | 0b0001 | 0b0000 | 0b000 | SCTLR_EL2 | System Control Register (EL2)
0b11 | 0b100 | 0b0001 | 0b0000 | 0b001 | ACTLR_EL2 | Auxiliary Control Register (EL2)
0b11 | 0b100 | 0b0001 | 0b0001 | 0b000 | HCR_EL2 | Hypervisor Configuration Register
0b11 | 0b100 | 0b0001 | 0b0001 | 0b001 | MDCR_EL2 | Monitor Debug Configuration Register (EL2)
0b11 | 0b100 | 0b0001 | 0b0001 | 0b010 | CPTR_EL2 | Architectural Feature Trap Register (EL2)
0b11 | 0b100 | 0b0001 | 0b0001 | 0b011 | HSTR_EL2 | Hypervisor System Trap Register
0b11 | 0b100 | 0b0001 | 0b0001 | 0b111 | HACR_EL2 | Hypervisor Auxiliary Control Register
0b11 | 0b100 | 0b0001 | 0b0010 | 0b000 | ZCR_EL2 | SVE Control Register for EL2
0b11 | 0b100 | 0b0001 | 0b0010 | 0b001 | TRFCR_EL2 | Trace Filter Control Register (EL2)
0b11 | 0b100 | 0b0001 | 0b0011 | 0b001 | SDER32_EL2 | AArch32 Secure Debug Enable Register
0b11 | 0b100 | 0b0010 | 0b0000 | 0b000 | TTBR0_EL2 | Translation Table Base Register 0 (EL2)
0b11 | 0b100 | 0b0010 | 0b0000 | 0b001 | TTBR1_EL2 | Translation Table Base Register 1 (EL2)
0b11 | 0b100 | 0b0010 | 0b0000 | 0b010 | TCR_EL2 | Translation Control Register (EL2)
0b11 | 0b100 | 0b0010 | 0b0001 | 0b000 | VTTBR_EL2 | Virtualization Translation Table Base Register
0b11 | 0b100 | 0b0010 | 0b0001 | 0b010 | VTCR_EL2 | Virtualization Translation Control Register
0b11 | 0b100 | 0b0010 | 0b0010 | 0b000 | VNCR_EL2 | Virtual Nested Control Register
0b11 | 0b100 | 0b0010 | 0b0110 | 0b000 | VSTTBR_EL2 | Virtualization Secure Translation Table Base Register
0b11 | 0b100 | 0b0010 | 0b0110 | 0b010 | VSTCR_EL2 | Virtualization Secure Translation Control Register
0b11 | 0b100 | 0b0011 | 0b0000 | 0b000 | DACR32_EL2 | Domain Access Control Register
0b11 | 0b100 | 0b0100 | 0b0000 | 0b000 | SPSR_EL2 | Saved Program Status Register (EL2)
0b11 | 0b100 | 0b0100 | 0b0000 | 0b001 | ELR_EL2 | Exception Link Register (EL2)
0b11 | 0b100 | 0b0100 | 0b0001 | 0b000 | SP_EL1 | Stack Pointer (EL1)
0b11 | 0b100 | 0b0100 | 0b0011 | 0b000 | SPSR_irq | Saved Program Status Register (IRQ mode)
0b11 | 0b100 | 0b0100 | 0b0011 | 0b001 | SPSR_abt | Saved Program Status Register (Abort mode)
0b11 | 0b100 | 0b0100 | 0b0011 | 0b010 | SPSR_und | Saved Program Status Register (Undefined mode)
0b11 | 0b100 | 0b0100 | 0b0011 | 0b011 | SPSR_fiq | Saved Program Status Register (FIQ mode)
0b11 | 0b100 | 0b0101 | 0b0000 | 0b001 | IFSR32_EL2 | Instruction Fault Status Register (EL2)
0b11 | 0b100 | 0b0101 | 0b0001 | 0b000 | AFSR0_EL2 | Auxiliary Fault Status Register 0 (EL2)
0b11 | 0b100 | 0b0101 | 0b0001 | 0b001 | AFSR1_EL2 | Auxiliary Fault Status Register 1 (EL2)
0b11 | 0b100 | 0b0101 | 0b0010 | 0b000 | ESR_EL2 | Exception Syndrome Register (EL2)
0b11 | 0b100 | 0b0101 | 0b0010 | 0b011 | VSESR_EL2 | Virtual SError Exception Syndrome Register
0b11 | 0b100 | 0b0101 | 0b0011 | 0b000 | FPEXC32_EL2 | Floating-Point Exception Control register
0b11 | 0b100 | 0b0110 | 0b0000 | 0b000 | FAR_EL2 | Fault Address Register (EL2)
0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 | HPFAR_EL2 | Hypervisor IPA Fault Address Register
0b11 | 0b100 | 0b0110 | 0b0101 | 0b000 | TFSR_EL2 | Tag Fail Status Register (EL2).
0b11 | 0b100 | 0b1001 | 0b1001 | 0b000 | PMSCR_EL2 | Statistical Profiling Control Register (EL2)
0b11 | 0b100 | 0b1010 | 0b0010 | 0b000 | MAIR_EL2 | Memory Attribute Indirection Register (EL2)
0b11 | 0b100 | 0b1010 | 0b0011 | 0b000 | AMAIR_EL2 | Auxiliary Memory Attribute Indirection Register (EL2)
0b11 | 0b100 | 0b1010 | 0b0100 | 0b000 | MPAMHCR_EL2 | MPAM Hypervisor Control Register (EL2)
0b11 | 0b100 | 0b1010 | 0b0100 | 0b001 | MPAMVPMV_EL2 | MPAM Virtual Partition Mapping Valid Register
0b11 | 0b100 | 0b1010 | 0b0101 | 0b000 | MPAM2_EL2 | MPAM2 Register (EL2)
0b11 | 0b100 | 0b1010 | 0b0110 | 0b000 | MPAMVPM0_EL2 | MPAM Virtual PARTID Mapping Register 0
0b11 | 0b100 | 0b1010 | 0b0110 | 0b001 | MPAMVPM1_EL2 | MPAM Virtual PARTID Mapping Register 1
0b11 | 0b100 | 0b1010 | 0b0110 | 0b010 | MPAMVPM2_EL2 | MPAM Virtual PARTID Mapping Register 2
0b11 | 0b100 | 0b1010 | 0b0110 | 0b011 | MPAMVPM3_EL2 | MPAM Virtual PARTID Mapping Register 3
0b11 | 0b100 | 0b1010 | 0b0110 | 0b100 | MPAMVPM4_EL2 | MPAM Virtual PARTID Mapping Register 4
0b11 | 0b100 | 0b1010 | 0b0110 | 0b101 | MPAMVPM5_EL2 | MPAM Virtual PARTID Mapping Register 5
0b11 | 0b100 | 0b1010 | 0b0110 | 0b110 | MPAMVPM6_EL2 | MPAM Virtual PARTID Mapping Register 6
0b11 | 0b100 | 0b1010 | 0b0110 | 0b111 | MPAMVPM7_EL2 | MPAM Virtual PARTID Mapping Register 7
0b11 | 0b100 | 0b1100 | 0b0000 | 0b000 | VBAR_EL2 | Vector Base Address Register (EL2)
0b11 | 0b100 | 0b1100 | 0b0000 | 0b001 | RVBAR_EL2 | Reset Vector Base Address Register (if EL3 not implemented)
0b11 | 0b100 | 0b1100 | 0b0000 | 0b010 | RMR_EL2 | Reset Management Register (EL2)
0b11 | 0b100 | 0b1100 | 0b0001 | 0b001 | VDISR_EL2 | Virtual Deferred Interrupt Status Register
0b11 | 0b100 | 0b1100 | 0b1000 | 0b0[n:1:0] | ICH_AP0R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 0 Registers
0b11 | 0b100 | 0b1100 | 0b1001 | 0b0[n:1:0] | ICH_AP1R<n>_EL2 | Interrupt Controller Hyp Active Priorities Group 1 Registers
0b11 | 0b100 | 0b1100 | 0b1001 | 0b101 | ICC_SRE_EL2 | Interrupt Controller System Register Enable register (EL2)
0b11 | 0b100 | 0b1100 | 0b1011 | 0b000 | ICH_HCR_EL2 | Interrupt Controller Hyp Control Register
0b11 | 0b100 | 0b1100 | 0b1011 | 0b001 | ICH_VTR_EL2 | Interrupt Controller VGIC Type Register
0b11 | 0b100 | 0b1100 | 0b1011 | 0b010 | ICH_MISR_EL2 | Interrupt Controller Maintenance Interrupt State Register
0b11 | 0b100 | 0b1100 | 0b1011 | 0b011 | ICH_EISR_EL2 | Interrupt Controller End of Interrupt Status Register
0b11 | 0b100 | 0b1100 | 0b1011 | 0b101 | ICH_ELRSR_EL2 | Interrupt Controller Empty List Register Status Register
0b11 | 0b100 | 0b1100 | 0b1011 | 0b111 | ICH_VMCR_EL2 | Interrupt Controller Virtual Machine Control Register
0b11 | 0b100 | 0b1100 | 0b110[n:3] | 0b[n:2:0] | ICH_LR<n>_EL2 | Interrupt Controller List Registers
0b11 | 0b100 | 0b1101 | 0b0000 | 0b001 | CONTEXTIDR_EL2 | Context ID Register (EL2)
0b11 | 0b100 | 0b1101 | 0b0000 | 0b010 | TPIDR_EL2 | EL2 Software Thread ID Register
0b11 | 0b100 | 0b1101 | 0b0000 | 0b111 | SCXTNUM_EL2 | EL2 Read/Write Software Context Number
0b11 | 0b100 | 0b1110 | 0b0000 | 0b011 | CNTVOFF_EL2 | Counter-timer Virtual Offset register
0b11 | 0b100 | 0b1110 | 0b0001 | 0b000 | CNTHCTL_EL2 | Counter-timer Hypervisor Control register
0b11 | 0b100 | 0b1110 | 0b0010 | 0b000 | CNTHP_TVAL_EL2 | Counter-timer Physical Timer TimerValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0010 | 0b001 | CNTHP_CTL_EL2 | Counter-timer Hypervisor Physical Timer Control register
0b11 | 0b100 | 0b1110 | 0b0010 | 0b010 | CNTHP_CVAL_EL2 | Counter-timer Physical Timer CompareValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0011 | 0b000 | CNTHV_TVAL_EL2 | Counter-timer Virtual Timer TimerValue Register (EL2)
0b11 | 0b100 | 0b1110 | 0b0011 | 0b001 | CNTHV_CTL_EL2 | Counter-timer Virtual Timer Control register (EL2)
0b11 | 0b100 | 0b1110 | 0b0011 | 0b010 | CNTHV_CVAL_EL2 | Counter-timer Virtual Timer CompareValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0100 | 0b000 | CNTHVS_TVAL_EL2 | Counter-timer Secure Virtual Timer TimerValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0100 | 0b001 | CNTHVS_CTL_EL2 | Counter-timer Secure Virtual Timer Control register (EL2)
0b11 | 0b100 | 0b1110 | 0b0100 | 0b010 | CNTHVS_CVAL_EL2 | Counter-timer Secure Virtual Timer CompareValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0101 | 0b000 | CNTHPS_TVAL_EL2 | Counter-timer Secure Physical Timer TimerValue register (EL2)
0b11 | 0b100 | 0b1110 | 0b0101 | 0b001 | CNTHPS_CTL_EL2 | Counter-timer Secure Physical Timer Control register (EL2)
0b11 | 0b100 | 0b1110 | 0b0101 | 0b010 | CNTHPS_CVAL_EL2 | Counter-timer Secure Physical Timer CompareValue register (EL2)
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000 | SCTLR_EL3 | System Control Register (EL3)
0b11 | 0b110 | 0b0001 | 0b0000 | 0b001 | ACTLR_EL3 | Auxiliary Control Register (EL3)
0b11 | 0b110 | 0b0001 | 0b0001 | 0b000 | SCR_EL3 | Secure Configuration Register
0b11 | 0b110 | 0b0001 | 0b0001 | 0b001 | SDER32_EL3 | AArch32 Secure Debug Enable Register
0b11 | 0b110 | 0b0001 | 0b0001 | 0b010 | CPTR_EL3 | Architectural Feature Trap Register (EL3)
0b11 | 0b110 | 0b0001 | 0b0010 | 0b000 | ZCR_EL3 | SVE Control Register for EL3
0b11 | 0b110 | 0b0001 | 0b0011 | 0b001 | MDCR_EL3 | Monitor Debug Configuration Register (EL3)
0b11 | 0b110 | 0b0010 | 0b0000 | 0b000 | TTBR0_EL3 | Translation Table Base Register 0 (EL3)
0b11 | 0b110 | 0b0010 | 0b0000 | 0b010 | TCR_EL3 | Translation Control Register (EL3)
0b11 | 0b110 | 0b0100 | 0b0000 | 0b000 | SPSR_EL3 | Saved Program Status Register (EL3)
0b11 | 0b110 | 0b0100 | 0b0000 | 0b001 | ELR_EL3 | Exception Link Register (EL3)
0b11 | 0b110 | 0b0100 | 0b0001 | 0b000 | SP_EL2 | Stack Pointer (EL2)
0b11 | 0b110 | 0b0101 | 0b0001 | 0b000 | AFSR0_EL3 | Auxiliary Fault Status Register 0 (EL3)
0b11 | 0b110 | 0b0101 | 0b0001 | 0b001 | AFSR1_EL3 | Auxiliary Fault Status Register 1 (EL3)
0b11 | 0b110 | 0b0101 | 0b0010 | 0b000 | ESR_EL3 | Exception Syndrome Register (EL3)
0b11 | 0b110 | 0b0110 | 0b0000 | 0b000 | FAR_EL3 | Fault Address Register (EL3)
0b11 | 0b110 | 0b0110 | 0b0110 | 0b000 | TFSR_EL3 | Tag Fail Status Register (EL3).
0b11 | 0b110 | 0b1010 | 0b0010 | 0b000 | MAIR_EL3 | Memory Attribute Indirection Register (EL3)
0b11 | 0b110 | 0b1010 | 0b0011 | 0b000 | AMAIR_EL3 | Auxiliary Memory Attribute Indirection Register (EL3)
0b11 | 0b110 | 0b1010 | 0b0101 | 0b000 | MPAM3_EL3 | MPAM3 Register (EL3)
0b11 | 0b110 | 0b1100 | 0b0000 | 0b000 | VBAR_EL3 | Vector Base Address Register (EL3)
0b11 | 0b110 | 0b1100 | 0b0000 | 0b001 | RVBAR_EL3 | Reset Vector Base Address Register (if EL3 implemented)
0b11 | 0b110 | 0b1100 | 0b0000 | 0b010 | RMR_EL3 | Reset Management Register (EL3)
0b11 | 0b110 | 0b1100 | 0b1100 | 0b100 | ICC_CTLR_EL3 | Interrupt Controller Control Register (EL3)
0b11 | 0b110 | 0b1100 | 0b1100 | 0b101 | ICC_SRE_EL3 | Interrupt Controller System Register Enable register (EL3)
0b11 | 0b110 | 0b1100 | 0b1100 | 0b111 | ICC_IGRPEN1_EL3 | Interrupt Controller Interrupt Group 1 Enable register (EL3)
0b11 | 0b110 | 0b1101 | 0b0000 | 0b010 | TPIDR_EL3 | EL3 Software Thread ID Register
0b11 | 0b110 | 0b1101 | 0b0000 | 0b111 | SCXTNUM_EL3 | EL3 Read/Write Software Context Number
0b11 | 0b111 | 0b1110 | 0b0010 | 0b000 | CNTPS_TVAL_EL1 | Counter-timer Physical Secure Timer TimerValue register
0b11 | 0b111 | 0b1110 | 0b0010 | 0b001 | CNTPS_CTL_EL1 | Counter-timer Physical Secure Timer Control register
0b11 | 0b111 | 0b1110 | 0b0010 | 0b010 | CNTPS_CVAL_EL1 | Counter-timer Physical Secure Timer CompareValue register

## Accessed using TLBI:

Register selectors | Name | Description
--- | --- | ---
op0 | op1 | CRn | CRm | op2 | Rt
0b01 | 0b000 | 0b1000 | 0b0001 | 0b000 | 0b11111 | TLBI VMALLE1OS | TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0001 | 0b001 | - | TLBI VAE1OS | TLB Invalidate by VA, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0001 | 0b010 | - | TLBI ASIDE1OS | TLB Invalidate by ASID, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0001 | 0b011 | - | TLBI VAAE1OS | TLB Invalidate by VA, All ASID, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0001 | 0b101 | - | TLBI VALE1OS | TLB Invalidate by VA, Last level, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0001 | 0b111 | - | TLBI VAALE1OS | TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0010 | 0b001 | - | TLBI RVAE1IS | TLB Range Invalidate by VA, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0010 | 0b011 | - | TLBI RVAAE1IS | TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0010 | 0b101 | - | TLBI RVALE1IS | TLB Range Invalidate by VA, Last level, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0010 | 0b111 | - | TLBI RVAALE1IS | TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b000 | 0b11111 | TLBI VMALLE1IS | TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b001 | - | TLBI VAE1IS | TLB Invalidate by VA, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b010 | - | TLBI ASIDE1IS | TLB Invalidate by ASID, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b011 | - | TLBI VAAE1IS | TLB Invalidate by VA, All ASID, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b101 | - | TLBI VALE1IS | TLB Invalidate by VA, Last level, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0011 | 0b111 | - | TLBI VAALE1IS | TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
0b01 | 0b000 | 0b1000 | 0b0101 | 0b001 | - | TLBI RVAE1OS | TLB Range Invalidate by VA, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0101 | 0b011 | - | TLBI RVAAE1OS | TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0101 | 0b101 | - | TLBI RVALE1OS | TLB Range Invalidate by VA, Last level, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0101 | 0b111 | - | TLBI RVAALE1OS | TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable
0b01 | 0b000 | 0b1000 | 0b0110 | 0b001 | - | TLBI RVAE1 | TLB Range Invalidate by VA, EL1
0b01 | 0b000 | 0b1000 | 0b0110 | 0b011 | - | TLBI RVAAE1 | TLB Range Invalidate by VA, All ASID, EL1
0b01 | 0b000 | 0b1000 | 0b0110 | 0b101 | - | TLBI RVALE1 | TLB Range Invalidate by VA, Last level, EL1
0b01 | 0b000 | 0b1000 | 0b0110 | 0b111 | - | TLBI RVAALE1 | TLB Range Invalidate by VA, All ASID, Last level, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b000 | 0b11111 | TLBI VMALLE1 | TLB Invalidate by VMID, All at stage 1, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b001 | - | TLBI VAE1 | TLB Invalidate by VA, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b010 | - | TLBI ASIDE1 | TLB Invalidate by ASID, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b011 | - | TLBI VAAE1 | TLB Invalidate by VA, All ASID, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b101 | - | TLBI VALE1 | TLB Invalidate by VA, Last level, EL1
0b01 | 0b000 | 0b1000 | 0b0111 | 0b111 | - | TLBI VAALE1 | TLB Invalidate by VA, All ASID, Last level, EL1
0b01 | 0b100 | 0b1000 | 0b0000 | 0b001 | - | TLBI IPAS2E1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0000 | 0b010 | - | TLBI RIPAS2E1IS | TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0000 | 0b101 | - | TLBI IPAS2LE1IS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0000 | 0b110 | - | TLBI RIPAS2LE1IS | TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0001 | 0b000 | 0b11111 | TLBI ALLE2OS | TLB Invalidate All, EL2, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0001 | 0b001 | - | TLBI VAE2OS | TLB Invalidate by VA, EL2, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0001 | 0b100 | 0b11111 | TLBI ALLE1OS | TLB Invalidate All, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0001 | 0b101 | - | TLBI VALE2OS | TLB Invalidate by VA, Last level, EL2, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0001 | 0b110 | 0b11111 | TLBI VMALLS12E1OS | TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0010 | 0b001 | - | TLBI RVAE2IS | TLB Range Invalidate by VA, EL2, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0010 | 0b101 | - | TLBI RVALE2IS | TLB Range Invalidate by VA, Last level, EL2, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0011 | 0b000 | 0b11111 | TLBI ALLE2IS | TLB Invalidate All, EL2, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0011 | 0b001 | - | TLBI VAE2IS | TLB Invalidate by VA, EL2, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0011 | 0b100 | 0b11111 | TLBI ALLE1IS | TLB Invalidate All, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0011 | 0b101 | - | TLBI VALE2IS | TLB Invalidate by VA, Last level, EL2, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0011 | 0b110 | 0b11111 | TLBI VMALLS12E1IS | TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
0b01 | 0b100 | 0b1000 | 0b0100 | 0b000 | - | TLBI IPAS2E1OS | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0100 | 0b001 | - | TLBI IPAS2E1 | TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
0b01 | 0b100 | 0b1000 | 0b0100 | 0b010 | - | TLBI RIPAS2E1 | TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1
0b01 | 0b100 | 0b1000 | 0b0100 | 0b011 | - | TLBI RIPAS2E1OS | TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0100 | 0b100 | - | TLBI IPAS2LE1OS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0100 | 0b101 | - | TLBI IPAS2LE1 | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
0b01 | 0b100 | 0b1000 | 0b0100 | 0b110 | - | TLBI RIPAS2LE1 | TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
0b01 | 0b100 | 0b1000 | 0b0100 | 0b111 | - | TLBI RIPAS2LE1OS | TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0101 | 0b001 | - | TLBI RVAE2OS | TLB Range Invalidate by VA, EL2, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0101 | 0b101 | - | TLBI RVALE2OS | TLB Range Invalidate by VA, Last level, EL2, Outer Shareable
0b01 | 0b100 | 0b1000 | 0b0110 | 0b001 | - | TLBI RVAE2 | TLB Range Invalidate by VA, EL2
0b01 | 0b100 | 0b1000 | 0b0110 | 0b101 | - | TLBI RVALE2 | TLB Range Invalidate by VA, Last level, EL2
0b01 | 0b100 | 0b1000 | 0b0111 | 0b000 | 0b11111 | TLBI ALLE2 | TLB Invalidate All, EL2
0b01 | 0b100 | 0b1000 | 0b0111 | 0b001 | - | TLBI VAE2 | TLB Invalidate by VA, EL2
0b01 | 0b100 | 0b1000 | 0b0111 | 0b100 | 0b11111 | TLBI ALLE1 | TLB Invalidate All, EL1
0b01 | 0b100 | 0b1000 | 0b0111 | 0b101 | - | TLBI VALE2 | TLB Invalidate by VA, Last level, EL2
0b01 | 0b100 | 0b1000 | 0b0111 | 0b110 | 0b11111 | TLBI VMALLS12E1 | TLB Invalidate by VMID, All at Stage 1 and 2, EL1
0b01 | 0b110 | 0b1000 | 0b0001 | 0b000 | 0b11111 | TLBI ALLE3OS | TLB Invalidate All, EL3, Outer Shareable
0b01 | 0b110 | 0b1000 | 0b0001 | 0b001 | - | TLBI VAE3OS | TLB Invalidate by VA, EL3, Outer Shareable
0b01 | 0b110 | 0b1000 | 0b0001 | 0b101 | - | TLBI VALE3OS | TLB Invalidate by VA, Last level, EL3, Outer Shareable
0b01 | 0b110 | 0b1000 | 0b0010 | 0b001 | - | TLBI RVAE3IS | TLB Range Invalidate by VA, EL3, Inner Shareable
0b01 | 0b110 | 0b1000 | 0b0010 | 0b101 | - | TLBI RVALE3IS | TLB Range Invalidate by VA, Last level, EL3, Inner Shareable
0b01 | 0b110 | 0b1000 | 0b0011 | 0b000 | 0b11111 | TLBI ALLE3IS | TLB Invalidate All, EL3, Inner Shareable
0b01 | 0b110 | 0b1000 | 0b0011 | 0b001 | - | TLBI VAE3IS | TLB Invalidate by VA, EL3, Inner Shareable
0b01 | 0b110 | 0b1000 | 0b0011 | 0b101 | - | TLBI VALE3IS | TLB Invalidate by VA, Last level, EL3, Inner Shareable
0b01 | 0b110 | 0b1000 | 0b0101 | 0b001 | - | TLBI RVAE3OS | TLB Range Invalidate by VA, EL3, Outer Shareable
0b01 | 0b110 | 0b1000 | 0b0101 | 0b101 | - | TLBI RVALE3OS | TLB Range Invalidate by VA, Last level, EL3, Outer Shareable
0b01 | 0b110 | 0b1000 | 0b0110 | 0b001 | - | TLBI RVAE3 | TLB Range Invalidate by VA, EL3
0b01 | 0b110 | 0b1000 | 0b0110 | 0b101 | - | TLBI RVALE3 | TLB Range Invalidate by VA, Last level, EL3
0b01 | 0b110 | 0b1000 | 0b0111 | 0b000 | 0b11111 | TLBI ALLE3 | TLB Invalidate All, EL3
0b01 | 0b110 | 0b1000 | 0b0111 | 0b001 | - | TLBI VAE3 | TLB Invalidate by VA, EL3
0b01 | 0b110 | 0b1000 | 0b0111 | 0b101 | - | TLBI VALE3 | TLB Invalidate by VA, Last level, EL3

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47

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