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# GICR_SYNCR, Redistributor Synchronize Register

The GICR_SYNCR characteristics are:

## Purpose

Indicates completion of physical Redistributor operations.

## Configuration

A copy of this register is provided for each Redistributor.

## Attributes

GICR_SYNCR is a 32-bit register.

## Field descriptions

The GICR_SYNCR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | Busy

#### Bits [31:1]

Reserved, RES0.

#### Busy, bit [0]

Indicates completion of any Redistributor operations as follows:

Busy | Meaning
--- | ---
0b0 | No operations are in progress.
0b1 | A write is in progress to one or more of the following registers: GICR_CLRLPIR. GICR_INVLPIR. GICR_INVALLR.

This field also indicates completion of any operations initiated by writes to GICR_PENDBASER or GICR_PROPBASER.

## Accessing the GICR_SYNCR

Optionally, when this register is accessed, an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.

This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.

#### GICR_SYNCR can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | RD_base | 0x00C0 | GICR_SYNCR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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