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# S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED registers

The S3_<op1>_<Cn>_<Cm>_<op2> characteristics are:

## Purpose

This area of the instruction set space is reserved for IMPLEMENTATION DEFINED registers.

## Configuration

## Attributes

S3_<op1>_<Cn>_<Cm>_<op2> is a 64-bit register.

## Field descriptions

The S3_<op1>_<Cn>_<Cm>_<op2> bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

## Accessing the S3_<op1>_<Cn>_<Cm>_<op2>

Accesses to this register use the following encodings:

#### MRS <Xt>, S3_<op1>_C<Cn>_C<Cm>_<op2>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b[op1:2:0] | 0b1x11 | 0b[Cm:3:0] | 0b[op2:2:0]

if PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else IMPLEMENTATION_DEFINED ""; else IMPLEMENTATION_DEFINED "";

#### MSR S3_<op1>_C<Cn>_C<Cm>_<op2>, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b[op1:2:0] | 0b1x11 | 0b[Cm:3:0] | 0b[op2:2:0]

if PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else IMPLEMENTATION_DEFINED ""; else IMPLEMENTATION_DEFINED "";

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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