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# ZCR_EL1, SVE Control Register for EL1

The ZCR_EL1 characteristics are:

## Purpose

The SVE Control Register for EL1 is used to control aspects of SVE visible at Exception levels EL1 and EL0.

## Configuration

This register is present only when SVE is implemented. Otherwise, direct accesses to ZCR_EL1 are UNDEFINED.

When HCR_EL2.{E2H, TGE} == {1, 1} and EL2 is enabled in the current Security state, the fields in this register have no effect on execution at EL0

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ZCR_EL1 is a 64-bit register.

## Field descriptions

The ZCR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | RAZ/WI | LEN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:9]

Reserved, RES0.

#### Bits [8:4]

Reserved, RAZ/WI.

#### LEN, bits [3:0]

Constrains the scalable vector register length for EL1 and EL0 to (LEN+1)x128 bits. For all purposes other than returning the result of a direct read of ZCR_EL1 then this field behaves as if it is set to the minimum of the stored value and the constrained length inherited from more privileged Exception levels in the current Security state, rounded down to the nearest implemented vector length.

An indirect read of ZCR_EL1.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.

This field resets to an architecturally UNKNOWN value.

## Accessing the ZCR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ZCR_EL1 or ZCR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

#### MRS <Xt>, ZCR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0001 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.ZEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x1E0]; else return ZCR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); elsif HCR_EL2.E2H == '1' then return ZCR_EL2; else return ZCR_EL1; elsif PSTATE.EL == EL3 then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else return ZCR_EL1;

#### MSR ZCR_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0001 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.ZEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x1E0] = X[t]; else ZCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); elsif HCR_EL2.E2H == '1' then ZCR_EL2 = X[t]; else ZCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t];

#### MRS <Xt>, ZCR_EL12

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b101 | 0b0001 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x1E0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if HCR_EL2.E2H == '0' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else return ZCR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else return ZCR_EL1; else UNDEFINED;

#### MSR ZCR_EL12, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b101 | 0b0001 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x1E0] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if HCR_EL2.E2H == '0' && CPTR_EL2.TZ == '1' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HCR_EL2.E2H == '1' && CPTR_EL2.ZEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x19); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then if CPTR_EL3.EZ == '0' then AArch64.SystemAccessTrap(EL3, 0x19); else ZCR_EL1 = X[t]; else UNDEFINED;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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