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# ERR<n>PFGCTL, Pseudo-fault Generation Control Register, n = 0 - 65534

The ERR<n>PFGCTL characteristics are:

## Purpose

Enables controlled fault generation.

## Configuration

Some or all RW fields of this register have defined reset values.

This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERR<n>PFGCTL are RES0.

Present only when the RAS Common Fault Injection Model Extension is implemented by this node so that ERR<n>FR.INJ != 0b00, error record <n> is implemented, and error record <n> is the first error record owned by a node. Otherwise, RES0.

ERR<n>FR describes the features implemented by the node.

## Attributes

ERR<n>PFGCTL is a 64-bit register.

## Field descriptions

The ERR<n>PFGCTL bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
CDNEN | R | RES0 | MV | AV | PN | ER | CI | CE | DE | UEO | UER | UEU | UC | OF
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### CDNEN, bit [31]

Countdown Enable. Controls transfers from the value that is held in the ERR<n>PFGCDN into the Error Generation Counter, and enables this counter.

CDNEN | Meaning
--- | ---
0b0 | The Error Generation Counter is disabled.
0b1 | The Error Generation Counter is enabled. On a write of 1 to this bit, the Error Generation Counter is set to ERR<n>PFGCDN.CDN.

On a Cold reset, this field resets to 0.

#### R, bit [30]

Restart. Controls whether, on reaching zero, the Error Generation Counter restarts from the ERR<n>PFGCDN value, or stops.

R | Meaning
--- | ---
0b0 | On reaching 0, the Error Generation Counter stops.
0b1 | On reaching 0, the Error Generation Counter is set to ERR<n>PFGCDN.CDN.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### Bits [29:13]

Reserved, RES0.

#### MV, bit [12]

Miscellaneous syndrome. The value that is written to ERR<n>STATUS.MV when an injected error is recorded.

MV | Meaning
--- | ---
0b0 | ERR<n>STATUS.MV is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.MV is set to 1 when an injected error is recorded.

This bit reads-as-one if the node always records some syndrome in ERR<n>MISC<m>, setting ERR<n>STATUS.MV to 1, when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### AV, bit [11]

Address syndrome. The value that is written to ERR<n>STATUS.AV when an injected error is recorded.

AV | Meaning
--- | ---
0b0 | ERR<n>STATUS.AV is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.AV is set to 1 when an injected error is recorded,

This bit reads-as-one if the node always sets ERR<n>STATUS.AV to 1 when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### PN, bit [10]

Poison flag. The value that is written to ERR<n>STATUS.PN when an injected error is recorded.

PN | Meaning
--- | ---
0b0 | ERR<n>STATUS.PN is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.PN is set to 1 when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### ER, bit [9]

Error Reported flag. The value that is written to ERR<n>STATUS.ER when an injected error is recorded.

ER | Meaning
--- | ---
0b0 | ERR<n>STATUS.ER is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.ER is set to 1 when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CI, bit [8]

Critical Error flag. The value that is written to ERR<n>STATUS.CI when an injected error is recorded.

CI | Meaning
--- | ---
0b0 | ERR<n>STATUS.CI is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.CI is set to 1 when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CE, bits [7:6]

Corrected Error generation enable. Controls the type of Corrected Error condition that might be generated.

CE | Meaning
--- | ---
0b00 | No error of this type is generated.
0b01 | A non-specific Corrected Error, that is, a Corrected Error that is recorded as ERR<n>STATUS.CE == 0b10, might be generated when the Error Generation Counter decrements to zero.
0b10 | A transient Corrected Error, that is, a Corrected Error that is recorded as ERR<n>STATUS.CE == 0b01, might be generated when the Error Generation Counter decrements to zero.
0b11 | A persistent Corrected Error, that is, a Corrected Error that is recorded as ERR<n>STATUS.CE == 0b11, might be generated when the Error Generation Counter decrements to zero.

The set of permitted values for this field is defined by ERR<n>PFGF.CE.

This field is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### DE, bit [5]

Deferred Error generation enable. Controls whether this type of error condition might be generated. It is IMPLEMENTATION DEFINED whether the error is generated if the data is not consumed.

DE | Meaning
--- | ---
0b0 | No error of this type is generated.
0b1 | An error of this type might be generated when the Error Generation Counter decrements to zero.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### UEO, bit [4]

Latent or Restartable Error generation enable. Controls whether this type of error condition might be generated. It is IMPLEMENTATION DEFINED whether the error is generated if the data is not consumed.

UEO | Meaning
--- | ---
0b0 | No error of this type is generated.
0b1 | An error of this type might be generated when the Error Generation Counter decrements to zero.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### UER, bit [3]

Signaled or Recoverable Error generation enable. Controls whether this type of error condition might be generated. It is IMPLEMENTATION DEFINED whether the error is generated if the data is not consumed.

UER | Meaning
--- | ---
0b0 | No error of this type is generated.
0b1 | An error of this type might be generated when the Error Generation Counter decrements to zero.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### UEU, bit [2]

Unrecoverable Error generation enable. Controls whether this type of error condition might be generated. It is IMPLEMENTATION DEFINED whether the error is generated if the data is not consumed.

UEU | Meaning
--- | ---
0b0 | No error of this type is generated.
0b1 | An error of this type might be generated when the Error Generation Counter decrements to zero.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### UC, bit [1]

Uncontainable Error generation enable. Controls whether this type of error condition might be generated. It is IMPLEMENTATION DEFINED whether the error is generated if the data is not consumed.

UC | Meaning
--- | ---
0b0 | No error of this type is generated.
0b1 | An error of this type might be generated when the Error Generation Counter decrements to zero.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### OF, bit [0]

Overflow flag. The value that is written to ERR<n>STATUS.OF when an injected error is recorded.

OF | Meaning
--- | ---
0b0 | ERR<n>STATUS.OF is set to 0 when an injected error is recorded.
0b1 | ERR<n>STATUS.OF is set to 1 when an injected error is recorded.

This bit is RES0 if the node does not support this control.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

## Accessing the ERR<n>PFGCTL

#### ERR<n>PFGCTL can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0x808 + 64n | ERR<n>PFGCTL

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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