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# CNTKCTL, Counter-timer Kernel Control register

The CNTKCTL characteristics are:

## Purpose

Controls the generation of an event stream from the virtual counter, and access from EL0 modes to the physical counter, virtual counter, EL1 physical timers, and the virtual timer.

## Configuration

AArch32 System register CNTKCTL bits [31:0] are architecturally mapped to AArch64 System register CNTKCTL_EL1[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

CNTKCTL is a 32-bit register.

## Field descriptions

The CNTKCTL bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PL0PTEN | PL0VTEN | EVNTI | EVNTDIR | EVNTEN | PL0VCTEN | PL0PCTEN

#### Bits [31:10]

Reserved, RES0.

#### PL0PTEN, bit [9]

Traps PL0 accesses to the physical timer registers to Undefined mode.

PL0PTEN | Meaning
--- | ---
0b0 | PL0 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL registers are trapped to Undefined mode.
0b1 | This control does not cause any instructions to be trapped.

This field resets to an architecturally UNKNOWN value.

#### PL0VTEN, bit [8]

Traps PL0 accesses to the virtual timer registers to Undefined mode.

PL0VTEN | Meaning
--- | ---
0b0 | PL0 accesses to the CNTV_CTL, CNTV_CVAL, and CNTV_TVAL registers are trapped to Undefined mode.
0b1 | This control does not cause any instructions to be trapped.

This field resets to an architecturally UNKNOWN value.

#### EVNTI, bits [7:4]

Selects which bit (0 to 15) of the counter register CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled.

This field resets to an architecturally UNKNOWN value.

#### EVNTDIR, bit [3]

Controls which transition of the counter register CNTVCT trigger bit, defined by EVNTI, generates an event when the event stream is enabled:

EVNTDIR | Meaning
--- | ---
0b0 | A 0 to 1 transition of the trigger bit triggers an event.
0b1 | A 1 to 0 transition of the trigger bit triggers an event.

This field resets to an architecturally UNKNOWN value.

#### EVNTEN, bit [2]

Enables the generation of an event stream from the counter register CNTVCT:

EVNTEN | Meaning
--- | ---
0b0 | Disables the event stream.
0b1 | Enables the event stream.

This field resets to an architecturally UNKNOWN value.

#### PL0VCTEN, bit [1]

Traps PL0 accesses to the frequency register and virtual counter register to Undefined mode.

PL0VCTEN | Meaning
--- | ---
0b0 | PL0 accesses to the CNTVCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0PCTEN is also 0.
0b1 | This control does not cause any instructions to be trapped.

This field resets to an architecturally UNKNOWN value.

#### PL0PCTEN, bit [0]

Traps PL0 accesses to the frequency register and physical counter register to Undefined mode.

PL0PCTEN | Meaning
--- | ---
0b0 | PL0 accesses to the CNTPCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0VCTEN is also 0.
0b1 | This control does not cause any instructions to be trapped.

This field resets to an architecturally UNKNOWN value.

## Accessing the CNTKCTL

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1110 | 0b0001 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return CNTKCTL; elsif PSTATE.EL == EL2 then return CNTKCTL; elsif PSTATE.EL == EL3 then return CNTKCTL;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1110 | 0b0001 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then CNTKCTL = R[t]; elsif PSTATE.EL == EL2 then CNTKCTL = R[t]; elsif PSTATE.EL == EL3 then CNTKCTL = R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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