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# ERR<n>MISC1, Error Record Miscellaneous Register 1, n = 0 - 65534

The ERR<n>MISC1 characteristics are:

## Purpose

IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers can contain:

- A Corrected error counter or counters.

- Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.

- Other state information not present in the corresponding status and address registers.

## Configuration

This register is present only when RAS is implemented. Otherwise, direct accesses to ERR<n>MISC1 are UNDEFINED.

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, ERR<n>MISC1 is RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

## Attributes

ERR<n>MISC1 is a 64-bit register.

## Field descriptions

The ERR<n>MISC1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

## Accessing the ERR<n>MISC1

Arm recommends that a miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.

When ERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.

#### ERR<n>MISC1 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0x028 + 64n | ERR<n>MISC1

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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