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# PMCFGR, Performance Monitors Configuration Register

The PMCFGR characteristics are:

## Purpose

Contains PMU-specific configuration data.

## Configuration

PMCFGR is in the Core power domain.

## Attributes

PMCFGR is a 32-bit register.

## Field descriptions

The PMCFGR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NCG | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N

#### NCG, bits [31:28]

This feature is not supported, so this field is RAZ.

#### Bits [27:20]

Reserved, RES0.

#### UEN, bit [19]

User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.

#### WT, bit [18]

This feature is not supported, so this bit is RAZ.

#### NA, bit [17]

This feature is not supported, so this bit is RAZ.

#### EX, bit [16]

Export supported. Value is IMPLEMENTATION DEFINED.

EX | Meaning
--- | ---
0b0 | PMCR_EL0.X is RES0.
0b1 | PMCR_EL0.X is read/write.

#### CCD, bit [15]

Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL, and RAZ otherwise.

CCD | Meaning
--- | ---
0b0 | PMCR_EL0.D is RES0.
0b1 | PMCR_EL0.D is read/write.

#### CC, bit [14]

Dedicated cycle counter (counter 31) supported. This bit is RAO.

#### SIZE, bits [13:8]

Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.

In Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.

This field is used by software to determine the spacing of the counters in the memory-map. In Armv8, the counters are a doubleword-aligned addresses.

#### N, bits [7:0]

Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31.

N | Meaning
--- | ---
0x00 | Only PMCCNTR_EL0 implemented.
0x01 | PMCCNTR_EL0 plus one event counter implemented.

and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented.

## Accessing the PMCFGR

Note

AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

#### PMCFGR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
PMU | 0xE00 | PMCFGR

This interface is accessible as follows:

- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and AllowExternalPMUAccess() access to this register is RO.
- Otherwise access to this register returns an Error.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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