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# TRCBBCTLR, Branch Broadcast Control Register

The TRCBBCTLR characteristics are:

## Purpose

Controls the regions in the memory map where branch broadcasting is active.

## Configuration

External register TRCBBCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCBBCTLR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR0.TRCBB == 0b1, TRCIDR4.NUMACPAIRS > 0b0000 and ETE is implemented. Otherwise, direct accesses to TRCBBCTLR are RES0.

## Attributes

TRCBBCTLR is a 32-bit register.

## Field descriptions

The TRCBBCTLR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | MODE | RANGE<m>, bit [m]

#### Bits [31:9]

Reserved, RES0.

#### MODE, bit [8]

Mode bit.

MODE | Meaning
--- | ---
0b0 | Exclude Mode. Branch broadcasting is not active for instructions in the address ranges defined by RANGE. If RANGE == 0x00 then branch broadcasting is active for all instructions.
0b1 | Include Mode. Branch broadcasting is active for instructions in the address ranges defined by RANGE. If RANGE == 0x00 then the behavior of the trace unit is CONSTRAINED UNPREDICTABLE. That is, the trace unit might or might not consider any instructions to be in a branch broadcasting region.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### RANGE<m>, bit [m], for m = 0 to 7

Address range field.

Selects which Address Range Comparators are in use with branch broadcasting.

RANGE<m> | Meaning
--- | ---
0b0 | The address range that Address Range Comparator m defines, is not selected.
0b1 | The address range that Address Range Comparator m defines, is selected.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCBBCTLR

Must be programmed if TRCCONFIGR.BB == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCBBCTLR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x03C

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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