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# ID_PFR2_EL1, AArch32 Processor Feature Register 2

The ID_PFR2_EL1 characteristics are:

## Purpose

Gives information about the AArch32 programmers' model.

Must be interpreted with ID_PFR0_EL1 and ID_PFR1_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

AArch64 System register ID_PFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR2[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_PFR2_EL1 is a 64-bit register.

## Field descriptions

The ID_PFR2_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | RAS_frac | SSBS | CSV3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:12]

Reserved, RES0.

#### RAS_frac, bits [11:8]
When ARMv8.4-RAS is implemented:

RAS Extension fractional field.

RAS_frac | Meaning
--- | ---
0b0000 | If ID_PFR0_EL1.RAS == 0b0001, RAS Extension implemented.
0b0001 | If ID_PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension.

All other values are reserved.

This field is valid only if ID_PFR0_EL1.RAS == 0b0001.

####
Otherwise:

Reserved, RES0.

#### SSBS, bits [7:4]
From Armv8.5:

Speculative Store Bypassing controls in AArch64 state. Defined values are:

SSBS | Meaning
--- | ---
0b0000 | AArch32 provides no mechanism to control the use of Speculative Store Bypassing.
0b0001 | AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe.

From Armv8.0, the permitted values are 0b0000 and 0b0001.

From Armv8.5, the only permitted value is 0b0001.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### CSV3, bits [3:0]
From Armv8.5:

Speculative use of faulting data. Defined values are:

CSV3 | Meaning
--- | ---
0b0000 | This Device does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the load in the speculative sequence
0b0001 | Data loaded under speculation with a permission or domain fault cannot be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the laod in the speculative sequence

From Armv8.0, the permitted values are 0b0000 and 0b0001.

From Armv8.5, the only permitted value is 0b0001.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_PFR2_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_PFR2_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0011 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_PFR2_EL1; elsif PSTATE.EL == EL2 then return ID_PFR2_EL1; elsif PSTATE.EL == EL3 then return ID_PFR2_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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