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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCDEVARCH, Device Architecture Register

The TRCDEVARCH characteristics are:

## Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

## Configuration

AArch64 System register TRCDEVARCH bits [31:0] are architecturally mapped to External register TRCDEVARCH[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCDEVARCH are UNDEFINED.

## Attributes

TRCDEVARCH is a 64-bit register.

## Field descriptions

The TRCDEVARCH bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
ARCHITECT | PRESENT | REVISION | ARCHVER | ARCHPART
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### ARCHITECT, bits [31:21]

Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.

ARCHITECT | Meaning
--- | ---
0b01000111011 | JEP106 continuation code 0x4, ID code 0x3B. ARM Limited.

Other values are defined by the JEDEC JEP106 standard.

This field reads as 0x23B.

#### PRESENT, bit [20]

DEVARCH Present. Defines that the DEVARCH register is present.

PRESENT | Meaning
--- | ---
0b0 | Device Architecture information not present.
0b1 | Device Architecture information present.

This bit reads as 0b1.

#### REVISION, bits [19:16]

Revision. Defines the architecture revision of the component.

REVISION | Meaning
--- | ---
0b0000 | ETE Version 1.0.

All other values are reserved.

#### ARCHVER, bits [15:12]

Architecture Version. Defines the architecture version of the component.

ARCHVER | Meaning
--- | ---
0b0101 | ETE Version 1.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].

This field reads as 0x5.

#### ARCHPART, bits [11:0]

Architecture Part. Defines the architecture of the component.

ARCHPART | Meaning
--- | ---
0xA13 | Arm PE trace architecture.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].

This field reads as 0xA13.

## Accessing the TRCDEVARCH

External debugger accesses to this register are unaffected by the OS Lock.

Accesses to this register use the following encodings:

#### MRS <Xt>, TRCDEVARCH

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0111 | 0b1111 | 0b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCDEVARCH; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCDEVARCH; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCDEVARCH;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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