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# PMSWINC_EL0, Performance Monitors Software Increment register

The PMSWINC_EL0 characteristics are:

## Purpose

Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D5.

## Configuration

External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMSWINC_EL0[31:0] .

External register PMSWINC_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMSWINC[31:0] .

PMSWINC_EL0 is in the Core power domain.

Implementation of this register is OPTIONAL.

If this register is implemented, use of it is deprecated.

If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface.

## Attributes

PMSWINC_EL0 is a 32-bit register.

## Field descriptions

The PMSWINC_EL0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | P<n>, bit [n]

#### Bit [31]

Reserved, RES0.

#### P<n>, bit [n], for n = 0 to 30

Event counter software increment bit for PMEVCNTR<n>_EL0.

If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are WI.

P<n> | Meaning
--- | ---
0b0 | No action. The write to this bit is ignored.
0b1 | It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter n.

## Accessing the PMSWINC_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

#### PMSWINC_EL0 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
PMU | 0xCA0 | PMSWINC_EL0

This interface is accessible as follows:

- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and SoftwareLockStatus() access to this register is WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus(), AllowExternalPMUAccess() and !SoftwareLockStatus() access to this register is WO.
- Otherwise access to this register returns an Error.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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