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# DBGDEVID, Debug Device ID register 0

The DBGDEVID characteristics are:

## Purpose

Adds to the information given by the DBGDIDR by describing other features of the debug implementation.

## Configuration

This register is required in all implementations.

## Attributes

DBGDEVID is a 32-bit register.

## Field descriptions

The DBGDEVID bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CIDMask | AuxRegs | DoubleLock | VirtExtns | VectorCatch | BPAddrMask | WPAddrMask | PCSample

#### CIDMask, bits [31:28]

Indicates the level of support for the Context ID matching breakpoint masking capability. Permitted values of this field are:

CIDMask | Meaning
--- | ---
0b0000 | Context ID masking is not implemented.
0b0001 | Context ID masking is implemented.

All other values are reserved. The value of this for Armv8 is 0b0000.

#### AuxRegs, bits [27:24]

Indicates support for Auxiliary registers. Permitted values for this field are:

AuxRegs | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Support for External Debug Auxiliary Control Register, EDACR.

All other values are reserved.

#### DoubleLock, bits [23:20]

OS Double Lock implemented. This field indicates the presence of the OS Double Lock and the behavior of the DBGOSDLR, OS Double Lock Register. Permitted values of this field are:

DoubleLock | Meaning
--- | ---
0b0000 | The OS Double Lock is not implemented. DBGOSDLR is RAZ/WI.
0b0001 | The OS Double Lock is implemented. DBGOSDLR is RW.

All other values are reserved.

#### VirtExtns, bits [19:16]

Indicates whether EL2 is implemented. Permitted values of this field are:

VirtExtns | Meaning
--- | ---
0b0000 | EL2 is not implemented.
0b0001 | EL2 is implemented.

All other values are reserved.

#### VectorCatch, bits [15:12]

Defines the form of Vector Catch exception implemented. Permitted values of this field are:

VectorCatch | Meaning
--- | ---
0b0000 | Address matching Vector Catch exception implemented.
0b0001 | Exception matching Vector Catch exception implemented.

All other values are reserved.

#### BPAddrMask, bits [11:8]

Indicates the level of support for the instruction address matching breakpoint masking capability. Permitted values of this field are:

BPAddrMask | Meaning
--- | ---
0b0000 | Breakpoint address masking might be implemented. If not implemented, DBGBCR<n>[28:24] is RAZ/WI.
0b0001 | Breakpoint address masking is implemented.
0b1111 | Breakpoint address masking is not implemented. DBGBCR<n>[28:24] is RES0.

All other values are reserved. The value of this for Armv8 is 0b1111.

#### WPAddrMask, bits [7:4]

Indicates the level of support for the data address matching watchpoint masking capability. Permitted values of this field are:

WPAddrMask | Meaning
--- | ---
0b0000 | Watchpoint address masking might be implemented. If not implemented, DBGWCR<n>.MASK (Address mask) is RAZ/WI.
0b0001 | Watchpoint address masking is implemented.
0b1111 | Watchpoint address masking is not implemented. DBGWCR<n>.MASK (Address mask) is RES0.

All other values are reserved. The value of this for Armv8 is 0b0001.

#### PCSample, bits [3:0]

Indicates the level of PC Sample-based Profiling support using external debug registers. Permitted values of this field are:

PCSample | Meaning
--- | ---
0b0000 | PC Sample-based Profiling Extension is not implemented in the external debug registers space.
0b0010 | Only EDPCSR and EDCIDSR are implemented. This option is only permitted if EL3 and EL2 are not implemented.
0b0011 | EDPCSR, EDCIDSR, and EDVIDSR are implemented.

All other values are reserved.

When ARMv8.2-PCSample is implemented, the only permitted value is 0b0000.

Note

ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMDEVID.PCSample.

## Accessing the DBGDEVID

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1110 | 0b000 | 0b0111 | 0b0010 | 0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDEVID; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDEVID; elsif PSTATE.EL == EL3 then return DBGDEVID;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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