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# CNTID, Counter Identification Register

The CNTID characteristics are:

## Purpose

Indicates whether counter scaling is implemented.

## Configuration

The power domain of CNTID is IMPLEMENTATION DEFINED.

This register is present only when ARMv8.4-CNTSC is implemented. Otherwise, direct accesses to CNTID are RES0.

## Attributes

CNTID is a 32-bit register.

## Field descriptions

The CNTID bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | CNTSC

#### Bits [31:4]

Reserved, RES0.

#### CNTSC, bits [3:0]

Indicates whether Counter Scaling is implemented

CNTSC | Meaning
--- | ---
0b0000 | Counter scaling is not implemented.
0b0001 | Counter scaling is implemented.

All other values are reserved.

## Accessing the CNTID

In a system that supports Secure and Non-secure memory maps, the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.

#### CNTID can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
Timer | CNTControlBase | 0x1C | CNTID

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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