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# ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0

The ID_AA64AFR0_EL1 characteristics are:

## Purpose

Provides information about the IMPLEMENTATION DEFINED features of the PE in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

## Attributes

ID_AA64AFR0_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64AFR0_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### IMPLEMENTATION DEFINED, bits [31:28]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [27:24]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [23:20]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [19:16]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [15:12]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [11:8]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [7:4]

IMPLEMENTATION DEFINED.

#### IMPLEMENTATION DEFINED, bits [3:0]

IMPLEMENTATION DEFINED.

## Accessing the ID_AA64AFR0_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64AFR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0101 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64AFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64AFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64AFR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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