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# GMID_EL1, Multiple tag transfer ID register

The GMID_EL1 characteristics are:

## Purpose

Indicates the block size that is accessed by the LDGM and STGM System instructions.

## Configuration

This register is present only when ARMv8.5-MemTag is implemented. Otherwise, direct accesses to GMID_EL1 are UNDEFINED.

## Attributes

GMID_EL1 is a 64-bit register.

## Field descriptions

The GMID_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | BS
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:4]

Reserved, RES0.

#### BS, bits [3:0]

Log2 of the block size in words. The minimum supported size is 16B (value == 2) and the maximum is 256B (value == 6).

## Accessing the GMID_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, GMID_EL1

CRn | op0 | op1 | op2 | CRm
--- | --- | --- | --- | ---
0b0000 | 0b11 | 0b001 | 0b100 | 0b0000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID5 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return GMID_EL1; elsif PSTATE.EL == EL2 then return GMID_EL1; elsif PSTATE.EL == EL3 then return GMID_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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