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# FPCR, Floating-point Control Register

The FPCR characteristics are:

## Purpose

Controls floating-point behavior.

## Configuration

The named fields in this register map to the equivalent fields in the AArch32 FPSCR.

It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to non-zero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ.

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

FPCR is a 64-bit register.

## Field descriptions

The FPCR bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | AHP | DN | FZ | RMode | Stride | FZ16 | Len | IDE | RES0 | IXE | UFE | OFE | DZE | IOE | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:27]

Reserved, RES0.

#### AHP, bit [26]

Alternative half-precision control bit:

AHP | Meaning
--- | ---
0b0 | IEEE half-precision format selected.
0b1 | Alternative half-precision format selected.

This bit is only used for conversions between half-precision floating-point and other floating-point formats.

The data-processing instructions added as part of the ARMv8.2-FP16 extension always use the IEEE half-precision format, and ignore the value of this bit.

This field resets to an architecturally UNKNOWN value.

#### DN, bit [25]

Default NaN mode control bit:

DN | Meaning
--- | ---
0b0 | NaN operands propagate through to the output of a floating-point operation.
0b1 | Any operation involving one or more NaNs returns the Default NaN.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

This field resets to an architecturally UNKNOWN value.

#### FZ, bit [24]

Flush-to-zero mode control bit:

FZ | Meaning
--- | ---
0b0 | Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
0b1 | Flush-to-zero mode enabled.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

This bit has no effect on half-precision calculations.

This field resets to an architecturally UNKNOWN value.

#### RMode, bits [23:22]

Rounding Mode control field. The encoding of this field is:

RMode | Meaning
--- | ---
0b00 | Round to Nearest (RN) mode.
0b01 | Round towards Plus Infinity (RP) mode.
0b10 | Round towards Minus Infinity (RM) mode.
0b11 | Round towards Zero (RZ) mode.

The specified rounding mode is used by both scalar and Advanced SIMD floating-point instructions.

This field resets to an architecturally UNKNOWN value.

#### Stride, bits [21:20]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Stride field.

This field resets to an architecturally UNKNOWN value.

#### FZ16, bit [19]
When ARMv8.2-FP16 is implemented:

Flush-to-zero mode control bit on half-precision data-processing instructions:

FZ16 | Meaning
--- | ---
0b0 | Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
0b1 | Flush-to-zero mode enabled.

The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations. A half-precision floating-point number that is flushed to zero as a result of the value of the FZ16 bit does not generate an Input Denormal exception.

This field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Len, bits [18:16]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Len field.

This field resets to an architecturally UNKNOWN value.

#### IDE, bit [15]

Input Denormal floating-point exception trap enable. Possible values are:

IDE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IDC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit. The trap handling software can decide whether to set the FPSR.IDC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### Bits [14:13]

Reserved, RES0.

#### IXE, bit [12]

Inexact floating-point exception trap enable. Possible values are:

IXE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IXC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit. The trap handling software can decide whether to set the FPSR.IXC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### UFE, bit [11]

Underflow floating-point exception trap enable. Possible values are:

UFE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.UFC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.UFC bit. The trap handling software can decide whether to set the FPSR.UFC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### OFE, bit [10]

Overflow floating-point exception trap enable. Possible values are:

OFE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.OFC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit. The trap handling software can decide whether to set the FPSR.OFC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### DZE, bit [9]

Divide by Zero floating-point exception trap enable. Possible values are:

DZE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.DZC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit. The trap handling software can decide whether to set the FPSR.DZC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### IOE, bit [8]

Invalid Operation floating-point exception trap enable. Possible values are:

IOE | Meaning
--- | ---
0b0 | Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IOC bit is set to 1.
0b1 | Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit. The trap handling software can decide whether to set the FPSR.IOC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RAZ/WI.

This field resets to an architecturally UNKNOWN value.

#### Bits [7:0]

Reserved, RES0.

## Accessing the FPCR

Accesses to this register use the following encodings:

#### MRS <Xt>, FPCR

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0100 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL1 then if CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPCR;

#### MSR FPCR, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0100 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.FPEN != '11' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL1 then if CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPCR = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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