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# TRCCLAIMCLR, Claim Tag Clear Register

The TRCCLAIMCLR characteristics are:

## Purpose

In conjunction with TRCCLAIMSET, provides Claim Tag bits that can be separately set and cleared to indicate whether functionality is in use by a debug agent.

For additional information see the CoreSight Architecture Specification.

## Configuration

External register TRCCLAIMCLR bits [31:0] are architecturally mapped to AArch64 System register TRCCLAIMCLR[31:0] .

Some or all RW fields of this register have defined reset values.

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCCLAIMCLR are RES0.

## Attributes

TRCCLAIMCLR is a 32-bit register.

## Field descriptions

The TRCCLAIMCLR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CLR<m>, bit [m]

#### CLR<m>, bit [m], for m = 0 to 31

Claim Tag Clear. Indicates the current status of the Claim Tag bit m, and is used to clear Claim Tag bit m to 0b0.

CLR<m> | Meaning
--- | ---
0b0 | On a read: Claim Tag bit m is not set. On a write: Ignored.
0b1 | On a read: Claim Tag bit m is set. On a write: Clear Claim tag bit m to 0b0.

The number of Claim Tag bits implemented is indicated in TRCCLAIMSET.

On a Trace unit reset, this field resets to 0.

## Accessing the TRCCLAIMCLR

#### TRCCLAIMCLR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xFA4

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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