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# LORC_EL1, LORegion Control (EL1)

The LORC_EL1 characteristics are:

## Purpose

Enables and disables LORegions, and selects the current LORegion descriptor.

## Configuration

This register is present only from Armv8.1. Otherwise, direct accesses to LORC_EL1 are UNDEFINED.

If no LORegion descriptors are supported by the PE, then this register is RES0.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

LORC_EL1 is a 64-bit register.

## Field descriptions

The LORC_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | DS | RES0 | EN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:10]

Reserved, RES0.

#### DS, bits [9:2]
From Armv8.1:

Descriptor Select. Selects the current LORegion descriptor accessed by LORSA_EL1, LOREA_EL1, and LORN_EL1.

The number of LORegion descriptors in IMPLEMENTATION DEFINED. The maximum number of LORegion descriptors supported is 256. If the number is less than 256, then bits[63:M+2] are RES0, where M is Log2(Number of LORegion descriptors supported by the implementation).

If this field points to an LORegion descriptor that is not supported by an implementation, then the registers LORN_EL1, LOREA_EL1, and LORSA_EL1 are RES0.

This field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [1]

Reserved, RES0.

#### EN, bit [0]
From Armv8.1:

Enable. Indicates whether LORegions are enabled.

EN | Meaning
--- | ---
0b0 | Disabled. Memory accesses do not match any LORegions.
0b1 | Enabled. Memory accesses may match a LORegion.

This bit is permitted to be cached in a TLB.

This field resets to 0.

####
Otherwise:

Reserved, RES0.

## Accessing the LORC_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, LORC_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0100 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORC_EL1; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORC_EL1; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else return LORC_EL1;

#### MSR LORC_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0100 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORC_EL1 = X[t]; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORC_EL1 = X[t]; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else LORC_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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