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# DBGPRCR_EL1, Debug Power Control Register

The DBGPRCR_EL1 characteristics are:

## Purpose

Controls behavior of the PE on powerdown request.

## Configuration

AArch64 System register DBGPRCR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGPRCR[31:0] .

Bit [0] of this register is mapped to EDPRCR.CORENPDRQ, bit [0] of the external view of this register.

The other bits in these registers are not mapped to each other.

This register is in the Cold reset domain. Some or all RW fields of this register have defined reset values. On a Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.

## Attributes

DBGPRCR_EL1 is a 64-bit register.

## Field descriptions

The DBGPRCR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | CORENPDRQ
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:1]

Reserved, RES0.

#### CORENPDRQ, bit [0]

Core no powerdown request. Requests emulation of powerdown.

This request is typically passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system. The power controller must not allow the Core power domain to switch off while this bit is 1.

CORENPDRQ | Meaning
--- | ---
0b0 | If the system responds to a powerdown request, it powers down Core power domain.
0b1 | If the system responds to a powerdown request, it does not powerdown the Core power domain, but instead emulates a powerdown of that domain.

In an implementation that includes the recommended external debug interface, this bit drives the DBGNOPWRDWN signal.

It is IMPLEMENTATION DEFINED whether this bit is reset to the value of EDPRCR.COREPURQ on exit from an IMPLEMENTATION DEFINED software-visible retention state. For more information about retention states see Core power domain power states.

Note

Writes to this bit are not prohibited by the IMPLEMENTATION DEFINED authentication interface. This means that a debugger can request emulation of powerdown regardless of whether invasive debug is permitted.

On a Cold reset, this field resets to the value in EDPRCR.COREPURQ.

## Accessing the DBGPRCR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, DBGPRCR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b000 | 0b0001 | 0b0100 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDOSA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return DBGPRCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return DBGPRCR_EL1; elsif PSTATE.EL == EL3 then return DBGPRCR_EL1;

#### MSR DBGPRCR_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b000 | 0b0001 | 0b0100 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDOSA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else DBGPRCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else DBGPRCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then DBGPRCR_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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