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# AMCNTENSET1_EL0, Activity Monitors Count Enable Set Register 1

The AMCNTENSET1_EL0 characteristics are:

## Purpose

Enable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>_EL0.

## Configuration

AArch64 System register AMCNTENSET1_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET1[31:0] .

AArch64 System register AMCNTENSET1_EL0 bits [31:0] are architecturally mapped to External register AMCNTENSET1[31:0] .

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET1_EL0 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

AMCNTENSET1_EL0 is a 64-bit register.

## Field descriptions

The AMCNTENSET1_EL0 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
P<n>, bit [n]
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### P<n>, bit [n], for n = 0 to 31

Activity monitor event counter enable bit for AMEVCNTR1<n>_EL0.

Bits [31:N] are RAZ/WI. N is the value in AMCGCR_EL0.CG1NC.

Possible values of each bit are:

P<n> | Meaning
--- | ---
0b0 | When read, means that AMEVCNTR1<n>_EL0 is disabled. When written, has no effect.
0b1 | When read, means that AMEVCNTR1<n>_EL0 is enabled. When written, enables AMEVCNTR1<n>_EL0.

On a Cold reset, this field resets to 0.

## Accessing the AMCNTENSET1_EL0

If the number of auxiliary activity monitor event counters implemented is zero, reads and writes of AMCNTENSET1_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:

- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.

Note

The number of auxiliary activity monitor counters implemented is zero when AMCFGR_EL0.NCG == 0b0000.

Accesses to this register use the following encodings:

#### MRS <Xt>, AMCNTENSET1_EL0

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1101 | 0b0011 | 0b001

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMCNTENSET1_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMCNTENSET1_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return AMCNTENSET1_EL0; elsif PSTATE.EL == EL3 then return AMCNTENSET1_EL0;

#### MSR AMCNTENSET1_EL0, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1101 | 0b0011 | 0b001

if IsHighestEL(PSTATE.EL) then AMCNTENSET1_EL0 = X[t]; else UNDEFINED;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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