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# PAN, Privileged Access Never

The PAN characteristics are:

## Purpose

Allows access to the Privileged Access Never bit.

## Configuration

This register is present only when ARMv8.1-PAN is implemented. Otherwise, direct accesses to PAN are UNDEFINED.

## Attributes

PAN is a 64-bit register.

## Field descriptions

The PAN bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | PAN | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:23]

Reserved, RES0.

#### PAN, bit [22]

Privileged Access Never.

PAN | Meaning
--- | ---
0b0 | The translation system is the same as Armv8.0.
0b1 | Disables privileged read and write accesses to addresses accessible at EL0.

The value of this bit is usually preserved on taking an exception, except in the following situations:

- When the target of the exception is EL1, and the value of the SCTLR_EL1.SPAN bit is 0, this bit is set to 1.
- When the target of the exception is EL2, HCR_EL2.{E2H, TGE} is {1, 1}, and the value of the SCTLR_EL2.SPAN bit is 0, this bit is set to 1.

#### Bits [21:0]

Reserved, RES0.

## Accessing the PAN

For details on the operation of the MSR (immediate) accessor, see MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Accesses to this register use the following encodings:

#### MRS <Xt>, PAN

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0100 | 0b0010 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return Zeros(41):PSTATE.PAN:Zeros(22); elsif PSTATE.EL == EL2 then return Zeros(41):PSTATE.PAN:Zeros(22); elsif PSTATE.EL == EL3 then return Zeros(41):PSTATE.PAN:Zeros(22);

#### MSR PAN, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0100 | 0b0010 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PSTATE.PAN = X[t]<22>; elsif PSTATE.EL == EL2 then PSTATE.PAN = X[t]<22>; elsif PSTATE.EL == EL3 then PSTATE.PAN = X[t]<22>;

#### MSR PAN, #<imm>

op0 | op1 | CRn | op2
--- | --- | --- | ---
0b00 | 0b000 | 0b0100 | 0b100

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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