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# ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1

The ID_AA64MMFR1_EL1 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

## Attributes

ID_AA64MMFR1_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64MMFR1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### XNX, bits [31:28]
From Armv8.2:

Support for execute-never control distinction by Exception level at stage 2. Defined values are:

XNX | Meaning
--- | ---
0b0000 | Distinction between EL0 and EL1 execute-never control at stage 2 not supported.
0b0001 | Distinction between EL0 and EL1 execute-never control at stage 2 supported.

All other values are reserved.

ARMv8.2-TTS2UXN implements the functionality identified by the value 0b0001.

From Armv8.2, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### SpecSEI, bits [27:24]
When RAS is implemented:

Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:

SpecSEI | Meaning
--- | ---
0b0000 | The PE never generates an SError interrupt due to an External abort on a speculative read.
0b0001 | The PE might generate an SError interrupt due to an External abort on a speculative read.

All other values are reserved.

####
Otherwise:

Reserved, RES0. This provides no information about whether the PE generates a speculative SError interrupt.

#### PAN, bits [23:20]
From Armv8.1:

Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. Defined values are:

PAN | Meaning
--- | ---
0b0000 | PAN not supported.
0b0001 | PAN supported.
0b0010 | PAN supported and AT S1E1RP and AT S1E1WP instructions supported.

All other values are reserved.

ARMv8.1-PAN implements the functionality identified by the value 0b0001.

ARMv8.2-ATS1E1 implements the functionality added by the value 0b0010.

In Armv8.1, the only permitted value is 0b0001.

From Armv8.2, the only permitted value is 0b0010.

####
Otherwise:

Reserved, RES0.

#### LO, bits [19:16]
From Armv8.1:

LORegions. Indicates support for LORegions. Defined values are:

LO | Meaning
--- | ---
0b0000 | LORegions not supported.
0b0001 | LORegions supported.

All other values are reserved.

ARMv8.1-LOR implements the functionality identified by the value 0b0001.

From Armv8.1, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### HPDS, bits [15:12]
From Armv8.1:

Hierarchical permission disables bits in translation tables. Defined values are:

HPDS | Meaning
--- | ---
0b0000 | Disabling of hierarchical controls not supported.
0b0001 | Disabling of hierarchical controls supported with the TCR_EL1.{HPD1, HPD0}, TCR_EL2.HPD or TCR_EL2.{HPD1, HPD0}, and TCR_EL3.HPD bits.
0b0010 | As for value 0b0001, and adds possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level for IMPLEMENTATION DEFINED use.

All other values are reserved.

ARMv8.1-HPD implements the functionality identified by the value 0b0001.

ARMv8.2-TTPBHA implements the functionality identified by the value 0b0010.

From Armv8.1, the value 0b0000 is not permitted.

####
Otherwise:

Reserved, RES0.

#### VH, bits [11:8]
From Armv8.1:

Virtualization Host Extensions. Defined values are:

VH | Meaning
--- | ---
0b0000 | Virtualization Host Extensions not supported.
0b0001 | Virtualization Host Extensions supported.

All other values are reserved.

ARMv8.1-VHE implements the functionality identified by the value 0b0001.

From Armv8.1, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### VMIDBits, bits [7:4]
From Armv8.1:

Number of VMID bits. Defined values are:

VMIDBits | Meaning
--- | ---
0b0000 | 8 bits
0b0010 | 16 bits

All other values are reserved.

ARMv8.1-VMID16 implements the functionality identified by the value 0b0010.

From Armv8.1, the permitted values are 0b0000 and 0b0010.

####
Otherwise:

Reserved, RES0.

#### HAFDBS, bits [3:0]
From Armv8.1:

Hardware updates to Access flag and Dirty state in translation tables. Defined values are:

HAFDBS | Meaning
--- | ---
0b0000 | Hardware update of the Access flag and dirty state are not supported.
0b0001 | Hardware update of the Access flag is supported.
0b0010 | Hardware update of both the Access flag and dirty state is supported.

All other values are reserved.

ARMv8.1-TTHM implements the functionality identified by the values 0b0001 and 0b0010.

From Armv8.1, the permitted values are 0b0000, 0b0001, and 0b0010.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_AA64MMFR1_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64MMFR1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0111 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64MMFR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64MMFR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64MMFR1_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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