AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# CTIDEVARCH, CTI Device Architecture register

The CTIDEVARCH characteristics are:

## Purpose

Identifies the programmers' model architecture of the CTI component.

If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory.

Arm recommends that the CTI is CTIv2.

In an Armv8.5 compliant implementation the CTI must be CTIv2.

If this register is not implemented, CTIDEVAFF0 and CTIDEVAFF1 are also not implemented.

## Configuration

CTIDEVARCH is in the Debug power domain.

Implementation of this register is OPTIONAL.

## Attributes

CTIDEVARCH is a 32-bit register.

## Field descriptions

The CTIDEVARCH bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ARCHITECT | PRESENT | REVISION | ARCHID

#### ARCHITECT, bits [31:21]

Defines the architecture of the component. For CTI, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0x4.

Bits [27:21] are the JEP106 ID code, 0x3B.

#### PRESENT, bit [20]

When set to 1, indicates that the DEVARCH is present.

This field is 1 in Armv8.

#### REVISION, bits [19:16]

Revision.

Defines the architecture revision of the component.

REVISION | Meaning | Applies when
--- | --- | ---
0b0000 | First revision.
0b0001 | As 0b0000, and also adds support for CTIDEVCTL. | When ARMv8.3-DoPD is implemented

All other values are reserved.

#### ARCHID, bits [15:0]

Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.

For CTI:

- Bits [15:12] are the architecture version, 0x1.
- Bits [11:0] are the architecture part number, 0xA14.

This corresponds to CTI architecture version CTIv2.

## Accessing the CTIDEVARCH

#### CTIDEVARCH can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0xFBC | CTIDEVARCH

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.