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# MPIDR, Multiprocessor Affinity Register

The MPIDR characteristics are:

## Purpose

In a multiprocessor system, provides an additional PE identification mechanism for scheduling purposes.

## Configuration

AArch32 System register MPIDR bits [31:0] are architecturally mapped to AArch64 System register MPIDR_EL1[31:0] .

In a uniprocessor system Arm recommends that each Aff<n> field of this register returns a value of 0.

## Attributes

MPIDR is a 32-bit register.

## Field descriptions

The MPIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
M | U | RES0 | MT | Aff2 | Aff1 | Aff0

#### M, bit [31]

Indicates whether this implementation includes the functionality introduced by the ARMv7 Multiprocessing Extensions. The possible values of this bit are:

M | Meaning
--- | ---
0b0 | This implementation does not include the ARMv7 Multiprocessing Extensions functionality.
0b1 | This implementation includes the ARMv7 Multiprocessing Extensions functionality.

In Armv8, this bit is RAO.

#### U, bit [30]

Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:

U | Meaning
--- | ---
0b0 | Processor is part of a multiprocessor system.
0b1 | Processor is part of a uniprocessor system.

#### Bits [29:25]

Reserved, RES0.

#### MT, bit [24]

Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels. The possible values of this bit are:

MT | Meaning
--- | ---
0b0 | Performance of PEs at the lowest affinity level is largely independent.
0b1 | Performance of PEs at the lowest affinity level is very interdependent.

#### Aff2, bits [23:16]

Affinity level 2. See the description of Aff0 for more information.

#### Aff1, bits [15:8]

Affinity level 1. See the description of Aff0 for more information.

#### Aff0, bits [7:0]

Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.

## Accessing the MPIDR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) then return VMPIDR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) then return VMPIDR; else return MPIDR; elsif PSTATE.EL == EL2 then return MPIDR; elsif PSTATE.EL == EL3 then return MPIDR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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