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# IC IALLU, Instruction Cache Invalidate All to PoU

The IC IALLU characteristics are:

## Purpose

Invalidate all instruction caches to Point of Unification.

## Configuration

AArch64 System instruction IC IALLU performs the same function as AArch32 System instruction ICIALLU.

## Attributes

IC IALLU is a 64-bit System instruction.

## Field descriptions

IC IALLU ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

## Executing the IC IALLU instruction

Accesses to this instruction use the following encodings:

#### IC IALLU{, <Xt>}

op0 | op1 | CRn | CRm | op2 | Rt
--- | --- | --- | --- | --- | ---
0b01 | 0b000 | 0b0111 | 0b0101 | 0b000 | 0b11111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TOCU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FB == '1' then IC_IALLUIS(); else IC_IALLU(); elsif PSTATE.EL == EL2 then IC_IALLU(); elsif PSTATE.EL == EL3 then IC_IALLU();

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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