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# ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1

The ICV_BPR1_EL1 characteristics are:

## Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines virtual Group 1 interrupt preemption.

## Configuration

AArch64 System register ICV_BPR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ICV_BPR1[31:0] .

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ICV_BPR1_EL1 is a 64-bit register.

## Field descriptions

The ICV_BPR1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | BinaryPoint
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:3]

Reserved, RES0.

#### BinaryPoint, bits [2:0]

If the GIC is configured to use separate binary point fields for virtual Group 0 and virtual Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:

Binary point value | Group priority field | Subpriority field | Field with binary point
--- | --- | --- | ---
0 | - | - | -
1 | [7:1] | [0] | ggggggg.s
2 | [7:2] | [1:0] | gggggg.ss
3 | [7:3] | [2:0] | ggggg.sss
4 | [7:4] | [3:0] | gggg.ssss
5 | [7:5] | [4:0] | ggg.sssss
6 | [7:6] | [5:0] | gg.ssssss
7 | [7] | [6:0] | g.sssssss

Writing 0 to this field will set this field to its reset value.

If ICV_CTLR_EL1.CBPR is set to 1, Non-secure EL1 reads return ICV_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL1 writes are ignored.

If ICV_CTLR_EL1.CBPR is set to 1, Secure EL1 reads return ICV_BPR0_EL1. Secure EL1 writes modify ICV_BPR0_EL1.

This field resets to an IMPLEMENTATION DEFINED non-zero value.

## Accessing the ICV_BPR1_EL1

The reset value is IMPLEMENTATION DEFINED, but is equal to the minimum value of ICV_BPR0_EL1 plus one.

An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.

Accesses to this register use the following encodings:

#### MRS <Xt>, ICC_BPR1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1100 | 0b1100 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then return ICV_BPR1_EL1; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_BPR1_EL1_S; else return ICC_BPR1_EL1_NS; else return ICC_BPR1_EL1; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_BPR1_EL1_S; else return ICC_BPR1_EL1_NS; else return ICC_BPR1_EL1; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x03); else if SCR_EL3.NS == '0' then return ICC_BPR1_EL1_S; else return ICC_BPR1_EL1_NS;

#### MSR ICC_BPR1_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1100 | 0b1100 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_BPR1_EL1 = X[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_BPR1_EL1_S = X[t]; else ICC_BPR1_EL1_NS = X[t]; else ICC_BPR1_EL1 = X[t]; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_BPR1_EL1_S = X[t]; else ICC_BPR1_EL1_NS = X[t]; else ICC_BPR1_EL1 = X[t]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x03); else if SCR_EL3.NS == '0' then ICC_BPR1_EL1_S = X[t]; else ICC_BPR1_EL1_NS = X[t];

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15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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