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# ISR_EL1, Interrupt Status Register

The ISR_EL1 characteristics are:

## Purpose

Shows the pending status of the IRQ, FIQ, or SError interrupt.

When executing at EL2, EL3 or Secure EL1 when SCR_EL3.EEL2 == 0b0, this shows the pending status of the physical IRQ, FIQ, or SError interrupts.

When executing at either Non-secure EL1 or at Secure EL1 when SCR_EL3.EEL2 == 0b1:

- If the HCR_EL2.{IMO,FMO,AMO} bit has a value of 1, the corresponding ISR_EL1.{I,F,A} bit shows the pending status of the virtual IRQ, FIQ, or SError.
- If the HCR_EL2.{IMO,FMO,AMO} bit has a value of 0, the corresponding ISR_EL1.{I,F,A} bit shows the pending status of the physical IRQ, FIQ, or SError.

## Configuration

AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ISR[31:0] .

## Attributes

ISR_EL1 is a 64-bit register.

## Field descriptions

The ISR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | A | I | F | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:9]

Reserved, RES0.

#### A, bit [8]

SError interrupt pending bit.

A | Meaning
--- | ---
0b0 | No pending SError.
0b1 | An SError interrupt is pending.

If the SError interrupt is edge-triggered, this field is cleared to zero when the physical SError interrupt is taken.

#### I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

I | Meaning
--- | ---
0b0 | No pending IRQ.
0b1 | An IRQ interrupt is pending.

#### F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

F | Meaning
--- | ---
0b0 | No pending FIQ.
0b1 | An FIQ interrupt is pending.

#### Bits [5:0]

Reserved, RES0.

## Accessing the ISR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ISR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1100 | 0b0001 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return ISR_EL1; elsif PSTATE.EL == EL2 then return ISR_EL1; elsif PSTATE.EL == EL3 then return ISR_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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