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# MIDR, Main ID Register

The MIDR characteristics are:

## Purpose

Provides identification information for the PE, including an implementer code for the device and a device ID number.

## Configuration

AArch32 System register MIDR bits [31:0] are architecturally mapped to AArch64 System register MIDR_EL1[31:0] .

AArch32 System register MIDR bits [31:0] are architecturally mapped to External register MIDR_EL1[31:0] .

Some fields of the MIDR are IMPLEMENTATION DEFINED. For details of the values of these fields for a particular Armv8 implementation, and any implementation-specific significance of these values, see the product documentation.

## Attributes

MIDR is a 32-bit register.

## Field descriptions

The MIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Implementer | Variant | Architecture | PartNum | Revision

#### Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:

Hex representation | Implementer
--- | ---
0x00 | Reserved for software use
0xC0 | Ampere Computing
0x41 | Arm Limited
0x42 | Broadcom Corporation
0x43 | Cavium Inc.
0x44 | Digital Equipment Corporation
0x49 | Infineon Technologies AG
0x4D | Motorola or Freescale Semiconductor Inc.
0x4E | NVIDIA Corporation
0x50 | Applied Micro Circuits Corporation
0x51 | Qualcomm Inc.
0x56 | Marvell International Ltd.
0x69 | Intel Corporation

Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.

#### Variant, bits [23:20]

An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

#### Architecture, bits [19:16]

The permitted values of this field are:

Architecture | Meaning
--- | ---
0b0001 | Armv4.
0b0010 | Armv4T.
0b0011 | Armv5 (obsolete).
0b0100 | Armv5T.
0b0101 | Armv5TE.
0b0110 | Armv5TEJ.
0b0111 | Armv6.
0b1111 | Architectural features are individually identified in the ID_* registers, see 'ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K12.5.3.

All other values are reserved.

#### PartNum, bits [15:4]

An IMPLEMENTATION DEFINED primary part number for the device.

On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

#### Revision, bits [3:0]

An IMPLEMENTATION DEFINED revision number for the device.

## Accessing the MIDR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) then return VPIDR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) then return VPIDR; else return MIDR; elsif PSTATE.EL == EL2 then return MIDR; elsif PSTATE.EL == EL3 then return MIDR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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