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# GICV_STATUSR, Virtual Machine Error Reporting Status Register

The GICV_STATUSR characteristics are:

## Purpose

Provides software with a mechanism to detect:

- Accesses to reserved locations.
- Writes to read-only locations.
- Reads of write-only locations.

## Configuration

In systems where this register is implemented, Arm expects that when a virtual machine is scheduled, the hypervisor ensures that this register is cleared to 0. The hypervisor might check for illegal accesses when the virtual machine is unscheduled.

## Attributes

GICV_STATUSR is a 32-bit register.

## Field descriptions

The GICV_STATUSR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | WROD | RWOD | WRD | RRD

#### Bits [31:4]

Reserved, RES0.

#### WROD, bit [3]

Write to an RO location.

WROD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### RWOD, bit [2]

Read of a WO location.

RWOD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### WRD, bit [1]

Write to a reserved location.

WRD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### RRD, bit [0]

Read of a reserved location.

RRD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

## Accessing the GICV_STATUSR

This is an optional register. If the register is implemented, GICC_STATUSR must also be implemented. If the register is not implemented, the location is RAZ/WI.

This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent function might be provided by appropriate traps and exceptions.

#### GICV_STATUSR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual CPU interface | 0x002C | GICV_STATUSR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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