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# AMCIDR2, Activity Monitors Component Identification Register 2

The AMCIDR2 characteristics are:

## Purpose

Provides information to identify an activity monitors component.

For more information, see About the Component identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

## Configuration

The power domain of AMCIDR2 is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMCIDR2 are RES0.

## Attributes

AMCIDR2 is a 32-bit register.

## Field descriptions

The AMCIDR2 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PRMBL_2

#### Bits [31:8]

Reserved, RES0.

#### PRMBL_2, bits [7:0]

Preamble. Reads as 0x05.

## Accessing the AMCIDR2

#### AMCIDR2 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
AMU | 0xFF8 | AMCIDR2

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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