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# CNTACR<n>, Counter-timer Access Control Registers, n = 0 - 7

The CNTACR<n> characteristics are:

## Purpose

Provides top-level access controls for the elements of a timer frame. CNTACR<n> provides the controls for frame CNTBaseN.

In addition to the CNTACR<n> control:

- CNTNSAR controls whether CNTACR<n> is accessible by Non-secure accesses.
- If frame CNTEL0BaseN is implemented, the CNTEL0ACR in frame CNTBaseN provides additional control of accesses to frame CNTEL0BaseN.

## Configuration

The power domain of CNTACR<n> is IMPLEMENTATION DEFINED.

On a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Implemented only if the value of CNTTIDR.Frame<n> is 1.

An implementation of the counters might not provide configurable access to some or all of the features. In this case, the associated field in the CNTACR<n> register is:

- RAZ/WI if access is always denied.
- RAO/WI if access is always permitted.

## Attributes

CNTACR<n> is a 32-bit register.

## Field descriptions

The CNTACR<n> bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | RWPT | RWVT | RVOFF | RFRQ | RVCT | RPCT

#### Bits [31:6]

Reserved, RES0.

#### RWPT, bit [5]

Read/write access to the EL1 Physical Timer registers CNTP_CVAL, CNTP_TVAL, and CNTP_CTL, in frame <n>. The possible values of this bit are:

RWPT | Meaning
--- | ---
0b0 | No access to the EL1 Physical Timer registers in frame <n>. The registers are RES0.
0b1 | Read/write access to the EL1 Physical Timer registers in frame <n>.

This field resets to an architecturally UNKNOWN value.

#### RWVT, bit [4]

Read/write access to the Virtual Timer register CNTV_CVAL, CNTV_TVAL, and CNTV_CTL, in frame <n>. The possible values of this bit are:

RWVT | Meaning
--- | ---
0b0 | No access to the Virtual Timer registers in frame <n>. The registers are RES0.
0b1 | Read/write access to the Virtual Timer registers in frame <n>.

This field resets to an architecturally UNKNOWN value.

#### RVOFF, bit [3]

Read-only access to CNTVOFF, in frame <n>. The possible values of this bit are:

RVOFF | Meaning
--- | ---
0b0 | No access to CNTVOFF in frame <n>. The register is RES0.
0b1 | Read-only access to CNTVOFF in frame <n>.

This field resets to an architecturally UNKNOWN value.

#### RFRQ, bit [2]

Read-only access to CNTFRQ, in frame <n>. The possible values of this bit are:

RFRQ | Meaning
--- | ---
0b0 | No access to CNTFRQ in frame <n>. The register is RES0.
0b1 | Read-only access to CNTFRQ in frame <n>.

This field resets to an architecturally UNKNOWN value.

#### RVCT, bit [1]

Read-only access to CNTVCT, in frame <n>. The possible values of this bit are:

RVCT | Meaning
--- | ---
0b0 | No access to CNTVCT in frame <n>. The register is RES0.
0b1 | Read-only access to CNTVCT in frame <n>.

This field resets to an architecturally UNKNOWN value.

#### RPCT, bit [0]

Read-only access to CNTPCT, in frame <n>. The possible values of this bit are:

RPCT | Meaning
--- | ---
0b0 | No access to CNTPCT in frame <n>. The register is RES0.
0b1 | Read-only access to CNTPCT in frame <n>.

This field resets to an architecturally UNKNOWN value.

## Accessing the CNTACR<n>

In a system that recognizes two Security states:

- CNTACR<n> is always accessible by Secure accesses.
- CNTNSAR.NS<n> determines whether CNTACR<n> is accessible by Non-secure accesses.

#### CNTACR<n> can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
Timer | CNTCTLBase | 0x040 + 4n | CNTACR<n>

Access on this interface is RW.

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27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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