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# EDDFR, External Debug Feature Register

The EDDFR characteristics are:

## Purpose

Provides top level information about the debug system.

Note

Debuggers must use EDDEVARCH to determine the Debug architecture version.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

## Configuration

It is IMPLEMENTATION DEFINED whether EDDFR is implemented in the Core power domain or in the Debug power domain.

## Attributes

EDDFR is a 64-bit register.

## Field descriptions

The EDDFR bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | TraceFilt | UNKNOWN
CTX_CMPs | RES0 | WRPs | RES0 | BRPs | PMUVer | TraceVer | UNKNOWN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:44]

Reserved, RES0.

#### TraceFilt, bits [43:40]
When ARMv8.4-Trace is implemented:

Armv8.4 Self-hosted Trace Extension version. The defined values of this field are:

TraceFilt | Meaning
--- | ---
0b0000 | Armv8.4 Self-hosted Trace Extension is not implemented.
0b0001 | Armv8.4 Self-hosted Trace Extension is implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### Bits [39:32]

Reserved, UNKNOWN.

#### CTX_CMPs, bits [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.CTX_CMPs.

#### Bits [27:24]

Reserved, RES0.

#### WRPs, bits [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.WRPs.

#### Bits [19:16]

Reserved, RES0.

#### BRPs, bits [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.BRPs.

#### PMUVer, bits [11:8]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the Alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.1.4.

Defined values are:

PMUVer | Meaning
--- | ---
0b0000 | Performance Monitors Extension not implemented.
0b0001 | Performance Monitors Extension implemented, PMUv3.
0b0100 | PMUv3 for Armv8.1. As 0b0001, and also includes support for: Extended 16-bit PMEVTYPER<n>_EL0.evtCount field. If EL2 is implemented, the MDCR_EL2.HPMD control bit.
0b0101 | PMUv3 for Armv8.4. As 0b0100 and also includes support for the PMMIR register.
0b0110 | PMUv3 for Armv8.5. As 0b0101 and also includes support for: 64-bit event counters. If EL2 is implemented, the MDCR_EL2.HCCD control bit. If EL3 is implemented, the MDCR_EL3.SCCD control bit.
0b1111 | IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value in new implementations.

ARMv8.1-PMU implements the functionality added by the value 0b0100.

ARMv8.4-PMU implements the functionality added by the value 0b0101.

ARMv8.5-PMU implements the functionality added by the value 0b0110.

All other values are reserved.

From Armv8.1, the value 0b0001 is not permitted.

From Armv8.4, the value 0b0100 is not permitted.

From Armv8.5, the value 0b0101 is not permitted.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.PMUVer.

#### TraceVer, bits [7:4]

Trace support. Indicates whether System register interface to a PE trace unit is implemented. Defined values are:

TraceVer | Meaning
--- | ---
0b0000 | PE trace unit System registers not implemented.
0b0001 | PE trace unit System registers implemented.

All other values are reserved.

A value of 0b0000 only indicates that no System register interface to a PE trace unit is implemented. A PE trace unit might nevertheless be implemented without a System register interface.

In an Armv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.TraceVer.

#### Bits [3:0]

Reserved, UNKNOWN.

## Accessing the EDDFR

#### EDDFR can be accessed through the external debug interface:

Component | Offset | Instance | Range
--- | --- | --- | ---
Debug | 0xD28 | EDDFR | 31:0

This interface is accessible as follows:

- When IsCorePowered() and !DoubleLockStatus() access to this register is RO.
- Otherwise access to this register is IMPDEF.

Component | Offset | Instance | Range
--- | --- | --- | ---
Debug | 0xD2C | EDDFR | 63:32

This interface is accessible as follows:

- When IsCorePowered() and !DoubleLockStatus() access to this register is RO.
- Otherwise access to this register is IMPDEF.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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