AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# GICC_STATUSR, CPU Interface Status Register

The GICC_STATUSR characteristics are:

## Purpose

Provides software with a mechanism to detect:

- Accesses to reserved locations.
- Writes to read-only locations.
- Reads of write-only locations.

## Configuration

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions.

## Attributes

GICC_STATUSR is a 32-bit register.

## Field descriptions

The GICC_STATUSR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | ASV | WROD | RWOD | WRD | RRD

#### Bits [31:5]

Reserved, RES0.

#### ASV, bit [4]

Attempted security violation.

ASV | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A Non-secure access to a Secure register has been detected.

Note

This bit is not set to 1 for registers where any of the fields are Non-secure.

#### WROD, bit [3]

Write to an RO location.

WROD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### RWOD, bit [2]

Read of a WO location.

RWOD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### WRD, bit [1]

Write to a reserved location.

WRD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

#### RRD, bit [0]

Read of a reserved location.

RRD | Meaning
--- | ---
0b0 | Normal operation.
0b1 | A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

## Accessing the GICC_STATUSR

This is an optional register. If the register is not implemented, the location is RAZ/WI.

If this register is implemented, GICV_STATUSR must also be implemented.

#### GICC_STATUSR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC CPU interface | 0x002C | GICC_STATUSR (S)

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.

Component | Offset | Instance
--- | --- | ---
GIC CPU interface | 0x002C | GICC_STATUSR (NS)

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When !IsAccessSecure() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.