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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# SCTLR_EL3, System Control Register (EL3)

The SCTLR_EL3 characteristics are:

## Purpose

Provides top level control of the system, including its memory system, at EL3.

## Configuration

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

SCTLR_EL3 is a 64-bit register.

## Field descriptions

The SCTLR_EL3 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | TME DSSBS | RES0 ATA | TMT RES0 | RES0 TCF | DSSBS RES0 | ATA ITFSB | RES0 BT | TCF RES0 | RES0 | ITFSB | BT | RES0
EnIA | EnIB | RES1 | EnDA | RES0 | EE | RES0 | RES1 | EIS | IESB | RES0 | WXN | RES1 | RES0 | RES1 | RES0 | EnDB | I | EOS | RES0 | nAA | RES1 | SA | C | A | M
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:54 45]

Reserved, RES0.

#### TME, bit [53]
When TME is implemented:

Enables the Transactional Memory Extension at EL3.

TME | Meaning
--- | ---
0b0 | Any attempt to execute a TSTART instruction at EL3 is trapped, unless HCR_EL2.TME or SCR_EL3.TME causes TSTART instructions to be UNDEFINED at EL3.
0b1 | This control does not cause any TSTART instruction to be trapped.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [52]

Reserved, RES0.

#### TMT, bit [51]
When TME is implemented:

Forces a trivial implementation of the Transactional Memory Extension at EL3.

TMT | Meaning
--- | ---
0b0 | This control does not cause any TSTART instruction to fail.
0b1 | When the TSTART instruction is executed at EL3, the transaction fails with a TRIVIAL failure cause.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [50:45]

Reserved, RES0.

#### DSSBS, bit [44]
From Armv8.5:

Default PSTATE.SSBS value on Exception Entry. The defined values are:

DSSBS | Meaning
--- | ---
0b0 | PSTATE.SSBS is set to 0 on an exception to EL3
0b1 | PSTATE.SSBS is set to 1 on an exception to EL3

In a system where the PE resets into EL3, this field resets to an IMPLEMENTATION DEFINED value.

####
Otherwise:

Reserved, RES0.

#### ATA, bit [43]
When ARMv8.5-MemTag is implemented:

Allocation Tag Access in EL3. Controls EL3 access to Allocation Tags.

When access to Allocation Tags is prevented:

- Instructions which Load or Store data are Unchecked.

- Instructions which Load or Store Allocation Tags treat the Allocation Tag as RAZ/WI.

- Instructions which insert Logical Address Tags into addresses treat the Allocation Tag used to generate the Logical Address Tag as 0.

- Cache maintenance instructions which invalidate Allocation Tags from caches behave as the equivalent Clean and Invalidate operation on Allocation Tags.

ATA | Meaning
--- | ---
0b0 | Access to Allocation Tags is prevented.
0b1 | Access to Allocation Tags is not prevented.

This bit is permitted to be cached in a TLB.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [42]

Reserved, RES0.

#### TCF, bits [41:40]
When ARMv8.5-MemTag is implemented:

Tag Check Fail in EL3. Controls the effect of tag check fails due to Loads and Stores in EL3.

TCF | Meaning
--- | ---
0b00 | Tag check fails have no effect on the PE.
0b01 | Tag check fails causes a synchronous exception.
0b10 | Tag check fails are asynchronously accumulated.

The value 0b11 is reserved.

This field is permitted to be cached in a TLB.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [39:38]

Reserved, RES0.

#### ITFSB, bit [37]
When ARMv8.5-MemTag is implemented:

When asynchronous exceptions are being generated by Tag Check fails which are generated for Loads and Stores at any exception level, controls the auto-synchronisaton of Tag Check fails into TFSRE0_EL1 and TFSR_ELx.

ITFSB | Meaning
--- | ---
0b0 | Tag check fails are not synchronized on entry to EL3.
0b1 | Tag check fails are synchronized on entry to EL3.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### BT, bit [36]
When ARMv8.5-BTI is implemented:

PAC Branch Type compatibility at EL3.

BT | Meaning
--- | ---
0b0 | When the PE is executing at EL3, PACIASP and PACIBSP are compatible with PSTATE.BTYPE == 0b11.
0b1 | When the PE is executing at EL3, PACIASP and PACIBSP are not compatible with PSTATE.BTYPE == 0b11.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [35:32]

Reserved, RES0.

#### EnIA, bit [31]
From Armv8.3:

Controls enabling of pointer authentication (using the APIAKey_EL1 key) of instruction addresses in the EL3 translation regime.

Possible values of this bit are:

EnIA | Meaning
--- | ---
0b0 | Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is not enabled.
0b1 | Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is enabled.

Note

This field controls the behavior of the AddPACIA and AuthIA pseudocode functions. Specifically, when the field is 1, AddPACIA returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EnIB, bit [30]
From Armv8.3:

Controls enabling of pointer authentication (using the APIBKey_EL1 key) of instruction addresses in the EL3 translation regime.

Possible values of this bit are:

EnIB | Meaning
--- | ---
0b0 | Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is not enabled.
0b1 | Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is enabled.

Note

This field controls the behavior of the AddPACIB and AuthIB pseudocode functions. Specifically, when the field is 1, AddPACIB returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [29:28]

Reserved, RES1.

#### EnDA, bit [27]
From Armv8.3:

Controls enabling of pointer authentication (using the APDAKey_EL1 key) of instruction addresses in the EL3 translation regime.

EnDA | Meaning
--- | ---
0b0 | Pointer authentication (using the APDAKey_EL1 key) of data addresses is not enabled.
0b1 | Pointer authentication (using the APDAKey_EL1 key) of data addresses is enabled.

Note

This field controls the behavior of the AddPACDA and AuthDA pseudocode functions. Specifically, when the field is 1, AddPACDA returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [26]

Reserved, RES0.

#### EE, bit [25]

Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime.

The possible values of this bit are:

EE | Meaning
--- | ---
0b0 | Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are little-endian.
0b1 | Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are big-endian.

If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES0.

If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES1.

The EE bit is permitted to be cached in a TLB.

In a system where the PE resets into EL3, this field resets to an IMPLEMENTATION DEFINED value.

#### Bit [24]

Reserved, RES0.

#### Bit [23]

Reserved, RES1.

#### EIS, bit [22]
From Armv8.5:

Exception Entry is Context Synchronizing.

EIS | Meaning
--- | ---
0b0 | The taking of an exception to EL3 is not a context synchronizing event.
0b1 | The taking of an exception to EL3 is a context synchronizing event.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES1.

#### IESB, bit [21]
When ARMv8.2-IESB is implemented:

Implicit Error Synchronization event enable.

IESB | Meaning
--- | ---
0b0 | Disabled.
0b1 | An implicit error synchronization event is added: After each exception taken to EL3. Before the operational pseudocode of each ERET instruction executed at EL3.

When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event is added after each DCPSx instruction taken to EL3 and before each DRPS instruction executed at EL3, in addition to the other cases where it is added.

When ARMv8.4-DFE is implemented, and the Effective value of SCR_EL3.NMEA is 1, this field is ignored and its Effective value is 1.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [20]

Reserved, RES0.

#### WXN, bit [19]

Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:

WXN | Meaning
--- | ---
0b0 | This control has no effect on memory access permissions.
0b1 | Any region that is writable in the EL3 translation regime is forced to XN for accesses from software executing at EL3.

The WXN bit is permitted to be cached in a TLB.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

#### Bit [18]

Reserved, RES1.

#### Bit [17]

Reserved, RES0.

#### Bit [16]

Reserved, RES1.

#### Bits [15:14]

Reserved, RES0.

#### EnDB, bit [13]
From Armv8.3:

Controls enabling of pointer authentication (using the APDBKey_EL1 key) of instruction addresses in the EL3 translation regime.

EnDB | Meaning
--- | ---
0b0 | Pointer authentication (using the APDBKey_EL1 key) of data addresses is not enabled.
0b1 | Pointer authentication (using the APDBKey_EL1 key) of data addresses is enabled.

Note

This field controls the behavior of the AddPACDB and AuthDB pseudocode functions. Specifically, when the field is 1, AddPACDB returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### I, bit [12]

Instruction access Cacheability control, for accesses at EL3:

I | Meaning
--- | ---
0b0 | All instruction access to Normal memory from EL3 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory.
0b1 | This control has no effect on the Cacheability of instruction access to Normal memory from EL3. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.

This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.

In a system where the PE resets into EL3, this field resets to 0.

#### EOS, bit [11]
From Armv8.5:

Exception Exit is Context Synchronizing.

EOS | Meaning
--- | ---
0b0 | An exception return from EL3 is not a context synchronizing event
0b1 | An exception return from EL3 is a context synchronizing event

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES1.

#### Bits [10:7]

Reserved, RES0.

#### nAA, bit [6]
When ARMv8.4-LSE is implemented:

Non-aligned access. This bit controls generation of Alignment faults at EL3 under certain conditions.

nAA | Meaning
--- | ---
0b0 | LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAPURW, LDAR, LDARH, LDLAR, LDLARH, STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH generate an Alignment fault if all bytes being accessed are not within a single 16-byte quantity, aligned to 16 bytes for accesses.
0b1 | This control bit does not cause LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAPURW, LDAR, LDARH, LDLAR, LDLARH, STLLR, STLLRH, STLR, STLRH, STLUR, or STLURH to generate an Alignment fault if all bytes being accessed are not within a single 16-byte quantity, aligned to 16 bytes.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [5:4]

Reserved, RES1.

#### SA, bit [3]

SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model).

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

#### C, bit [2]

Cacheability control, for data accesses.

C | Meaning
--- | ---
0b0 | All data access to Normal memory from EL3, and all Normal memory accesses to the EL3 translation tables, are Non-cacheable for all levels of data and unified cache.
0b1 | This control has no effect on the Cacheability of: Data access to Normal memory from EL3. Normal memory accesses to the EL3 translation tables.

This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.

In a system where the PE resets into EL3, this field resets to 0.

#### A, bit [1]

Alignment check enable. This is the enable bit for Alignment fault checking at EL3.

A | Meaning
--- | ---
0b0 | Alignment fault checking disabled when executing at EL3. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed.
0b1 | Alignment fault checking enabled when executing at EL3. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception.

Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.

In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.

#### M, bit [0]

MMU enable for EL3 stage 1 address translation. Possible values of this bit are:

M | Meaning
--- | ---
0b0 | EL3 stage 1 address translation disabled. See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory.
0b1 | EL3 stage 1 address translation enabled.

In a system where the PE resets into EL3, this field resets to 0.

## Accessing the SCTLR_EL3

Accesses to this register use the following encodings:

#### MRS <Xt>, SCTLR_EL3

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return SCTLR_EL3;

#### MSR SCTLR_EL3, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then SCTLR_EL3 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15 27/04 03/2019 16 21:47 59; 8c23526ba8a13a72aada4137daf3e3977b49036e e5e4db499bf9867a4b93324c4dbac985d3da9376

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