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# GITS_CBASER, ITS Command Queue Descriptor

The GITS_CBASER characteristics are:

## Purpose

Specifies the base address and size of the ITS command queue.

## Configuration

Some or all RW fields of this register have defined reset values.

Bits [63:32] and bits [31:0] are accessible separately.

## Attributes

GITS_CBASER is a 64-bit register.

## Field descriptions

The GITS_CBASER bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
Valid | RES0 | InnerCache | RES0 | OuterCache | RES0 | Physical_Address
Physical_Address | Shareability | RES0 | Size
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Valid, bit [63]

Indicates whether software has allocated memory for the command queue:

Valid | Meaning
--- | ---
0b0 | No memory is allocated for the command queue.
0b1 | Memory is allocated to the command queue.

This field resets to 0.

#### Bit [62]

Reserved, RES0.

#### InnerCache, bits [61:59]

Indicates the Inner Cacheability attributes of accesses to the command queue. The possible values of this field are:

InnerCache | Meaning
--- | ---
0b000 | Device-nGnRnE.
0b001 | Normal Inner Non-cacheable.
0b010 | Normal Inner Cacheable Read-allocate, Write-through.
0b011 | Normal Inner Cacheable Read-allocate, Write-back.
0b100 | Normal Inner Cacheable Write-allocate, Write-through.
0b101 | Normal Inner Cacheable Write-allocate, Write-back.
0b110 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

This field resets to an architecturally UNKNOWN value.

#### Bits [58:56]

Reserved, RES0.

#### OuterCache, bits [55:53]

Indicates the Outer Cacheability attributes of accesses to the command queue. The possible values of this field are:

OuterCache | Meaning
--- | ---
0b000 | Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.
0b001 | Normal Outer Non-cacheable.
0b010 | Normal Outer Cacheable Read-allocate, Write-through.
0b011 | Normal Outer Cacheable Read-allocate, Write-back.
0b100 | Normal Outer Cacheable Write-allocate, Write-through.
0b101 | Normal Outer Cacheable Write-allocate, Write-back.
0b110 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

#### Bit [52]

Reserved, RES0.

#### Physical_Address, bits [51:12]

Bits [51:12] of the base physical address of the command queue. Bits [11:0] of the base address are 0.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

If bits [15:12] are not all zeros, behavior is a CONSTRAINED UNPREDICTABLE choice:

- Bits [15:12] are treated as if all the bits are zero. The value read back from those bits is either the value written or zero.
- The result of the calculation of an address for a command queue read can be corrupted.

This field resets to an architecturally UNKNOWN value.

#### Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the command queue. The possible values of this field are:

Shareability | Meaning
--- | ---
0b00 | Non-shareable.
0b01 | Inner Shareable.
0b10 | Outer Shareable.
0b11 | Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

This field resets to an architecturally UNKNOWN value.

#### Bits [9:8]

Reserved, RES0.

#### Size, bits [7:0]

The number of 4KB pages of physical memory allocated to the command queue, minus one.

This field resets to an architecturally UNKNOWN value.

The command queue is a circular buffer and wraps at Physical Address [47:0] + (4096 * (Size + 1)).

Note

When this register is successfully written, the value of GITS_CREADR is set to zero.

## Accessing the GITS_CBASER

When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE.

#### GITS_CBASER can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC ITS control | 0x0080 | GITS_CBASER

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RW.
- When IsAccessSecure() access to this register is RW.
- When !IsAccessSecure() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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