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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCRSCTLR<n>, Resource Selection Control Register <n>, n = 2 - 31

The TRCRSCTLR<n> characteristics are:

## Purpose

Controls the selection of the resources in the trace unit.

## Configuration

External register TRCRSCTLR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCRSCTLR<n>[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMRSPAIR > 0b0000 and ETE is implemented. Otherwise, direct accesses to TRCRSCTLR<n> are RES0.

Resource selector 0 always returns FALSE.

Resource selector 1 always returns TRUE.

Resource selectors are implemented in pairs. Each odd numbered resource selector is part of a pair with the even numbered resource selector that is numbered as one less than it. For example, resource selectors 2 and 3 form a pair.

## Attributes

TRCRSCTLR<n> is a 32-bit register.

## Field descriptions

The TRCRSCTLR<n> bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PAIRINV | INV | GROUP | SELECT

#### Bits [31:22]

Reserved, RES0.

#### PAIRINV, bit [21]

For TRCRSCTLR<n>, where n is even, bit controls whether the combined result from a resource selector pair is inverted.

PAIRINV | Meaning
--- | ---
0b0 | Do not invert the combined output of the 2 resource selectors.
0b1 | Invert the combined output of the 2 resource selectors.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### INV, bit [20]

Controls whether the resource, that GROUP and SELECT selects, is inverted.

INV | Meaning
--- | ---
0b0 | Do not invert the output of this selector.
0b1 | Invert the output of this selector.

If:

- A is the register TRCRSCTLR<m> where m is even.

- B is the register TRCRSCTLR<m+1>.

Then the combined output of the 2 resource selectors A and B depends on the value of (A.PAIRINV, A.INV, B.INV) as follows:

- 0b000 -> A and B.
- 0b001 -> RESERVED.
- 0b010 -> not(A) and B.
- 0b011 -> not(A) and not(B).
- 0b100 -> not(A) or not(B).
- 0b101 -> not(A) or B.
- 0b110 -> RESERVED.
- 0b111 -> A or B.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### GROUP, bits [19:16]

Selects a group of resources.

GROUP | Meaning
--- | ---
0b0000 | External input selectors.
0b0001 | PE Comparator Inputs.
0b0010 | Counters and Sequencer.
0b0011 | Single-shot Comparator Controls.
0b0100 | Single Address Comparators.
0b0101 | Address Range Comparators.
0b0110 | Context Identifier Comparators.
0b0111 | Virtual Context Identifier Comparators.

All other values are reserved.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### SELECT, bits [15:0]

Resource Specific Controls. Contains the controls specific to the resource group selected by GROUP, described in the following sections.

### SELECT encoding for an external input selectors.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | EXTIN<m>, bit [m]

#### Bits [15:4]

Reserved, RES0.

#### EXTIN<m>, bit [m], for m = 0 to 3

Selects one or more External inputs.

EXTIN<m> | Meaning
--- | ---
0b0 | Ignore EXTIN m.
0b1 | Select EXTIN m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for a PE Comparator Inputs.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PECOMP<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### PECOMP<m>, bit [m], for m = 0 to 7

Selects one or more PE Comparator Inputs.

PECOMP<m> | Meaning
--- | ---
0b0 | Ignore PE Comparator Input m.
0b1 | Select PE Comparator Input m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for counters and Sequencer.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SEQUENCER<m>, bit [m+4] | COUNTERS<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### SEQUENCER<m>, bit [m+4], for m = 0 to 3

Sequencer states.

SEQUENCER<m> | Meaning
--- | ---
0b0 | Ignore Sequencer state m.
0b1 | Select Sequencer state m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### COUNTERS<m>, bit [m], for m = 0 to 3

Counters resources at zero.

COUNTERS<m> | Meaning
--- | ---
0b0 | Ignore Counter m.
0b1 | Select Counter m is zero.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for a single-shot Comparator Controls.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SINGLE_SHOT<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### SINGLE_SHOT<m>, bit [m], for m = 0 to 7

Selects one or more Single-shot Comparator Controls.

SINGLE_SHOT<m> | Meaning
--- | ---
0b0 | Ignore Single-shot Comparator Control m.
0b1 | Select Single-shot Comparator Control m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for a single Address Comparators.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SAC<m>, bit [m]

#### SAC<m>, bit [m], for m = 0 to 15

Selects one or more Single Address Comparators.

SAC<m> | Meaning
--- | ---
0b0 | Ignore Single Address Comparator m.
0b1 | Select Single Address Comparator m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for address Range Comparators.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | ARC<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### ARC<m>, bit [m], for m = 0 to 7

Selects one or more Address Range Comparators.

ARC<m> | Meaning
--- | ---
0b0 | Ignore Address Range Comparator m.
0b1 | Select Address Range Comparator m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for a context Identifier Comparators.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | CID<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### CID<m>, bit [m], for m = 0 to 7

Selects one or more Context Identifier Comparators.

CID<m> | Meaning
--- | ---
0b0 | Ignore Context Identifier Comparator m.
0b1 | Select Context Identifier Comparator m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

### SELECT encoding for a virtual Context Identifier Comparators.

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | VMID<m>, bit [m]

#### Bits [15:8]

Reserved, RES0.

#### VMID<m>, bit [m], for m = 0 to 7

Selects one or more Virtual Context Identifier Comparators.

VMID<m> | Meaning
--- | ---
0b0 | Ignore Virtual Context Identifier Comparator m.
0b1 | Select Virtual Context Identifier Comparator m.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCRSCTLR<n>

Must be programmed if any of the following are true:

- TRCCNTCTLR<a>.RLDEVENT.TYPE == 0b0 and TRCCNTCTLR<a>.RLDEVENT.SEL == n.

- TRCCNTCTLR<a>.RLDEVENT.TYPE == 0b1 and TRCCNTCTLR<a>.RLDEVENT.SEL == n/2.

- TRCCNTCTLR<a>.CNTEVENT.TYPE == 0b0 and TRCCNTCTLR<a>.CNTEVENT.SEL == n.

- TRCCNTCTLR<a>.CNTEVENT.TYPE == 0b1 and TRCCNTCTLR<a>.CNTEVENT.SEL == n/2.

- TRCEVENTCTL0R.EVENT0.TYPE == 0b0 and TRCEVENTCTL0R.EVENT0.SEL == n.

- TRCEVENTCTL0R.EVENT0.TYPE == 0b1 and TRCEVENTCTL0R.EVENT0.SEL == n/2.

- TRCEVENTCTL0R.EVENT1.TYPE == 0b0 and TRCEVENTCTL0R.EVENT1.SEL == n.

- TRCEVENTCTL0R.EVENT1.TYPE == 0b1 and TRCEVENTCTL0R.EVENT1.SEL == n/2.

- TRCEVENTCTL0R.EVENT2.TYPE == 0b0 and TRCEVENTCTL0R.EVENT2.SEL == n.

- TRCEVENTCTL0R.EVENT2.TYPE == 0b1 and TRCEVENTCTL0R.EVENT2.SEL == n/2.

- TRCEVENTCTL0R.EVENT3.TYPE == 0b0 and TRCEVENTCTL0R.EVENT3.SEL == n.

- TRCEVENTCTL0R.EVENT3.TYPE == 0b1 and TRCEVENTCTL0R.EVENT3.SEL == n/2.

- TRCSEQEVR<a>.B.TYPE == 0b0 and TRCSEQEVR<a>.B.SEL = n.

- TRCSEQEVR<a>.B.TYPE == 0b1 and TRCSEQEVR<a>.B.SEL = n/2.

- TRCSEQEVR<a>.F.TYPE == 0b0 and TRCSEQEVR<a>.F.SEL = n.

- TRCSEQEVR<a>.F.TYPE == 0b1 and TRCSEQEVR<a>.F.SEL = n/2.

- TRCSEQRSTEVR.RST.TYPE == 0b0 and TRCSEQRSTEVR.RST.SEL == n.

- TRCSEQRSTEVR.RST.TYPE == 0b1 and TRCSEQRSTEVR.RST.SEL == n/2.

- TRCTSCTLR.EVENT.TYPE == 0b0 and TRCTSCTLR.EVENT.SEL == n.

- TRCTSCTLR.EVENT.TYPE == 0b1 and TRCTSCTLR.EVENT.SEL == n/2.

- TRCVICTLR.EVENT.TYPE == 0b0 and TRCVICTLR.EVENT.SEL == n.

- TRCVICTLR.EVENT.TYPE == 0b1 and TRCVICTLR.EVENT.SEL == n/2.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCRSCTLR<n> can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x200 + 4n

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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