AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# ICH_MISR_EL2, Interrupt Controller Maintenance Interrupt State Register

The ICH_MISR_EL2 characteristics are:

## Purpose

Indicates which maintenance interrupts are asserted.

## Configuration

AArch64 System register ICH_MISR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_MISR[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ICH_MISR_EL2 is a 64-bit register.

## Field descriptions

The ICH_MISR_EL2 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | VGrp1D | VGrp1E | VGrp0D | VGrp0E | NP | LRENP | U | EOI
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:8]

Reserved, RES0.

#### VGrp1D, bit [7]

vPE Group 1 Disabled.

VGrp1D | Meaning
--- | ---
0b0 | vPE Group 1 Disabled maintenance interrupt not asserted.
0b1 | vPE Group 1 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.

This field resets to 0.

#### VGrp1E, bit [6]

vPE Group 1 Enabled.

VGrp1E | Meaning
--- | ---
0b0 | vPE Group 1 Enabled maintenance interrupt not asserted.
0b1 | vPE Group 1 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.

This field resets to 0.

#### VGrp0D, bit [5]

vPE Group 0 Disabled.

VGrp0D | Meaning
--- | ---
0b0 | vPE Group 0 Disabled maintenance interrupt not asserted.
0b1 | vPE Group 0 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.

This field resets to 0.

#### VGrp0E, bit [4]

vPE Group 0 Enabled.

VGrp0E | Meaning
--- | ---
0b0 | vPE Group 0 Enabled maintenance interrupt not asserted.
0b1 | vPE Group 0 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.

This field resets to 0.

#### NP, bit [3]

No Pending.

NP | Meaning
--- | ---
0b0 | No Pending maintenance interrupt not asserted.
0b1 | No Pending maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and no List register is in pending state.

This field resets to 0.

#### LRENP, bit [2]

List Register Entry Not Present.

LRENP | Meaning
--- | ---
0b0 | List Register Entry Not Present maintenance interrupt not asserted.
0b1 | List Register Entry Not Present maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 and ICH_HCR_EL2.EOIcount is non-zero.

This field resets to 0.

#### U, bit [1]

Underflow.

U | Meaning
--- | ---
0b0 | Underflow maintenance interrupt not asserted.
0b1 | Underflow maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits do not equal 0x0.

This field resets to 0.

#### EOI, bit [0]

End Of Interrupt.

EOI | Meaning
--- | ---
0b0 | End Of Interrupt maintenance interrupt not asserted.
0b1 | End Of Interrupt maintenance interrupt asserted.

This maintenance interrupt is asserted when at least one bit in ICH_EISR_EL2 is 1.

This field resets to 0.

The U and NP bits do not include the status of any pending/active VSET packets because these bits control generation of interrupts that allow software management of the contents of the List Registers (which are not affected by VSET packets).

## Accessing the ICH_MISR_EL2

Accesses to this register use the following encodings:

#### MRS <Xt>, ICH_MISR_EL2

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b1100 | 0b1011 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else return ICH_MISR_EL2; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return ICH_MISR_EL2;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.