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# MPAM1_EL1, MPAM1 Register (EL1)

The MPAM1_EL1 characteristics are:

## Purpose

MPAM1_EL1 holds information to generate MPAM labels for memory requests when executing at EL1.

When EL2 is present and enabled, the MPAM virtualization option is present, MPAMHCR_EL2.GSTAPP_PLK == 1 and HCR_EL2.TGE == 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate MPAM labels for memory requests when executing at EL0.

MPAM1_EL1 is an alias for MPAM2_EL2 when executing at EL2 with HCR_EL2.E2H == 1.

MPAM1_EL12 is an alias for MPAM1_EL1 when executing at EL2 or EL3 with HCR_EL2.E2H == 1.

If EL2 is is present and enabled, the MPAM virtualization option is present and MPAMHCR_EL2.EL1_VPMEN == 1, MPAM PARTIDs in MPAM1_EL1 are virtual and mapped into physical PARTIDs for the current Security state. This mapping of MPAM1_EL1 virtual PARTIDs to physical PARTIDs when EL1_VPMEN is 1 also applies when MPAM1_EL1 is used at EL0 due to MPAMHCR_EL2.GSTAPP_PLK.

## Configuration

AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM3_EL3[63] when HaveEL(EL3).

AArch64 System register MPAM1_EL1 bit [63] is architecturally mapped to AArch64 System register MPAM2_EL2[63] when !HaveEL(EL3) and HaveEL(EL2).

This register is present only when MPAM is implemented. Otherwise, direct accesses to MPAM1_EL1 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

MPAM1_EL1 is a 64-bit register.

## Field descriptions

The MPAM1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
MPAMEN | RES0 | PMG_D | PMG_I
PARTID_D | PARTID_I
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### MPAMEN, bit [63]

MPAM Enable: MPAM is enabled when MPAMEN == 1. When disabled, all PARTIDs and PMGs are output as their default value in the corresponding ID space.

Values of this field are:

MPAMEN | Meaning
--- | ---
0b0 | The default PARTID and default PMG are output in MPAM information.
0b1 | MPAM information is output based on the MPAMn_ELx register for ELn according the MPAM configuration.

If neither EL3 nor EL2 is implemented, this field is read/write.

If EL3 is implemented, this field is read-only and reads the current value of the read/write bit MPAM3_EL3.MPAMEN.

If EL3 is not implemented and EL2 is implemented, this field is read-only and reads the current value of the read/write bit MPAM2_EL2.MPAMEN.

This field resets to 0.

Accessing this field has the following behavior:

- When !HaveEL(EL3) and !HaveEL(EL2), access to this field is RW.
- Otherwise, access to this field is RO.

#### Bits [62:48]

Reserved, RES0.

#### PMG_D, bits [47:40]

Performance monitoring group property for PARTID_D.

This field resets to an architecturally UNKNOWN value.

#### PMG_I, bits [39:32]

Performance monitoring group property for PARTID_I.

This field resets to an architecturally UNKNOWN value.

#### PARTID_D, bits [31:16]

Partition ID for data accesses, including load and store accesses, made from EL1.

This field resets to an architecturally UNKNOWN value.

#### PARTID_I, bits [15:0]

Partition ID for instruction accesses made from EL1.

This field resets to an architecturally UNKNOWN value.

## Accessing the MPAM1_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the mnemonic MPAM1_EL1 or MPAM1_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

None of the fields in this register are permitted to be cached in a TLB.

Accesses to this register use the following encodings:

#### MRS <Xt>, MPAM1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0101 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MPAM2_EL2.TRAPMPAM1EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x900]; else return MPAM1_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return MPAM2_EL2; else return MPAM1_EL1; elsif PSTATE.EL == EL3 then return MPAM1_EL1;

#### MSR MPAM1_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0101 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MPAM2_EL2.TRAPMPAM1EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x900] = X[t]; else MPAM1_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then MPAM2_EL2 = X[t]; else MPAM1_EL1 = X[t]; elsif PSTATE.EL == EL3 then MPAM1_EL1 = X[t];

#### MRS <Xt>, MPAM1_EL12

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b101 | 0b1010 | 0b0101 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x900]; elsif EL2Enabled() && HCR_EL2.NV == '1' then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return MPAM1_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then return MPAM1_EL1; else UNDEFINED;

#### MSR MPAM1_EL12, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b101 | 0b1010 | 0b0101 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x900] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if EL2Enabled() && HCR_EL2.E2H == '1' then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else MPAM1_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && HCR_EL2.E2H == '1' then MPAM1_EL1 = X[t]; else UNDEFINED;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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