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# PMVIDSR, VMID Sample Register

The PMVIDSR characteristics are:

## Purpose

Contains the sampled VMID value that is captured on reading PMPCSR[31:0].

## Configuration

PMVIDSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

This register is present only from Armv8.2. Otherwise, direct accesses to PMVIDSR are RES0.

Implemented only when ARMv8.2-PCSample is implemented.

Note

Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.

If EL2 is not implemented, this register is RES0.

## Attributes

PMVIDSR is a 32-bit register.

## Field descriptions

The PMVIDSR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | VMID

#### Bits [31:16]

Reserved, RES0.

#### VMID, bits [15:0]
From Armv8.2:

VMID sample. The VMID associated with the most recent PMPCSR sample.

- If EL2 is implemented and is using AArch64, then the VMID is held in VTTBR_EL2.VMID.
- If EL2 is implemented and is using AArch32, then the VMID is held in VTTBR.VMID.
- This field is set to an UNKNOWN value if any of the following apply:
  - PMPCSR.NS == 0.
  - PMPCSR.EL == 0b10.
  - PMPCSR.NS == 1, PMPCSR.EL == 0b00, EL2 is using AArch64, HCR_EL2.E2H == 1, and HCR_EL2.TGE == 1.
- If EL2 is not implemented, then this field is RES0.
- If 16-bit VMIDs are not supported, PMVIDSR.VMID[15:8] is RES0.
- If 16-bit VMIDs are supported, but VTTBRx.VMID[15:8] are not used, PMVIDSR.VMID[15:8] is set to RES0.

On a Cold reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

## Accessing the PMVIDSR

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile

#### PMVIDSR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
PMU | 0x20C | PMVIDSR

This interface is accessible as follows:

- When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus() access to this register is RO.
- Otherwise access to this register returns an Error.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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