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# ERRIRQSR, Error Interrupt Status Register

The ERRIRQSR characteristics are:

## Purpose

Interrupt status register.

## Configuration

External register ERRIRQSR is architecturally mapped to External register ERRIRQCR15.

RW fields in this register reset to architecturally UNKNOWN values.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

## Attributes

ERRIRQSR is a 64-bit register.

## Field descriptions

The ERRIRQSR bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | CRIERR | CRI | ERIERR | ERI | FHIERR | FHI
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:6]

Reserved, RES0.

#### CRIERR, bit [5]

Critical error interrupt error.

CRIERR | Meaning
--- | ---
0b0 | Interrupt write has not returned an error since this bit was last cleared to 0.
0b1 | Interrupt write has returned an error since this bit was last cleared to 0.

This bit is read/write-one-to-clear.

The following resets apply:

- On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### CRI, bit [4]

Critical error interrupt write in progress.

CRI | Meaning
--- | ---
0b0 | Interrupt write not in progress.
0b1 | Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

#### ERIERR, bit [3]

Error recovery interrupt error.

ERIERR | Meaning
--- | ---
0b0 | Interrupt write has not returned an error since this bit was last cleared to 0.
0b1 | Interrupt write has returned an error since this bit was last cleared to 0.

This bit read/write-one-to-clear.

The following resets apply:

- On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### ERI, bit [2]

Error recovery interrupt write in progress.

ERI | Meaning
--- | ---
0b0 | Interrupt write not in progress.
0b1 | Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

#### FHIERR, bit [1]

Fault handling interrupt error.

FHIERR | Meaning
--- | ---
0b0 | Interrupt write has not returned an error since this bit was last cleared to 0.
0b1 | Interrupt write has returned an error since this bit was last cleared to 0.

This bit read/write-one-to-clear.

The following resets apply:

- On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

#### FHI, bit [0]

Fault handling interrupt write in progress.

FHI | Meaning
--- | ---
0b0 | Interrupt write not in progress.
0b1 | Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

## Accessing the ERRIRQSR

#### ERRIRQSR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0xEF8 | ERRIRQSR

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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