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# MPIDR_EL1, Multiprocessor Affinity Register

The MPIDR_EL1 characteristics are:

## Purpose

In a multiprocessor system, provides an additional PE identification mechanism for scheduling purposes.

## Configuration

AArch64 System register MPIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MPIDR[31:0] .

In a uniprocessor system Arm recommends that each Aff<n> field of this register returns a value of 0.

## Attributes

MPIDR_EL1 is a 64-bit register.

## Field descriptions

The MPIDR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | Aff3
RES1 | U | RES0 | MT | Aff2 | Aff1 | Aff0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:40]

Reserved, RES0.

#### Aff3, bits [39:32]

Affinity level 3. See the description of Aff0 for more information.

Aff3 is not supported in AArch32 state.

#### Bit [31]

Reserved, RES1.

#### U, bit [30]

Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:

U | Meaning
--- | ---
0b0 | Processor is part of a multiprocessor system.
0b1 | Processor is part of a uniprocessor system.

#### Bits [29:25]

Reserved, RES0.

#### MT, bit [24]

Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels. The possible values of this bit are:

MT | Meaning
--- | ---
0b0 | Performance of PEs at the lowest affinity level is largely independent.
0b1 | Performance of PEs at the lowest affinity level is very interdependent.

#### Aff2, bits [23:16]

Affinity level 2. See the description of Aff0 for more information.

#### Aff1, bits [15:8]

Affinity level 1. See the description of Aff0 for more information.

#### Aff0, bits [7:0]

Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.

## Accessing the MPIDR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, MPIDR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0000 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) then return VMPIDR_EL2; else return MPIDR_EL1; elsif PSTATE.EL == EL2 then return MPIDR_EL1; elsif PSTATE.EL == EL3 then return MPIDR_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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