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# LORSA_EL1, LORegion Start Address (EL1)

The LORSA_EL1 characteristics are:

## Purpose

Indicates whether the current LORegion descriptor selected by LORC_EL1.DS is enabled, and holds the physical address of the start of the LORegion.

## Configuration

This register is present only from Armv8.1. Otherwise, direct accesses to LORSA_EL1 are UNDEFINED.

This register is RES0 if any of the following apply:

- No LORegion descriptors are supported by the PE.
- LORC_EL1.DS points to a LORegion that is not supported by the PE.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

LORSA_EL1 is a 64-bit register.

## Field descriptions

The LORSA_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | SA[51:48] | SA[47:16]
SA[47:16] | RES0 | Valid
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

Any of the fields in this register are permitted to be cached in a TLB.

#### Bits [63:52]

Reserved, RES0.

#### SA[51:48], bits [51:48]
From Armv8.2:

Extension to SA[47:16]. See SA[47:16] for more details.

This field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### SA[47:16], bits [47:16]

Bits [47:16] of the start physical address of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS. Bits[15:0] of this address are defined to be 0x0000. For implementations with fewer than 48 bits, the upper bits of this field are RES0.

When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, SA[51:48] form the upper part of the address value. Otherwise, for implementations with fewer than 52 physical address bits, SA[51:48] are RES0.

This field resets to an architecturally UNKNOWN value.

#### Bits [15:1]

Reserved, RES0.

#### Valid, bit [0]

Indicates whether the current LORegion Descriptor is enabled.

Valid | Meaning
--- | ---
0b0 | Disabled
0b1 | Enabled

This field resets to 0.

## Accessing the LORSA_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, LORSA_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0100 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORSA_EL1; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return LORSA_EL1; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else return LORSA_EL1;

#### MSR LORSA_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1010 | 0b0100 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if SCR_EL3.NS == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TLOR == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORSA_EL1 = X[t]; elsif PSTATE.EL == EL2 then if SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.TLOR == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else LORSA_EL1 = X[t]; elsif PSTATE.EL == EL3 then if SCR_EL3.NS == '0' then UNDEFINED; else LORSA_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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