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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCTRACEIDR, Trace ID Register

The TRCTRACEIDR characteristics are:

## Purpose

Sets the trace ID for instruction trace.

## Configuration

External register TRCTRACEIDR bits [31:0] are architecturally mapped to AArch64 System register TRCTRACEIDR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR5.TRACEIDSIZE != 0x00 and ETE is implemented. Otherwise, direct accesses to TRCTRACEIDR are RES0.

## Attributes

TRCTRACEIDR is a 32-bit register.

## Field descriptions

The TRCTRACEIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | TRACEID

#### Bits [31:7]

Reserved, RES0.

#### TRACEID, bits [6:0]

Trace ID field. Sets the trace ID value for instruction trace. The width of the field is indicated by the value of TRCIDR5.TRACEIDSIZE. Unimplemented bits are RES0.

If an implementation supports AMBA ATB, then:

- The width of the field is 7 bits.
- Writing a reserved trace ID value does not affect behavior of the trace unit but it might cause UNPREDICTABLE behavior of the trace capture infrastructure.

See the AMBA ATB Protocol Specification for information about which ATID values are reserved.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCTRACEIDR

Must be programmed if implemented.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCTRACEIDR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x040

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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