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# ERRFHICR1, Fault-Handling Interrupt Configuration Register 1

The ERRFHICR1 characteristics are:

## Purpose

Interrupt configuration register.

## Configuration

External register ERRFHICR1 bits [31:0] are architecturally mapped to External register ERRIRQCR1[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRFHICR1 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

## Attributes

ERRFHICR1 is a 32-bit register.

## Field descriptions

The ERRFHICR1 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA

#### DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

- On a Error recovery reset, this field resets to an architecturally UNKNOWN value.

- On a Cold reset, this field resets to an architecturally UNKNOWN value.

## Accessing the ERRFHICR1

#### ERRFHICR1 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0xE88 | ERRFHICR1

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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