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# TRCSTATR, Trace Status Register

The TRCSTATR characteristics are:

## Purpose

Returns the trace unit status.

## Configuration

External register TRCSTATR bits [31:0] are architecturally mapped to AArch64 System register TRCSTATR[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSTATR are RES0.

## Attributes

TRCSTATR is a 32-bit register.

## Field descriptions

The TRCSTATR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PMSTABLE | IDLE

#### Bits [31:2]

Reserved, RES0.

#### PMSTABLE, bit [1]

Programmers' model stable bit.

PMSTABLE | Meaning
--- | ---
0b0 | The programmers' model is not stable.
0b1 | The programmers' model is stable.

This bit is UNKNOWN while the trace unit is enabled.

#### IDLE, bit [0]

Idle Status bit.

IDLE | Meaning
--- | ---
0b0 | The trace unit is not idle.
0b1 | The trace unit is idle.

## Accessing the TRCSTATR

#### TRCSTATR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x00C

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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