AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# DBGDIDR, Debug ID Register

The DBGDIDR characteristics are:

## Purpose

Specifies which version of the Debug architecture is implemented, and some features of the debug implementation.

## Configuration

If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.

## Attributes

DBGDIDR is a 32-bit register.

## Field descriptions

The DBGDIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
WRPs | BRPs | CTX_CMPs | Version | RES1 | nSUHD_imp | RES0 | SE_imp | RES0

#### WRPs, bits [31:28]

The number of watchpoints implemented, minus 1.

Permitted values of this field are from 0b0001 for 2 implemented watchpoints, to 0b1111 for 16 implemented watchpoints.

The value of 0b0000 is reserved.

If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.WRPs.

#### BRPs, bits [27:24]

The number of breakpoints implemented, minus 1.

Permitted values of this field are from 0b0001 for 2 implemented breakpoint, to 0b1111 for 16 implemented breakpoints.

The value of 0b0000 is reserved.

If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.BRPs.

#### CTX_CMPs, bits [23:20]

The number of breakpoints that can be used for Context matching, minus 1.

Permitted values of this field are from 0b0000 for 1 Context matching breakpoint, to 0b1111 for 16 Context matching breakpoints.

The Context matching breakpoints must be the highest addressed breakpoints. For example, if six breakpoints are implemented and two are Context matching breakpoints, they must be breakpoints 4 and 5.

If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.

#### Version, bits [19:16]

The Debug architecture version. Defined values are:

Version | Meaning
--- | ---
0b0001 | Armv6, v6 Debug architecture.
0b0010 | Armv6, v6.1 Debug architecture.
0b0011 | Armv7, v7 Debug architecture, with baseline CP14 registers implemented.
0b0100 | Armv7, v7 Debug architecture, with all CP14 registers implemented.
0b0101 | Armv7, v7.1 Debug architecture.
0b0110 | Armv8, v8 Debug architecture.
0b0111 | Armv8.1, v8 Debug architecture, with Virtualization Host Extensions.
0b1000 | Armv8.2, v8.2 Debug architecture.
0b1001 | Armv8.4, v8.4 Debug architecture.

All other values are reserved.

In any Armv8 implementation, the values 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted.

- If ARMv8.1-VHE is not implemented, the only permitted value is 0b0110.

- In an Armv8.0 implementation, the value 0b1000 or higher is not permitted.

#### Bit [15]

Reserved, RES1.

#### nSUHD_imp, bit [14]

In Armv7-A, was Secure User Halting Debug not implemented.

The value of this bit must match the value of the SE_imp bit.

#### Bit [13]

Reserved, RES0.

#### SE_imp, bit [12]

EL3 implemented. The meanings of the values of this bit are:

SE_imp | Meaning
--- | ---
0b0 | EL3 not implemented.
0b1 | EL3 implemented.

The value of this bit must match the value of the nSUHD_imp bit.

#### Bits [11:0]

Reserved, RES0.

## Accessing the DBGDIDR

Arm deprecates any access to this register from EL0.

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1110 | 0b000 | 0b0000 | 0b0000 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); else AArch64.AArch32SystemAccessTrap(EL1, 0x05); elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL3 then return DBGDIDR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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