AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCIDR8, ID Register 8

The TRCIDR8 characteristics are:

## Purpose

Returns the maximum speculation depth of the instruction trace element stream.

## Configuration

External register TRCIDR8 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR8[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR8 are RES0.

## Attributes

TRCIDR8 is a 32-bit register.

## Field descriptions

The TRCIDR8 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MAXSPEC

#### MAXSPEC, bits [31:0]

Indicates the maximum speculation depth of the instruction trace element stream. This is the maximum number of P0 elements in the trace element stream that can be speculative at any time.

## Accessing the TRCIDR8

#### TRCIDR8 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x180

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.