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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCSSCSR<n>, Single-shot Comparator Control Status Register <n>, n = 0 - 7

The TRCSSCSR<n> characteristics are:

## Purpose

Returns the status of the corresponding Single-shot Comparator Control.

## Configuration

AArch64 System register TRCSSCSR<n> bits [31:0] are architecturally mapped to External register TRCSSCSR<n>[31:0] .

This register is present only when TRCIDR4.NUMSSCC > n and ETE is implemented. Otherwise, direct accesses to TRCSSCSR<n> are UNDEFINED.

## Attributes

TRCSSCSR<n> is a 64-bit register.

## Field descriptions

The TRCSSCSR<n> bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
STATUS | PENDING | RES0 | PC | DV | DA | INST
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### STATUS, bit [31]

Single-shot Comparator Control status. Indicates if any of the comparators selected by this Single-shot Comparator control have matched. The selected comparators are defined by TRCSSCCR<n>.ARC, TRCSSCCR<n>.SAC, and TRCSSPCICR<n>.PC.

STATUS | Meaning
--- | ---
0b0 | No match has occurred. When the first match occurs, this field takes a value of 0b1. It remains at 0b1 until explicitly modified by a write to this register.
0b1 | One or more matches has occurred. If TRCSSCCR<n>.RST == 0b0 then: There is only one match and no more matches are possible. Software must reset this bit to 0b0 to re-enable the Single-shot Comparator Control.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### PENDING, bit [30]

Single-shot pending status. The Single-shot Comparator Control fired while the resources were in the Paused state.

PENDING | Meaning
--- | ---
0b0 | No match has occurred.
0b1 | One or more matches has occurred.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### Bits [29:4]

Reserved, RES0.

#### PC, bit [3]

PE Comparator Input support. Indicates if the Single-shot Comparator Control supports PE Comparator Inputs.

PC | Meaning
--- | ---
0b0 | This Single-shot Comparator Control does not support PE Comparator Inputs. Selecting any PE Comparator Inputs using the associated TRCSSPCICR<n> results in CONSTRAINED UNPREDICTABLE behavior of the Single-shot Comparator Control resource. The Single-shot Comparator Control might match unexpectedly or might not match.
0b1 | This Single-shot Comparator Control supports PE Comparator Inputs.

Access to this field is RO.

#### DV, bit [2]

Data value comparator support. Data value comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

DV | Meaning
--- | ---
0b0 | This Single-shot Comparator Control does not support data value comparisons.
0b1 | This Single-shot Comparator Control supports data value comparisons.

This bit reads as 0b0.

Access to this field is RO.

#### DA, bit [1]

Data address comparator support. Data address comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

DA | Meaning
--- | ---
0b0 | This Single-shot Comparator Control does not support data address comparisons.
0b1 | This Single-shot Comparator Control supports data address comparisons.

This bit reads as 0b0.

Access to this field is RO.

#### INST, bit [0]

Instruction address comparator support. Indicates if the Single-shot Comparator Control supports instruction address comparisons.

INST | Meaning
--- | ---
0b0 | This Single-shot Comparator Control does not support instruction address comparisons.
0b1 | This Single-shot Comparator Control supports instruction address comparisons.

This bit reads as 0b1.

Access to this field is RO.

## Accessing the TRCSSCSR<n>

Must be programmed if TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

Accesses to this register use the following encodings:

#### MRS <Xt>, TRCSSCSR<n>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0001 | 0b1[n:2:0] | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCSR[UInt(CRm<2:0>)]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCSR[UInt(CRm<2:0>)]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCSSCSR[UInt(CRm<2:0>)];

#### MSR TRCSSCSR<n>, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0001 | 0b1[n:2:0] | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCSR[UInt(CRm<2:0>)] = X[t]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCSR[UInt(CRm<2:0>)] = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCSSCSR[UInt(CRm<2:0>)] = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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