AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6

The ID_ISAR6_EL1 characteristics are:

## Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1 and ID_ISAR5_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

AArch64 System register ID_ISAR6_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_ISAR6[31:0] .

This register is present only from Armv8.2. Otherwise, direct accesses to ID_ISAR6_EL1 are RES0.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_ISAR6_EL1 is a 64-bit register.

## Field descriptions

The ID_ISAR6_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | SPECRES | SB | FHM | DP | JSCVT
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:20]

Reserved, RES0.

#### SPECRES, bits [19:16]

Speculation invalidation instruction support in AArch32 state. Defined values are:

SPECRES | Meaning
--- | ---
0b0000 | CFPRCTX, DVPRCTX, and CPPRCTX instructions are not implemented.
0b0001 | CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### SB, bits [15:12]

SB instruciton support in AArch64 state. Defined values are:

SB | Meaning
--- | ---
0b0000 | SB instruction is not implemented.
0b0001 | SB instruction is implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### FHM, bits [11:8]

Indicates whether VFMAL and VFMSL instructions are implemented.

FHM | Meaning
--- | ---
0b0000 | VFMAL and VMFSL instructions are not implemented.
0b0001 | VFMAL and VMFSL instructions are implemented.

ARMv8.2-FHM implements the functionality identified by the value 0b0001.

In Armv8.0 and Armv8.1, the only permitted value is 0b0000.

In Armv8.2, the permitted values are 0b0000 and 0b0001.

#### DP, bits [7:4]

Indicates the support for dot product instructions in AArch32 state.

DP | Meaning
--- | ---
0b0000 | No dot product instructions are implemented.
0b0001 | VUDOT and VSDOT instructions are implemented.

All other values are reserved.

ARMv8.2-DotProd implements the functionality identified by the value 0b0001.

In Armv8.0 and Armv8.1, the only permitted value is 0b0000.

In Armv8.2, the permitted values are 0b0000 and 0b0001.

#### JSCVT, bits [3:0]
From Armv8.3:

Indicates whether the Javascript conversion instruction is implemented in AArch32 state. Defined values are:

JSCVT | Meaning
--- | ---
0b0000 | The VJCVT instruction is not implemented.
0b0001 | The VJCVT instruction is implemented.

All other values are reserved.

ARMv8.3-JSConv implements the functionality identified by 0b0001.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

From Armv8.3, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_ISAR6_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_ISAR6_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0010 | 0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_ISAR6_EL1; elsif PSTATE.EL == EL2 then return ID_ISAR6_EL1; elsif PSTATE.EL == EL3 then return ID_ISAR6_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.