AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# MPAMF_ECR, MPAM Error Control Register

The MPAMF_ECR characteristics are:

## Purpose

MPAMF_ECR is a 32-bit read-write register that controls MPAM error interrupts for this MSC.

## Configuration

The power domain of MPAMF_ECR is IMPLEMENTATION DEFINED.

If a MSC cannot encounter any of the error conditions listed in section 15.1, both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.

## Attributes

MPAMF_ECR is a 32-bit register.

## Field descriptions

The MPAMF_ECR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | INTEN

#### Bits [31:1]

Reserved, RES0.

#### INTEN, bit [0]

Interrupt Enable.

INTEN | Meaning
--- | ---
0b0 | MPAM error interrupts are not generated.
0b1 | MPAM error interrupts are generated.

## Accessing the MPAMF_ECR

This register is part of the MPAMF_BASE memory frame. In a system that supports Secure and Non-secure memory maps, the MPAMF_BASE frame must be accessible in both Secure and Non-secure memory address maps.

MPAMF_ECR must be accessible from the Non-secure and Secure address maps.

MPAMF_ECR must be banked for the Secure and Non-secure address maps. The Secure instance accesses the error interrupt controls used for Secure PARTIDs, and the Non-secure instance accesses the error interrupt controls used for Non-secure PARTIDs.

#### MPAMF_ECR can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_s | 0x00F0 | MPAMF_ECR_s

Access on this interface is RW.

Component | Frame | Offset | Instance
--- | --- | --- | ---
MPAM.any | MPAMF_BASE_ns | 0x00F0 | MPAMF_ECR_ns

Access on this interface is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.