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# TRCIDR0, ID Register 0

The TRCIDR0 characteristics are:

## Purpose

Returns the tracing capabilities of the trace unit.

## Configuration

External register TRCIDR0 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR0[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR0 are RES0.

## Attributes

TRCIDR0 is a 32-bit register.

## Field descriptions

The TRCIDR0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | COMMTRANS | COMMOPT | TSSIZE | RES0 | TRCEXDATA | QSUPP | QFILT | CONDTYPE | NUMEVENT | RETSTACK | RES0 | TRCCCI | TRCCOND | TRCBB | TRCDATA | INSTP0 | RES1

#### Bit [31]

Reserved, RES0.

#### COMMTRANS, bit [30]

Transaction Start element behavior.

COMMTRANS | Meaning
--- | ---
0b0 | Transaction Start elements are P0 elements.
0b1 | Transaction Start elements are not P0 elements.

#### COMMOPT, bit [29]

Indicates how the commit field in Cycle count packets is interpreted.

COMMOPT | Meaning
--- | ---
0b0 | Commit mode 0. Cycle count packets includes the Commit element to which the Cycle Count element is attached.
0b1 | Commit mode 1. Cycle count packets do not include Commit elements. The Cycle Count element is attached to the most recent Commit element.

This bit reads-as-one if TRCIDR0.TRCCCI == 0b1 and TRCIDR8.MAXSPEC == 0x0. This bit reads-as-zero if TRCIDR0.TRCCCI == 0b0.

#### TSSIZE, bits [28:24]

Indicates that the trace unit implements Global timestamping and the size of the timestamp value.

TSSIZE | Meaning
--- | ---
0b00000 | Global timestamping not implemented.
0b01000 | Global timestamping implemented with 64 bits of timestamp value.

All other values are reserved.

This field reads as 0b01000.

#### Bits [23:18]

Reserved, RES0.

#### TRCEXDATA, bit [17]
When TRCIDR0.TRCDATA != 0b00:

Indicates if the trace unit implements tracing of data transfers for exceptions and exception returns. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

TRCEXDATA | Meaning
--- | ---
0b0 | Tracing of data transfers for exceptions and exception returns not implemented.
0b1 | Tracing of data transfers for exceptions and exception returns implemented.

####
Otherwise:

Reserved, RES0.

#### QSUPP, bits [16:15]

Indicates that the trace unit implements Q element support.

QSUPP | Meaning
--- | ---
0b00 | Q element support is not implemented.
0b01 | Q element support is implemented, and only supports Q elements with instruction counts.
0b10 | Q element support is implemented, and only supports Q elements without instruction counts.
0b11 | Q element support is implemented, and supports: Q elements with instruction counts. Q elements without instruction counts.

#### QFILT, bit [14]
When TRCIDR0.QSUPP != 0b00:

Indicates if the trace unit implements Q element filtering.

QFILT | Meaning
--- | ---
0b0 | Q element filtering is not implemented.
0b1 | Q element filtering is implemented.

####
Otherwise:

Reserved, RES0.

#### CONDTYPE, bits [13:12]
When TRCIDR0.TRCCOND == 0b1:

Indicates how conditional instructions are traced. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

CONDTYPE | Meaning
--- | ---
0b00 | Conditional instructions are traced with an indication of whether they pass or fail their condition code check.
0b01 | Conditional instructions are traced with an indication of the APSR condition flags.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### NUMEVENT, bits [11:10]
When TRCIDR4.NUMRSPAIR == 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENT | Meaning
--- | ---
0b00 | The trace unit supports 0 ETEEvents.

All other values are reserved.

####
When TRCIDR4.NUMRSPAIR != 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENT | Meaning
--- | ---
0b00 | The trace unit supports 1 ETEEvent.
0b01 | The trace unit supports 2 ETEEvents.
0b10 | The trace unit supports 3 ETEEvents.
0b11 | The trace unit supports 4 ETEEvents.

####
Otherwise:

Reserved, RES0.

#### RETSTACK, bit [9]

Indicates if the trace unit supports the return stack.

RETSTACK | Meaning
--- | ---
0b0 | Return stack not implemented.
0b1 | Return stack implemented.

#### Bit [8]

Reserved, RES0.

#### TRCCCI, bit [7]

Indicates if the trace unit implements cycle counting.

TRCCCI | Meaning
--- | ---
0b0 | Cycle counting not implemented.
0b1 | Cycle counting implemented.

This bit reads as 0b1.

#### TRCCOND, bit [6]

Indicates if the trace unit implements conditional instruction tracing. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCCOND | Meaning
--- | ---
0b0 | Conditional instruction tracing not implemented.
0b1 | Conditional instruction tracing implemented.

This bit reads as 0b0.

#### TRCBB, bit [5]

Indicates if the trace unit implements branch broadcasting.

TRCBB | Meaning
--- | ---
0b0 | Branch broadcasting not implemented.
0b1 | Branch broadcasting implemented.

This bit reads as 0b1.

#### TRCDATA, bits [4:3]

Indicates if the trace unit implements data tracing. Data tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCDATA | Meaning
--- | ---
0b00 | Data tracing not implemented.
0b11 | Data tracing implemented.

All other values are reserved.

This field reads as 0b00.

#### INSTP0, bits [2:1]

Indicates if load and store instructions are P0 instructions. Load and store instructions as P0 instructions is not implemented in ETE and this field is reserved for other trace architectures.

INSTP0 | Meaning
--- | ---
0b00 | Load and store instructions are not P0 instructions.
0b11 | Load and store instructions are P0 instructions.

All other values are reserved.

This field reads as 0b00.

#### Bit [0]

Reserved, RES1.

## Accessing the TRCIDR0

#### TRCIDR0 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x1E0

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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