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# GICV_AHPPIR, Virtual Machine Aliased Highest Priority Pending Interrupt Register

The GICV_AHPPIR characteristics are:

## Purpose

Provides the INTID of the highest priority pending Group 1 virtual interrupt in the List registers.

This register corresponds to the physical CPU interface register GICC_AHPPIR.

## Configuration

This register is available when the GIC implementation supports interrupt virtualization.

## Attributes

GICV_AHPPIR is a 32-bit register.

## Field descriptions

The GICV_AHPPIR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | INTID

#### Bits [31:25]

Reserved, RES0.

#### INTID, bits [24:0]

The INTID of the signaled interrupt.

Note

INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.

When affinity routing is not enabled:

- Bits [23:13] are RES0.
- For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.

A read of this register returns the spurious INTID 1023 if any of the following are true:

- There are no pending interrupts of sufficiently high priority value to be signaled to the PE.
- The highest priority pending interrupt is in Group 0.

## Accessing the GICV_AHPPIR

This register is used only when System register access is not enabled. When System register access is enabled:

- For AArch32 implementations, ICC_HPPIR1 provides equivalent functionality.
- For AArch64 implementations, ICC_HPPIR1_EL1 provides equivalent functionality.

This register is used for Group 1 interrupts only. GICV_HPPIR provides equivalent functionality for Group 0 interrupts.

The register does not return the INTID of an interrupt that is active and pending.

When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.

#### GICV_AHPPIR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual CPU interface | 0x0028 | GICV_AHPPIR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.

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27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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