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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCIDR5, ID Register 5

The TRCIDR5 characteristics are:

## Purpose

Returns the tracing capabilities of the trace unit.

## Configuration

External register TRCIDR5 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR5[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR5 are RES0.

## Attributes

TRCIDR5 is a 32-bit register.

## Field descriptions

The TRCIDR5 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | NUMCNTR | NUMSEQSTATE | RES0 | LPOVERRIDE | ATBTRIG | TRACEIDSIZE | RES0 | NUMEXTINSEL | NUMEXTIN

#### Bit [31]

Reserved, RES0.

#### NUMCNTR, bits [30:28]

Indicates the number of counters that are available for tracing.

NUMCNTR | Meaning
--- | ---
0b000 | No counters are available.
0b001 | One counter implemented.
0b010 | Two counters implemented.
0b011 | Three counters implemented.
0b100 | Four counters implemented.

All other values are reserved.

This field is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

#### NUMSEQSTATE, bits [27:25]

Indicates if the sequencer is implemented and the number of sequencer states that are implemented.

NUMSEQSTATE | Meaning
--- | ---
0b000 | The sequencer is not implemented.
0b100 | Four sequencer states are implemented.

All other values are reserved.

This field is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

#### Bit [24]

Reserved, RES0.

#### LPOVERRIDE, bit [23]

Indicates support for Low-power Override Mode.

LPOVERRIDE | Meaning
--- | ---
0b0 | The trace unit does not support Low-power Override Mode.
0b1 | The trace unit support Low-power Override Mode.

#### ATBTRIG, bit [22]

Indicates if the implementation can support ATB triggers.

ATBTRIG | Meaning
--- | ---
0b0 | The implementation does not support ATB triggers.
0b1 | The implementation supports ATB triggers.

This bit is RES0 if TRCIDR4.NUMRSPAIR == 0b0000.

#### TRACEIDSIZE, bits [21:16]

Indicates the trace ID width.

TRACEIDSIZE | Meaning
--- | ---
0b000000 | The external trace interface is not implemented.
0b000111 | The implementation supports a 7-bit trace ID.

All other values are reserved.

Note that AMBA ATB requires a 7-bit trace ID width.

#### Bits [15:12]

Reserved, RES0.

#### NUMEXTINSEL, bits [11:9]

Indicates how many external input selector resources are implemented.

NUMEXTINSEL | Meaning
--- | ---
0b000 | No external input selector resources are available.
0b001 | 1 external input selector resource is available.
0b010 | 2 external input selector resources are available.
0b011 | 3 external input selector resources are available.
0b100 | 4 external input selector resources are available.

All other values are reserved.

#### NUMEXTIN, bits [8:0]

Indicates how many external inputs are implemented.

NUMEXTIN | Meaning
--- | ---
0b111111111 | Unified PMU event selection.

All other values are reserved.

## Accessing the TRCIDR5

#### TRCIDR5 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x1F4

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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