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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCACATR<n>, Address Comparator Access Type Register <n>, n = 0 - 15

The TRCACATR<n> characteristics are:

## Purpose

Defines the type of access for the corresponding TRCACVR<n> Register. This register configures the context type, Exception levels, alignment, masking that is applied by the address comparator, and how the address comparator behaves when it is one half of an Address Range Comparator.

## Configuration

AArch64 System register TRCACATR<n> bits [63:0] are architecturally mapped to External register TRCACATR<n>[63:0] .

This register is present only when TRCIDR4.NUMACPAIRS * 2 > n and ETE is implemented. Otherwise, direct accesses to TRCACATR<n> are UNDEFINED.

## Attributes

TRCACATR<n> is a 64-bit register.

## Field descriptions

The TRCACATR<n> bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | EXLEVEL_NS_EL2 | EXLEVEL_NS_EL1 | EXLEVEL_NS_EL0 | EXLEVEL_S_EL3 | EXLEVEL_S_EL2 | EXLEVEL_S_EL1 | EXLEVEL_S_EL0 | RES0 | CONTEXT | CONTEXTTYPE | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:15]

Reserved, RES0.

#### EXLEVEL_NS_EL2, bit [14]
When Non-secure EL2 is implemented:

Non-secure EL2 address comparison control. Controls whether a comparison can occur at EL2 in Non-secure state.

EXLEVEL_NS_EL2 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Non-secure EL2.
0b1 | The address comparator does not perform comparisons in Non-secure EL2.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_NS_EL1, bit [13]
When Non-secure EL1 is implemented:

Non-secure EL1 address comparison control. Controls whether a comparison can occur at EL1 in Non-secure state.

EXLEVEL_NS_EL1 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Non-secure EL1.
0b1 | The address comparator does not perform comparisons in Non-secure EL1.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_NS_EL0, bit [12]
When Non-secure EL0 is implemented:

Non-secure EL0 address comparison control. Controls whether a comparison can occur at EL0 in Non-secure state.

EXLEVEL_NS_EL0 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Non-secure EL0.
0b1 | The address comparator does not perform comparisons in Non-secure EL0.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_S_EL3, bit [11]
When HaveEL(EL3):

Secure EL3 address comparison control. Controls whether a comparison can occur at EL3 in Secure state.

EXLEVEL_S_EL3 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Secure EL3.
0b1 | The address comparator does not perform comparisons in Secure EL3.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_S_EL2, bit [10]
When HaveEL(EL2) and ARMv8.4-SecEL2 is implemented:

Secure EL2 address comparison control. Controls whether a comparison can occur at EL2 in Secure state.

EXLEVEL_S_EL2 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Secure EL2.
0b1 | The address comparator does not perform comparisons in Secure EL2.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_S_EL1, bit [9]
When Secure EL1 is implemented:

Secure EL1 address comparison control. Controls whether a comparison can occur at EL1 in Secure state.

EXLEVEL_S_EL1 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Secure EL1.
0b1 | The address comparator does not perform comparisons in Secure EL1.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### EXLEVEL_S_EL0, bit [8]
When Secure EL0 is implemented:

Secure EL0 address comparison control. Controls whether a comparison can occur at EL0 in Secure state.

EXLEVEL_S_EL0 | Meaning
--- | ---
0b0 | The address comparator performs comparisons in Secure EL0.
0b1 | The address comparator does not perform comparisons in Secure EL0.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [7]

Reserved, RES0.

#### CONTEXT, bits [6:4]

Selects a Context Identifier Comparator or Virtual Context Identifier Comparator:

CONTEXT | Meaning
--- | ---
0b000 | Comparator 0.
0b001 | Comparator 1.
0b010 | Comparator 2.
0b011 | Comparator 3.
0b100 | Comparator 4.
0b101 | Comparator 5.
0b110 | Comparator 6.
0b111 | Comparator 7.

The width of this field is dependent on the maximum number of Context Identifier Comparators or Virtual Context Identifier Comparators implemented. Unimplemented bits are RES0.

If TRCIDR4.NUMCIDC == 0b0000 and TRCIDR4.NUMVMIDC == 0b0000, then this field is RES0.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### CONTEXTTYPE, bits [3:2]

Controls whether the address comparator is dependent on a Context Identifier Comparator, a Virtual Context Identifier Comparator, or both comparisons:

CONTEXTTYPE | Meaning
--- | ---
0b00 | The address comparator is not dependent on the Context Identifier Comparators or Virtual Context Identifier Comparators.
0b01 | The address comparator is dependent on the Context Identifier Comparator that the CONTEXT field specifies. If both the Context Identifier Comparator and the address comparison match, the address comparator signals a match.
0b10 | The address comparator is dependent on the Virtual Context Identifier Comparator that the CONTEXT field specifies. If both the Virtual Context Identifier Comparator and the address comparison match, the address comparator signals a match.
0b11 | The address comparator is dependent on the Context Identifier Comparator and Virtual Context Identifier Comparator that the CONTEXT field specifies. If the Context Identifier Comparator, the Virtual Context Identifier Comparator and address comparison all match, the address comparator signals a match.

If TRCIDR4.NUMCIDC == 0b0000, then bit [2] is RES0.

If TRCIDR4.NUMVMIDC == 0b0000, then bit [3] is RES0.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### Bits [1:0]

Reserved, RES0.

## Accessing the TRCACATR<n>

Must be programmed if any of the following are true:

- TRCBBCTLR.RANGE[n/2] == 0b1.

- TRCRSCTLR<a>.GROUP == 0b0100 and TRCRSCTLR<a>.SAC[n] == 0b1.

- TRCRSCTLR<a>.GROUP == 0b0101 and TRCRSCTLR<a>.ARC[n/2] == 0b1.

- TRCVIIECTLR.EXCLUDE[n/2] == 0b1.

- TRCVIIECTLR.INCLUDE[n/2] == 0b1.

- TRCVISSCTLR.START[n] == 0b1.

- TRCVISSCTLR.STOP[n] == 0b1.

- TRCSSCCR<>.ARC[n/2] == 0b1.

- TRCSSCCR<>.SAC[n] == 0b1.

- TRCQCTLR.RANGE[n/2] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Accesses to this register use the following encodings:

#### MRS <Xt>, TRCACATR<n>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0010 | 0b[n:2:0]0 | 0b01[n:3]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCACATR[UInt(op2<0>:CRm<3:1>)]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCACATR[UInt(op2<0>:CRm<3:1>)]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCACATR[UInt(op2<0>:CRm<3:1>)];

#### MSR TRCACATR<n>, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0010 | 0b[n:2:0]0 | 0b01[n:3]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCACATR[UInt(op2<0>:CRm<3:1>)] = X[t]; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCACATR[UInt(op2<0>:CRm<3:1>)] = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCACATR[UInt(op2<0>:CRm<3:1>)] = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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