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# ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4

The ID_MMFR4_EL1 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and ID_MMFR3_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

AArch64 System register ID_MMFR4_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR4[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_MMFR4_EL1 is a 64-bit register.

## Field descriptions

The ID_MMFR4_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
EVT | CCIDX | LSM | HPDS | CnP | XNX | AC2 | SpecSEI
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### EVT, bits [31:28]
When ARMv8.2-EVT is implemented:

Enhanced Virtualization Traps. If EL2 is implemented, indicates support for the HCR2.{TTLBIS, TOCU, TICAB, TID4} traps. Defined values are:

EVT | Meaning
--- | ---
0b0000 | HCR2.{TTLBIS, TOCU, TICAB, TID4} traps are not supported.
0b0001 | HCR2.{TOCU, TICAB, TID4} traps are supported. HCR2.TTLBIS trap is not supported.
0b0010 | HCR2.{TTLBIS, TOCU, TICAB, TID4} traps are supported.

All other values are reserved.

In Armv8.0, the only permitted value is 0b0000.

From Armv8.1, the permitted values are 0b0000, 0b0001, and 0b0010.

From Armv8.5 the permitted values are:

- 0b0000 when EL2 is not implemented.
- 0b0001 when EL2 is implemented. This feature is identified as ARMv8.2-EVT.

####
Otherwise:

Reserved, RES0.

#### CCIDX, bits [27:24]
From Armv8.3:

Support for use of the revised CCSIDR format and the presence of the CCSIDR2 is indicated. Defined values are:

CCIDX | Meaning
--- | ---
0b0000 | 32-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is not implemented.
0b0001 | 64-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is implemented.

All other values are reserved.

From Armv8.3, the permitted values are 0b0000 and 0b0001. This feature is identified as ARMv8.3-CCIDX.

####
Otherwise:

Reserved, RAZ.

#### LSM, bits [23:20]
From Armv8.2:

Indicates support for LSMAOE and nTLSMD bits in HSCTLR and SCTLR. Defined values are:

LSM | Meaning
--- | ---
0b0000 | LSMAOE and nTLSMD bits not supported.
0b0001 | LSMAOE and nTLSMD bits supported.

All other values are reserved.

ARMv8.2-LSMAOC implements the functionality identified by the value 0b0001.

####
Otherwise:

Reserved, RAZ.

#### HPDS, bits [19:16]
From Armv8.2:

Hierarchical permission disables bits in translation tables. Defined values are:

HPDS | Meaning
--- | ---
0b0000 | Disabling of hierarchical controls not supported.
0b0001 | Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits.
0b0010 | As for value 0b0001, and adds possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level for IMPLEMENTATION DEFINED use.

All other values are reserved.

ARMv8.2-AA32HPD implements the functionality identified by the value 0b0001.

ARMv8.2-TTPBHA implements the functionality added by the value 0b0010.

Note

The value 0b0000 implies that the encoding for TTBCR2 is unallocated.

####
Otherwise:

Reserved, RAZ.

#### CnP, bits [15:12]
From Armv8.2:

Common not Private translations. Defined values are:

CnP | Meaning
--- | ---
0b0000 | Common not Private translations not supported.
0b0001 | Common not Private translations supported.

All other values are reserved.

ARMv8.2-TTCNP implements the functionality identified by the value 0b0001.

From Armv8.2 the only permitted value is 0b0001.

####
Otherwise:

Reserved, RAZ.

#### XNX, bits [11:8]
From Armv8.2:

Support for execute-never control distinction by Exception level at stage 2. Defined values are:

XNX | Meaning
--- | ---
0b0000 | Distinction between EL0 and EL1 execute-never control at stage 2 not supported.
0b0001 | Distinction between EL0 and EL1 execute-never control at stage 2 supported.

All other values are reserved.

ARMv8.2-TTS2UXN implements the functionality identified by the value 0b0001.

When ARMv8.2-TTS2UXN is implemented:

- If all of the following conditions are true it is IMPLEMENTATION DEFINED whether the value of ID_MMFR4_EL1.XNX is 0b0000 or 0b0001:
  - ID_AA64MMFR1_EL1.XNX ==1.
  - EL2 cannot use AArch32.
  - EL1 can use AArch32.
- If EL2 can use AArch32 then the only permitted value is 0b0001.

####
Otherwise:

Reserved, RAZ.

#### AC2, bits [7:4]

Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2. Defined values are:

AC2 | Meaning
--- | ---
0b0000 | ACTLR2 and HACTLR2 are not implemented.
0b0001 | ACTLR2 and HACTLR2 are implemented.

All other values are reserved.

In Armv8.0 and Armv8.1 the permitted values are 0b0000 and 0b0001.

From Armv8.2, the only permitted value is 0b0001.

#### SpecSEI, bits [3:0]
When RAS is implemented:

Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:

SpecSEI | Meaning
--- | ---
0b0000 | The PE never generates an SError interrupt due to an External abort on a speculative read.
0b0001 | The PE might generate an SError interrupt due to an External abort on a speculative read.

All other values are reserved.

####
Otherwise:

Reserved, RES0. This provides no information about whether the PE generates a speculative SError interrupt.

## Accessing the ID_MMFR4_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_MMFR4_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0010 | 0b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_MMFR4_EL1) || boolean IMPLEMENTATION_DEFINED "ID_MMFR4_EL1 trapped by HCR_EL2.TID3 and ID_MMFR4 trapped by HCR_EL2.TID3 and HCR.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_MMFR4_EL1; elsif PSTATE.EL == EL2 then return ID_MMFR4_EL1; elsif PSTATE.EL == EL3 then return ID_MMFR4_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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