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# TRCIDR3, ID Register 3

The TRCIDR3 characteristics are:

## Purpose

Returns the base architecture of the trace unit.

## Configuration

AArch64 System register TRCIDR3 bits [31:0] are architecturally mapped to External register TRCIDR3[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR3 are UNDEFINED.

## Attributes

TRCIDR3 is a 64-bit register.

## Field descriptions

The TRCIDR3 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
NOOVERFLOW | NUMPROC[2:0] | SYSSTALL | STALLCTL | SYNCPR | TRCERR | RES0 | EXLEVEL_NS_EL2 | EXLEVEL_NS_EL1 | EXLEVEL_NS_EL0 | EXLEVEL_S_EL3 | EXLEVEL_S_EL2 | EXLEVEL_S_EL1 | EXLEVEL_S_EL0 | RES0 | NUMPROC[4:3] | CCITMIN
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### NOOVERFLOW, bit [31]

Indicates if overflow prevention is implemented.

NOOVERFLOW | Meaning
--- | ---
0b0 | Overflow prevention is not implemented.
0b1 | Overflow prevention is implemented.

#### NUMPROC[2:0], bits [30:28]

This field is bits[2:0] of NUMPROC[4:0].

Indicates the number of PEs available for tracing.

NUMPROC | Meaning
--- | ---
0b00000 | The trace unit can trace one PE.

This field reads as 0b00000.

The NUMPROC field is split as follows:

- NUMPROC[2:0] is TRCIDR3[30:28].
- NUMPROC[4:3] is TRCIDR3[13:12].

#### SYSSTALL, bit [27]
When TRCIDR3.STALLCTL == 0b1:

Indicates if stalling of the PE is permitted.

SYSSTALL | Meaning
--- | ---
0b0 | Stalling of the PE is not permitted.
0b1 | Stalling of the PE is permitted.

The value of this field might be dynamic and change based on system conditions.

####
Otherwise:

Reserved, RES0.

#### STALLCTL, bit [26]

Indicates if trace unit implements stalling of the PE.

STALLCTL | Meaning
--- | ---
0b0 | Stalling of the PE is not implemented.
0b1 | Stalling of the PE is implemented.

#### SYNCPR, bit [25]

Indicates if an implementation has a fixed synchronization period.

SYNCPR | Meaning
--- | ---
0b0 | TRCSYNCPR is read-write so software can change the synchronization period.
0b1 | TRCSYNCPR is read-only so the synchronization period is fixed.

This bit reads as 0b0.

#### TRCERR, bit [24]

Indicates forced tracing of System Error exceptions is implemented.

TRCERR | Meaning
--- | ---
0b0 | Forced tracing of System Error exceptions is not implemented.
0b1 | Forced tracing of System Error exceptions is implemented.

This bit reads as 0b1.

#### Bit [23]

Reserved, RES0.

#### EXLEVEL_NS_EL2, bit [22]

Indicates if Non-secure EL2 implemented.

EXLEVEL_NS_EL2 | Meaning
--- | ---
0b0 | Non-secure EL2 is not implemented.
0b1 | Non-secure EL2 is implemented.

#### EXLEVEL_NS_EL1, bit [21]

Indicates if Non-secure EL1 implemented.

EXLEVEL_NS_EL1 | Meaning
--- | ---
0b0 | Non-secure EL1 is not implemented.
0b1 | Non-secure EL1 is implemented.

#### EXLEVEL_NS_EL0, bit [20]

Indicates if Non-secure EL0 implemented.

EXLEVEL_NS_EL0 | Meaning
--- | ---
0b0 | Non-secure EL0 is not implemented.
0b1 | Non-secure EL0 is implemented.

#### EXLEVEL_S_EL3, bit [19]

Indicates if Secure EL3 implemented.

EXLEVEL_S_EL3 | Meaning
--- | ---
0b0 | Secure EL3 is not implemented.
0b1 | Secure EL3 is implemented.

#### EXLEVEL_S_EL2, bit [18]

Indicates if Secure EL2 implemented.

EXLEVEL_S_EL2 | Meaning
--- | ---
0b0 | Secure EL2 is not implemented.
0b1 | Secure EL2 is implemented.

#### EXLEVEL_S_EL1, bit [17]

Indicates if Secure EL1 implemented.

EXLEVEL_S_EL1 | Meaning
--- | ---
0b0 | Secure EL1 is not implemented.
0b1 | Secure EL1 is implemented.

#### EXLEVEL_S_EL0, bit [16]

Indicates if Secure EL0 implemented.

EXLEVEL_S_EL0 | Meaning
--- | ---
0b0 | Secure EL0 is not implemented.
0b1 | Secure EL0 is implemented.

#### Bits [15:14]

Reserved, RES0.

#### NUMPROC[4:3], bits [13:12]

This field is bits[4:3] of NUMPROC[4:0].

See NUMPROC[2:0] for the field description.

#### CCITMIN, bits [11:0]
When TRCIDR0.TRCCCI == 0b1:

Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.

When cycle counting in the instruction trace is supported, that is TRCIDR0.TRCCCI == 0b1, then the minimum value of this field is 0x001.

####
Otherwise:

Reserved, RES0.

## Accessing the TRCIDR3

Accesses to this register use the following encodings:

#### MRS <Xt>, TRCIDR3

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0000 | 0b1011 | 0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR3; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR3; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR3;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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