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# TLBI VMALLS12E1, TLB Invalidate by VMID, All at Stage 1 and 2, EL1

The TLBI VMALLS12E1 characteristics are:

## Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

- The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.

- If SCR_EL3.NS is 0, then

  - The entry would be required to translate an address using the Secure EL1&0 translation regime.

  - If ARMv8.4-SecEL2 is implemented and enabled, the entry would be used with the current VMID.

- If SCR_EL3.NS is 1, then:

  - The entry would be required to translate an address using the Non-secure EL1&0 translation regime.

  - If Non-secure EL2 is implemented, the entry would be used with the current VMID.

The invalidation applies to the PE that executes this System instruction.

Note

For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.

## Configuration

## Attributes

TLBI VMALLS12E1 is a 64-bit System instruction.

## Field descriptions

TLBI VMALLS12E1 ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

## Executing the TLBI VMALLS12E1 instruction

Accesses to this instruction use the following encodings:

#### TLBI VMALLS12E1{, <Xt>}

op0 | op1 | CRn | CRm | op2 | Rt
--- | --- | --- | --- | --- | ---
0b01 | 0b100 | 0b1000 | 0b0111 | 0b110 | 0b11111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12E1(); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALLE1(); else TLBI_VMALLS12E1();

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27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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