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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCIDR1, ID Register 1

The TRCIDR1 characteristics are:

## Purpose

Returns the tracing capabilities of the trace unit.

## Configuration

External register TRCIDR1 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR1[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCIDR1 are RES0.

## Attributes

TRCIDR1 is a 32-bit register.

## Field descriptions

The TRCIDR1 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DESIGNER | RES0 | RES1 | TRCARCHMAJ | TRCARCHMIN | REVISION

#### DESIGNER, bits [31:24]

Indicates which company designed the trace unit.

DESIGNER | Meaning
--- | ---
0x41 | Arm Limited.

All other values are reserved.

#### Bits [23:16]

Reserved, RES0.

#### Bits [15:12]

Reserved, RES1.

#### TRCARCHMAJ, bits [11:8]

Major architecture version.

TRCARCHMAJ | Meaning
--- | ---
0b1111 | If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH.

All other values are reserved.

This field reads as 0b1111.

#### TRCARCHMIN, bits [7:4]

Minor architecture version.

TRCARCHMIN | Meaning
--- | ---
0b1111 | If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH.

All other values are reserved.

This field reads as 0b1111.

#### REVISION, bits [3:0]

Implementation revision.

Returns an IMPLEMENTATION DEFINED value that identifies the revision of:

- The trace registers.
- The OS Lock registers.

Arm recommends that the initial implementation sets REVISION == 0x0 and the field then increments for any subsequent implementations. However, it is acceptable to omit some values or use another scheme to identify the revision number.

Arm recommends that TRCPIDR2.REVISION == TRCIDR1.REVISION. However, in situations where it is difficult to align these fields, such as with a metal layer fix then it is acceptable to change the REVISION fields independently.

## Accessing the TRCIDR1

#### TRCIDR1 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x1E4

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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