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# TLBI ALLE3OS, TLB Invalidate All, EL3, Outer Shareable

The TLBI ALLE3OS characteristics are:

## Purpose

If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

- The entry is a stage 1 translation table entry, from any level of the translation table walk.

- The entry would be required to translate an address using the EL3 translation regime.

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.

## Configuration

This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI ALLE3OS are UNDEFINED.

## Attributes

TLBI ALLE3OS is a 64-bit System instruction.

## Field descriptions

TLBI ALLE3OS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

## Executing the TLBI ALLE3OS instruction

Accesses to this instruction use the following encodings:

#### TLBI ALLE3OS{, <Xt>}

op0 | op1 | CRn | CRm | op2 | Rt
--- | --- | --- | --- | --- | ---
0b01 | 0b110 | 0b1000 | 0b0001 | 0b000 | 0b11111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then TLBI_ALLE3OS();

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15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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