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# EDRCR, External Debug Reserve Control Register

The EDRCR characteristics are:

## Purpose

This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.

## Configuration

EDRCR is in the Core power domain.

## Attributes

EDRCR is a 32-bit register.

## Field descriptions

The EDRCR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | CBRRQ | CSPA | CSE | RES0

#### Bits [31:5]

Reserved, RES0.

#### CBRRQ, bit [4]

Allow imprecise entry to Debug state. The actions on writing to this bit are:

CBRRQ | Meaning
--- | ---
0b0 | No action.
0b1 | Allow imprecise entry to Debug state, for example by canceling pending bus accesses.

Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.

This feature is optional. If this feature is not implemented, writes to this bit are ignored.

#### CSPA, bit [3]

Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:

CSPA | Meaning
--- | ---
0b0 | No action.
0b1 | Clear the EDSCR.PipeAdv bit to 0.

#### CSE, bit [2]

Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:

CSE | Meaning
--- | ---
0b0 | No action.
0b1 | Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the PE is in Debug state, the EDSCR.ITO bit, to 0.

#### Bits [1:0]

Reserved, RES0.

## Accessing the EDRCR

#### EDRCR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
Debug | 0x090 | EDRCR

This interface is accessible as follows:

- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() access to this register is WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() access to this register is WO.
- Otherwise access to this register returns an Error.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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