AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TLBI RIPAS2LE1IS, TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

The TLBI RIPAS2LE1IS characteristics are:

## Purpose

If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

- The entry is a stage 2 only translation table entry, from the final level of the translation table walk.

- One of the following applies:

  - SCR_EL3.NS==1 and the entry would be required to translate the specified IPA using the Non-secure EL1&0 translation regime.

  - SCR_EL3.NS==0 and the entry would be required to translate the specified IPA using the Secure EL1&0 translation regime.

- The entry would be used with the current VMID.

- The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2^(5*SCALE +1) * Translation_Granule_Size)].

The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.

The range of addresses invalidated is UNPREDICTABLE when:

- For the 4K translation granule:

  - If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.

  - If TTL==10 and BaseADDR[20:12] is not equal to 000000000.

- For the 16K translation granule:

  - If TTL==10 and BaseADDR[24:14] is not equal to 00000000000.

- For the 64K translation granule:

  - If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.

  - If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.

For more information about the architectural requirements for this System instruction see 'Invalidation of TLB entries from stage 2 translations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

## Configuration

This instruction is present only when ARMv8.4-TLBI is implemented. Otherwise, direct accesses to TLBI RIPAS2LE1IS are UNDEFINED.

## Attributes

TLBI RIPAS2LE1IS is a 64-bit System instruction.

## Field descriptions

The TLBI RIPAS2LE1IS input value bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
NS | RES0 | TG | SCALE | NUM | TTL | BaseADDR
BaseADDR
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### NS, bit [63]
When ARMv8.4-SecEL2 is implemented:

Not Secure. Specifies the IPA space.

NS | Meaning
--- | ---
0b0 | IPA is in the Secure IPA space.
0b1 | IPA is in the Non-secure IPA space.

When the instruction is executed in Non-secure state, this field is RES0, and the instruction applies only to the Non-secure IPA space.

When ARMv8.4-SecEL2 is not implemented or is disabled in the current Security state, this field is RES0.

####
Otherwise:

Reserved, RES0.

#### Bits [62:48]

Reserved, RES0.

#### TG, bits [47:46]

Translation granule size.

TG | Meaning
--- | ---
0b00 | Reserved.
0b01 | 4K translation granule.
0b10 | 16K translation granule.
0b11 | 64K translation granule.

The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.

#### SCALE, bits [45:44]

The exponent element of the calculation that is used to produce the upper range.

#### NUM, bits [43:39]

The base element of the calculation that is used to produce the upper range.

#### TTL, bits [38:37]

TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.

TTL | Meaning
--- | ---
0b00 | The entries in the range can be using any level for the translation table entries.
0b01 | When using a 4KB or 64KB translation granule, all entries to invalidate are Level 1 translation table entries. When using a 16KB translation granule, this value is reserved. Hardware should treat this field as 0b00.
0b10 | All entries to invalidate are Level 2 translation table entries.
0b11 | All entries to invalidate are Level 3 translation table entries.

#### BaseADDR, bits [36:0]

The starting address for the range of the maintenance instruction.

When using a 4KB translation granule, this field is BaseADDR[48:12].

When using a 16KB translation granule, this field is BaseADDR[50:14].

When using a 64KB translation granule, this field is BaseADDR[52:16].

## Executing the TLBI RIPAS2LE1IS instruction

Accesses to this instruction use the following encodings:

#### TLBI RIPAS2LE1IS{, <Xt>}

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b01 | 0b100 | 0b1000 | 0b0000 | 0b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_RIPAS2LE1IS(X[t]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then //no operation else TLBI_RIPAS2LE1IS(X[t]);

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.