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# ERRCIDR1, Component Identification Register 1

The ERRCIDR1 characteristics are:

## Purpose

Provides discovery information for the component.

## Configuration

Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRCIDR1 are RES0.

## Attributes

ERRCIDR1 is a 32-bit register.

## Field descriptions

The ERRCIDR1 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | CLASS | PRMBL_1

#### Bits [31:8]

Reserved, RES0.

#### CLASS, bits [7:4]

Component class.

CLASS | Meaning
--- | ---
0b1111 | Generic peripheral with IMPLEMENTATION DEFINED register layout.

This field reads as 0xF.

Other values are defined by the CoreSight Architecture.

#### PRMBL_1, bits [3:0]

Component identification preamble, segment 1. This field reads as 0x0.

## Accessing the ERRCIDR1

#### ERRCIDR1 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0xFF4 | ERRCIDR1

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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