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# ID_ISAR0, Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:

## Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register ID_ISAR0 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR0_EL1[31:0] .

## Attributes

ID_ISAR0 is a 32-bit register.

## Field descriptions

The ID_ISAR0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | Divide | Debug | Coproc | CmpBranch | BitField | BitCount | Swap

#### Bits [31:28]

Reserved, RES0.

#### Divide, bits [27:24]

Indicates the implemented Divide instructions. Defined values are:

Divide | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds SDIV and UDIV in the T32 instruction set.
0b0010 | As for 0b0001, and adds SDIV and UDIV in the A32 instruction set.

All other values are reserved.

In Armv8-A the only permitted value is 0b0010.

#### Debug, bits [23:20]

Indicates the implemented Debug instructions. Defined values are:

Debug | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds BKPT.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

#### Coproc, bits [19:16]

Indicates the implemented System register access instructions. Defined values are:

Coproc | Meaning
--- | ---
0b0000 | None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions.
0b0001 | Adds generic CDP, LDC, MCR, MRC, and STC.
0b0010 | As for 0b0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2.
0b0011 | As for 0b0010, and adds generic MCRR and MRRC.
0b0100 | As for 0b0011, and adds generic MCRR2 and MRRC2.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### CmpBranch, bits [15:12]

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set. Defined values are:

CmpBranch | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds CBNZ and CBZ.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

#### BitField, bits [11:8]

Indicates the implemented BitField instructions. Defined values are:

BitField | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds BFC, BFI, SBFX, and UBFX.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

#### BitCount, bits [7:4]

Indicates the implemented Bit Counting instructions. Defined values are:

BitCount | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds CLZ.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

#### Swap, bits [3:0]

Indicates the implemented Swap instructions in the A32 instruction set. Defined values are:

Swap | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds SWP and SWPB.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

## Accessing the ID_ISAR0

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR0; elsif PSTATE.EL == EL2 then return ID_ISAR0; elsif PSTATE.EL == EL3 then return ID_ISAR0;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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