AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# ICC_AP1R<n>_EL1, Interrupt Controller Active Priorities Group 1 Registers, n = 0 - 3

The ICC_AP1R<n>_EL1 characteristics are:

## Purpose

Provides information about Group 1 active priorities.

## Configuration

AArch64 System register ICC_AP1R<n>_EL1 bits [31:0] (S) are architecturally mapped to AArch32 System register ICC_AP1R<n>[31:0] (S) .

AArch64 System register ICC_AP1R<n>_EL1 bits [31:0] (NS) are architecturally mapped to AArch32 System register ICC_AP1R<n>[31:0] (NS) .

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ICC_AP1R<n>_EL1 is a 64-bit register.

## Field descriptions

The ICC_AP1R<n>_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
IMPLEMENTATION DEFINED
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

This field resets to 0.

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

## Accessing the ICC_AP1R<n>_EL1

Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the interrupt prioritization system, causing:

- Interrupts that should preempt execution to not preempt execution.
- Interrupts that should not preempt execution to preempt execution.

ICC_AP1R1_EL1 is only implemented in implementations that support 6 or more bits of priority. ICC_AP1R2_EL1 and ICC_AP1R3_EL1 are only implemented in implementations that support 7 or more bits of priority. Unimplemented registers are UNDEFINED.

Note

The number of bits of preemption is indicated by ICH_VTR_EL2.PREbits.

Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:

- ICC_AP0R<n>_EL1.
- Secure ICC_AP1R<n>_EL1.
- Non-secure ICC_AP1R<n>_EL1.

Accesses to this register use the following encodings:

#### MRS <Xt>, ICC_AP1R<n>_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1100 | 0b1001 | 0b0[n:1:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then return ICV_AP1R_EL1[UInt(op2<1:0>)]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)]; else return ICC_AP1R_EL1[UInt(op2<1:0>)]; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)]; else return ICC_AP1R_EL1[UInt(op2<1:0>)]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x03); else if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)];

#### MSR ICC_AP1R<n>_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1100 | 0b1001 | 0b0[n:1:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then AArch64.SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x03); else if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.