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# TRFCR_EL2, Trace Filter Control Register (EL2)

The TRFCR_EL2 characteristics are:

## Purpose

Provides EL2 controls for Trace.

## Configuration

AArch64 System register TRFCR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HTRFCR[31:0] .

This register is present only when ARMv8.4-Trace is implemented. Otherwise, direct accesses to TRFCR_EL2 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

TRFCR_EL2 is a 64-bit register.

## Field descriptions

The TRFCR_EL2 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | TS | RES0 | CX | RES0 | E2TRE | E0HTRE
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:7]

Reserved, RES0.

#### TS, bits [6:5]

Timestamp Control. Controls which timebase is used for trace timestamps.

TS | Meaning
--- | ---
0b00 | Timestamp controlled by TRFCR_EL1.TS or TRFCR.TS.
0b01 | Virtual timestamp. The traced timestamp is the physical counter value, minus the value of CNTVOFF_EL2.
0b11 | Physical timestamp. The traced timestamp is the physical counter value.

This field is ignored if SelfHostedTraceEnabled() == FALSE.

On a Warm reset, this field resets to 0.

#### Bit [4]

Reserved, RES0.

#### CX, bit [3]

CONTEXTIDR_EL2 and VMID trace enable.

CX | Meaning
--- | ---
0b0 | CONTEXTIDR_EL2 and VMID trace prohibited.
0b1 | CONTEXTIDR_EL2 and VMID trace allowed.

This field is ignored if SelfHostedTraceEnabled() == FALSE.

On a Warm reset, this field resets to 0.

#### Bit [2]

Reserved, RES0.

#### E2TRE, bit [1]

EL2 Trace Enable.

E2TRE | Meaning
--- | ---
0b0 | Trace is prohibited at EL2.
0b1 | Trace is allowed at EL2.

When SelfHostedTraceEnabled() == FALSE, this field is ignored.

On a Warm reset, this field resets to 0.

#### E0HTRE, bit [0]

EL0 Trace Enable.

E0HTRE | Meaning
--- | ---
0b0 | Trace is prohibited at EL0 when HCR_EL2.TGE == 1.
0b1 | Trace is allowed at EL0 when HCR_EL2.TGE == 1.

This field is ignored if any of the following are true:

- HCR_EL2.TGE == 0.
- SelfHostedTraceEnabled() == FALSE.
- EL2 is disabled in the current security state.

On a Warm reset, this field resets to 0.

## Accessing the TRFCR_EL2

Accesses to this register use the following encodings:

#### MRS <Xt>, TRFCR_EL2

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0001 | 0b0010 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRFCR_EL2; elsif PSTATE.EL == EL3 then return TRFCR_EL2;

#### MSR TRFCR_EL2, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b100 | 0b0001 | 0b0010 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRFCR_EL2 = X[t]; elsif PSTATE.EL == EL3 then TRFCR_EL2 = X[t];

#### MRS <Xt>, TRFCR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0001 | 0b0010 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x880]; else return TRFCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return TRFCR_EL2; else return TRFCR_EL1; elsif PSTATE.EL == EL3 then return TRFCR_EL1;

#### MSR TRFCR_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0001 | 0b0010 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x880] = X[t]; else TRFCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then TRFCR_EL2 = X[t]; else TRFCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRFCR_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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