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# SPSR, Saved Program Status Register

The SPSR characteristics are:

## Purpose

Holds the saved process state for the current mode.

## Configuration

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

SPSR is a 32-bit register.

## Field descriptions

The SPSR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
N | Z | C | V | Q | IT[1:0] | J | SSBS | PAN | DIT | IL | GE | IT[7:2] | E | A | I | F | T | M[4] | M[3:0]

#### N, bit [31]

Set to the value of PSTATE.N on taking an exception to the current mode, and copied to PSTATE.N on executing an exception return operation in the current mode.

#### Z, bit [30]

Set to the value of PSTATE.Z on taking an exception to the current mode, and copied to PSTATE.Z on executing an exception return operation in the current mode.

#### C, bit [29]

Set to the value of PSTATE.C on taking an exception to the current mode, and copied to PSTATE.C on executing an exception return operation in the current mode.

#### V, bit [28]

Set to the value of PSTATE.V on taking an exception to the current mode, and copied to PSTATE.V on executing an exception return operation in the current mode.

#### Q, bit [27]

Set to the value of PSTATE.Q on taking an exception to the current mode, and copied to PSTATE.Q on executing an exception return operation in the current mode.

#### IT[1:0], bits [26:25]

IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field.

#### J, bit [24]

RES0.

In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. Armv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.

#### SSBS, bit [23]
When ARMv8.0-SSBS is implemented:

Speculative Store Bypass Safe. This bit is set to the value of PSTATE.SSBS on taking an exception to the current mode, and copied to PSTATE.SSBS on executing an exception return operation in the current mode.

####
Otherwise:

Reserved, RES0.

#### PAN, bit [22]
When ARMv8.1-PAN is implemented:

Privileged Access Never. This bit is set to the value of PSTATE.PAN on taking an exception to the current mode, and copied to PSTATE.PAN on executing an exception return operation in the current mode.

####
Otherwise:

Reserved, RES0.

#### DIT, bit [21]
When ARMv8.4-DIT is implemented:

Data Independent Timing. This bit is set to the value of PSTATE.DIT on taking an exception to the current mode, and copied to PSTATE.DIT on executing an exception return operation in the current mode.

####
Otherwise:

Reserved, RES0.

#### IL, bit [20]

Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.

#### GE, bits [19:16]

Greater than or Equal flags, for parallel addition and subtraction.

#### IT[7:2], bits [15:10]

IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts.

- IT[7:5] holds the base condition for the IT block. The base condition is the top 3 bits of the condition code specified by the first condition field of the IT instruction.
- IT[4:0] encodes the size of the IT block, which is the number of instructions that are to be conditionally executed, by the position of the least significant 1 in this field. It also encodes the value of the least significant bit of the condition code for each instruction in the block.

The IT field is 0b00000000 when no IT block is active.

#### E, bit [9]

Endianness state bit. Controls the load and store endianness for data accesses:

E | Meaning
--- | ---
0b0 | Little-endian operation
0b1 | Big-endian operation.

Instruction fetches ignore this bit.

If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.

If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.

Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.

When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.

#### A, bit [8]

SError interrupt mask bit.

A | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

#### I, bit [7]

IRQ mask bit.

I | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

#### F, bit [6]

FIQ mask bit.

F | Meaning
--- | ---
0b0 | Exception not masked.
0b1 | Exception masked.

#### T, bit [5]

T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from.

T | Meaning
--- | ---
0b0 | Taken from A32 state.
0b1 | Taken from T32 state.

#### M[4], bit [4]

Execution state that the exception was taken from.

M[4] | Meaning
--- | ---
0b1 | Exception taken from AArch32.

#### M[3:0], bits [3:0]

AArch32 mode that an exception was taken from.

M[3:0] | Meaning
--- | ---
0b0000 | User.
0b0001 | FIQ.
0b0010 | IRQ.
0b0011 | Supervisor.
0b0110 | Monitor (only valid in Secure state, if EL3 is implemented and can use AArch32).
0b0111 | Abort.
0b1010 | Hyp.
0b1011 | Undefined.
0b1111 | System.

Other values are reserved.

## Accessing the SPSR

SPSR can be read using the MRS instruction and written using the MSR (register) or MSR (immediate) instructions. For more details, see MRS, MSR (register), and MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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