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# ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1

The ID_MMFR1_EL1 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

AArch64 System register ID_MMFR1_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR1[31:0] .

In an implementation that supports only AArch64 state, this register is UNKNOWN.

## Attributes

ID_MMFR1_EL1 is a 64-bit register.

## Field descriptions

The ID_MMFR1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
BPred | L1TstCln | L1Uni | L1Hvd | L1UniSW | L1HvdSW | L1UniVA | L1HvdVA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### BPred, bits [31:28]

Branch Predictor. Indicates branch predictor management requirements. Defined values are:

BPred | Meaning
--- | ---
0b0000 | No branch predictor, or no MMU present. Implies a fixed MPU configuration.
0b0001 | Branch predictor requires flushing on: Enabling or disabling a stage of address translation. Writing new data to instruction locations. Writing new mappings to the translation tables. Changes to the TTBR0, TTBR1, or TTBCR registers. Changes to the ContextID or ASID, or to the FCSE ProcessID if this is supported.
0b0010 | Branch predictor requires flushing on: Enabling or disabling a stage of address translation. Writing new data to instruction locations. Writing new mappings to the translation tables. Any change to the TTBR0, TTBR1, or TTBCR registers without a change to the corresponding ContextID or ASID, or FCSE ProcessID if this is supported.
0b0011 | Branch predictor requires flushing only on writing new data to instruction locations.
0b0100 | For execution correctness, branch predictor requires no flushing at any time.

All other values are reserved.

In Armv8-A the permitted values are 0b0010, 0b0011, or 0b0100. For values other than 0b0000 and 0b0100 the Arm Architecture Reference Manual, or the product documentation, might give more information about the required maintenance.

#### L1TstCln, bits [27:24]

Level 1 cache Test and Clean. Indicates the supported Level 1 data cache test and clean operations, for Harvard or unified cache implementations. Defined values are:

L1TstCln | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported Level 1 data cache test and clean operations are: Test and clean data cache.
0b0010 | As for 0001, and adds: Test, clean, and invalidate data cache.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1Uni, bits [23:20]

Level 1 Unified cache. Indicates the supported entire Level 1 cache maintenance operations for a unified cache implementation. Defined values are:

L1Uni | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported entire Level 1 cache operations are: Invalidate cache, including branch predictor if appropriate. Invalidate branch predictor, if appropriate.
0b0010 | As for 0001, and adds: Clean cache, using a recursive model that uses the cache dirty status bit. Clean and invalidate cache, using a recursive model that uses the cache dirty status bit.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1Hvd, bits [19:16]

Level 1 Harvard cache. Indicates the supported entire Level 1 cache maintenance operations for a Harvard cache implementation. Defined values are:

L1Hvd | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported entire Level 1 cache operations are: Invalidate instruction cache, including branch predictor if appropriate. Invalidate branch predictor, if appropriate.
0b0010 | As for 0001, and adds: Invalidate data cache. Invalidate data cache and instruction cache, including branch predictor if appropriate.
0b0011 | As for 0010, and adds: Clean data cache, using a recursive model that uses the cache dirty status bit. Clean and invalidate data cache, using a recursive model that uses the cache dirty status bit.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1UniSW, bits [15:12]

Level 1 Unified cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a unified cache implementation. Defined values are:

L1UniSW | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported Level 1 unified cache line maintenance operations by set/way are: Clean cache line by set/way.
0b0010 | As for 0001, and adds: Clean and invalidate cache line by set/way.
0b0011 | As for 0010, and adds: Invalidate cache line by set/way.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1HvdSW, bits [11:8]

Level 1 Harvard cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard cache implementation. Defined values are:

L1HvdSW | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported Level 1 Harvard cache line maintenance operations by set/way are: Clean data cache line by set/way. Clean and invalidate data cache line by set/way.
0b0010 | As for 0001, and adds: Invalidate data cache line by set/way.
0b0011 | As for 0010, and adds: Invalidate instruction cache line by set/way.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1UniVA, bits [7:4]

Level 1 Unified cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a unified cache implementation. Defined values are:

L1UniVA | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported Level 1 unified cache line maintenance operations by VA are: Clean cache line by VA. Invalidate cache line by VA. Clean and invalidate cache line by VA.
0b0010 | As for 0001, and adds: Invalidate branch predictor by VA, if branch predictor is implemented.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### L1HvdVA, bits [3:0]

Level 1 Harvard cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a Harvard cache implementation. Defined values are:

L1HvdVA | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Supported Level 1 Harvard cache line maintenance operations by VA are: Clean data cache line by VA. Invalidate data cache line by VA. Clean and invalidate data cache line by VA. Clean instruction cache line by VA.
0b0010 | As for 0001, and adds: Invalidate branch predictor by VA, if branch predictor is implemented.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

## Accessing the ID_MMFR1_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_MMFR1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0001 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_MMFR1_EL1; elsif PSTATE.EL == EL2 then return ID_MMFR1_EL1; elsif PSTATE.EL == EL3 then return ID_MMFR1_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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