AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCSYNCPR, Synchronization Period Register

The TRCSYNCPR characteristics are:

## Purpose

Controls how often trace protocol synchronization requests occur.

## Configuration

External register TRCSYNCPR bits [31:0] are architecturally mapped to AArch64 System register TRCSYNCPR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCSYNCPR are RES0.

## Attributes

TRCSYNCPR is a 32-bit register.

## Field descriptions

The TRCSYNCPR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PERIOD

#### Bits [31:5]

Reserved, RES0.

#### PERIOD, bits [4:0]

Defines the number of bytes of trace between each periodic trace protocol synchronization request.

PERIOD | Meaning
--- | ---
0b00000 | Trace protocol synchronization is disabled.
0b01000 | Trace protocol synchronization request occurs after 28 bytes of trace.
0b01001 | Trace protocol synchronization request occurs after 29 bytes of trace.
0b01010 | Trace protocol synchronization request occurs after 210 bytes of trace.
0b01011 | Trace protocol synchronization request occurs after 211 bytes of trace.
0b01100 | Trace protocol synchronization request occurs after 212 bytes of trace.
0b01101 | Trace protocol synchronization request occurs after 213 bytes of trace.
0b01110 | Trace protocol synchronization request occurs after 214 bytes of trace.
0b01111 | Trace protocol synchronization request occurs after 215 bytes of trace.
0b10000 | Trace protocol synchronization request occurs after 216 bytes of trace.
0b10001 | Trace protocol synchronization request occurs after 217 bytes of trace.
0b10010 | Trace protocol synchronization request occurs after 218 bytes of trace.
0b10011 | Trace protocol synchronization request occurs after 219 bytes of trace.
0b10100 | Trace protocol synchronization request occurs after 220 bytes of trace.

Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is CONSTRAINED UNPREDICTABLE and one of the following behaviors occurs:

- No trace protocol synchronization requests are generated by this counter.
- Trace protocol synchronization requests occur at the specified period.
- Trace protocol synchronization requests occur at some other UNKNOWN period which can vary.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCSYNCPR

Must be programmed if TRCIDR3.SYNCPR == 0b0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCSYNCPR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x034

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.