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# AMPIDR0, Activity Monitors Peripheral Identification Register 0

The AMPIDR0 characteristics are:

## Purpose

Provides information to identify an activity monitors component.

For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

## Configuration

The power domain of AMPIDR0 is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMPIDR0 are RES0.

## Attributes

AMPIDR0 is a 32-bit register.

## Field descriptions

The AMPIDR0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PART_0

#### Bits [31:8]

Reserved, RES0.

#### PART_0, bits [7:0]

Part number, least significant byte.

The value of this field is IMPLEMENTATION DEFINED.

## Accessing the AMPIDR0

#### AMPIDR0 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
AMU | 0xFE0 | AMPIDR0

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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