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# ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1

The ID_AA64ISAR1_EL1 characteristics are:

## Purpose

Provides information about the features and instructions implemented in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

## Attributes

ID_AA64ISAR1_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64ISAR1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0 | SPECRES | SB | FRINTTS
GPI | GPA | LRCPC | FCMA | JSCVT | API | APA | DPB
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:44]

Reserved, RES0.

#### SPECRES, bits [43:40]

Speculation invalidation instruction support in AArch64 state. Defined values are:

SPECRES | Meaning
--- | ---
0b0000 | CFP RCTX, DVP RCTX, and CPP RCTX instructions are not implemented.
0b0001 | CFP RCTX, DVP RCTX, and CPP RCTX instructions are implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### SB, bits [39:36]

SB instruction support in AArch64 state. Defined values are:

SB | Meaning
--- | ---
0b0000 | SB instruction is not implemented.
0b0001 | SB instruction is implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### FRINTTS, bits [35:32]

Indicates whether FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions are implemented. Defined values are:

FRINTTS | Meaning
--- | ---
0b0000 | FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions are not implemented.
0b0001 | FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions are implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### GPI, bits [31:28]
From Armv8.3:

Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:

GPI | Meaning
--- | ---
0b0000 | Generic Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented.
0b0001 | Generic Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves the PACGA instruction.

All other values are reserved.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

If the value of ID_AA64ISAR1_EL1.GPA is non-zero, this field must have the value 0b0000.

####
Otherwise:

Reserved, RES0.

#### GPA, bits [27:24]
From Armv8.3:

Indicates whether QARMA or Architected algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:

GPA | Meaning
--- | ---
0b0000 | Generic Authentication using an Architected algorithm is not implemented.
0b0001 | Generic Authentication using the QARMA algorithm is implemented. This involves the PACGA instruction.

All other values are reserved.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

If the value of ID_AA64ISAR1_EL1.GPI is non-zero, this field must have the value 0b0000.

####
Otherwise:

Reserved, RES0.

#### LRCPC, bits [23:20]
From Armv8.4:

Indicates support for weaker release consistency, RCpc based model. Defined values are:

LRCPC | Meaning
--- | ---
0b0000 | The LDAPUR*, STLUR*, and LDAPR* instructions are not implemented.
0b0001 | The LDAPR* instructions are implemented.
0b0010 | The LDAPUR*, STLUR*, and LDAPR* instructions are implemented.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

In Armv8.3, the only permitted value is 0b0001. ARMv8.3-RCPC implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0010. ARMv8.4-RCPC implements the functionality identified by the value 0b0010.

All other values are reserved.

####
From Armv8.3:

Indicates support for weaker release consistency, RCpc based model. Defined values are:

LRCPC | Meaning
--- | ---
0b0000 | The LDAPRB, LDAPRH and LDAPR instructions are not implemented.
0b0001 | The LDAPRB, LDAPRH and LDAPR instructions are implemented.

All other values are reserved.

ARMv8.3-RCPC implements the functionality identified by the value 0b0001.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

In Armv8.3, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### FCMA, bits [19:16]
From Armv8.3:

Indicates support for complex number addition and multiplication, where numbers are stored in vectors. Defined values are:

FCMA | Meaning
--- | ---
0b0000 | The FCMLA and FCADD instructions are not implemented.
0b0001 | The FCMLA and FCADD instructions are implemented.

All other values are reserved.

ARMv8.3-CompNum implements the functionality identified by the value 0b0001.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

From Armv8.3, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### JSCVT, bits [15:12]
From Armv8.3:

Indicates support for javascript conversion from double precision floating point values to integers in AArch64 state. Defined values are:

JSCVT | Meaning
--- | ---
0b0000 | The FJCVTZS instruction is not implemented.
0b0001 | The FJCVTZS instruction is implemented.

All other values are reserved.

ARMv8.3.JSConv implements the functionality identified by 0b0001.

In Armv8.0, Armv8.1, and Armv8.2, the only permitted value is 0b0000.

From Armv8.3, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### API, bits [11:8]
From Armv8.3:

Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:

API | Meaning
--- | ---
0b0000 | Address Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented.
0b0001 | Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves all Pointer Authentication instructions other than the PACGA instruction.
0b0010 | Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented, with the EnhancedPAC() function returning TRUE. This applies to all Pointer Authentication instructions other than the PACGA instruction.

All other values are reserved.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

If the value of ID_AA64ISAR1_EL1.APA is non-zero, this field must have the value 0b0000.

####
Otherwise:

Reserved, RES0.

#### APA, bits [7:4]
From Armv8.3:

Indicates whether QARMA or Architected algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:

APA | Meaning
--- | ---
0b0000 | Address Authentication using an Architected algorithm is not implemented.
0b0001 | Address Authentication using the QARMA algorithm is implemented, with the EnhancedPAC() function returning FALSE. This applies to all Pointer Authentication instructions other than the PACGA instruction.
0b0010 | Address Authentication using the QARMA algorithm is implemented, with the EnhancedPAC() function returning TRUE. This applies to all Pointer Authentication instructions other than the PACGA instruction.

All other values are reserved.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

If the value of the ID_AA64ISAR1_EL1.API is non-zero, this field must have the value 0b0000.

####
Otherwise:

Reserved, RES0.

#### DPB, bits [3:0]
From Armv8.2:

Data Persistence writeback. Indicates support for the DC CVAP and DC CVADP instructions in AArch64 state. Defined values are:

DPB | Meaning
--- | ---
0b0000 | DC CVAP not supported.
0b0001 | DC CVAP supported.
0b0010 | DC CVAP and DC CVADP supported.

All other values are reserved.

ARMv8.2-DCPoP implements the functionality identified by the value 0b0001.

ARMv8.2-DCCVADP implements the functionality identified by the value 0b0010.

From Armv8.2 to Armv8.4, the only permitted value is 0b0001.

From Armv8.5, the only permitted value is 0b0010

####
Otherwise:

Reserved, RES0.

If API == 0000 and APA == 0000, then:

- The TCR_EL1.{TBID,TBID0}, TCR_EL2.{TBID0,TBID1}, TCR_EL2.TBID and TCR_EL3.TBID bits are RES0.
- APIAKeyHi_EL1, APIAKeyLo_EL1, APIBKeyHi_EL1, APIBKeyLo_EL1, APDAKeyHi_EL1, APDAKeyLo_EL1, APDBKeyHi_EL1, APDBKeyLo_EL1 are not allocated.
- SCTLR_ELx.EnIA, SCTLR_ELx.EnIB, SCTLR_ELx.EnDA, SCTLR_ELx.EnDB are all RES0.

If API == 0000 and APA == 0000 and GPI == 0000 and GPA == 0000, then:

- HCR_EL2.APK and HCR_EL2.API are RES0.
- SCR_EL3.APK and SCR_EL3.API are RES0.

## Accessing the ID_AA64ISAR1_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64ISAR1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0110 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64ISAR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64ISAR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64ISAR1_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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