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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRBIDR_EL1, Trace Buffer ID Register

The TRBIDR_EL1 characteristics are:

## Purpose

Provides information to software as to whether the trace buffer can be programmed at the current Exception level.

## Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are UNDEFINED.

## Attributes

TRBIDR_EL1 is a 64-bit register.

## Field descriptions

The TRBIDR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | F | P | Align
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:6]

Reserved, RES0.

#### F, bit [5]

Flag Updates. Defines whether the address translation performed by the Trace Buffer Extension manages the Access Flag and dirty state.

F | Meaning
--- | ---
0b0 | Trace buffer address translation does not manage the Access flag and dirty state in translation tables.
0b1 | Trace buffer address translation manages the Access Flag and dirty state in the same way as the MMU on this PE.

#### P, bit [4]

Programming not allowed. The trace buffer is owned by a higher Exception level or by the other Security state.

P | Meaning
--- | ---
0b0 | The owning Exception level is the current Exception level or a lower Exception level, and the owning Security state is the current Security state.
0b1 | The owning Exception level is a higher Exception level, or the owning Security state is not the current Security state.

The value read from this field depends on the current Exception level and the values of MDCR_EL3.NSTB and MDCR_EL2.E2TB:

- If MDCR_EL3.NSTB == 0b00 or 0b01, this bit reads as one from Non-secure EL2 and EL1.

- If MDCR_EL3.NSTB == 0b10 or 0b11, this bit reads as one from Secure EL2 and EL1.

- If EL2 is implemented and enabled, and MDCR_EL2.E2TB == 0b00, this bit reads as one from EL1.

Otherwise, this bit reads as zero.

#### Align, bits [3:0]

Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.

Align | Meaning
--- | ---
0b0000 | Byte.
0b0001 | Halfword.
0b0010 | Word.
0b0011 | Doubleword.
0b0100 | 16 bytes.
0b0101 | 32 bytes.
0b0110 | 64 bytes.
0b0111 | 128 bytes.
0b1000 | 256 bytes.
0b1001 | 512 bytes.
0b1010 | 1KB.
0b1011 | 2KB.

All other values are reserved.

## Accessing the TRBIDR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, TRBIDR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1001 | 0b1011 | 0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return TRBIDR_EL1; elsif PSTATE.EL == EL2 then return TRBIDR_EL1; elsif PSTATE.EL == EL3 then return TRBIDR_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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