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# MDCCSR_EL0, Monitor DCC Status Register

The MDCCSR_EL0 characteristics are:

## Purpose

Read-only register containing control status flags for the DCC.

## Configuration

AArch64 System register MDCCSR_EL0 bits [30:29] are architecturally mapped to External register EDSCR[30:29] .

AArch64 System register MDCCSR_EL0 bits [30:29] are architecturally mapped to AArch32 System register DBGDSCRint[30:29] .

## Attributes

MDCCSR_EL0 is a 64-bit register.

## Field descriptions

The MDCCSR_EL0 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | RXfull | TXfull | RES0 | RAZ | RES0 | RAZ | RES0 | RAZ | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:31]

Reserved, RES0.

#### RXfull, bit [30]

DTRRX full. Read-only view of the equivalent bit in the EDSCR.

#### TXfull, bit [29]

DTRTX full. Read-only view of the equivalent bit in the EDSCR.

#### Bits [28:19]

Reserved, RES0.

#### Bits [18:15]

Reserved, RAZ.

#### Bits [14:13]

Reserved, RES0.

#### Bit [12]

Reserved, RAZ.

#### Bits [11:6]

Reserved, RES0.

#### Bits [5:2]

Reserved, RAZ.

#### Bits [1:0]

Reserved, RES0.

## Accessing the MDCCSR_EL0

Accesses to this register use the following encodings:

#### MRS <Xt>, MDCCSR_EL0

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b011 | 0b0000 | 0b0001 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCCSR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCCSR_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return MDCCSR_EL0; elsif PSTATE.EL == EL3 then return MDCCSR_EL0;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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