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# DBGOSDLR, Debug OS Double Lock Register

The DBGOSDLR characteristics are:

## Purpose

Locks out the external debug interface.

## Configuration

AArch32 System register DBGOSDLR bits [31:0] are architecturally mapped to AArch64 System register OSDLR_EL1[31:0] .

This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

DBGOSDLR is a 32-bit register.

## Field descriptions

The DBGOSDLR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | DLK

#### Bits [31:1]

Reserved, RES0.

#### DLK, bit [0]
When ARMv8.0-DoubleLock is implemented:

OS Double Lock control bit.

DLK | Meaning
--- | ---
0b0 | OS Double Lock unlocked.
0b1 | OS Double Lock locked, if DBGPRCR.CORENPDRQ (Core no powerdown request) bit is set to 0 and the PE is in Non-debug state.

On a Warm reset, this field resets to 0.

####
Otherwise:

Reserved, RAZ/WI.

## Accessing the DBGOSDLR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1110 | 0b000 | 0b0001 | 0b0011 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDOSA> != '00' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL2.TDOSA") then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDOSA> != '00' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by HDCR.TDOSA") then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL3.TDOSA") then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGOSDLR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL3.TDOSA") then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGOSDLR; elsif PSTATE.EL == EL3 then return DBGOSDLR;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1110 | 0b000 | 0b0001 | 0b0011 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDOSA> != '00' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL2.TDOSA") then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDOSA> != '00' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by HDCR.TDOSA") then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL3.TDOSA") then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGOSDLR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDOSA == '1' && (IsFeatureImplemented(ARMv8.0-DoubleLock) || boolean IMPLEMENTATION_DEFINED "Trapped by MDCR_EL3.TDOSA") then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGOSDLR = R[t]; elsif PSTATE.EL == EL3 then DBGOSDLR = R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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