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# ID_ISAR6, Instruction Set Attribute Register 6

The ID_ISAR6 characteristics are:

## Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4 and ID_ISAR5.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register ID_ISAR6 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR6_EL1[31:0] .

## Attributes

ID_ISAR6 is a 32-bit register.

## Field descriptions

The ID_ISAR6 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SPECRES | SB | FHM | DP | JSCVT

#### Bits [31:20]

Reserved, RES0.

#### SPECRES, bits [19:16]

Speculation invalidation instruction support in AArch32 state. Defined values are:

SPECRES | Meaning
--- | ---
0b0000 | CFPRCTX, DVPRCTX, and CPPRCTX instructions are not implemented.
0b0001 | CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### SB, bits [15:12]

SB instruction support in AArch32 state. Defined values are:

SB | Meaning
--- | ---
0b0000 | SB instruction is not implemented.
0b0001 | SB instruction is implemented.

All other values are reserved.

From Armv8.5, the only permitted value is 0b0001.

#### FHM, bits [11:8]
From Armv8.2:

Indicates whether VFMAL and VFMSL instructions are implemented.

FHM | Meaning
--- | ---
0b0000 | VFMAL and VMFSL instructions not implemented.
0b0001 | VFMAL and VMFSL instructions implemented.

ARMv8.2-FHM implements the functionality identified by the value 0b0001.

####
Otherwise:

Reserved, RES0.

#### DP, bits [7:4]
From Armv8.2:

Indicates the support for dot product instructions in AArch32 state.

DP | Meaning
--- | ---
0b0000 | No dot product instructions implemented.
0b0001 | VUDOT and VSDOT instructions implemented.

All other values are reserved.

ARMv8.2-DotProd implements the functionality identified by the value 0b0001.

####
Otherwise:

Reserved, RES0.

#### JSCVT, bits [3:0]
From Armv8.3:

Indicates whether the Javascript conversion instruction is implemented in AArch32 state. Defined values are:

JSCVT | Meaning
--- | ---
0b0000 | The VJCVT instruction is not implemented.
0b0001 | The VJCVT instruction is implemented.

All other values are reserved.

In Armv8.0, Armv8.1 and Armv8.2 the only permitted value is 0b0000.

From Armv8.3 the only permitted value is 0b0001. This feature is identified as ARMv8.3.JSConv.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_ISAR6

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR6; elsif PSTATE.EL == EL2 then return ID_ISAR6; elsif PSTATE.EL == EL3 then return ID_ISAR6;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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