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# CTIDEVCTL, CTI Device Control register

The CTIDEVCTL characteristics are:

## Purpose

Provides target-specific device controls

## Configuration

CTIDEVCTL is in the Debug power domain. Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.

This register is present only when ARMv8.3-DoPD is implemented. Otherwise, direct accesses to CTIDEVCTL are RES0.

## Attributes

CTIDEVCTL is a 32-bit register.

## Field descriptions

The CTIDEVCTL bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | RCE | OSUCE

#### Bits [31:2]

Reserved, RES0.

#### RCE, bit [1]

Reset Catch Enable.

RCE | Meaning
--- | ---
0b0 | Reset Catch debug event disabled.
0b1 | Reset Catch debug event enabled.

On a External debug reset, this field resets to 0.

#### OSUCE, bit [0]

OS Unlock Catch Enable

OSUCE | Meaning
--- | ---
0b0 | OS Unlock Catch debug event disabled.
0b1 | OS Unlock Catch debug event enabled.

On a External debug reset, this field resets to 0.

## Accessing the CTIDEVCTL

#### CTIDEVCTL can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0x150 | CTIDEVCTL

This interface is accessible as follows:

- When SoftwareLockStatus() access to this register is RO.
- When !SoftwareLockStatus() access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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