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# VMPIDR, Virtualization Multiprocessor ID Register

The VMPIDR characteristics are:

## Purpose

Holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR.

## Configuration

AArch32 System register VMPIDR bits [31:0] are architecturally mapped to AArch64 System register VMPIDR_EL2[31:0] .

If EL2 is not implemented but EL3 is implemented, this register takes the value of the MPIDR.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 with EL2 using AArch32, or into EL3 with EL3 using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

VMPIDR is a 32-bit register.

## Field descriptions

The VMPIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
M | U | RES0 | MT | Aff2 | Aff1 | Aff0

#### M, bit [31]

Indicates whether this implementation includes the functionality introduced by the ARMv7 Multiprocessing Extensions. The possible values of this bit are:

M | Meaning
--- | ---
0b0 | This implementation does not include the ARMv7 Multiprocessing Extensions functionality.
0b1 | This implementation includes the ARMv7 Multiprocessing Extensions functionality.

In Armv8 this bit is RES1.

#### U, bit [30]

Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:

U | Meaning
--- | ---
0b0 | Processor is part of a multiprocessor system.
0b1 | Processor is part of a uniprocessor system.

In a system where the PE resets into EL2 or EL3, this field resets to the value in MPIDR.U.

#### Bits [29:25]

Reserved, RES0.

#### MT, bit [24]

Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels. The possible values of this bit are:

MT | Meaning
--- | ---
0b0 | Performance of PEs at the lowest affinity level is largely independent.
0b1 | Performance of PEs at the lowest affinity level is very interdependent.

In a system where the PE resets into EL2 or EL3, this field resets to the value in MPIDR.MT.

#### Aff2, bits [23:16]

Affinity level 2. See the description of Aff0 for more information.

In a system where the PE resets into EL2 or EL3, this field resets to the value in MPIDR.Aff2.

#### Aff1, bits [15:8]

Affinity level 1. See the description of Aff0 for more information.

In a system where the PE resets into EL2 or EL3, this field resets to the value in MPIDR.Aff1.

#### Aff0, bits [7:0]

Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.

In a system where the PE resets into EL2 or EL3, this field resets to the value in MPIDR.Aff0.

## Accessing the VMPIDR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then return VMPIDR; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return MPIDR; elsif SCR.NS == '0' then UNDEFINED; else return VMPIDR;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then VMPIDR = R[t]; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then //no operation elsif SCR.NS == '0' then UNDEFINED; else VMPIDR = R[t];

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) then return VMPIDR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) then return VMPIDR; else return MPIDR; elsif PSTATE.EL == EL2 then return MPIDR; elsif PSTATE.EL == EL3 then return MPIDR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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