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# ID_ISAR2, Instruction Set Attribute Register 2

The ID_ISAR2 characteristics are:

## Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4, and ID_ISAR5.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register ID_ISAR2 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR2_EL1[31:0] .

## Attributes

ID_ISAR2 is a 32-bit register.

## Field descriptions

The ID_ISAR2 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Reversal | PSR_AR | MultU | MultS | Mult | MultiAccessInt | MemHint | LoadStore

#### Reversal, bits [31:28]

Indicates the implemented Reversal instructions. Defined values are:

Reversal | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds the REV, REV16, and REVSH instructions.
0b0010 | As for 0b0001, and adds the RBIT instruction.

All other values are reserved.

In Armv8-A the only permitted value is 0b0010.

#### PSR_AR, bits [27:24]

Indicates the implemented A and R profile instructions to manipulate the PSR. Defined values are:

PSR_AR | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds the MRS and MSR instructions, and the exception return forms of data-processing instructions.

All other values are reserved.

In Armv8-A the only permitted value is 0b0001.

The exception return forms of the data-processing instructions are:

- In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set. These instructions might be affected by the WithShifts attribute.
- In the T32 instruction set, the SUBS PC,LR,#N instruction.

#### MultU, bits [23:20]

Indicates the implemented advanced unsigned Multiply instructions. Defined values are:

MultU | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds the UMULL and UMLAL instructions.
0b0010 | As for 0b0001, and adds the UMAAL instruction.

All other values are reserved.

In Armv8-A the only permitted value is 0b0010.

#### MultS, bits [19:16]

Indicates the implemented advanced signed Multiply instructions. Defined values are:

MultS | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds the SMULL and SMLAL instructions.
0b0010 | As for 0b0001, and adds the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. Also adds the Q bit in the PSRs.
0b0011 | As for 0b0010, and adds the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.

All other values are reserved.

In Armv8-A the only permitted value is 0b0011.

#### Mult, bits [15:12]

Indicates the implemented additional Multiply instructions. Defined values are:

Mult | Meaning
--- | ---
0b0000 | No additional instructions implemented. This means only MUL is implemented.
0b0001 | Adds the MLA instruction.
0b0010 | As for 0b0001, and adds the MLS instruction.

All other values are reserved.

In Armv8-A the only permitted value is 0b0010.

#### MultiAccessInt, bits [11:8]

Indicates the support for interruptible multi-access instructions. Defined values are:

MultiAccessInt | Meaning
--- | ---
0b0000 | No support. This means the LDM and STM instructions are not interruptible.
0b0001 | LDM and STM instructions are restartable.
0b0010 | LDM and STM instructions are continuable.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

#### MemHint, bits [7:4]

Indicates the implemented Memory Hint instructions. Defined values are:

MemHint | Meaning
--- | ---
0b0000 | None implemented.
0b0001 | Adds the PLD instruction.
0b0010 | Adds the PLD instruction. (0b0001 and 0b0010 have identical effects.)
0b0011 | As for 0b0001 (or 0b0010), and adds the PLI instruction.
0b0100 | As for 0b0011, and adds the PLDW instruction.

All other values are reserved.

In Armv8-A the only permitted value is 0b0100.

#### LoadStore, bits [3:0]

Indicates the implemented additional load/store instructions. Defined values are:

LoadStore | Meaning
--- | ---
0b0000 | No additional load/store instructions implemented.
0b0001 | Adds the LDRD and STRD instructions.
0b0010 | As for 0b0001, and adds the Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD) and Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD) instructions.

All other values are reserved.

In Armv8-A the only permitted value is 0b0010.

## Accessing the ID_ISAR2

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR2; elsif PSTATE.EL == EL2 then return ID_ISAR2; elsif PSTATE.EL == EL3 then return ID_ISAR2;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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