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# CTIPIDR3, CTI Peripheral Identification Register 3

The CTIPIDR3 characteristics are:

## Purpose

Provides information to identify a CTI component.

For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).

## Configuration

CTIPIDR3 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

## Attributes

CTIPIDR3 is a 32-bit register.

## Field descriptions

The CTIPIDR3 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | REVAND | CMOD

#### Bits [31:8]

Reserved, RES0.

#### REVAND, bits [7:4]

Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.

#### CMOD, bits [3:0]

Customer modified. Indicates someone other than the Designer has modified the component.

## Accessing the CTIPIDR3

#### CTIPIDR3 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0xFEC | CTIPIDR3

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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