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# ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1

The ID_AA64PFR1_EL1 characteristics are:

## Purpose

Reserved for future expansion of information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

## Attributes

ID_AA64PFR1_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64PFR1_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | RAS_frac | MTE | SSBS | BT
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:16]

Reserved, RES0.

#### RAS_frac, bits [15:12]
When ARMv8.4-RAS is implemented:

RAS Extension fractional field.

RAS_frac | Meaning
--- | ---
0b0000 | If ID_AA64PFR0_EL1.RAS == 0b0001, RAS Extension implemented.
0b0001 | If ID_AA64PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for: Additional ERXMISC<m>_EL1 System registers. Additional System registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1, and the SCR_EL3.FIEN and HCR_EL2.FIEN trap controls, to support the optional RAS Common Fault Injection Model Extension. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.

All other values are reserved.

This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.

####
Otherwise:

Reserved, RES0.

#### MTE, bits [11:8]
When ARMv8.5-MemTag is implemented:

Support for the Tagged Memory Extension.

MTE | Meaning
--- | ---
0b0000 | Tagged Memory Extension is not implemented.
0b0001 | Tagged Memory Extension Instructions and Registers only are implemented. All other Tagged Memory Extension state added as part of the implementation is RES0.
0b0010 | Tagged Memory Extension is implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### SSBS, bits [7:4]
From Armv8.5:

Speculative Store Bypassing controls in AArch64 state. Defined values are:

SSBS | Meaning
--- | ---
0b0000 | AArch64 provides no mechanism to control the use of Speculative Store Bypassing.
0b0001 | AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe.
0b0010 | AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe, and the MSR and MRS instructions to directly read and write the PSTATE.SSBS field

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### BT, bits [3:0]
From Armv8.5:

Branch Target Identification mechanism support in AArch64 state. Defined values are:

BT | Meaning
--- | ---
0b0000 | The Branch Target Identification mechanism is not implemented.
0b0001 | The Branch Target Identification mechanism is implemented.

All other values are reserved.

ARMv8.5-BTI implements the functionality identified by the value 0b0001.

From Armv8.5, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

## Accessing the ID_AA64PFR1_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64PFR1_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0100 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64PFR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64PFR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64PFR1_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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