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# ERRPIDR2, Peripheral Identification Register 2

The ERRPIDR2 characteristics are:

## Purpose

Provides discovery information about the component.

For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

## Configuration

Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR2 are RES0.

## Attributes

ERRPIDR2 is a 32-bit register.

## Field descriptions

The ERRPIDR2 bit assignments are:

### When the component uses a 12-bit part number:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | REVISION | JEDEC | DES_1

#### Bits [31:8]

Reserved, RES0.

#### REVISION, bits [7:4]

Component major revision. This field and ERRPIDR3.REVAND together form the revision number of the component, with REVISION being the most significant part and REVAND the least significant part.

This field reads as an IMPLEMENTATION DEFINED value.

#### JEDEC, bit [3]

JEDEC-assigned JEP106 implementer code is used. This bit is RAO.

#### DES_1, bits [2:0]

Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and this field together form the JEDEC-assigned JEP106 identification code for the designer of the component.

This field reads as an IMPLEMENTATION DEFINED value.

Note

For a component designed by Arm Limited, the JEP106 identification code is 0x3B.

### When the component uses a 16-bit part number:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PART_2 | JEDEC | DES_1

#### Bits [31:8]

Reserved, RES0.

#### PART_2, bits [7:4]

Part number, bits [15:12]

The part number is selected by the designer of the component. It is stored in this field, ERRPIDR1.PART_1 and ERRPIDR0.PART_0.

This field reads as an IMPLEMENTATION DEFINED value.

#### JEDEC, bit [3]

JEDEC-assigned JEP106 implementer code is used. This bit is RAO.

#### DES_1, bits [2:0]

Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and this field together form the JEDEC-assigned JEP106 identification code for the designer of the component.

This field reads as an IMPLEMENTATION DEFINED value.

Note

For a component designed by Arm Limited, the JEP106 identification code is 0x3B.

## Accessing the ERRPIDR2

#### ERRPIDR2 can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
RAS | 0xFE8 | ERRPIDR2

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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