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# ICV_CTLR, Interrupt Controller Virtual Control Register

The ICV_CTLR characteristics are:

## Purpose

Controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.

## Configuration

AArch32 System register ICV_CTLR bits [31:0] are architecturally mapped to AArch64 System register ICV_CTLR_EL1[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

ICV_CTLR is a 32-bit register.

## Field descriptions

The ICV_CTLR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | ExtRange | RSS | RES0 | A3V | SEIS | IDbits | PRIbits | RES0 | EOImode | CBPR

#### Bits [31:20]

Reserved, RES0.

#### ExtRange, bit [19]

Extended INTID range (read-only).

ExtRange | Meaning
--- | ---
0b0 | CPU interface does not support INTIDs in the range 1024..8191. Behaviour is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Note Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them.
0b1 | CPU interface supports INTIDs in the range 1024..8191. All INTIDs in the range 1024..8191 are treated as requiring deactivation.

ICV_CTLR.ExtRange is an alias of ICC_CTLR.ExtRange.

#### RSS, bit [18]

Range Selector Support. Possible values are:

RSS | Meaning
--- | ---
0b0 | Targeted SGIs with affinity level 0 values of 0 - 15 are supported.
0b1 | Targeted SGIs with affinity level 0 values of 0 - 255 are supported.

This bit is read-only.

#### Bits [17:16]

Reserved, RES0.

#### A3V, bit [15]

Affinity 3 Valid. Read-only and writes are ignored. Possible values are:

A3V | Meaning
--- | ---
0b0 | The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.
0b1 | The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

#### SEIS, bit [14]

SEI Support. Read-only and writes are ignored. Indicates whether the virtual CPU interface supports local generation of SEIs:

SEIS | Meaning
--- | ---
0b0 | The virtual CPU interface logic does not support local generation of SEIs.
0b1 | The virtual CPU interface logic supports local generation of SEIs.

#### IDbits, bits [13:11]

Identifier bits. Read-only and writes are ignored. The number of virtual interrupt identifier bits supported:

IDbits | Meaning
--- | ---
0b000 | 16 bits.
0b001 | 24 bits.

All other values are reserved.

#### PRIbits, bits [10:8]

Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.

An implementation must implement at least 32 levels of physical priority (5 priority bits).

Note

This field always returns the number of priority bits implemented.

The division between group priority and subpriority is defined in the binary point registers ICV_BPR0 and ICV_BPR1.

#### Bits [7:2]

Reserved, RES0.

#### EOImode, bit [1]

Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:

EOImode | Meaning
--- | ---
0b0 | ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR are UNPREDICTABLE.
0b1 | ICV_EOIR0 and ICV_EOIR1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality.

This field resets to an architecturally UNKNOWN value.

#### CBPR, bit [0]

Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts:

CBPR | Meaning
--- | ---
0b0 | ICV_BPR0 determines the preemption group for virtual Group 0 interrupts only. ICV_BPR1 determines the preemption group for virtual Group 1 interrupts.
0b1 | ICV_BPR0 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts. Reads of ICV_BPR1 return ICV_BPR0 plus one, saturated to 0b111. Writes to ICV_BPR1 are ignored.

This field resets to an architecturally UNKNOWN value.

## Accessing the ICV_CTLR

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TC == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then return ICV_CTLR; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then return ICV_CTLR; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.FMO == '1' then return ICV_CTLR; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then return ICV_CTLR; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then if SCR.NS == '0' then return ICC_CTLR_S; else return ICC_CTLR_NS; else return ICC_CTLR; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then return ICC_CTLR_NS; else return ICC_CTLR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else if SCR.NS == '0' then return ICC_CTLR_S; else return ICC_CTLR_NS;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TC == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then ICV_CTLR = R[t]; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_CTLR = R[t]; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.FMO == '1' then ICV_CTLR = R[t]; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then ICV_CTLR = R[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then if SCR.NS == '0' then ICC_CTLR_S = R[t]; else ICC_CTLR_NS = R[t]; else ICC_CTLR = R[t]; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then ICC_CTLR_NS = R[t]; else ICC_CTLR = R[t]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else if SCR.NS == '0' then ICC_CTLR_S = R[t]; else ICC_CTLR_NS = R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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