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# TRCSSCCR<n>, Single-shot Comparator Control Register <n>, n = 0 - 7

The TRCSSCCR<n> characteristics are:

## Purpose

Controls the corresponding Single-shot Comparator Control resource.

## Configuration

External register TRCSSCCR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSCCR<n>[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR4.NUMSSCC > n and ETE is implemented. Otherwise, direct accesses to TRCSSCCR<n> are RES0.

## Attributes

TRCSSCCR<n> is a 32-bit register.

## Field descriptions

The TRCSSCCR<n> bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | RST | ARC<m>, bit [m+16] | SAC<m>, bit [m]

#### Bits [31:25]

Reserved, RES0.

#### RST, bit [24]

Selects the Single-shot Comparator Control mode.

RST | Meaning
--- | ---
0b0 | The Single-shot Comparator Control is in single-shot mode.
0b1 | The Single-shot Comparator Control is in multi-shot mode.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### ARC<m>, bit [m+16], for m = 0 to 7

Selects one or more Address Range Comparators for Single-shot control.

ARC<m> | Meaning
--- | ---
0b0 | The Address Range Comparator m, is not selected for Single-shot control.
0b1 | The Address Range Comparator m, is selected for Single-shot control.

This bit is RES0 if m >= TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### SAC<m>, bit [m], for m = 0 to 15

Selects one or more Single Address Comparators for Single-shot control.

SAC<m> | Meaning
--- | ---
0b0 | The Single Address Comparator m, is not selected for Single-shot control.
0b1 | The Single Address Comparator m, is selected for Single-shot control.

This bit is RES0 if m >= 2 × TRCIDR4.NUMACPAIRS.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCSSCCR<n>

Must be programmed if any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 0b1.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCSSCCR<n> can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x280 + 4n

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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