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# TRCOSLSR, Trace OS Lock Status Register

The TRCOSLSR characteristics are:

## Purpose

Returns the status of the Trace OS Lock.

## Configuration

AArch64 System register TRCOSLSR bits [31:0] are architecturally mapped to External register TRCOSLSR[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCOSLSR are UNDEFINED.

## Attributes

TRCOSLSR is a 64-bit register.

## Field descriptions

The TRCOSLSR bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | OSLM[2:1] | RES0 | OSLK | OSLM[0]
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:5]

Reserved, RES0.

#### OSLM[2:1], bits [4:3]

This field is bits[2:1] of OSLM[2:0].

OS Lock model.

OSLM | Meaning
--- | ---
0b000 | Trace OS Lock is not implemented.
0b010 | Trace OS Lock is implemented.
0b100 | Trace OS Lock is not implemented, and the trace unit is controlled by the PE OS Lock.

All other values are reserved.

This field reads as 0b100.

The OSLM field is split as follows:

- OSLM[2:1] is TRCOSLSR[4:3].
- OSLM[0] is TRCOSLSR[0].

#### Bit [2]

Reserved, RES0.

#### OSLK, bit [1]

OS Lock status.

OSLK | Meaning
--- | ---
0b0 | The OS Lock is unlocked.
0b1 | The OS Lock is locked.

Note that this field indicates the state of the PE OS Lock.

#### OSLM[0], bit [0]

This field is bit[0] of OSLM[2:0].

See OSLM[2:1] for the field description.

## Accessing the TRCOSLSR

External debugger accesses to this register are unaffected by the OS Lock.

Accesses to this register use the following encodings:

#### MRS <Xt>, TRCOSLSR

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b10 | 0b001 | 0b0001 | 0b0001 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCOSLSR; elsif PSTATE.EL == EL2 then if CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCOSLSR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCOSLSR;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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