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# SSBS, Speculative Store Bypass Safe

The SSBS characteristics are:

## Purpose

Allows access to the Speculative Store Bypass Safe bit.

## Configuration

This register is present only when ARMv8.0-SSBS is implemented. Otherwise, direct accesses to SSBS are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

SSBS is a 64-bit register.

## Field descriptions

The SSBS bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | SSBS | RES0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:13]

Reserved, RES0.

#### SSBS, bit [12]

Speculative Store Bypass Safe.

Prohibits speculative loads or stores which might practically allow a cache timing side channel.

A cache timing side channel might be exploited where a load or store uses an address that is derived from a register that is being loaded from memory using a load instruction speculatively read from a memory location. If PSTATE.SSBS is enabled, the address derived from the load instruction might be from earlier in the coherence order than the lastest store to that memory location with the same virtual address.

SSBS | Meaning
--- | ---
0b0 | Hardware is not permitted to load or store speculatively, in a manner that could practically give rise to a cache timing side channel, using an address derived from a register value that has been loaded from memory using a load instruction (L) that speculatively reads an entry from earlier in the coherence order from that location being loaded from than the entry generated by the latest store (S) to that location using the same virtual address as L.
0b1 | Hardware is permitted to load or store speculatively, in a manner that could practically give rise to a cache timing side channel, using an address derived from a register value that has been loaded from memory using a load instruction (L) that speculatively reads an entry from earlier in the coherence order fro that location being loaded from than the entry generated by the latest store (S) to that location using the same virtual address as L.

The value of this bit is set to the value in the SCTLR_ELx.DSSBS field on taking an exception to ELx.

This field resets to an IMPLEMENTATION DEFINED value.

#### Bits [11:0]

Reserved, RES0.

## Accessing the SSBS

For details on the operation of the MSR (immediate) accessor, see MSR (immediate) in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Accesses to this register use the following encodings:

#### MRS <Xt>, SSBS

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0010 | 0b110

if PSTATE.EL == EL0 then return Zeros(51):PSTATE.SSBS:Zeros(12); elsif PSTATE.EL == EL1 then return Zeros(51):PSTATE.SSBS:Zeros(12); elsif PSTATE.EL == EL2 then return Zeros(51):PSTATE.SSBS:Zeros(12); elsif PSTATE.EL == EL3 then return Zeros(51):PSTATE.SSBS:Zeros(12);

#### MSR SSBS, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0100 | 0b0010 | 0b110

if PSTATE.EL == EL0 then PSTATE.SSBS = X[t]<12>; elsif PSTATE.EL == EL1 then PSTATE.SSBS = X[t]<12>; elsif PSTATE.EL == EL2 then PSTATE.SSBS = X[t]<12>; elsif PSTATE.EL == EL3 then PSTATE.SSBS = X[t]<12>;

#### MSR SSBS, #<imm>

op0 | op1 | CRn | op2
--- | --- | --- | ---
0b00 | 0b011 | 0b0100 | 0b001

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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