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# ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

The ID_AA64PFR0_EL1 characteristics are:

## Purpose

Provides additional information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D10.4.1.

## Configuration

The external register EDPFR gives information from this register.

## Attributes

ID_AA64PFR0_EL1 is a 64-bit register.

## Field descriptions

The ID_AA64PFR0_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
CSV3 | CSV2 | RES0 | DIT | AMU | MPAM | SEL2 | SVE
RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### CSV3, bits [63:60]
From Armv8.5:

Speculative use of faulting data. Defined values are:

CSV3 | Meaning
--- | ---
0b0000 | This Device does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the load in the speculative sequence
0b0001 | Data loaded under speculation with a permission or domain fault cannot be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the laod in the speculative sequence

From Armv8.5, the only permitted value is 0b0001.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### CSV2, bits [59:56]
From Armv8.5:

Speculative use of out of context branch targets. Defined values are:

CSV2 | Meaning
--- | ---
0b0000 | This Device does not disclose whether branch targets trained in one hardware described context can affect speculative execution in a different hardware described context.
0b0001 | Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. Contexts do not include the SCXTNUM_ELx register contexts, and these registers are not supported.
0b0010 | Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. Contexts include the SCXTNUM_ELx register contexts, and these registers are supported.

From Armv8.5 the only permitted values are 0b0001 or 0b0010.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### Bits [55:52]

Reserved, RES0.

#### DIT, bits [51:48]
From Armv8.4:

Data Independent Timing. Defined values are:

DIT | Meaning
--- | ---
0b0000 | AArch64 does not guarantee constant execution time of any instructions.
0b0001 | AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions.

All other values are reserved.

ARMv8.4-DIT implements the functionality identified by the value 0b0001.

From Armv8.4, the only permitted value is 0b0001.

####
Otherwise:

Reserved, RES0.

#### AMU, bits [47:44]
From Armv8.4:

Activity Monitors Extension. Defined values are:

AMU | Meaning
--- | ---
0b0000 | Activity Monitors Extension is not implemented.
0b0001 | Activity Monitors Extension Version 1 is implemented.

All other values are reserved.

AMUv1 implements the functionality identified by the value 0b0001.

In Armv8.0, Armv8.1, Armv8.2, and Armv8.3, the only permitted value is 0b0000.

From Armv8.4, the permitted values are 0b0000 and 0b0001.

####
Otherwise:

Reserved, RES0.

#### MPAM, bits [43:40]
From Armv8.2:

MPAM Extension. Defined values are:

MPAM | Meaning
--- | ---
0b0000 | MPAM is not implemented.
0b0001 | MPAM is implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### SEL2, bits [39:36]
From Armv8.4:

Secure EL2. Defined values are:

SEL2 | Meaning
--- | ---
0b0000 | Secure EL2 is not implemented.
0b0001 | Secure EL2 is implemented.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### SVE, bits [35:32]
From Armv8.2:

Scalable Vector Extension. Defined values are:

SVE | Meaning
--- | ---
0b0000 | SVE architectural state and programmers' model are not implemented.
0b0001 | SVE architectural state and programmers' model are implemented.

All other values are reserved.

If implemented, refer to ID_AA64ZFR0_EL1 for information about which SVE instructions are available.

####
Otherwise:

Reserved, RES0.

#### RAS, bits [31:28]

RAS Extension version. The defined values of this field are:

RAS | Meaning
--- | ---
0b0000 | No RAS Extension.
0b0001 | RAS Extension present.
0b0010 | ARMv8.4-RAS present. As 0b0001, and adds support for: If EL3 is implemented, ARMv8.4-DFE. Additional ERXMISC<m>_EL1 System registers. Additional System registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1, and the SCR_EL3.FIEN and HCR_EL2.FIEN trap controls, to support the optional RAS Common Fault Injection Model Extension. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.

All other values are reserved.

From Armv8.4, when ARMv8.4-DFE is not implemented, and ERRIDR_EL1.NUM is zero, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010. Otherwise from Armv8.4 the only permitted value is 0b0010.

ARMv8.4-RAS implements the functionality identified by the value 0b0010.

In Armv8.2, the only permitted value is 0b0001.

In Armv8.1 and Armv8.0, the permitted values are 0b0000 and 0b0001.

#### GIC, bits [27:24]

System register GIC interface support. Defined values are:

GIC | Meaning
--- | ---
0b0000 | No System register interface to the GIC is supported.
0b0001 | System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.

All other values are reserved.

#### AdvSIMD, bits [23:20]

Advanced SIMD. Defined values are:

AdvSIMD | Meaning
--- | ---
0b0000 | Advanced SIMD is implemented, including support for the following SISD and SIMD operations: Integer byte, halfword, word and doubleword element operations. Single-precision and double-precision floating-point arithmetic. Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0b0001 | As for 0b0000, and also includes support for half-precision floating-point arithmetic.
0b1111 | Advanced SIMD is not implemented.

All other values are reserved.

This field must have the same value as the FP field.

The permitted values are:

- 0b0000 in an implementation with Advanced SIMD support that does not include the ARMv8.2-FP16 extension.
- 0b0001 in an implementation with Advanced SIMD support that includes the ARMv8.2-FP16 extension.
- 0b1111 in an implementation without Advanced SIMD support.

#### FP, bits [19:16]

Floating-point. Defined values are:

FP | Meaning
--- | ---
0b0000 | Floating-point is implemented, and includes support for: Single-precision and double-precision floating-point types. Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0b0001 | As for 0b0000, and also includes support for half-precision floating-point arithmetic.
0b1111 | Floating-point is not implemented.

All other values are reserved.

This field must have the same value as the AdvSIMD field.

The permitted values are:

- 0b0000 in an implementation with floating-point support that does not include the ARMv8.2-FP16 extension.
- 0b0001 in an implementation with floating-point support that includes the ARMv8.2-FP16 extension.
- 0b1111 in an implementation without floating-point support.

#### EL3, bits [15:12]

EL3 Exception level handling. Defined values are:

EL3 | Meaning
--- | ---
0b0000 | EL3 is not implemented.
0b0001 | EL3 can be executed in AArch64 state only.
0b0010 | EL3 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

#### EL2, bits [11:8]

EL2 Exception level handling. Defined values are:

EL2 | Meaning
--- | ---
0b0000 | EL2 is not implemented.
0b0001 | EL2 can be executed in AArch64 state only.
0b0010 | EL2 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

#### EL1, bits [7:4]

EL1 Exception level handling. Defined values are:

EL1 | Meaning
--- | ---
0b0001 | EL1 can be executed in AArch64 state only.
0b0010 | EL1 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

#### EL0, bits [3:0]

EL0 Exception level handling. Defined values are:

EL0 | Meaning
--- | ---
0b0001 | EL0 can be executed in AArch64 state only.
0b0010 | EL0 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

## Accessing the ID_AA64PFR0_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, ID_AA64PFR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0100 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64PFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64PFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64PFR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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