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# CTIDEVAFF0, CTI Device Affinity register 0

The CTIDEVAFF0 characteristics are:

## Purpose

Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the CTI component relates to.

If the CTI is CTIv1, this register is OPTIONAL. If the CTI is CTIv2, this register is mandatory.

Arm recommends that the CTI is CTIv2.

In an Armv8.5 compliant implementation the CTI must be CTIv2.

If this register is implemented, then CTIDEVAFF1 must also be implemented. If the CTI of a PE does not implement the CTI Device Affinity registers, the CTI block of the external debug memory map must be located 64KB above the debug registers in the external debug interface.

## Configuration

CTIDEVAFF0 is in the Debug power domain.

Implementation of this register is OPTIONAL.

## Attributes

CTIDEVAFF0 is a 32-bit register.

## Field descriptions

The CTIDEVAFF0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MPIDR_EL1 low half

#### MPIDR_EL1 low half, bits [31:0]

MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented Exception level.

## Accessing the CTIDEVAFF0

#### CTIDEVAFF0 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0xFA8 | CTIDEVAFF0

Access on this interface is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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