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# CNTFRQ_EL0, Counter-timer Frequency register

The CNTFRQ_EL0 characteristics are:

## Purpose

This register is provided so that software can discover the frequency of the system counter. It must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.

## Configuration

AArch64 System register CNTFRQ_EL0 bits [31:0] are architecturally mapped to AArch32 System register CNTFRQ[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

CNTFRQ_EL0 is a 64-bit register.

## Field descriptions

The CNTFRQ_EL0 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
Clock frequency
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:32]

Reserved, RES0.

#### Bits [31:0]

Clock frequency. Indicates the system counter clock frequency, in Hz.

This field resets to an architecturally UNKNOWN value.

## Accessing the CNTFRQ_EL0

Accesses to this register use the following encodings:

#### MRS <Xt>, CNTFRQ_EL0

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1110 | 0b0000 | 0b000

if PSTATE.EL == EL0 then return CNTFRQ_EL0; elsif PSTATE.EL == EL1 then return CNTFRQ_EL0; elsif PSTATE.EL == EL2 then return CNTFRQ_EL0; elsif PSTATE.EL == EL3 then return CNTFRQ_EL0;

#### MSR CNTFRQ_EL0, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1110 | 0b0000 | 0b000

if IsHighestEL(PSTATE.EL) then CNTFRQ_EL0 = X[t]; else UNDEFINED;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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