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# TRCSEQSTR, Sequencer State Register

The TRCSEQSTR characteristics are:

## Purpose

Use this to set, or read, the sequencer state.

## Configuration

External register TRCSEQSTR bits [31:0] are architecturally mapped to AArch64 System register TRCSEQSTR[31:0] .

RW fields in this register reset to architecturally UNKNOWN values.

This register is present only when TRCIDR5.NUMSEQSTATE != 0b000 and ETE is implemented. Otherwise, direct accesses to TRCSEQSTR are RES0.

## Attributes

TRCSEQSTR is a 32-bit register.

## Field descriptions

The TRCSEQSTR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | STATE

#### Bits [31:2]

Reserved, RES0.

#### STATE, bits [1:0]

Set or returns the state of the sequencer.

STATE | Meaning
--- | ---
0b00 | State 0.
0b01 | State 1.
0b10 | State 2.
0b11 | State 3.

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing the TRCSEQSTR

Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.SEQUENCER != 0b0000.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

#### TRCSEQSTR can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0x11C

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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