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# EDITR, External Debug Instruction Transfer Register

The EDITR characteristics are:

## Purpose

Used in Debug state for passing instructions to the PE for execution.

## Configuration

EDITR is in the Core power domain.

## Attributes

EDITR is a 32-bit register.

## Field descriptions

The EDITR bit assignments are:

### When in AArch32 state:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
T32Second | T32First

#### T32Second, bits [31:16]

Second halfword of the T32 instruction to be executed on the PE. When EDITR contains a 16-bit T32 instruction, this field is ignored. For more information see 'Behavior in Debug state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H2, Debug State.

#### T32First, bits [15:0]

First halfword of the T32 instruction to be executed on the PE.

### When in AArch64 state:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
A64 instruction to be executed on the PE

#### Bits [31:0]

A64 instruction to be executed on the PE.

## Accessing the EDITR

If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any instruction issued through the ITR in Normal access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:

- It must complete execution in Debug state before the PE executes the restart sequence.
- It must complete execution in Non-debug state before the PE executes the restart sequence.
- It must be abandoned. This means that the instruction does not execute. Any registers or memory accessed by the instruction are left in an UNKNOWN state.

EDITR ignores writes if the PE is in Non-debug state.

#### EDITR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
Debug | 0x084 | EDITR

This interface is accessible as follows:

- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus() access to this register is WI.
- When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus() access to this register is WO.
- Otherwise access to this register returns an Error.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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