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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCAUTHSTATUS, Authentication Status Register

The TRCAUTHSTATUS characteristics are:

## Purpose

Provides information about the state of the IMPLEMENTATION DEFINED authentication interface for debug.

For additional information see the CoreSight Architecture Specification.

## Configuration

External register TRCAUTHSTATUS bits [31:0] are architecturally mapped to AArch64 System register TRCAUTHSTATUS[31:0] .

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCAUTHSTATUS are RES0.

## Attributes

TRCAUTHSTATUS is a 32-bit register.

## Field descriptions

The TRCAUTHSTATUS bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SNID | SID | NSNID | NSID

#### Bits [31:8]

Reserved, RES0.

#### SNID, bits [7:6]

Secure Non-invasive Debug. Indicates whether Secure non-invasive debug features are implemented and enabled.

SNID | Meaning
--- | ---
0b00 | Secure non-invasive debug features not implemented.
0b10 | Implemented and disabled.
0b11 | Implemented and enabled.

All other values are reserved.

When EL3 is implemented, this field takes the value 0b10 or 0b11 depending whether Secure non-invasive debug is enabled.

When EL3 is not implemented and the PE is Non-secure, this field reads as 0b00.

When EL3 is not implemented and the PE is Secure, this field takes the value 0b10 or 0b11 depending whether Secure non-invasive debug is enabled.

#### SID, bits [5:4]

Secure Invasive Debug. Indicates whether Secure invasive debug features are implemented and enabled.

SID | Meaning
--- | ---
0b00 | Secure invasive debug features not implemented.
0b10 | Implemented and disabled.
0b11 | Implemented and enabled.

All other values are reserved.

This field reads as 0b00.

#### NSNID, bits [3:2]

Non-secure Non-invasive Debug. Indicates whether Non-secure non-invasive debug features are implemented and enabled.

NSNID | Meaning
--- | ---
0b00 | Non-secure non-invasive debug features not implemented.
0b10 | Implemented and disabled.
0b11 | Implemented and enabled.

All other values are reserved.

When EL3 is implemented, this field reads as 0b11.

When EL3 is not implemented and the PE is Non-secure, this field reads as 0b11.

When EL3 is not implemented and the PE is Secure, this field reads as 0b00.

#### NSID, bits [1:0]

Non-secure Invasive Debug. Indicates whether Non-secure invasive debug features are implemented and enabled.

NSID | Meaning
--- | ---
0b00 | Non-secure invasive debug features not implemented.
0b10 | Implemented and disabled.
0b11 | Implemented and enabled.

All other values are reserved.

This field reads as 0b00.

## Accessing the TRCAUTHSTATUS

For implementations that support multiple access mechanisms, different access mechanisms can return different values for reads of TRCAUTHSTATUS if the authentication signals have changed and that change has not yet been synchronized by a Context synchronization event. This scenario can happen if, for example, the external debugger view is implemented separately from the system instruction view to allow for separate power domains, and so observes changes on the signals differently.

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCAUTHSTATUS can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xFB8

This interface is accessible as follows:

- When !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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