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# GICH_VTR, Virtual Type Register

The GICH_VTR characteristics are:

## Purpose

Indicates the number of implemented virtual priority bits and List registers.

## Configuration

This register is available when the GIC implementation supports interrupt virtualization.

## Attributes

GICH_VTR is a 32-bit register.

## Field descriptions

The GICH_VTR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRIbits | PREbits | IDbits | SEIS | A3V | RES0 | ListRegs

#### PRIbits, bits [31:29]

The number of virtual priority bits implemented, minus one.

An implementation must implement at least 32 levels of virtual priority (5 priority bits).

#### PREbits, bits [28:26]

The number of virtual preemption bits implemented, minus one.

An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).

The value of this field must be less than or equal to the value of GICH_VTR.PRIbits.

#### IDbits, bits [25:23]

The number of virtual interrupt identifier bits supported:

IDbits | Meaning
--- | ---
0b000 | 16 bits.
0b001 | 24 bits.

All other values are reserved.

#### SEIS, bit [22]

SEI support. Indicates whether the virtual CPU interface supports generation of SEIs:

SEIS | Meaning
--- | ---
0b0 | The virtual CPU interface logic does not support generation of SEIs.
0b1 | The virtual CPU interface logic supports generation of SEIs.

#### A3V, bit [21]

Affinity 3 valid. Possible values are:

A3V | Meaning
--- | ---
0b0 | The virtual CPU interface logic only supports zero values of the Aff3 field in ICC_SGI0R_EL1, ICC_SGI1R_EL1, and ICC_ASGI1R_EL1.
0b1 | The virtual CPU interface logic supports nonzero values of the Aff3 field in ICC_SGI0R_EL1, ICC_SGI1R_EL1, and ICC_ASGI1R_EL1.

#### Bits [20:5]

Reserved, RES0.

#### ListRegs, bits [4:0]

The number of implemented List registers, minus one.

## Accessing the GICH_VTR

This register is used only when System register access is not enabled. When System register access is enabled:

- For AArch32 implementations, ICH_VTR provides equivalent functionality.
- For AArch64 implementations, ICH_VTR_EL2 provides equivalent functionality.

#### GICH_VTR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual interface control | 0x0004 | GICH_VTR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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