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# TRBMAR_EL1, Trace Buffer Memory Attribute Register

The TRBMAR_EL1 characteristics are:

## Purpose

Controls Trace Buffer Extension accesses to memory.

If the trace buffer pointers specify virtual addresses, the address properties are defined by the page tables and this register is ignored.

## Configuration

This register is present only when TRBE is implemented. Otherwise, direct accesses to TRBMAR_EL1 are UNDEFINED.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

## Attributes

TRBMAR_EL1 is a 64-bit register.

## Field descriptions

The TRBMAR_EL1 bit assignments are:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
RES0
RES0 | SH | Attr[7:4] | Attr[3:0]
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0

#### Bits [63:10]

Reserved, RES0.

#### SH, bits [9:8]

Trace buffer shareability domain. Defines the shareability domain for Normal memory used by the trace buffer.

SH | Meaning
--- | ---
0b00 | Not shared.
0b10 | Outer shareable.
0b11 | Inner shareable.

All other values are reserved.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### Attr[7:4], bits [7:4]

Trace buffer memory type and attributes. Defines the memory type and, for Normal memory, the Outer cacheability attributes, for memory addressed by the trace buffer.

Attr[7:4] | Meaning
--- | ---
0b0000 | Device memory. The device memory type is defined by Attr[3:0].
0b0001 | Normal memory, Outer write-through cacheable, transient Write allocate.
0b0010 | Normal memory, Outer write-through cacheable, transient Read allocate.
0b0011 | Normal memory, Outer write-through cacheable, transient Read and Write allocate.
0b0100 | Normal memory, Outer non-cacheable.
0b0101 | Normal memory, Outer write-back cacheable, transient Write allocate.
0b0110 | Normal memory, Outer write-back cacheable, transient Read allocate.
0b0111 | Normal memory, Outer write-back cacheable, transient Read and Write allocate.
0b1000 | Normal memory, Outer write-through cacheable, No allocate.
0b1001 | Normal memory, Outer write-through cacheable, Write allocate.
0b1010 | Normal memory, Outer write-through cacheable, Read allocate.
0b1011 | Normal memory, Outer write-through cacheable, Read and Write allocate.
0b1100 | Normal memory, Outer write-back cacheable, No allocate.
0b1101 | Normal memory, Outer write-back cacheable, Write allocate.
0b1110 | Normal memory, Outer write-back cacheable, Read allocate.
0b1111 | Normal memory, Outer write-back cacheable, Read and Write allocate.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### Attr[3:0], bits [3:0]
When Attr[7:4] == 0b0000:

Trace buffer memory attributes. Defines the Device memory attributes for memory addressed by the trace buffer.

Attr[3:0] | Meaning
--- | ---
0b0000 | Device-nGnRnE.
0b0100 | Device-nGnRE.
0b1000 | Device-nGRE.
0b1100 | Device-GRE.

All other values are reserved.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

####
When Attr[7:4] != 0b0000:

Trace buffer memory attributes. Defines the Inner cacheability attributes for memory addressed by the trace buffer.

Attr[3:0] | Meaning
--- | ---
0b0001 | Normal memory, Inner write-through cacheable, transient Write allocate.
0b0010 | Normal memory, Inner write-through cacheable, transient Read allocate.
0b0011 | Normal memory, Inner write-through cacheable, transient Read and Write allocate.
0b0100 | Normal memory, Inner non-cacheable.
0b0101 | Normal memory, Inner write-back cacheable, transient Write allocate.
0b0110 | Normal memory, Inner write-back cacheable, transient Read allocate.
0b0111 | Normal memory, Inner write-back cacheable, transient Read and Write allocate.
0b1000 | Normal memory, Inner write-through cacheable, No allocate.
0b1001 | Normal memory, Inner write-through cacheable, Write allocate.
0b1010 | Normal memory, Inner write-through cacheable, Read allocate.
0b1011 | Normal memory, Inner write-through cacheable, Read and Write allocate.
0b1100 | Normal memory, Inner write-back cacheable, No allocate.
0b1101 | Normal memory, Inner write-back cacheable, Write allocate.
0b1110 | Normal memory, Inner write-back cacheable, Read allocate.
0b1111 | Normal memory, Inner write-back cacheable, Read and Write allocate.

All other values are reserved.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

## Accessing the TRBMAR_EL1

Accesses to this register use the following encodings:

#### MRS <Xt>, TRBMAR_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1001 | 0b1011 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRBMAR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRBMAR_EL1; elsif PSTATE.EL == EL3 then return TRBMAR_EL1;

#### MSR TRBMAR_EL1, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b1001 | 0b1011 | 0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else TRBMAR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSTB != '01' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSTB != '11' then AArch64.SystemAccessTrap(EL3, 0x18); else TRBMAR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRBMAR_EL1 = X[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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