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# MVFR1, Media and VFP Feature Register 1

The MVFR1 characteristics are:

## Purpose

Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.

Must be interpreted with MVFR0 and MVFR2.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register MVFR1 bits [31:0] are architecturally mapped to AArch64 System register MVFR1_EL1[31:0] .

Implemented only if the implementation includes Advanced SIMD and floating-point instructions.

## Attributes

MVFR1 is a 32-bit register.

## Field descriptions

The MVFR1 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SIMDFMAC | FPHP | SIMDHP | SIMDSP | SIMDInt | SIMDLS | FPDNaN | FPFtZ

#### SIMDFMAC, bits [31:28]

Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions. Defined values are:

SIMDFMAC | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | Implemented.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

The Advanced SIMD and floating-point implementations must provide the same level of support for these instructions.

#### FPHP, bits [27:24]

Floating Point Half Precision. Indicates the level of half-precision floating-point support. Defined values are:

FPHP | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision.
0b0010 | As for 0b0001, and adds instructions for conversion between double-precision and half-precision.
0b0011 | As for 0b0010, and adds support for half-precision floating-point arithmetic.

All other values are reserved.

In Armv8-A the permitted values are:

- 0b0000 in an implementation without floating-point support.
- 0b0010 in an implementation with floating-point support that does not include the ARMv8.2-FP16 extension.
- 0b0011 in an implementation with floating-point support that includes the ARMv8.2-FP16 extension.

The level of support indicated by this field must be equivalent to the level of support indicated by the SIMDHP field, meaning the permitted values are:

Half Precision instructions supported | FPHP | SIMDHP
--- | --- | ---
No support | 0b0000 | 0b0000
Conversions only | 0b0010 | 0b0001
Conversions and arithmetic | 0b0011 | 0b0010

#### SIMDHP, bits [23:20]

Advanced SIMD Half Precision. Indicates the level of half-precision floating-point support. Defined values are:

SIMDHP | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | SIMD half-precision conversion instructions are supported for conversion between single-precision and half-precision.
0b0010 | As for 0b0001, and adds support for half-precision floating-point arithmetic.

All other values are reserved.

In Armv8-A the permitted values are:

- 0b0000 in an implementation without SIMD floating-point support.
- 0b0010 in an implementation with SIMD floating-point support that does not include the ARMv8.2-FP16 extension.
- 0b0011 in an implementation with SIMD floating-point support that includes the ARMv8.2-FP16 extension.

The level of support indicated by this field must be equivalent to the level of support indicated by the FPHP field, meaning the permitted values are:

Half Precision instructions supported | FPHP | SIMDHP
--- | --- | ---
No support | 0b0000 | 0b0000
Conversions only | 0b0010 | 0b0001
Conversions and arithmetic | 0b0011 | 0b0010

#### SIMDSP, bits [19:16]

Advanced SIMD Single Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions. Defined values are:

SIMDSP | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | Implemented. This value is permitted only if the SIMDInt field is 0b0001.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

#### SIMDInt, bits [15:12]

Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions. Defined values are:

SIMDInt | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | Implemented.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

#### SIMDLS, bits [11:8]

Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions. Defined values are:

SIMDLS | Meaning
--- | ---
0b0000 | Not implemented.
0b0001 | Implemented.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

#### FPDNaN, bits [7:4]

Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode. Defined values are:

FPDNaN | Meaning
--- | ---
0b0000 | Not implemented, or hardware supports only the Default NaN mode.
0b0001 | Hardware supports propagation of NaN values.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

#### FPFtZ, bits [3:0]

Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation. Defined values are:

FPFtZ | Meaning
--- | ---
0b0000 | Not implemented, or hardware supports only the Flush-to-Zero mode of operation.
0b0001 | Hardware supports full denormalized number arithmetic.

All other values are reserved.

In Armv8-A the permitted values are 0b0000 and 0b0001.

## Accessing the MVFR1

Accesses to this register use the following encodings:

#### VMRS{<c>}{<q>} <Rt>, <spec_reg>

reg
0b0110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if ELUsingAArch32(EL1) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || CPACR.cp10 == '00') then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && ELUsingAArch32(EL2) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then AArch32.TakeHypTrapException(0x08); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x08); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x08); else return MVFR1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.AArch32SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && ELUsingAArch32(EL2) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then AArch32.TakeHypTrapException(0x00); else return MVFR1; elsif PSTATE.EL == EL3 then if CPACR.cp10 == '00' then UNDEFINED; else return MVFR1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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