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# GICH_MISR, Maintenance Interrupt Status Register

The GICH_MISR characteristics are:

## Purpose

Indicates which maintenance interrupts are asserted.

## Configuration

Some or all RW fields of this register have defined reset values.

This register is available when the GIC implementation supports interrupt virtualization.

## Attributes

GICH_MISR is a 32-bit register.

## Field descriptions

The GICH_MISR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | VGrp1D | VGrp1E | VGrp0D | VGrp0E | NP | LRENP | U | EOI

#### Bits [31:8]

Reserved, RES0.

#### VGrp1D, bit [7]

vPE Group 1 Disabled.

VGrp1D | Meaning
--- | ---
0b0 | vPE Group 1 Disabled maintenance interrupt not asserted.
0b1 | vPE Group 1 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp1DIE == 1 and GICH_VMCR.VENG1 == 0.

This field resets to 0.

#### VGrp1E, bit [6]

vPE Group 1 Enabled.

VGrp1E | Meaning
--- | ---
0b0 | vPE Group 1 Enabled maintenance interrupt not asserted.
0b1 | vPE Group 1 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp1EIE == 1 and GICH_VMCR.VENG1 == 1.

This field resets to 0.

#### VGrp0D, bit [5]

vPE Group 0 Disabled.

VGrp0D | Meaning
--- | ---
0b0 | vPE Group 0 Disabled maintenance interrupt not asserted.
0b1 | vPE Group 0 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp0DIE == 1 and GICH_VMCR.VENG0 == 0.

This field resets to 0.

#### VGrp0E, bit [4]

vPE Group 0 Enabled.

VGrp0E | Meaning
--- | ---
0b0 | vPE Group 0 Enabled maintenance interrupt not asserted.
0b1 | vPE Group 0 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp0EIE == 1 and GICH_VMCR.VENG0 == 1.

This field resets to 0.

#### NP, bit [3]

No Pending.

NP | Meaning
--- | ---
0b0 | No Pending maintenance interrupt not asserted.
0b1 | No Pending maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.NPIE == 1 and no List register is in the pending state.

This field resets to 0.

#### LRENP, bit [2]

List Register Entry Not Present.

LRENP | Meaning
--- | ---
0b0 | List Register Entry Not Present maintenance interrupt not asserted.
0b1 | List Register Entry Not Present maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.LRENPIE == 1 and GICH_HCR.EOICount is nonzero.

This field resets to 0.

#### U, bit [1]

Underflow.

U | Meaning
--- | ---
0b0 | Underflow maintenance interrupt not asserted.
0b1 | Underflow maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.UIE == 1 and zero or one of the List register entries are marked as a valid interrupt.

This field resets to 0.

#### EOI, bit [0]

End Of Interrupt.

EOI | Meaning
--- | ---
0b0 | End Of Interrupt maintenance interrupt not asserted.
0b1 | End Of Interrupt maintenance interrupt asserted.

This maintenance interrupt is asserted when at least one bit in GICH_EISR == 1.

This field resets to 0.

Note

A List register is in the pending state only if the corresponding GICH_LR<n> value is 0b01, that is, pending. The active and pending state is not included.

## Accessing the GICH_MISR

This register is used only when System register access is not enabled. When System register access is enabled:

- For AArch32 implementations, ICH_MISR provides equivalent functionality.
- For AArch64 implementations, ICH_MISR_EL2 provides equivalent functionality.

A maintenance interrupt is asserted only if at least one bit is set to 1 in this register and if GICH_HCR.En == 1.

#### GICH_MISR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual interface control | 0x0010 | GICH_MISR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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