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AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCPIDR1, Peripheral Identification Register 1

The TRCPIDR1 characteristics are:

## Purpose

Provides discovery information for the component.

For additional information see the CoreSight Architecture Specification.

## Configuration

This register is present only when ETE is implemented. Otherwise, direct accesses to TRCPIDR1 are RES0.

There are no configuration notes.

## Attributes

TRCPIDR1 is a 32-bit register.

## Field descriptions

The TRCPIDR1 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | DES_0 | PART_1

#### Bits [31:8]

Reserved, RES0.

#### DES_0, bits [7:4]

IMPLEMENTATION DEFINED.

Designer, JEP106 identification code, bits [3:0]. TRCPIDR1.DES_0 and TRCPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

Note that for a component designed by ARM Limited, the JEP106 identification code is 0x3B.

This field reads as an IMPLEMENTATION DEFINED value.

#### PART_1, bits [3:0]

IMPLEMENTATION DEFINED.

Part number, bits [11:8].

This field reads as an IMPLEMENTATION DEFINED value.

## Accessing the TRCPIDR1

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCPIDR1 can be accessed through the external debug interface:

Component | Offset
--- | ---
ETE | 0xFE4

This interface is accessible as follows:

- When !IsTraceCorePowered() access to this register returns an Error.
- Otherwise access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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