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# ID_DFR0, Debug Feature Register 0

The ID_DFR0 characteristics are:

## Purpose

Provides top level information about the debug system in AArch32 state.

Must be interpreted with the Main ID Register, MIDR.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.

## Configuration

AArch32 System register ID_DFR0 bits [31:0] are architecturally mapped to AArch64 System register ID_DFR0_EL1[31:0] .

## Attributes

ID_DFR0 is a 32-bit register.

## Field descriptions

The ID_DFR0 bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TraceFilt | PerfMon | MProfDbg | MMapTrc | CopTrc | MMapDbg | CopSDbg | CopDbg

#### TraceFilt, bits [31:28]

Armv8.4 Self-hosted Trace Extension version. Defined values are:

TraceFilt | Meaning
--- | ---
0b0000 | Armv8.4 Self-hosted Trace Extension not implemented.
0b0001 | Armv8.4 Self-hosted Trace Extension implemented.

All other values are reserved.

ARMv8.4-Trace implements the functionality added by the value 0b0001.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

#### PerfMon, bits [27:24]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the alternative ID scheme described in Alternative ID scheme used for the Performance Monitors Extension version.

Defined values are:

PerfMon | Meaning
--- | ---
0b0000 | Performance Monitors Extension not implemented.
0b0001 | Performance Monitors Extension version 1 implemented, PMUv1.
0b0010 | Performance Monitors Extension version 2 implemented, PMUv2.
0b0011 | Performance Monitors Extension version 3 implemented, PMUv3.
0b0100 | PMUv3 for Armv8.1. As 0b0011, and also includes support for: Extended 16-bit PMEVTYPER<n>.evtCount field. If EL2 is implemented, the HDCR.HPMD control bit.
0b0101 | PMUv3 for Armv8.4. As 0b0100 and also includes support for the PMMIR register.
0b0110 | PMUv3 for Armv8.5. As 0b0101 and also includes support for: 64-bit event counters. If EL2 is implemented, the HDCR.HCCD control bit. If EL3 is implemented, the SDCR.SCCD control bit.
0b1111 | IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value in new implementations.

ARMv8.1-PMU implements the functionality added by the value 0b0100.

ARMv8.4-PMU implements the functionality added by the value 0b0101.

ARMv8.5-PMU implements the functionality added by the value 0b0110.

All other values are reserved.

In any Armv8 implementation, the values 0b0001 and 0b0010 are not permitted.

From Armv8.1, the value 0b0011 is not permitted.

From Armv8.4, the value 0b0100 is not permitted.

From Armv8.5, the value 0b0101 is not permitted.

Note

In Armv7, the value 0b0000 can mean that PMUv1 is implemented. PMUv1 is not permitted in an Armv8 implementation.

#### MProfDbg, bits [23:20]

M Profile Debug. Support for memory-mapped debug model for M profile processors. Defined values are:

MProfDbg | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for M profile Debug architecture, with memory-mapped access.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

#### MMapTrc, bits [19:16]

Memory Mapped Trace. Support for memory-mapped trace model. Defined values are:

MMapTrc | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for Arm trace architecture, with memory-mapped access.

All other values are reserved.

In Armv8-A, the permitted values are 0b0000 and 0b0001.

See the ETM Architecture Specification for more information.

#### CopTrc, bits [15:12]

Support for System registers-based trace model, using registers in the coproc == 0b1110 encoding space. Defined values are:

CopTrc | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for Arm trace architecture, with System registers access.

All other values are reserved.

In Armv8-A, the permitted values are 0b0000 and 0b0001.

See the ETM Architecture Specification for more information.

#### MMapDbg, bits [11:8]

Memory Mapped Debug. Support for v7 memory-mapped debug model, for A and R profile processors.

In Armv8-A, this field is RES0.

The optional memory map defined by Armv8 is not compatible with Armv7.

#### CopSDbg, bits [7:4]

Support for a System registers-based Secure debug model, using registers in the coproc = 0b1110 encoding space, for an A profile processor that includes EL3.

If EL3 is not implemented and the implemented Security state is Non-secure state, this field is RES0. Otherwise, this field reads the same as bits [3:0].

#### CopDbg, bits [3:0]

Support for System registers-based debug model, using registers in the coproc == 0b1110 encoding space, for A and R profile processors. Defined values are:

CopDbg | Meaning
--- | ---
0b0000 | Not supported.
0b0010 | Support for Armv6, v6 Debug architecture, with System registers access.
0b0011 | Support for Armv6, v6.1 Debug architecture, with System registers access.
0b0100 | Support for Armv7, v7 Debug architecture, with System registers access.
0b0101 | Support for Armv7, v7.1 Debug architecture, with System registers access.
0b0110 | Support for Armv8 debug architecture, with System registers access.
0b0111 | Support for Armv8 debug architecture, with System registers access, and Virtualization Host extensions.
0b1000 | Support for Armv8.2 debug architecture.
0b1001 | Support for Armv8.4 debug architecture.

All other values are reserved.

In any Armv8 implementation, the values 0b0000, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted.

If ARMv8.1-VHE is not implemented, the only permitted value is 0b0110.

In an Armv8.0 implementation, the value 0b1000 is not permitted.

## Accessing the ID_DFR0

Accesses to this register use the following encodings:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_DFR0; elsif PSTATE.EL == EL2 then return ID_DFR0; elsif PSTATE.EL == EL3 then return ID_DFR0;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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