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# PMMIR, Performance Monitors Machine Identification Register

The PMMIR characteristics are:

## Purpose

Describes Performance Monitors parameters specific to the implementation.

## Configuration

PMMIR is in the Core power domain.

This register is present only when ARMv8.4-PMU is implemented. Otherwise, direct accesses to PMMIR are RES0.

## Attributes

PMMIR is a 32-bit register.

## Field descriptions

The PMMIR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SLOTS

#### Bits [31:8]

Reserved, RES0.

#### SLOTS, bits [7:0]

Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is implemented, this field must not be zero.

## Accessing the PMMIR

If the Core power domain is off or in a low-power state, access on this interface returns an Error.

#### PMMIR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
PMU | 0xE40 | PMMIR

This interface is accessible as follows:

- When !IsCorePowered(), or DoubleLockStatus(), or OSLockStatus() or !AllowExternalPMUAccess() access to this register returns an Error.
- Otherwise access to this register is RO.

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27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376

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