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# GICV_IIDR, Virtual Machine CPU Interface Identification Register

The GICV_IIDR characteristics are:

## Purpose

Provides information about the implementer and revision of the virtual CPU interface.

## Configuration

This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.

## Attributes

GICV_IIDR is a 32-bit register.

## Field descriptions

The GICV_IIDR bit assignments are:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ProductID | Architecture_version | Revision | Implementer

#### ProductID, bits [31:20]

An IMPLEMENTATION DEFINED product identifier.

#### Architecture_version, bits [19:16]

The version of the GIC architecture that is implemented.

Architecture_version | Meaning
--- | ---
0b0001 | GICv1.
0b0010 | GICv2.
0b0011 | GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.
0b0100 | GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1.

Other values are reserved.

#### Revision, bits [15:12]

An IMPLEMENTATION DEFINED revision number for the CPU interface.

#### Implementer, bits [11:0]

Contains the JEP106 code of the company that implemented the CPU interface.

- Bits [11:8] are the JEP106 continuation code of the implementer. For an Arm implementation, this field is 0x4.
- Bit [7] is always 0.
- Bits [6:0] are the JEP106 identity code of the implementer. For an Arm implementation, bits [7:0] are therefore 0x3B.

## Accessing the GICV_IIDR

#### GICV_IIDR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual CPU interface | 0x00FC | GICV_IIDR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0b0 access to this register is RO.
- When IsAccessSecure() access to this register is RO.
- When !IsAccessSecure() access to this register is RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

15/04/2019 16:47; 8c23526ba8a13a72aada4137daf3e3977b49036e

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