The MIPS configurations of gnu as
support these
special options:
-G
num-EB
-EL
as
can select big-endian or
little-endian output at run time (unlike the other gnu development
tools, which must be configured for one or the other). Use ‘-EB’
to select big-endian output, and ‘-EL’ for little-endian.
-KPIC
-mvxworks-pic
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips32r3
-mips32r5
-mips32r6
-mips64
-mips64r2
-mips64r3
-mips64r5
-mips64r6
-mgp32
-mfp32
The .set gp=32
and .set fp=32
directives allow the size
of registers to be changed for parts of an object. The default value is
restored by .set gp=default
and .set fp=default
.
On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
-mgp64
-mfp64
The .set gp=64
and .set fp=64
directives allow the size
of registers to be changed for parts of an object. The default value is
restored by .set gp=default
and .set fp=default
.
-mfpxx
The .set fp=xx
directive allows a part of an object to be marked
as not making assumptions about 32-bit or 64-bit FP registers. The
default value is restored by .set fp=default
.
-modd-spreg
-mno-odd-spreg
-mips16
-no-mips16
.module mips16
at the start of the assembly file. ‘-no-mips16’
turns off this option.
-mmips16e2
-mno-mips16e2
.module mips16e2
at the start of the assembly file.
‘-mno-mips16e2’ turns off this option.
-mmicromips
-mno-micromips
.module micromips
at the start of the assembly file.
‘-mno-micromips’ turns off this option. This is equivalent to putting
.module nomicromips
at the start of the assembly file.
-msmartmips
-mno-smartmips
.module smartmips
at the start of the assembly file.
‘-mno-smartmips’ turns off this option.
-mips3d
-no-mips3d
-mdmx
-no-mdmx
-mdsp
-mno-dsp
-mdspr2
-mno-dspr2
-mdspr3
-mno-dspr3
-mmt
-mno-mt
-mmcu
-mno-mcu
-mmsa
-mno-msa
-mxpa
-mno-xpa
-mvirt
-mno-virt
-minsn32
-mno-insn32
.set insn32
at
the start of the assembly file. ‘-mno-insn32’ turns off this
option. This is equivalent to putting .set noinsn32
at the
start of the assembly file. By default ‘-mno-insn32’ is
selected, allowing all instructions to be used.
-mfix7000
-mno-fix7000
-mfix-rm7000
-mno-fix-rm7000
-mfix-loongson2f-jump
-mno-fix-loongson2f-jump
-mfix-loongson2f-nop
-mno-fix-loongson2f-nop
or at,at,zero
to work around the Loongson2F
‘nop’ errata. Without it, under extreme cases, the CPU might
deadlock. The issue has been solved in later Loongson2F batches, but
this fix has no side effect to them.
-mfix-vr4120
-mno-fix-vr4120
-mfix-vr4130
-mno-fix-vr4130
-mfix-24k
-mno-fix-24k
-mfix-cn63xxp1
-mno-fix-cn63xxp1
pref
hints 0 - 4 and 6 - 24 with hint 28 to work around
certain CN63XXP1 errata.
-m4010
-no-m4010
-m4650
-no-m4650
-m3900
-no-m3900
-m4100
-no-m4100
-march=
cpu2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, i6400, p6600, loongson2e, loongson2f, loongson3a, octeon, octeon+, octeon2, octeon3, xlr, xlp
For compatibility reasons, ‘nx’ and ‘bfx’ are
accepted as synonyms for ‘nf1_1’. These values are
deprecated.
-mtune=
cpu-mabi=
abi-msym32
-mno-sym32
.set sym32
or .set nosym32
to
the beginning of the assembler input. See MIPS Symbol Sizes.
-nocpp
as
, there is no need for ‘-nocpp’, because the
gnu assembler itself never runs the C preprocessor.
-msoft-float
-mhard-float
-msingle-float
-mdouble-float
--construct-floats
--no-construct-floats
--no-construct-floats
option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register. This feature is useful if the processor
support the FR bit in its status register, and this bit is known (by
the programmer) to be set. This bit prevents the aliasing of the double
width register by the single width registers.
By default --construct-floats
is selected, allowing construction
of these floating point constants.
--relax-branch
--no-relax-branch
The BC1ANY2F
, BC1ANY2T
, BC1ANY4F
, BC1ANY4T
,
BPOSGE32
and BPOSGE64
instructions are excluded from
relaxation, because they have no complementing counterparts. They could
be relaxed with the use of a longer sequence involving another branch,
however this has not been implemented and if their target turns out of
reach, they produce an error even if branch relaxation is enabled.
Also no MIPS16 branches are ever relaxed.
By default ‘--no-relax-branch’ is selected, causing any out-of-range
branches to produce an error.
-mignore-branch-isa
-mno-ignore-branch-isa
The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. If the ISA modes do not match, then such a branch, if taken, will cause the ISA mode to remain unchanged and instructions that follow will be executed in the wrong ISA mode causing the program to misbehave or crash.
In the case of the BAL
instruction it may be possible to relax
it to an equivalent JALX
instruction so that the ISA mode is
switched at the run time as required. For other branches no relaxation
is possible and therefore GAS has checks implemented that verify in
branch assembly that the two ISA modes match, and report an error
otherwise so that the problem with code can be diagnosed at the assembly
time rather than at the run time.
However some assembly code, including generated code produced by some versions of GCC, may incorrectly include branches to data labels, which appear to require a mode switch but are either dead or immediately followed by valid instructions encoded for the same ISA the branch has been encoded for. While not strictly correct at the source level such code will execute as intended, so to help with these cases ‘-mignore-branch-isa’ is supported which disables ISA mode checks for branches.
By default ‘-mno-ignore-branch-isa’ is selected, causing any invalid branch requiring a transition between ISA modes to produce an error.
-mnan=
encoding.nan
directive to the beginning of the source file. See MIPS NaN Encodings.
-mnan=legacy is the default if no -mnan option or
.nan
directive is used.
--trap
--no-break
as
automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes as
to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
-mpdr
-mno-pdr
.pdr
sections. Off by default on IRIX, on
elsewhere.
-mshared
-mno-shared