Bitwise AND predicates.
Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Optionally sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
This instruction is used by the aliases MOVS (predicated) and MOV (predicate, predicated, zeroing) . See Alias Conditions below for details of when each alias is preferred.
It has encodings from 2 classes: Flag setting and Not flag setting
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Pm | 0 | 1 | Pg | 0 | Pn | 0 | Pd | ||||||||||||
S |
if !HaveSVE() then UNDEFINED; integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); boolean setflags = TRUE;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | 0 | 1 | Pg | 0 | Pn | 0 | Pd | ||||||||||||
S |
if !HaveSVE() then UNDEFINED; integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); boolean setflags = FALSE;
<Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
<Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
<Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
<Pm> |
Is the name of the second source scalable predicate register, encoded in the "Pm" field. |
Alias | Is preferred when |
---|---|
MOVS (predicated) | S == '1' && Pn == Pm |
MOV (predicate, predicated, zeroing) | S == '0' && Pn == Pm |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(PL) operand1 = P[n]; bits(PL) operand2 = P[m]; bits(PL) result; for e = 0 to elements-1 bit element1 = ElemP[operand1, e, esize]; bit element2 = ElemP[operand2, e, esize]; if ElemP[mask, e, esize] == '1' then ElemP[result, e, esize] = element1 AND element2; else ElemP[result, e, esize] = '0'; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d] = result;
Release: 00rel5-manual
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.