Conditionally select elements from two vectors.
Read active elements from the first source vector and inactive elements from the second source vector and place in the corresponding elements of the destination vector.
This instruction is used by the alias MOV (vector, predicated) . See Alias Conditions below for details of when the alias is preferred.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 1 | 1 | Pg | Zn | Zd |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
Alias | Is preferred when |
---|---|
MOV (vector, predicated) | Zd == Zm |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; bits(esize) element2 = Elem[operand2, e, esize]; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = element1; else Elem[result, e, esize] = element2; Z[d] = result;
Release: 00rel5-manual
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