CPTR_EL2, Architectural Feature Trap Register (EL2)

The CPTR_EL2 characteristics are:

Purpose

Controls:

Configuration

AArch64 System register CPTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HCPTR[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CPTR_EL2 is a 64-bit register.

Field descriptions

The CPTR_EL2 bit assignments are:

When HCR_EL2.E2H == 0:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
TCPACTAM000000000TTA000000110TFP1TZ11111111
313029282726252423222120191817161514131211109876543210

This format applies in all ARMv8.0 implementations.

Bits [63:32]

Reserved, RES0.

TCPAC, bit [31]

Traps EL1 accesses to CPACR_EL1 or CPACR to EL2 when it is enabled in the current Security state, from both Execution states.

TCPACMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when it is enabled in the current Security state.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

This field resets to an architecturally UNKNOWN value.

TAM, bit [30]

When AMUv1 is implemented:

Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, when EL2 is enabled in the current Security state.

TAMMeaning
0b0

Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.

0b1

Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [29:21]

Reserved, RES0.

TTA, bit [20]

From ARMv8.1:

Traps System register accesses to all implemented trace registers to EL2 when it is enabled in the current Security state, from both Execution states.

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1, or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state, unless it is trapped by CPACR.TRCDIS or CPACR_EL1.TTA.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [19:14]

Reserved, RES0.

Bits [13:12]

Reserved, RES1.

Bit [11]

Reserved, RES0.

TFP, bit [10]

Traps accesses to SVE, Advanced SIMD and floating-point functionality to EL2 when it is enabled in the current Security state, from both Execution states.

TFPMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1 or EL2, to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point execution is trapped to EL2 when it is enabled in the current Security state, subject to the exception prioritization rules, unless it is trapped by CPTR_EL2.TZ.

This field resets to an architecturally UNKNOWN value.

Bit [9]

Reserved, RES1.

TZ, bit [8]

When SVE is implemented:

Traps execution at EL2, EL1, or EL0 of SVE instructions and instructions that access SVE System registers to EL2 when it is enabled in the current Security state.

TZMeaning
0b0

This control does not cause any instruction to be trapped.

0b1

This control causes these instructions to be trapped, subject to the exception prioritization rules.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES1.

Bits [7:0]

Reserved, RES1.

When HCR_EL2.E2H == 1:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
TCPACTAM0TTA000000FPEN00ZEN0000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

TCPAC, bit [31]

From ARMv8.1:

When HCR_EL2.TGE is 0, traps EL1 accesses to CPACR_EL1 and CPACR to EL2 when it is enabled in the current Security state, from both Execution states.

TCPACMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when it is enabled in the current Security state.

When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

TAM, bit [30]

When AMUv1 is implemented:

Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2.

TAMMeaning
0b0

Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.

0b1

Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bit [29]

Reserved, RES0.

TTA, bit [28]

From ARMv8.1:

Traps System register accesses to all implemented trace registers to EL2 when it is enabled in the current Security state, from both Execution states.

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1 or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA.

When HCR_EL2.TGE is 1, any attempt at EL0 or EL2 to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [27:22]

Reserved, RES0.

FPEN, bits [21:20]

From ARMv8.1:

Traps EL0, EL2 and, when HCR_EL2.TGE is 0, EL1 accesses to the SVE, Advanced SIMD and floating-point registers to EL2 when it is enabled in the current Security state, from both Execution states.

FPENMeaning
0b00

This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN.

0b01

When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.

When HCR_EL2.TGE is 1, this control causes instructions at EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPTR_EL2.ZEN, but does not cause any instruction at EL2 to be trapped.

0b10

This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN.

0b11

This control does not cause any instructions to be trapped.

Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.

Note

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [19:18]

Reserved, RES0.

ZEN, bits [17:16]

When SVE is implemented:

Traps execution at EL2, EL1, and EL0 of SVE instructions or instructions that access SVE System registers to EL2 when it is enabled in the current Security state.

ZENMeaning
0b00

This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

0b01

When HCR_EL2.TGE is 0, this control does not cause any instruction to be trapped.

When HCR_EL2.TGE is 1, this control causes these instructions executed at EL0 to be trapped, but does not cause any instruction at EL2 to be trapped.

0b10

This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

0b11

This control does not cause any instruction to be trapped.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [15:0]

Reserved, RES0.

Accessing the CPTR_EL2

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0CRnop1op2CRm
CPTR_EL21100011000100001
CPACR_EL11100010000100000

Accessibility

The register is accessible as follows:

<systemreg>ConfigurationAccessibility
EL0EL1EL2EL3
CPTR_EL2SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0--n/aRW
CPTR_EL2HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)--RWRW
CPTR_EL2HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aRWRW
CPACR_EL1SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0-CPACR_EL1n/aCPACR_EL1
CPACR_EL1HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-CPACR_EL1CPACR_EL1CPACR_EL1
CPACR_EL1HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aCPACR_EL1CPACR_EL1
CPACR_EL1HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-CPACR_EL1RWCPACR_EL1
CPACR_EL1HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aRWCPACR_EL1

If an _EL1 accessor is used, refer to CPACR_EL1 for information on the effect of HCR_EL2.NV2 on this accessor.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.