Gather load signed words to vector (vector index).
Gather load of signed words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not read Device memory or signal faults, and are set to zero in the destination vector.
It has encodings from 4 classes: 32-bit unpacked scaled offset , 32-bit unpacked unscaled offset , 64-bit scaled offset and 64-bit unscaled offset
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1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | xs | 1 | Zm | 0 | 0 | 0 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 32; boolean unsigned = FALSE; boolean offs_unsigned = xs == '0'; integer scale = 2;
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1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | xs | 0 | Zm | 0 | 0 | 0 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 32; boolean unsigned = FALSE; boolean offs_unsigned = xs == '0'; integer scale = 0;
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1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | Zm | 1 | 0 | 0 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 64; boolean unsigned = FALSE; boolean offs_unsigned = TRUE; integer scale = 2;
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1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Zm | 1 | 0 | 0 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Zm); integer g = UInt(Pg); integer esize = 64; integer msize = 32; integer offs_size = 64; boolean unsigned = FALSE; boolean offs_unsigned = TRUE; integer scale = 0;
<Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
<mod> |
Is the index extend and shift specifier,
encoded in
xs:
|
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(VL) offset = Z[m]; bits(PL) mask = P[g]; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned); addr = base + (off << scale); data = Mem[addr, mbytes, AccType_NORMAL]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(); Z[t] = result;
Release: 00rel5-manual
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