The CPTR_EL3 characteristics are:
Controls trapping to EL3 of access to CPACR_EL1, CPTR_EL2, trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution. Also controls EL3 access to trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution.
RW fields in this register reset to architecturally UNKNOWN values.
CPTR_EL3 is a 64-bit register.
The CPTR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TCPAC | TAM | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TFP | 0 | EZ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Traps all of the following to EL3, from both Security states and both Execution states.
When CPTR_EL3.TCPAC is:
TCPAC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. |
This field resets to an architecturally UNKNOWN value.
Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL3.
TAM | Meaning |
---|---|
0b0 |
Accesses from EL2, EL1, and EL0 to Activity Monitor registers are not trapped. |
0b1 |
Accesses from EL2, EL1, and EL0 to Activity Monitor registers are trapped to EL3. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps System register accesses to the trace registers, from all Exception levels, both Security states, and both Execution states, to EL3.
TTA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any System register access to the trace registers is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPACR.TRCDIS, CPACR_EL1.TTA or CPTR_EL2.TTA. |
If System register access to trace functionality is not supported, this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps all accesses to SVE, Advanced SIMD and floating-point functionality, from all Exception levels, both Security states, and both Execution states, to EL3. Defined values are:
TFP | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt at any Exception level to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPTR_EL3.EZ. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps all accesses to SVE functionality and registers from all Exception levels, and both Security states, to EL3.
EZ | Meaning |
---|---|
0b0 |
This control causes these instructions executed at any Exception level to be trapped, subject to the exception prioritization rules. |
0b1 |
This control does not cause any instruction to be trapped. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
CPTR_EL3 | 11 | 0001 | 110 | 010 | 0001 |
The register is accessible as follows:
Configuration | Accessibility | |||
---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | |
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | - | n/a | RW |
HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | - | - | RW |
HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | - | RW |
15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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