Contiguous store non-temporal bytes from vector (scalar index).
Contiguous store non-temporal of bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rm | 0 | 1 | 1 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 8;
<Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(64) offset = X[m]; bits(VL) src; bits(PL) mask = P[g]; constant integer mbytes = esize DIV 8; if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; src = Z[t]; for e = 0 to elements-1 addr = base + UInt(offset) * mbytes; if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_STREAM] = Elem[src, e, esize]; offset = offset + 1;
Release: 00rel5-manual
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