ZCR_EL1, SVE Control Register for EL1

The ZCR_EL1 characteristics are:

Purpose

The SVE Control Register for EL1 is used to control aspects of SVE visible at Exception levels EL1 and EL0.

Configuration

This register is present only when SVE is implemented. Otherwise, direct accesses to ZCR_EL1 are UNDEFINED.

When HCR_EL2.{E2H, TGE} == {1, 1} and EL2 is enabled in the current Security state, the fields in this register have no effect on execution at EL0

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

ZCR_EL1 is a 64-bit register.

Field descriptions

The ZCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000000000000000000000000000LEN
313029282726252423222120191817161514131211109876543210

Bits [63:9]

Reserved, RES0.

Bits [8:4]

Reserved, RAZ/WI.

LEN, bits [3:0]

Constrains the scalable vector register length for EL1 and EL0 to (LEN+1)x128 bits. For all purposes other than returning the result of a direct read of ZCR_EL1 then this field behaves as if it is set to the minimum of the stored value and the constrained length inherited from more privileged Exception levels in the current Security state, rounded down to the nearest implemented vector length.

An indirect read of ZCR_EL1.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.

This field resets to an architecturally UNKNOWN value.

Accessing the ZCR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0CRnop1op2CRm
ZCR_EL11100010000000010
ZCR_EL121100011010000010

Accessibility

The register is accessible as follows:

<systemreg>ConfigurationAccessibility
EL0EL1EL2EL3
ZCR_EL1SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0-RWn/aRW
ZCR_EL1(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 0 || HCR_EL2.NV2 == 0) && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0-RWRWRW
ZCR_EL1HCR_EL2.NV == 1 && HCR_EL2.NV1 == 1 && HCR_EL2.NV2 == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0-[VNCR_EL2.BADDR << 12 + 0x1E0]RWRW
ZCR_EL1(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0-n/aRWRW
ZCR_EL1(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 0 || HCR_EL2.NV2 == 0) && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1-RWZCR_EL2RW
ZCR_EL1HCR_EL2.NV == 1 && HCR_EL2.NV1 == 1 && HCR_EL2.NV2 == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1-[VNCR_EL2.BADDR << 12 + 0x1E0]ZCR_EL2RW
ZCR_EL1(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1-n/aZCR_EL2RW
ZCR_EL12SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0--n/a-
ZCR_EL12(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 1 || HCR_EL2.NV2 == 0) && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0----
ZCR_EL12HCR_EL2.NV == 1 && HCR_EL2.NV1 == 0 && HCR_EL2.NV2 == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0-[VNCR_EL2.BADDR << 12 + 0x1E0]--
ZCR_EL12(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0-n/a--
ZCR_EL12(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 1 || HCR_EL2.NV2 == 0) && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1--RWRW
ZCR_EL12HCR_EL2.NV == 1 && HCR_EL2.NV1 == 0 && HCR_EL2.NV2 == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1-[VNCR_EL2.BADDR << 12 + 0x1E0]RWRW
ZCR_EL12(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1-n/aRWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ZCR_EL1 or ZCR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb

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