The CPTR_EL2 characteristics are:
Controls:
AArch64 System register CPTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HCPTR[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
CPTR_EL2 is a 64-bit register.
The CPTR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TCPAC | TAM | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | TFP | 1 | TZ | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
This format applies in all ARMv8.0 implementations.
Reserved, RES0.
Traps EL1 accesses to CPACR_EL1 or CPACR to EL2 when it is enabled in the current Security state, from both Execution states.
TCPAC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when it is enabled in the current Security state. |
This field resets to an architecturally UNKNOWN value.
Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, when EL2 is enabled in the current Security state.
TAM | Meaning |
---|---|
0b0 |
Accesses from EL1 and EL0 to Activity Monitor registers are not trapped. |
0b1 |
Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps System register accesses to all implemented trace registers to EL2 when it is enabled in the current Security state, from both Execution states.
TTA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt at EL0, EL1, or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state, unless it is trapped by CPACR.TRCDIS or CPACR_EL1.TTA. |
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
If System register access to the trace functionality is not supported, this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Traps accesses to SVE, Advanced SIMD and floating-point functionality to EL2 when it is enabled in the current Security state, from both Execution states.
TFP | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt at EL0, EL1 or EL2, to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point execution is trapped to EL2 when it is enabled in the current Security state, subject to the exception prioritization rules, unless it is trapped by CPTR_EL2.TZ. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Traps execution at EL2, EL1, or EL0 of SVE instructions and instructions that access SVE System registers to EL2 when it is enabled in the current Security state.
TZ | Meaning |
---|---|
0b0 |
This control does not cause any instruction to be trapped. |
0b1 |
This control causes these instructions to be trapped, subject to the exception prioritization rules. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES1.
Reserved, RES1.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TCPAC | TAM | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | FPEN | 0 | 0 | ZEN | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
When HCR_EL2.TGE is 0, traps EL1 accesses to CPACR_EL1 and CPACR to EL2 when it is enabled in the current Security state, from both Execution states.
TCPAC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when it is enabled in the current Security state. |
When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2.
TAM | Meaning |
---|---|
0b0 |
Accesses from EL1 and EL0 to Activity Monitor registers are not trapped. |
0b1 |
Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps System register accesses to all implemented trace registers to EL2 when it is enabled in the current Security state, from both Execution states.
TTA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt at EL0, EL1 or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA. When HCR_EL2.TGE is 1, any attempt at EL0 or EL2 to execute a System register access to an implemented trace register is trapped to EL2 when it is enabled in the current Security state. |
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
If System register access to the trace functionality is not supported, this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps EL0, EL2 and, when HCR_EL2.TGE is 0, EL1 accesses to the SVE, Advanced SIMD and floating-point registers to EL2 when it is enabled in the current Security state, from both Execution states.
FPEN | Meaning |
---|---|
0b00 |
This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN. |
0b01 |
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped. When HCR_EL2.TGE is 1, this control causes instructions at EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPTR_EL2.ZEN, but does not cause any instruction at EL2 to be trapped. |
0b10 |
This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN. |
0b11 |
This control does not cause any instructions to be trapped. |
Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps execution at EL2, EL1, and EL0 of SVE instructions or instructions that access SVE System registers to EL2 when it is enabled in the current Security state.
ZEN | Meaning |
---|---|
0b00 |
This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules. |
0b01 |
When HCR_EL2.TGE is 0, this control does not cause any instruction to be trapped. When HCR_EL2.TGE is 1, this control causes these instructions executed at EL0 to be trapped, but does not cause any instruction at EL2 to be trapped. |
0b10 |
This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules. |
0b11 |
This control does not cause any instruction to be trapped. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
CPTR_EL2 | 11 | 0001 | 100 | 010 | 0001 |
CPACR_EL1 | 11 | 0001 | 000 | 010 | 0000 |
The register is accessible as follows:
<systemreg> | Configuration | Accessibility | |||
---|---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | ||
CPTR_EL2 | SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | - | n/a | RW |
CPTR_EL2 | HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | - | RW | RW |
CPTR_EL2 | HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | RW | RW |
CPACR_EL1 | SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | CPACR_EL1 | n/a | CPACR_EL1 |
CPACR_EL1 | HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | CPACR_EL1 | CPACR_EL1 | CPACR_EL1 |
CPACR_EL1 | HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | CPACR_EL1 | CPACR_EL1 |
CPACR_EL1 | HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | CPACR_EL1 | RW | CPACR_EL1 |
CPACR_EL1 | HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | RW | CPACR_EL1 |
If an _EL1 accessor is used, refer to CPACR_EL1 for information on the effect of HCR_EL2.NV2 on this accessor.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If IsUsingAArch64(EL3) && CPTR_EL3.TCPAC == 1, then accesses at EL2 are trapped to EL3.
15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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