LDFF1W (vector plus immediate)

Gather load first-fault unsigned words to vector (immediate index).

Gather load with first-faulting behavior of unsigned words to active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive elements will not read Device memory or signal faults, and are set to zero in the destination vector.

It has encodings from 2 classes: 32-bit element and 64-bit element

32-bit element

313029282726252423222120191817161514131211109876543210
10000101001imm5111PgZnZt

32-bit element

LDFF1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer g = UInt(Pg); integer esize = 32; integer msize = 32; boolean unsigned = TRUE; integer offset = UInt(imm5);

64-bit element

313029282726252423222120191817161514131211109876543210
11000101001imm5111PgZnZt

64-bit element

LDFF1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer g = UInt(Pg); integer esize = 64; integer msize = 32; boolean unsigned = TRUE; integer offset = UInt(imm5);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<imm>

Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) base = Z[n]; bits(64) addr; bits(PL) mask = P[g]; bits(VL) result; bits(VL) orig = Z[t]; bits(msize) data; constant integer mbytes = msize DIV 8; boolean first = TRUE; boolean fault = FALSE; boolean faulted = FALSE; boolean unknown = FALSE; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then addr = ZeroExtend(Elem[base, e, esize], 64) + offset * mbytes; if first then // Mem[] will not return if a fault is detected for the first active element data = Mem[addr, mbytes, AccType_NORMAL]; first = FALSE; else // MemNF[] will return fault=TRUE if access is not performed for any reason (data, fault) = MemNF[addr, mbytes, AccType_NONFAULT]; else (data, fault) = (Zeros(msize), FALSE); // FFR elements set to FALSE following a supressed access/fault faulted = faulted || fault; if faulted then ElemFFR[e, esize] = '0'; // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE unknown = unknown || ElemFFR[e, esize] == '0'; if unknown then if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then Elem[result, e, esize] = Extend(data, esize, unsigned); elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then Elem[result, e, esize] = Zeros(); else // merge Elem[result, e, esize] = Elem[orig, e, esize]; else Elem[result, e, esize] = Extend(data, esize, unsigned); Z[t] = result;


Release: 00rel5-manual

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