CPACR_EL1, Architectural Feature Access Control Register

The CPACR_EL1 characteristics are:

Purpose

Controls access to trace, SVE, Advanced SIMD and floating-point functionality.

Configuration

AArch64 System register CPACR_EL1 bits [31:0] are architecturally mapped to AArch32 System register CPACR[31:0] .

When HCR_EL2.{E2H, TGE} == {1, 1}, the fields in this register have no effect on execution at EL0 and EL1. In this case, the controls provided by CPTR_EL2 are used.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CPACR_EL1 is a 64-bit register.

Field descriptions

The CPACR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000TTA000000FPEN00ZEN0000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:29]

Reserved, RES0.

TTA, bit [28]

Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states.

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

This control causes EL0 and EL1 System register accesses to all implemented trace registers to be trapped.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not implemented, this bit is RES0.

This field resets to an architecturally UNKNOWN value.

Bits [27:22]

Reserved, RES0.

FPEN, bits [21:20]

Traps EL0 and EL1 accesses to the SVE, Advanced SIMD, and floating-point registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states.

FPENMeaning
0b00

This control causes any instructions at EL0 or EL1 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPACR_EL1.ZEN.

0b01

This control causes any instructions at EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPACR_EL1.ZEN, but does not cause any instruction at EL1 to be trapped.

0b10

This control causes any instructions at EL0 or EL1 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPACR_EL1.ZEN.

0b11

This control does not cause any instructions to be trapped.

Writes to MVFR0, MVFR1 and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.

Note

This field resets to an architecturally UNKNOWN value.

Bits [19:18]

Reserved, RES0.

ZEN, bits [17:16]

When SVE is implemented:

Traps SVE instructions and instructions that access SVE System registers at EL0 and EL1 to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.

ZENMeaning
0b00

This control causes these instructions executed at EL0 or EL1 to be trapped.

0b01

This control causes these instructions executed at EL0 to be trapped, but does not cause any instruction at EL1 to be trapped.

0b10

This control causes these instructions executed at EL0 or EL1 to be trapped.

0b11

This control does not cause any instruction to be trapped.

If SVE is not implemented, this field is RES0.

This field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [15:0]

Reserved, RES0.

Accessing the CPACR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0CRnop1op2CRm
CPACR_EL11100010000100000
CPACR_EL121100011010100000

Accessibility

The register is accessible as follows:

<systemreg>ConfigurationAccessibility
EL0EL1EL2EL3
CPACR_EL1SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0-RWn/aRW
CPACR_EL1(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 0 || HCR_EL2.NV2 == 0) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-RWRWRW
CPACR_EL1HCR_EL2.NV == 1 && HCR_EL2.NV1 == 1 && HCR_EL2.NV2 == 1 && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-[VNCR_EL2.BADDR << 12 + 0x100]RWRW
CPACR_EL1HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aRWRW
CPACR_EL1(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 0 || HCR_EL2.NV2 == 0) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-RWCPTR_EL2RW
CPACR_EL1HCR_EL2.NV == 1 && HCR_EL2.NV1 == 1 && HCR_EL2.NV2 == 1 && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-[VNCR_EL2.BADDR << 12 + 0x100]CPTR_EL2RW
CPACR_EL1HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aCPTR_EL2RW
CPACR_EL12SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0--n/a-
CPACR_EL12(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 1 || HCR_EL2.NV2 == 0) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)----
CPACR_EL12HCR_EL2.NV == 1 && HCR_EL2.NV1 == 0 && HCR_EL2.NV2 == 1 && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-[VNCR_EL2.BADDR << 12 + 0x100]--
CPACR_EL12HCR_EL2.TGE == 1 && HCR_EL2.E2H == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/a--
CPACR_EL12(HCR_EL2.NV == 0 || HCR_EL2.NV1 == 1 || HCR_EL2.NV2 == 0) && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)--RWRW
CPACR_EL12HCR_EL2.NV == 1 && HCR_EL2.NV1 == 0 && HCR_EL2.NV2 == 1 && HCR_EL2.TGE == 0 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-[VNCR_EL2.BADDR << 12 + 0x100]RWRW
CPACR_EL12HCR_EL2.TGE == 1 && HCR_EL2.E2H == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aRWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CPACR_EL1 or CPACR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb

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