The ID_AA64ZFR0_EL1 characteristics are:
Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.
For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers
This register is present only when SVE is implemented. Otherwise, direct accesses to ID_AA64ZFR0_EL1 are RAZ.
ID_AA64ZFR0_EL1 is a 64-bit register.
The ID_AA64ZFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SVEver | |||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Scalable Vector Extension instruction set version. The defined values of this field are:
SVEver | Meaning |
---|---|
0b0000 |
SVE instructions are implemented. |
All other values are reserved. This field is only valid if the ID_AA64PFR0_EL1.SVE field is not zero.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
ID_AA64ZFR0_EL1 | 11 | 0000 | 000 | 100 | 0100 |
The register is accessible as follows:
Configuration | Accessibility | |||
---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | |
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | RO | n/a | RO |
HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | RO | RO | RO |
HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | RO | RO |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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