Move predicates (zeroing).
Read active elements from the source predicate and place in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
This is an alias of AND, ANDS (predicates). This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | 0 | 1 | Pg | 0 | Pn | 0 | Pd | ||||||||||||
S |
is equivalent to
AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pn>.B
and is the preferred disassembly when S == '0' && Pn == Pm.
<Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
<Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
<Pn> |
Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
The description of AND, ANDS (predicates) gives the operational pseudocode for this instruction.
Release: 00rel5-manual
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.