The HCR_EL2 characteristics are:
Provides configuration controls for virtualization, including defining whether various operations are trapped to EL2.
AArch64 System register HCR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HCR[31:0] .
AArch64 System register HCR_EL2 bits [63:32] are architecturally mapped to AArch32 System register HCR2[31:0] .
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
RW fields in this register reset to architecturally UNKNOWN values.
HCR_EL2 is a 64-bit register.
The HCR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FIEN | FWB | NV2 | AT | NV1 | NV | API | APK | 0 | MIOCNCE | TEA | TERR | TLOR | E2H | ID | CD |
RW | TRVM | HCD | TDZ | TGE | TVM | TTLB | TPU | TPCP | TSW | TACR | TIDCP | TSC | TID3 | TID2 | TID1 | TID0 | TWE | TWI | DC | BSU | FB | VSE | VI | VF | AMO | IMO | FMO | PTW | SWIO | VM | |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Fault Injection Enable. Unless this bit is set to 1, accesses to the ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1 registers from EL1 generate a Trap exception to EL2, when EL2 is enabled in the current Security state.
FIEN | Meaning |
---|---|
0b0 |
Accesses to the specified registers from EL1 are trapped to EL2, when EL2 is enabled in the current Security state. |
0b1 |
This control does not cause any instructions to be trapped. |
If EL2 is disabled in the current Security state, the Effective value of HCR_EL2.FIEN is 0b1.
If the RAS Common Fault Injection Model Extension is not implemented, this field is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Defines the combined cacheability attributes in a 2 stage translation regime.
FWB | Meaning |
---|---|
0b0 |
When this bit is 0, then:
|
0b1 |
When this bit is 1, then:
|
In Secure state, this bit applies to both the Secure stage 2 translation and the Non-secure stage 2 translation.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Nested Virtualization. Changes the behaviors of HCR_EL2.{NV, NV1} to provide a mechanism for hardware to transform reads and writes from System registers into reads and writes from memory.
NV2 | Meaning |
---|---|
0b0 |
This bit has no effect on the behavior of HCR_EL2.{NV, NV1}. |
0b1 |
Redefines behavior of HCR_EL2{NV, NV1} to enable:
|
When this bit is 0, the behavior of HCR_EL2.{NV, NV1} is as defined for ARMv8.3-NV.
When this is bit is 1, then any exception taken from EL1 and taken to EL1 causes SPSR_EL1.M[3:2] to be set to 0b10 and not 0b01
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Address Translation. EL1 execution of the following address translation instructions is trapped to EL2, when EL2 is enabled in the current Security state:
AT S1E0R, AT S1E0W, AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP
AT | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 execution of the specified instructions is trapped to EL2. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Nested Virtualization.
NV1 | Meaning |
---|---|
0b0 |
If HCR_EL2.{NV, NV2} are both 1, accesses executed from EL1 to implemented EL12, EL02, or EL2 registers are transformed to loads and stores. If HCR_EL2.NV2 is 0 or HCR_EL2.{NV, NV2} == {0, 1}, this control does not cause any instructions to be trapped. |
0b1 |
If HCR_EL2.NV2 is 1, accesses executed from EL1 to implemented EL2 registers are transformed to loads and stores. If HCR_EL2.NV2 is 0, EL1 accesses to VBAR_EL1, ELR_EL1, and SPSR_EL1, are trapped to EL2, when EL2 is enabled in the current Security state. |
If HCR_EL2.NV2 is 1, the value of HCR_EL2.NV1 defines which EL1 register accesses are transformed to loads and stores. These transformed accesses have priority over the trapping of registers.
The trapping of EL1 registers caused by other control bits has priority over the transformation of these accesses.
If a register is specified that is not implemented by an implementation, then access to that register is treated as unallocated.
For the list of registers affected, see Enhanced support for nested virtualization.
If HCR_EL2.{NV, NV1, NV2} are {1, 0, 0},any exception taken from EL1, and taken to EL1, causes the SPSR_EL1.M[3:2] to be set to 0b10, and not 0b01.
If HCR_EL2.{NV, NV1, NV2} are {1, 1, 0}, then:
If HCR_EL2.{NV, NV1, NV2} are {0, 1, 0}, then the behaviour is a CONSTRAINED UNPREDICTABLE choice of:
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Nested Virtualization. EL1 accesses to certain registers are trapped to EL2, when EL2 is enabled in the current Security state.
NV1 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to VBAR_EL1, ELR_EL1, SPSR_EL1 are trapped to EL2, when EL2 is enabled in the current Security state. |
If HCR_EL2.NV is 1 and HCR_EL2.NV1 is 0 then the following effects also apply:
If the bits HCR_EL2.NV and HCR_EL2.NV1 are both set to 1 then following effects also apply:
If HCR_EL2.NV is 0 and HCR_EL2.NV1 is 1 then the behaviour is a CONSTRAINED UNPREDICTABLE choice of:
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Nested Virtualization.
When HCR_EL2.NV2 is 1, redefines register accesses so that:
When HCR_EL2.NV2 is 0, or if ARMv8.4-NV is not implemented, traps functionality that is permitted at EL2 and would be UNDEFINED at EL1 if this field was 0, when EL2 is enabled in the current Security state. This applies to the following operations:
NV | Meaning |
---|---|
0b0 |
When this bit is set to 0, HCR_EL2.NV2 == 0 for all purposes other than reading this register. This control does not cause any instructions to be trapped. When HCR_EL2.NV2 is 1, no ARMv8.4-NV functionality is implemented. |
0b1 |
When HCR_EL2.NV2 is 0, or if ARMv8.4-NV is not implemented, EL1 accesses to the specified registers or the execution of the specified instructions are trapped to EL2, when EL2 is enabled in the current Security state. EL1 read accesses to the CurrentEL register return a value of 0x2. When HCR_EL2.NV2 is 1, this control redefines EL1 register accesses so that instructions accessing SPSR_EL2, ELR_EL2, ESR_EL2, and FAR_EL2 instead access SPSR_EL1, ELR_EL1, ESR_EL1, and FAR_EL1 respectively. |
When HCR_EL2.NV2 is 0, or if ARMv8.4-NV is not implemented, then:
The priority of this trap is higher than the priority of the HCR_EL2.API trap. If both of these bits are set so that EL1 execution of an ERETAA or ERETAB instruction is trapped to EL2, then the syndrome reported is 0x1A.
This field resets to an architecturally UNKNOWN value.
Nested Virtualization. Traps functionality that is permitted at EL2 and would be UNDEFINED at EL1 if this field was 0, when EL2 is enabled in the current Security state. This applies to the following operations:
The possible values are:
NV | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to the specified registers or the execution of the specified instructions are trapped to EL2, when EL2 is enabled in the current Security state. EL1 read accesses to the CurrentEL register return a value of 0x2. |
The System or Special-purpose registers for which accesses are trapped are as follows:
The instructions for which the execution is trapped are as follows:
The priority of this trap is higher than the priority of the HCR_EL2.API trap. If both of these bits are set so that EL1 execution of an ERETAA or ERETAB instruction is trapped to EL2, then the syndrome reported is 0x1A.
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Controls the use of instructions related to Pointer Authentication:
API | Meaning |
---|---|
0b0 |
The instructions related to Pointer Authentication are trapped to EL2, when EL2 is enabled in the current Security state and the instructions are enabled for the EL1&0 translation regime, from:
If HCR_EL2.NV is 1, the HCR_EL2.NV trap takes precedence over the HCR_EL2.API trap for the ERETAA and ERETAB instructions. |
0b1 |
This control does not cause any instructions to be trapped. |
If ARMv8.3-PAuth is implemented but EL2 is not implemented or disabled in the current Security state, the system behaves as if this bit is 1.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap registers holding "key" values for Pointer Authentication. Traps accesses to the following registers from EL1 to EL2, when EL2 is enabled in the current Security state:
APK | Meaning |
---|---|
0b0 |
Access to the registers holding "key" values for pointer authentication from EL1 are trapped to EL2, when EL2 is enabled in the current Security state. |
0b1 |
This control does not cause any instructions to be trapped. |
If ARMv8.3-PAuth is implemented but EL2 is not implemented or is disabled in the current Security state, the system behaves as if this bit is 1.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the EL1&0 translation regimes.
MIOCNCE | Meaning |
---|---|
0b0 |
For the EL1&0 translation regimes, for permitted accesses to a memory location that use a common definition of the Shareability and Cacheability of the location, there must be no loss of coherency if the Inner Cacheability attribute for those accesses differs from the Outer Cacheability attribute. |
0b1 |
For the EL1&0 translation regimes, for permitted accesses to a memory location that use a common definition of the Shareability and Cacheability of the location, there might be a loss of coherency if the Inner Cacheability attribute for those accesses differs from the Outer Cacheability attribute. |
For more information see 'Mismatched memory attributes' in the ARMv8 ARM, section B2 (The AArch64 Application Level Memory Model).
This field can be implemented as RAZ/WI.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Route synchronous External abort exceptions to EL2. If the RAS Extension is implemented, the possible values of this bit are:
TEA | Meaning |
---|---|
0b0 |
This control does not cause exceptions to be routed from EL0 and EL1 to EL2. |
0b1 |
Route synchronous External abort exceptions from EL0 and EL1 to EL2, when EL2 is enabled in the current Security state, if not routed to EL3. |
When the RAS Extension is not implemented, this field is RES0.
This field resets to an architecturally UNKNOWN value.
Trap Error record accesses. Trap accesses to the following registers from EL1 to EL2:
EL1 using AArch64: ERRIDR_EL1, ERRSELR_EL1, ERXADDR_EL1, ERXCTLR_EL1, ERXFR_EL1, ERXMISC0_EL1, ERXMISC1_EL1, and ERXSTATUS_EL1. When ARMv8.4-RAS is implemented, ERXMISC2_EL1, and ERXMISC3_EL1.
EL1 using AArch32: ERRIDR, ERRSELR, ERXADDR, ERXADDR2, ERXCTLR, ERXCTLR2, ERXFR, ERXFR2, ERXMISC0, ERXMISC1, ERXMISC2, ERXMISC3, and ERXSTATUS. When ARMv8.4-RAS is implemented, ERXMISC4, ERXMISC5, ERXMISC6, and ERXMISC7.
TERR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Accesses to the specified registers from EL1 generate a Trap exception to EL2, when EL2 is enabled in the current Security state. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap LOR registers. Traps accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from EL1 to EL2, when EL2 is enabled in the current Security state.
TLOR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to the LOR registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System's applications are running in EL0.
E2H | Meaning |
---|---|
0b0 |
The facilities to support a Host Operating System at EL2 are disabled. |
0b1 |
The facilities to support a Host Operating System at EL2 are enabled. |
For information on the behavior of this bit see Behavior of HCR_EL2.E2H.
This bit is permitted to be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Stage 2 Instruction access cacheability disable. For the EL1&0 translation regime, when EL2 is enabled in the current Security state and HCR_EL2.VM==1, this control forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable.
ID | Meaning |
---|---|
0b0 |
This control has no effect on stage 2 of the EL1&0 translation regime. |
0b1 |
Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable. |
This bit has no effect on the EL2, EL2&0, or EL3 translation regimes.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Stage 2 Data access cacheability disable. For the EL1&0 translation regime, when EL2 is enabled in the current Security state and HCR_EL2.VM==1, this control forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable.
CD | Meaning |
---|---|
0b0 |
This control has no effect on stage 2 of the EL1&0 translation regime for data accesses and translation table walks. |
0b1 |
Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable. |
This bit has no effect on the EL2, EL2&0, or EL3 translation regimes.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Execution state control for lower Exception levels:
RW | Meaning |
---|---|
0b0 |
Lower levels are all AArch32. |
0b1 |
The Execution state for EL1 is AArch64. The Execution state for EL0 is determined by the current value of PSTATE.nRW when executing at EL0. |
If all lower Exception levels cannot use AArch32 then this bit is RAO/WI.
In an implementation that includes EL3, when EL2 is not enabled in Secure state, the PE behaves as if this bit has the same value as the SCR_EL3.RW bit for all purposes other than a direct read or write access of HCR_EL2.
The RW bit is permitted to be cached in a TLB.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 1 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap Reads of Virtual Memory controls. Traps EL1 reads of the virtual memory control registers to EL2, when EL2 is enabled in the current Security state, from both Execution states. The registers for which read accesses are trapped are as follows:
EL1 using AArch64: SCTLR_EL1, TTBR0_EL1, TTBR1_EL1, TCR_EL1, ESR_EL1, FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1, CONTEXTIDR_EL1.
EL1 using AArch32: SCTLR, TTBR0, TTBR1, TTBCR, TTBCR2, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR, NMRR, MAIR0, MAIR1, AMAIR0, AMAIR1, CONTEXTIDR.
TRVM | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 read accesses to the specified Virtual Memory controls are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
HVC instruction disable. Disables EL1 execution of HVC instructions, from both Execution states, when EL2 is enabled in the current Security state.
HCD | Meaning |
---|---|
0b0 |
HVC instruction execution is enabled at EL2 and EL1. |
0b1 |
HVC instructions are UNDEFINED at EL2 and EL1. Any resulting exception is taken to the Exception level at which the HVC instruction is executed. |
HVC instructions are always UNDEFINED at EL0.
This bit is only implemented if EL3 is not implemented. Otherwise, it is RES0.
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap DC ZVA instructions. Traps EL0 and EL1 execution of DC ZVA instructions to EL2, when EL2 is enabled in the current Security state, from AArch64 state only.
TDZ | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
In AArch64 state, any attempt to execute an instruction this trap applies to at EL1, or at EL0 when the instruction is not UNDEFINED at EL0, is trapped to EL2 when EL2 is enabled in the current Security state. Reading the DCZID_EL0 returns a value that indicates that the instructions this trap applies to are not supported. |
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap General Exceptions, from EL0.
TGE | Meaning |
---|---|
0b0 |
This control has no effect on execution at EL0. |
0b1 |
When EL2 is not enabled in the current Security state, this control has no effect on execution at EL0. When EL2 is enabled in the current Security state, in all cases:
When EL2 is enabled in the current Security state and the value of HCR_EL2.E2H is 0, additionally:
For information on the behavior of this bit when E2H is 1, see Behavior of HCR_EL2.E2H. |
HCR_EL2.TGE must not be cached in a TLB.
This field resets to an architecturally UNKNOWN value.
Trap Virtual Memory controls. Traps EL1 writes to the virtual memory control registers to EL2, when EL2 is enabled in the current Security state, from both Execution states. The registers for which write accesses are trapped are as follows:
EL1 using AArch64: SCTLR_EL1, TTBR0_EL1, TTBR1_EL1, TCR_EL1, ESR_EL1, FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1, CONTEXTIDR_EL1.
EL1 using AArch32: SCTLR, TTBR0, TTBR1, TTBCR, TTBCR2, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR, NMRR, MAIR0, MAIR1, AMAIR0, AMAIR1, CONTEXTIDR.
TVM | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 write accesses to the specified EL1 virtual memory control registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap TLB maintenance instructions. Traps EL1 execution of TLB maintenance instructions to EL2, when EL2 is enabled in the current Security state, from both Execution states. This applies to the following instructions:
TTLB | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 execution of the specified TLB maintenance instructions are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap TLB maintenance instructions. Traps EL1 execution of TLB maintenance instructions to EL2, when EL2 is enabled in the current Security state, from both Execution states. This applies to the following instructions:
TTLB | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 execution of the specified TLB maintenance instructions are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trap cache maintenance instructions that operate to the Point of Unification. Traps execution of those cache maintenance instructions at EL1 or EL0 using AArch64, and at EL1 using AArch32, to EL2 when EL2 is enabled in the current Security state. This applies to the following instructions:
An exception generated because an instruction is UNDEFINED at EL0 is higher priority than this trap to EL2. In addition:
TPU | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Execution of the specified instructions is trapped to EL2, when EL2 is enabled in the current Security state. |
If the Point of Unification is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean by VA to the Point of Unification instruction can be trapped when the value of this control is 1.
If the Point of Unification is before any level of instruction cache, it is IMPLEMENTATION DEFINED whether the execution of any instruction cache invalidate to the Point of Unification instruction can be trapped when the value of this control is 1.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap data or unified cache maintenance instructions that operate to the Point of Coherency or Persistence. Traps execution of those cache maintenance instructions at EL1 or EL0 using AArch64, and at EL1 using AArch32, to EL2 when EL2 is enabled in the current Security state. This applies to the following instructions:
TPCP | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Execution of the specified instructions is trapped to EL2, when EL2 is enabled in the current Security state. |
If the Point of Coherency is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean, invalidate, or clean and invalidate instruction that operates by VA to the point of coherency can be trapped when the value of this control is 1.
If HCR_EL2.{E2H, TGE} is set to {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap data or unified cache maintenance instructions that operate to the Point of Coherency. Traps execution of those cache maintenance instructions at EL1 or EL0 using AArch64, and at EL1 using AArch32, to EL2 when EL2 is enabled in the current Security state. This applies to the following instructions:
TPC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Execution of the specified instructions is trapped to EL2, when EL2 is enabled in the current Security state. |
If the Point of Coherency is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean, invalidate, or clean and invalidate instruction that operates by VA to the point of coherency can be trapped when the value of this control is 1.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap data or unified cache maintenance instructions that operate by Set/Way. Traps execution of those cache maintenance instructions at EL1 using AArch64, and at EL1 using AArch32, to EL2 when EL2 is enabled in the current Security state. This applies to the following instructions:
An exception generated because an instruction is UNDEFINED at EL0 is higher priority than this trap to EL2, and these instructions are always UNDEFINED at EL0.
TSW | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Execution of the specified instructions is trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap Auxiliary Control Registers. Traps EL1 accesses to the Auxiliary Control Registers to EL2, when EL2 is enabled in the current Security state, from both Execution states. This applies to the following register accesses:
TACR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to the specified registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap IMPLEMENTATION DEFINED functionality. Traps EL1 accesses to the encodings reserved for IMPLEMENTATION DEFINED functionality to EL2, when EL2 is enabled in the current Security state. This applies to the following register accesses:
AArch64: The following reserved encoding spaces:
AArch32: MCR and MRC instructions accessing the following encodings:
When the value of HCR_EL2.TIDCP is 1, it is IMPLEMENTATION DEFINED whether any of this functionality accessed from EL0 is trapped to EL2. If it is not, then it is UNDEFINED, and any attempt to access it from EL0 generates an exception that is taken to EL1.
TIDCP | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
EL1 accesses to or execution of the specified encodings reserved for IMPLEMENTATION DEFINED functionality are trapped to EL2, when EL2 is enabled in the current Security state. |
This field resets to an architecturally UNKNOWN value.
Trap SMC instructions. Traps EL1 execution of SMC instructions to EL2, when EL2 is enabled in the current Security state, from both Execution states.
TSC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
If EL3 is implemented, then any attempt to execute an SMC instruction at EL1 using AArch64 or EL1 using AArch32 is trapped to EL2, when EL2 is enabled in the current Security state, regardless of the value of SCR_EL3.SMD. If EL3 is not implemented, ARMv8.3-NV is implemented, and HCR_EL2.NV is 1, then any attempt to execute an SMC instruction at EL1 using AArch64 is trapped to EL2, when EL2 is enabled in the current Security state. |
In AArch32 state, the ARMv8-A architecture permits, but does not require, this trap to apply to conditional SMC instructions that fail their condition code check, in the same way as with traps on other conditional instructions.
If EL3 is not implemented, and HCR_EL2.NV is 0, this bit is RES0.
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap ID group 3. Traps EL1 reads of the following registers to EL2, when EL2 is enabled in the current Security state:
AArch64: ID_PFR0_EL1, ID_PFR1_EL1, ID_DFR0_EL1, ID_AFR0_EL1, ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, ID_ISAR6_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1, ID_AA64PFR0_EL1, ID_AA64PFR1_EL1, ID_AA64DFR0_EL1, ID_AA64DFR1_EL1, ID_AA64ISAR0_EL1, ID_AA64ISAR1_EL1, ID_AA64MMFR0_EL1, ID_AA64MMFR1_EL1, ID_AA64MMFR2_EL1, ID_AA64AFR0_EL1, ID_AA64AFR1_EL1, ID_AA64ZFR0_EL1 (where SVE is implemented), and ID_MMFR4_EL1, except that if ID_MMFR4_EL1 is implemented as RAZ/WI then it is IMPLEMENTATION DEFINED whether accesses to ID_MMFR4_EL1 are trapped.
It is IMPLEMENTATION DEFINED whether this field traps MRS accesses to encodings in the following range that are not already mentioned in this field description:
AArch32: ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0, ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, MVFR2, and ID_MMFR4, except that if ID_MMFR4 is implemented as RAZ/WI then it is IMPLEMENTATION DEFINED whether accesses to ID_MMFR4 are trapped.
MRC access to any of the following encodings are also trapped:
It is IMPLEMENTATION DEFINED whether this bit traps MRC accesses to the following encodings:
TID3 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
The specified EL1 read accesses to ID group 3 registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap ID group 2. Traps the following register accesses to EL2, when EL2 is enabled in the current Security state:
AArch64:
AArch32:
TID2 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
The specified EL1 and EL0 accesses to ID group 2 registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Trap ID group 1. Traps EL1 reads of the following registers to EL2, when EL2 is enabled in the current Security state:
AArch64: REVIDR_EL1, AIDR_EL1.
AArch32: TCMTR, TLBTR, REVIDR, AIDR.
TID1 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
The specified EL1 read accesses to ID group 1 registers are trapped to EL2, when EL2 is enabled in the current Security state. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Trap ID group 0. Traps the following register accesses to EL2:
AArch64: None.
AArch32:
TID0 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
The specified EL1 read accesses to ID group 0 registers are trapped to EL2, when EL2 is enabled in the current Security state. |
In an AArch64 only implementation, this bit is RES0.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Traps EL0 and EL1 execution of WFE instructions to EL2, when EL2 is enabled in the current Security state, from both Execution states.
TWE | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt to execute a WFE instruction at EL0 or EL1 is trapped to EL2, when EL2 is enabled in the current Security state, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWE or SCTLR_EL1.nTWE. |
In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.
Since a WFE can complete at any time, even without a Wakeup event, the traps on WFE are not guaranteed to be taken, even if the WFE is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Traps EL0 and EL1 execution of WFI instructions to EL2, when EL2 is enabled in the current Security state, from both Execution states.
TWI | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Any attempt to execute a WFI instruction at EL0 or EL1 is trapped to EL2, when EL2 is enabled in the current Security state, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWI or SCTLR_EL1.nTWI. |
In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.
Since a WFI can complete at any time, even without a Wakeup event, the traps on WFI are not guaranteed to be taken, even if the WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Default Cacheability.
DC | Meaning |
---|---|
0b0 |
This control has no effect on the EL1&0 translation regime. |
0b1 |
In both Security states:
|
This field has no effect on the EL2, EL2&0, and EL3 translation regimes.
This field is permitted to be cached in a TLB.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this field.
This field resets to an architecturally UNKNOWN value.
Barrier Shareability upgrade. This field determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0:
BSU | Meaning |
---|---|
0b00 |
No effect. |
0b01 |
Inner Shareable. |
0b10 |
Outer Shareable. |
0b11 |
Full system. |
This value is combined with the specified level of the barrier held in its instruction, using the same principles as combining the shareability attributes from two stages of address translation.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0b00 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
Force broadcast. Causes the following instructions to be broadcast within the Inner Shareable domain when executed from EL1:
AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, ICIALLU, TLBIMVAL, TLBIMVAAL.
AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1, TLBI VALE1, TLBI VAALE1, IC IALLU, TLBI RVAE1, TLBI RVAAE1, TLBI RVALE1, TLBI RVAALE1.
FB | Meaning |
---|---|
0b0 |
This field has no effect on the operation of the specified instructions. |
0b1 |
When one of the specified instruction is executed at EL1, the instruction is broadcast within the Inner Shareable shareability domain. |
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Virtual SError interrupt.
VSE | Meaning |
---|---|
0b0 |
This mechanism is not making a virtual SError interrupt pending. |
0b1 |
A virtual SError interrupt is pending because of this mechanism. |
The virtual SError interrupt is only enabled when the value of HCR_EL2.{TGE, AMO} is {0, 1}.
This field resets to an architecturally UNKNOWN value.
Virtual IRQ Interrupt.
VI | Meaning |
---|---|
0b0 |
This mechanism is not making a virtual IRQ pending. |
0b1 |
A virtual IRQ is pending because of this mechanism. |
The virtual IRQ is enabled only when the value of HCR_EL2.{TGE, IMO} is {0, 1}.
This field resets to an architecturally UNKNOWN value.
Virtual FIQ Interrupt.
VF | Meaning |
---|---|
0b0 |
This mechanism is not making a virtual FIQ pending. |
0b1 |
A virtual FIQ is pending because of this mechanism. |
The virtual FIQ is enabled only when the value of HCR_EL2.{TGE, FMO} is {0, 1}.
This field resets to an architecturally UNKNOWN value.
Physical SError interrupt routing.
AMO | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL2, and EL2 is enabled in the current Security state: |
0b1 |
When executing at any Exception level, and EL2 is enabled in the current Security state:
|
If EL2 is enabled in the current Security state and the value of HCR_EL2.TGE is 1:
For more information, see 'Asynchronous exception routing' in the ARMv8 ARM, section D1 (The AArch64 System Level Programmers' Model).
This field resets to an architecturally UNKNOWN value.
Physical IRQ Routing.
IMO | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL2, and EL2 is enabled in the current Security state: |
0b1 |
When executing at any Exception level, and EL2 is enabled in the current Security state:
|
If EL2 is enabled in the current Security state, and the value of HCR_EL2.TGE is 1:
For more information, see 'Asynchronous exception routing' in the ARMv8 ARM, section D1.
This field resets to an architecturally UNKNOWN value.
Physical FIQ Routing.
FMO | Meaning |
---|---|
0b0 |
When executing at Exception levels below EL2, and EL2 is enabled in the current Security state: |
0b1 |
When executing at any Exception level, and EL2 is enabled in the current Security state:
|
If EL2 is enabled in the current Security state and the value of HCR_EL2.TGE is 1:
For more information, see 'Asynchronous exception routing' in the ARMv8 ARM, section D1.
This field resets to an architecturally UNKNOWN value.
Protected Table Walk. In the EL1&0 translation regime, a translation table access made as part of a stage 1 translation table walk is subject to a stage 2 translation. The combining of the memory type attributes from the two stages of translation means the access might be made to a type of Device memory. If this occurs, then the value of this bit determines the behavior:
PTW | Meaning |
---|---|
0b0 |
The translation table walk occurs as if it is to Normal Non-cacheable memory. This means it can be made speculatively. |
0b1 |
The memory access generates a stage 2 Permission fault. |
This field is permitted to be cached in a TLB.
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Set/Way Invalidation Override. Causes EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way:
SWIO | Meaning |
---|---|
0b0 |
This control has no effect on the operation of data cache invalidate by set/way instructions. |
0b1 |
Data cache invalidate by set/way instructions perform a data cache clean and invalidate by set/way. |
When the value of this bit is 1:
AArch32: DCISW performs the same invalidation as a DCCISW instruction.
AArch64: DC ISW performs the same invalidation as a DC CISW instruction.
This bit can be implemented as RES1.
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
This field resets to an architecturally UNKNOWN value.
Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime, when EL2 is enabled in the current Security state.
VM | Meaning |
---|---|
0b0 |
EL1&0 stage 2 address translation disabled. |
0b1 |
EL1&0 stage 2 address translation enabled. |
When the value of this bit is 1, data cache invalidate instructions executed at EL1 perform a data cache clean and invalidate. For the invalidate by set/way instruction this behavior applies regardless of the value of the HCR_EL2.SWIO bit.
This bit is permitted to be cached in a TLB.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This field resets to an architecturally UNKNOWN value.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
HCR_EL2 | 11 | 0001 | 100 | 000 | 0001 |
The register is accessible as follows:
Configuration | Accessibility | |||
---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | |
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | - | n/a | RW |
(HCR_EL2.NV == 0 || HCR_EL2.NV2 == 0) && HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | - | RW | RW |
HCR_EL2.NV == 1 && HCR_EL2.NV2 == 1 && HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | [VNCR_EL2.BADDR << 12 + 0x78] | RW | RW |
HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | RW | RW |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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