Copy general-purpose register to vector elements (predicated).
Copy the general-purpose scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.
This instruction is used by the alias MOV (scalar, predicated) . The alias is always the preferred disassembly.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | Pg | Rn | Zd |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Rn); integer d = UInt(Zd);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<R> |
Is a width specifier,
encoded in
size:
|
<n|SP> |
Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(64) operand1; if n == 31 then operand1 = SP[]; else operand1 = X[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = operand1<esize-1:0>; Z[d] = result;
Release: 00rel5-manual
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