ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

The ID_AA64PFR0_EL1 characteristics are:

Purpose

Provides additional information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D10.4.1.

Configuration

The external register EDPFR gives information from this register.

Attributes

ID_AA64PFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64PFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
000000000000DITAMUMPAMSEL2SVE
RASGICAdvSIMDFPEL3EL2EL1EL0
313029282726252423222120191817161514131211109876543210

Bits [63:52]

Reserved, RES0.

DIT, bits [51:48]

From ARMv8.4:

Data Independent Timing. Defined values are:

DITMeaning
0b0000

AArch64 does not guarantee constant execution time of any instructions.

0b0001

AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions.

All other values are reserved.

ARMv8.4-DIT implements the functionality identified by the value 0b0001.

From ARMv8.4, the only permitted value is 0b0001.


Otherwise:

Reserved, RES0.

AMU, bits [47:44]

From ARMv8.4:

Activity Monitors Extension. Defined values are:

AMUMeaning
0b0000

Activity Monitors Extension is not implemented.

0b0001

Activity Monitors Extension Version 1 is implemented.

All other values are reserved.

AMUv1 implements the functionality identified by the value 0b0001.

In ARMv8.0, ARMv8.1, ARMv8.2, and ARMv8.3, the only permitted value is 0b0000.

From ARMv8.4, the permitted values are 0b0000 and 0b0001.


Otherwise:

Reserved, RES0.

MPAM, bits [43:40]

From ARMv8.2, or if ARMv8.3 or ARMv8.4:

MPAM Extension. Defined values are:

MPAMMeaning
0b0000

MPAM is not implemented.

0b0001

MPAM is implemented.

All other values are reserved.


Otherwise:

Reserved, RES0.

SEL2, bits [39:36]

From ARMv8.4:

Secure EL2. Defined values are:

SEL2Meaning
0b0000

Secure EL2 is not implemented.

0b0001

Secure EL2 is implemented.

All other values are reserved.


Otherwise:

Reserved, RES0.

SVE, bits [35:32]

From ARMv8.2:

Scalable Vector Extension. Defined values are:

SVEMeaning
0b0000

SVE architectural state and programmers' model are not implemented.

0b0001

SVE architectural state and programmers' model are implemented.

All other values are reserved.


Otherwise:

Reserved, RES0.

RAS, bits [31:28]

RAS Extension version. The defined values of this field are:

RASMeaning
0b0000

No RAS Extension.

0b0001

RAS Extension present.

0b0010

ARMv8.4-RAS present. As 0b0001, and adds support for:

  • If EL3 is implemented, ARMv8.4-DFE.
  • Additional ERXMISC<m>_EL1 System registers.
  • Additional System registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1, and the SCR_EL3.FIEN and HCR_EL2.FIEN trap controls, to support the optional RAS Common Fault Injection Model Extension.

Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions.

All other values are reserved.

From ARMv8.4, the only permitted value is 0b0010.

ARMv8.4-RAS implements the functionality identified by the value 0b0010.

In ARMv8.2, the only permitted value is 0b0001.

In ARMv8.1 and ARMv8.0, the permitted values are 0b0000 and 0b0001.

GIC, bits [27:24]

System register GIC interface support. Defined values are:

GICMeaning
0b0000

No System register interface to the GIC is supported.

0b0001

System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.

All other values are reserved.

AdvSIMD, bits [23:20]

Advanced SIMD. Defined values are:

AdvSIMDMeaning
0b0000

Advanced SIMD is implemented, including support for the following SISD and SIMD operations:

  • Integer byte, halfword, word and doubleword element operations.

  • Single-precision and double-precision floating-point arithmetic.

  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.

0b0001

As for 0b0000, and also includes support for half-precision floating-point arithmetic.

0b1111

Advanced SIMD is not implemented.

All other values are reserved.

This field must have the same value as the FP field.

The permitted values are:

FP, bits [19:16]

Floating-point. Defined values are:

FPMeaning
0b0000

Floating-point is implemented, and includes support for:

  • Single-precision and double-precision floating-point types.

  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.

0b0001

As for 0b0000, and also includes support for half-precision floating-point arithmetic.

0b1111

Floating-point is not implemented.

All other values are reserved.

This field must have the same value as the AdvSIMD field.

The permitted values are:

EL3, bits [15:12]

EL3 Exception level handling. Defined values are:

EL3Meaning
0b0000

EL3 is not implemented.

0b0001

EL3 can be executed in AArch64 state only.

0b0010

EL3 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL2, bits [11:8]

EL2 Exception level handling. Defined values are:

EL2Meaning
0b0000

EL2 is not implemented.

0b0001

EL2 can be executed in AArch64 state only.

0b0010

EL2 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL1, bits [7:4]

EL1 Exception level handling. Defined values are:

EL1Meaning
0b0001

EL1 can be executed in AArch64 state only.

0b0010

EL1 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL0, bits [3:0]

EL0 Exception level handling. Defined values are:

EL0Meaning
0b0001

EL0 can be executed in AArch64 state only.

0b0010

EL0 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

Accessing the ID_AA64PFR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0CRnop1op2CRm
ID_AA64PFR0_EL11100000000000100

Accessibility

The register is accessible as follows:

ConfigurationAccessibility
EL0EL1EL2EL3
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0-ROn/aRO
HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-RORORO
HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1)-n/aRORO

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




15/10/2018 19:25; 79a37e9f651257790ccdbbdd2c8c3713837d12fb

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