LD1RH

Load and broadcast unsigned halfword to vector.

Load a single unsigned halfword from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 2 in the range 0 to 126.

Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.

It has encodings from 3 classes: 16-bit element , 32-bit element and 64-bit element

16-bit element

313029282726252423222120191817161514131211109876543210
1000010011imm6101PgRnZt

16-bit element

LD1RH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 16; integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

32-bit element

313029282726252423222120191817161514131211109876543210
1000010011imm6110PgRnZt

32-bit element

LD1RH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 32; integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

64-bit element

313029282726252423222120191817161514131211109876543210
1000010011imm6111PgRnZt

64-bit element

LD1RH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 64; integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; integer last = LastActiveElement(mask, esize); if last >= 0 then addr = base + offset * mbytes; data = Mem[addr, mbytes, AccType_NORMAL]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(); Z[t] = result;


Release: 00rel5-manual

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