Unsigned saturating increment vector by active predicate element count.
Counts the number of active elements in the source predicate and then uses the result to increment all destination vector elements. The results are saturated to the element unsigned integer range.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Pg | Zdn |
if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Zdn); boolean unsigned = TRUE;
<Zdn> |
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[dn]; bits(VL) result; integer count = 0; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then count = count + 1; for e = 0 to elements-1 integer element = Int(Elem[operand, e, esize], unsigned); (Elem[result, e, esize], -) = SatQ(element + count, esize, unsigned); Z[dn] = result;
Release: 00rel5-manual
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.