Below are indexes for registers and operations accessed in the following ways:
For AArch64
Register selectors | Name | Description | ||||
---|---|---|---|---|---|---|
op0 | op1 | CRn | CRm | op2 | ||
11 | 000 | 0000 | 0100 | 000 | ID_AA64PFR0_EL1 | AArch64 Processor Feature Register 0 |
11 | 000 | 0000 | 0100 | 100 | ID_AA64ZFR0_EL1 | SVE Feature ID register 0 |
11 | 000 | 0001 | 0000 | 010 | CPACR_EL1 | Architectural Feature Access Control Register |
11 | 000 | 0001 | 0010 | 000 | ZCR_EL1 | SVE Control Register for EL1 |
11 | 000 | 0010 | 0000 | 010 | TCR_EL1 | Translation Control Register (EL1) |
11 | 000 | 0101 | 0010 | 000 | ESR_EL1 | Exception Syndrome Register (EL1) |
11 | 100 | 0001 | 0001 | 000 | HCR_EL2 | Hypervisor Configuration Register |
11 | 100 | 0001 | 0001 | 010 | CPTR_EL2 | Architectural Feature Trap Register (EL2) |
11 | 100 | 0001 | 0010 | 000 | ZCR_EL2 | SVE Control Register for EL2 |
11 | 100 | 0010 | 0000 | 010 | TCR_EL2 | Translation Control Register (EL2) |
11 | 100 | 0101 | 0010 | 000 | ESR_EL2 | Exception Syndrome Register (EL2) |
11 | 110 | 0001 | 0001 | 010 | CPTR_EL3 | Architectural Feature Trap Register (EL3) |
11 | 110 | 0001 | 0010 | 000 | ZCR_EL3 | SVE Control Register for EL3 |
11 | 110 | 0101 | 0010 | 000 | ESR_EL3 | Exception Syndrome Register (EL3) |
15/10/2018 19:26
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