The ID_AA64PFR0_EL1 characteristics are:
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D10.4.1.
The external register EDPFR gives information from this register.
ID_AA64PFR0_EL1 is a 64-bit register.
The ID_AA64PFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIT | AMU | MPAM | SEL2 | SVE | |||||||||||||||
RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Data Independent Timing. Defined values are:
DIT | Meaning |
---|---|
0b0000 |
AArch64 does not guarantee constant execution time of any instructions. |
0b0001 |
AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions. |
All other values are reserved.
ARMv8.4-DIT implements the functionality identified by the value 0b0001.
From ARMv8.4, the only permitted value is 0b0001.
Reserved, RES0.
Activity Monitors Extension. Defined values are:
AMU | Meaning |
---|---|
0b0000 |
Activity Monitors Extension is not implemented. |
0b0001 |
Activity Monitors Extension Version 1 is implemented. |
All other values are reserved.
AMUv1 implements the functionality identified by the value 0b0001.
In ARMv8.0, ARMv8.1, ARMv8.2, and ARMv8.3, the only permitted value is 0b0000.
From ARMv8.4, the permitted values are 0b0000 and 0b0001.
Reserved, RES0.
MPAM Extension. Defined values are:
MPAM | Meaning |
---|---|
0b0000 |
MPAM is not implemented. |
0b0001 |
MPAM is implemented. |
All other values are reserved.
Reserved, RES0.
Secure EL2. Defined values are:
SEL2 | Meaning |
---|---|
0b0000 |
Secure EL2 is not implemented. |
0b0001 |
Secure EL2 is implemented. |
All other values are reserved.
Reserved, RES0.
Scalable Vector Extension. Defined values are:
SVE | Meaning |
---|---|
0b0000 |
SVE architectural state and programmers' model are not implemented. |
0b0001 |
SVE architectural state and programmers' model are implemented. |
All other values are reserved.
Reserved, RES0.
RAS Extension version. The defined values of this field are:
RAS | Meaning |
---|---|
0b0000 |
No RAS Extension. |
0b0001 |
RAS Extension present. |
0b0010 |
ARMv8.4-RAS present. As 0b0001, and adds support for:
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions. |
All other values are reserved.
From ARMv8.4, the only permitted value is 0b0010.
ARMv8.4-RAS implements the functionality identified by the value 0b0010.
In ARMv8.2, the only permitted value is 0b0001.
In ARMv8.1 and ARMv8.0, the permitted values are 0b0000 and 0b0001.
System register GIC interface support. Defined values are:
GIC | Meaning |
---|---|
0b0000 |
No System register interface to the GIC is supported. |
0b0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
All other values are reserved.
Advanced SIMD. Defined values are:
AdvSIMD | Meaning |
---|---|
0b0000 |
Advanced SIMD is implemented, including support for the following SISD and SIMD operations:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Advanced SIMD is not implemented. |
All other values are reserved.
This field must have the same value as the FP field.
The permitted values are:
Floating-point. Defined values are:
FP | Meaning |
---|---|
0b0000 |
Floating-point is implemented, and includes support for:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Floating-point is not implemented. |
All other values are reserved.
This field must have the same value as the AdvSIMD field.
The permitted values are:
EL3 Exception level handling. Defined values are:
EL3 | Meaning |
---|---|
0b0000 |
EL3 is not implemented. |
0b0001 |
EL3 can be executed in AArch64 state only. |
0b0010 |
EL3 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL2 Exception level handling. Defined values are:
EL2 | Meaning |
---|---|
0b0000 |
EL2 is not implemented. |
0b0001 |
EL2 can be executed in AArch64 state only. |
0b0010 |
EL2 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL1 Exception level handling. Defined values are:
EL1 | Meaning |
---|---|
0b0001 |
EL1 can be executed in AArch64 state only. |
0b0010 |
EL1 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL0 Exception level handling. Defined values are:
EL0 | Meaning |
---|---|
0b0001 |
EL0 can be executed in AArch64 state only. |
0b0010 |
EL0 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
ID_AA64PFR0_EL1 | 11 | 0000 | 000 | 000 | 0100 |
The register is accessible as follows:
Configuration | Accessibility | |||
---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | |
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | RO | n/a | RO |
HCR_EL2.TGE == 0 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | RO | RO | RO |
HCR_EL2.TGE == 1 && (SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) | - | n/a | RO | RO |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
15/10/2018 19:25; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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