Interleave even or odd elements from two vectors.
Interleave alternating even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated.
It has encodings from 2 classes: Even and Odd
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 1 | 1 | 1 | 0 | 0 | Zn | Zd |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer part = 0;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 1 | 1 | 1 | 0 | 1 | Zn | Zd |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer part = 1;
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); integer pairs = VL DIV (esize * 2); bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for p = 0 to pairs-1 Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize]; Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize]; Z[d] = result;
Release: 00rel5-manual
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