ST1W (scalar plus scalar)

Contiguous store words from vector (scalar index).

Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 4 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.

313029282726252423222120191817161514131211109876543210
111001010sizeRm010PgRnZt

SVE

ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

if !HaveSVE() then UNDEFINED; if size != '1x' then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 8 << UInt(size); integer msize = 32;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; bits(64) offset = X[m]; bits(VL) src = Z[t]; constant integer mbytes = msize DIV 8; if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; for e = 0 to elements-1 addr = base + UInt(offset) * mbytes; if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>; offset = offset + 1;


Release: 00rel5-manual

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