NAND, NANDS

Bitwise NAND predicates.

Bitwise NAND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Optionally sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

It has encodings from 2 classes: Flag setting and Not flag setting

Flag setting

313029282726252423222120191817161514131211109876543210
001001011100Pm01Pg1Pn1Pd

Flag setting

NANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

if !HaveSVE() then UNDEFINED; integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); boolean setflags = TRUE;

Not flag setting

313029282726252423222120191817161514131211109876543210
001001011000Pm01Pg1Pn1Pd

Not flag setting

NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

if !HaveSVE() then UNDEFINED; integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); boolean setflags = FALSE;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(PL) operand1 = P[n]; bits(PL) operand2 = P[m]; bits(PL) result; for e = 0 to elements-1 bit element1 = ElemP[operand1, e, esize]; bit element2 = ElemP[operand2, e, esize]; if ElemP[mask, e, esize] == '1' then ElemP[result, e, esize] = NOT(element1 AND element2); else ElemP[result, e, esize] = '0'; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d] = result;


Release: 00rel5-manual

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