Bitwise OR vectors (unpredicated).
Bitwise inclusive OR all elements of the second source vector with corresponding elements of the first source vector and place the first in the corresponding elements of the destination vector. This instruction is unpredicated.
This instruction is used by the alias MOV (vector, unpredicated) . See Alias Conditions below for details of when the alias is preferred.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 0 | 0 | 1 | 1 | 0 | 0 | Zn | Zd |
if !HaveSVE() then UNDEFINED; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
Alias | Is preferred when |
---|---|
MOV (vector, unpredicated) | Zn == Zm |
CheckSVEEnabled(); bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; Z[d] = operand1 OR operand2;
Release: 00rel5-manual
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