The ZCR_EL3 characteristics are:
The SVE Control Register for EL3 is used to control aspects of SVE visible at all Exception levels.
This register is present only when SVE is implemented. Otherwise, direct accesses to ZCR_EL3 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
ZCR_EL3 is a 64-bit register.
The ZCR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LEN | |||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RAZ/WI.
Constrains the scalable vector register length for all Exception levels to (LEN+1)x128 bits. For all purposes other than returning the result of a direct read of ZCR_EL3 then this field behaves as if rounded down to the nearest implemented vector length.
An indirect read of ZCR_EL3.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.
This field resets to an architecturally UNKNOWN value.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | CRn | op1 | op2 | CRm |
---|---|---|---|---|---|
ZCR_EL3 | 11 | 0001 | 110 | 000 | 0010 |
The register is accessible as follows:
Configuration | Accessibility | |||
---|---|---|---|---|
EL0 | EL1 | EL2 | EL3 | |
SCR_EL3.NS == 0 && SCR_EL3.EEL2 == 0 | - | - | n/a | RW |
(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 0 | - | - | - | RW |
(SCR_EL3.NS == 1 || SCR_EL3.EEL2 == 1) && HCR_EL2.TGE == 1 | - | n/a | - | RW |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If CPTR_EL3.EZ == 0b0, then accesses at EL3 are trapped to EL3.
15/10/2018 19:26; 79a37e9f651257790ccdbbdd2c8c3713837d12fb
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