SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#2.0.

Where:

<const> Is the floating-point immediate value, encoded in i1:
i1 <const>
0 #0.5
1 #2.0

SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.5 and 1->#1.0.

Where:

<const> Is the floating-point immediate value, encoded in i1:
i1 <const>
0 #0.5
1 #1.0

SVE floating-point arithmetic with immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point arithmetic with immediate (predicated)<const>

Original text: Is the floating-point immediate value, encoded in the "i1" field, where 0->#0.0 and 1->#1.0.

Where:

<const> Is the floating-point immediate value, encoded in i1:
i1 <const>
0 #0.0
1 #1.0

SVE floating-point compare with zero<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point serial reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point serial reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 RESERVED
01 H
10 S
11 D

SVE floating-point round to integral value<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point unary operations<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point arithmetic (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point reciprocal estimate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point multiply-accumulate writing addend<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point multiply-accumulate writing multiplicand<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point arithmetic (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point recursive reduction<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point recursive reduction<V>

Original text: Is a width specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 RESERVED
01 H
10 S
11 D

SVE floating-point complex add (predicated)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 0->#90 and 1->#270.

Where:

<const> Is the const specifier, encoded in rot:
rot <const>
0 #90
1 #270

SVE floating-point complex add (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point complex multiply-add (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point complex multiply-add (predicated)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.

Where:

<const> Is the const specifier, encoded in rot:
rot <const>
00 #0
01 #90
10 #180
11 #270

SVE floating-point complex multiply-add (indexed)<const>

Original text: Is the const specifier, encoded in the "rot" field, where 00->#0, 01->#90, 10->#180 and 11->#270.

Where:

<const> Is the const specifier, encoded in rot:
rot <const>
00 #0
01 #90
10 #180
11 #270

SVE floating-point trig multiply-add coefficient<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE integer add/subtract immediate (unpredicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

Where:

<shift> Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in sh:
sh <shift>
0 LSL #0
1 LSL #8

SVE integer add/subtract immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer min/max immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer multiply immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer add/subtract vectors (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE address generation<amount>

Original text: Is the index shift amount, encoded in "msz", where 00->[absent], 01->#1, 10->#2 and 11->#3.

Where:

<amount> Is the index shift amount, encoded in msz:
msz <amount>
00 [absent]
01 #1
10 #2
11 #3

SVE address generation<mod>

Original text: Is the index extend and shift specifier, encoded in "msz", where 00->[absent], 10->LSL and x1->LSL.

Where:

<mod> Is the index extend and shift specifier, encoded in msz:
msz <mod>
00 [absent]
x1 LSL
10 LSL

SVE address generation<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in sz:
sz <T>
0 S
1 D

SVE floating-point trig select coefficient<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE floating-point exponential accelerator<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE bitwise shift by wide elements (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 RESERVED

SVE bitwise shift by immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.

Where:

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
00 00 RESERVED
00 01 B
00 1x H
01 xx S
1x xx D

SVE integer add/subtract vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer min/max/difference (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer multiply vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer divide vectors (predicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE bitwise logical operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE bitwise shift by immediate (predicated)<T>

Original text: Is the size specifier, encoded in "tszh:tszl", where 0000->RESERVED, 0001->B, 001x->H, 01xx->S and 1xxx->D.

Where:

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
00 00 RESERVED
00 01 B
00 1x H
01 xx S
1x xx D

SVE bitwise shift by vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE bitwise shift by wide elements (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 RESERVED

SVE partition break condition<ZM>

Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.

Where:

<ZM> Is the predication qualifier, encoded in M:
M <ZM>
0 Z
1 M

SVE integer compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer compare vectors<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 RESERVED

SVE integer compare with wide elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 RESERVED

SVE element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE inc/dec register by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE saturating inc/dec register by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE inc/dec vector by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE saturating inc/dec vector by predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE saturating inc/dec vector by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE inc/dec vector by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE conditionally terminate scalars<R>

Original text: Is a width specifier, encoded in "sz", where 0->W and 1->X.

Where:

<R> Is a width specifier, encoded in sz:
sz <R>
0 W
1 X

SVE broadcast floating-point immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE copy floating-point immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE broadcast integer immediate (unpredicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

Where:

<shift> Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in sh:
sh <shift>
0 LSL #0
1 LSL #8

SVE broadcast integer immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE broadcast integer immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE copy integer immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE copy integer immediate (predicated)<shift>

Original text: Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in "sh", where 0->LSL #0 and 1->LSL #8.

Where:

<shift> Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in sh:
sh <shift>
0 LSL #0
1 LSL #8

SVE copy integer immediate (predicated)<ZM>

Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.

Where:

<ZM> Is the predication qualifier, encoded in M:
M <ZM>
0 Z
1 M

SVE copy integer immediate (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE broadcast bitmask immediate<T>

Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.

Where:

<T> Is the size specifier, encoded in imm13<12>:imm13<5:0>:
imm13<12> imm13<5:0> <T>
0 0xxxxx S
0 10xxxx H
0 110xxx B
0 1110xx B
0 11110x B
0 111110 RESERVED
0 111111 RESERVED
1 xxxxxx D

SVE index generation (immediate start, immediate increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE index generation (immediate start, register increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE index generation (immediate start, register increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE index generation (register start, immediate increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE index generation (register start, immediate increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE index generation (register start, register increment)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE index generation (register start, register increment)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE bitwise logical with immediate (unpredicated)<T>

Original text: Is the size specifier, encoded in "imm13<12>:imm13<5:0>", where 0111111->RESERVED, 0111110->RESERVED, 011110x->B, 01110xx->B, 0110xxx->B, 010xxxx->H, 00xxxxx->S and 1xxxxxx->D.

Where:

<T> Is the size specifier, encoded in imm13<12>:imm13<5:0>:
imm13<12> imm13<5:0> <T>
0 0xxxxx S
0 10xxxx H
0 110xxx B
0 1110xx B
0 11110x B
0 111110 RESERVED
0 111111 RESERVED
1 xxxxxx D

SVE integer multiply-add writing multiplicand (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer multiply-accumulate writing addend (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE constructive prefix (predicated)<ZM>

Original text: Is the predication qualifier, encoded in "M", where 0->Z and 1->M.

Where:

<ZM> Is the predication qualifier, encoded in M:
M <ZM>
0 Z
1 M

SVE constructive prefix (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE predicate count<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE permute predicate elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE permute vector elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE conditionally extract element to general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE conditionally extract element to general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE conditionally extract element to SIMD&FP scalar<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE conditionally extract element to SIMD&FP scalar<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE conditionally broadcast element to vector<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE compress active elements<T>

Original text: Is the size specifier, encoded in "sz", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in sz:
sz <T>
0 S
1 D

SVE copy general register to vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE copy general register to vector (predicated)<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE copy SIMD&FP scalar register to vector (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE copy SIMD&FP scalar register to vector (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE broadcast indexed element<V>

Original text: Is a width specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.

Where:

<V> Is a width specifier, encoded in tsz:
tsz <V>
00000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
10000 Q

SVE broadcast indexed element<T>

Original text: Is the size specifier, encoded in "tsz", where 00000->RESERVED, 10000->Q, x1000->D, xx100->S, xxx10->H and xxxx1->B.

Where:

<T> Is the size specifier, encoded in tsz:
tsz <T>
00000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
10000 Q

SVE broadcast general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE broadcast general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE insert general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE insert general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE insert SIMD&FP scalar register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE insert SIMD&FP scalar register<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE extract element to general register<R>

Original text: Is a width specifier, encoded in "size", where 01->W, 11->X and x0->W.

Where:

<R> Is a width specifier, encoded in size:
size <R>
01 W
x0 W
11 X

SVE extract element to general register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE extract element to SIMD&FP scalar register<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE extract element to SIMD&FP scalar register<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE reverse within elements<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE reverse within elements<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE reverse within elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE reverse predicate elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE reverse vector elements<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE vector splice (destructive)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE table lookup<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE unpack vector elements<Tb>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->B, 10->H and 11->S.

Where:

<Tb> Is the size specifier, encoded in size:
size <Tb>
00 RESERVED
01 B
10 H
11 S

SVE unpack vector elements<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE predicate next active<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE inc/dec register by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE saturating inc/dec register by element count<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE predicate initialize<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE predicate initialize<pattern>

Original text: Is the optional pattern specifier, defaulting to ALL, encoded in the "pattern" field, where 00000->POW2, 00001->VL1, 00010->VL2, 00011->VL3, 00100->VL4, 00101->VL5, 00110->VL6, 00111->VL7, 01000->VL8, 01001->VL16, 01010->VL32, 01011->VL64, 01100->VL128, 01101->VL256, 0111x->#uimm5, 10110->#uimm5, 101x1->#uimm5, 11101->MUL4, 11110->MUL3, 11111->ALL, 1x010->#uimm5, 1x0x1->#uimm5 and 1xx00->#uimm5.

Where:

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL

SVE integer add reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->RESERVED.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 RESERVED

SVE integer add reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer min/max reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer min/max reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE bitwise logical reduction (predicated)<V>

Original text: Is a width specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<V> Is a width specifier, encoded in size:
size <V>
00 B
01 H
10 S
11 D

SVE bitwise logical reduction (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer compare with signed immediate<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE select vector elements (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer compare with unsigned immediate<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE integer unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE bitwise unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE bitwise unary operations (predicated)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE integer compare scalar count and limit<R>

Original text: Is a width specifier, encoded in "sf", where 0->W and 1->X.

Where:

<R> Is a width specifier, encoded in sf:
sf <R>
0 W
1 X

SVE integer compare scalar count and limit<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE integer dot product (unpredicated)<Tb>

Original text: Is the size specifier, encoded in "size<0>", where 0->B and 1->H.

Where:

<Tb> Is the size specifier, encoded in size<0>:
size<0> <Tb>
0 B
1 H

SVE integer dot product (unpredicated)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit gather prefetch (vector plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE 64-bit gather prefetch (vector plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE contiguous store (scalar plus immediate)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "size", where 00->RESERVED, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 RESERVED
01 H
10 S
11 D

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "size<0>", where 0->S and 1->D.

Where:

<T> Is the size specifier, encoded in size<0>:
size<0> <T>
0 S
1 D

SVE contiguous store (scalar plus scalar)<T>

Original text: Is the size specifier, encoded in "size", where 00->B, 01->H, 10->S and 11->D.

Where:

<T> Is the size specifier, encoded in size:
size <T>
00 B
01 H
10 S
11 D

SVE contiguous prefetch (scalar plus immediate)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE contiguous prefetch (scalar plus scalar)<prfop>

Original text: Is the prefetch operation specifier, encoded in "prfop", where 0000->PLDL1KEEP, 0001->PLDL1STRM, 0010->PLDL2KEEP, 0011->PLDL2STRM, 0100->PLDL3KEEP, 0101->PLDL3STRM, 1000->PSTL1KEEP, 1001->PSTL1STRM, 1010->PSTL2KEEP, 1011->PSTL2STRM, 1100->PSTL3KEEP, 1101->PSTL3STRM and x11x->#uimm4.

Where:

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop <prfop>
0000 PLDL1KEEP
0001 PLDL1STRM
0010 PLDL2KEEP
0011 PLDL2STRM
0100 PLDL3KEEP
0101 PLDL3STRM
x11x #uimm4
1000 PSTL1KEEP
1001 PSTL1STRM
1010 PSTL2KEEP
1011 PSTL2STRM
1100 PSTL3KEEP
1101 PSTL3STRM

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)<mod>

Original text: Is the index extend and shift specifier, encoded in "xs", where 0->UXTW and 1->SXTW.

Where:

<mod> Is the index extend and shift specifier, encoded in xs:
xs <mod>
0 UXTW
1 SXTW

Release: 00rel5-manual

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