AESD

AES single round decryption.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size00Vd001101M0Vm

A1

AESD.<dt> <Qd>, <Qm>

if ! HaveCryptoExt() then UNDEFINED; if size != '00' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm);

T1

15141312111098765432101514131211109876543210
111111111D11size00Vd001101M0Vm

T1

AESD.<dt> <Qd>, <Qm>

if InITBlock() then UNPREDICTABLE; if ! HaveCryptoExt() then UNDEFINED; if size != '00' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm);

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<dt> Is the data type, encoded in size:
size <dt>
00 8
01 RESERVED
1x RESERVED
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckCryptoEnabled32(); op1 = Q[d>>1]; op2 = Q[m>>1]; Q[d>>1] = AESInvSubBytes(AESInvShiftRows(op1 EOR op2));


Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43

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