Load Multiple (exception return) loads multiple registers from consecutive memory locations using an address from a base register. The SPSR of the current mode is copied to the CPSR. An address adjusted by the size of the data loaded can optionally be written back to the base register.
The registers loaded include the PC. The word loaded for the PC is treated as an address and a branch occurs to that address.
Load Multiple (exception return) is:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 0 | 0 | P | U | 1 | W | 1 | Rn | 1 | register_list | ||||||||||||||||||||
cond |
n = UInt(Rn); registers = register_list; wback = (W == '1'); increment = (U == '1'); wordhigher = (P == U); if n == 15 then UNPREDICTABLE; if wback && registers<n> == '1' then UNPREDICTABLE;
If wback && registers<n> == '1', then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
! |
The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0. |
Instructions with similar syntax but without the PC included in the registers list are described in LDM (User registers).
if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; // UNDEFINED or NOP else length = 4*BitCount(registers) + 4; address = if increment then R[n] else R[n]-length; if wordhigher then address = address+4; for i = 0 to 14 if registers<i> == '1' then R[i] = MemA[address,4]; address = address + 4; new_pc_value = MemA[address,4]; if wback && registers<n> == '0' then R[n] = if increment then R[n]+length else R[n]-length; if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; AArch32.ExceptionReturn(new_pc_value, SPSR[]);
If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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