Store multiple single elements from one, two, three, or four registers stores elements to memory from one, two, three, or four registers, without interleaving. Every element of each register is stored. For details of the addressing mode see Advanced SIMD addressing mode.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 , A2 , A3 and A4 ) and T32 ( T1 , T2 , T3 and T4 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 0 | 1 | 1 | 1 | size | align | Rm |
regs = 1; if align<1> == '1' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
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1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 1 | 0 | 1 | 0 | size | align | Rm |
regs = 2; if align == '11' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
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1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 0 | 1 | 1 | 0 | size | align | Rm |
regs = 3; if align<1> == '1' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
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1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 0 | 0 | 1 | 0 | size | align | Rm |
regs = 4; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 0 | 1 | 1 | 1 | size | align | Rm |
regs = 1; if align<1> == '1' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 1 | 0 | 1 | 0 | size | align | Rm |
regs = 2; if align == '11' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 0 | 1 | 1 | 0 | size | align | Rm |
regs = 3; if align<1> == '1' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
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1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 0 | 0 | 1 | 0 | size | align | Rm |
regs = 4; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST1 (multiple single elements).
Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.
<c> |
For encoding A1, A2, A3 and A4: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding T1, T2, T3 and T4: see Standard assembler syntax fields. |
<q> |
<size> |
Is the data size,
encoded in
size:
|
<Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
<Rm> |
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field. |
For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode.
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; iswrite = TRUE; - = AArch32.CheckAlignment(address, alignment, AccType_VEC, iswrite); for r = 0 to regs-1 for e = 0 to elements-1 if ebytes != 8 then MemU[address,ebytes] = Elem[D[d+r],e]; else - = AArch32.CheckAlignment(address, ebytes, AccType_NORMAL, iswrite); bits(64) data = Elem[D[d+r],e]; MemU[address,4] = if BigEndian() then data<63:32> else data<31:0>; MemU[address+4,4] = if BigEndian() then data<31:0> else data<63:32>; address = address + ebytes; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 8*regs;
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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