Pop Multiple Registers from Stack loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data.
This is an alias of LDM, LDMIA, LDMFD. This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | register_list | ||||||||||||||||||
cond | W | Rn |
POP{<c>}{<q>} <registers>
is equivalent to
LDM{<c>}{<q>} SP!, <registers>
and is the preferred disassembly when BitCount(register_list) > 1.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | P | M | (0) | register_list | ||||||||||||
W | Rn | register_list<13> |
POP{<c>}.W <registers> // (All registers in R0-R7, PC)
POP{<c>}{<q>} <registers>
is equivalent to
LDM{<c>}{<q>} SP!, <registers>
and is the preferred disassembly when BitCount(P:M:register_list) > 1.
<c> |
<q> |
The description of LDM, LDMIA, LDMFD gives the operational pseudocode for this instruction.
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
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