Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be accomodated as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | 0 | 0 | 1 | Vd | 1 | 0 | 1 | 1 | 1 | 1 | M | 0 | Vm | |||||||||
cond |
if !HaveFJCVTZSExt() then UNDEFINED; if cond != '1110' then UNPREDICTABLE; d = UInt(Vd:D); m = UInt(M:Vm);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | 0 | 0 | 1 | Vd | 1 | 0 | 1 | 1 | 1 | 1 | M | 0 | Vm |
if !HaveFJCVTZSExt() then UNDEFINED; if InITBlock() then UNPREDICTABLE; d = UInt(Vd:D); m = UInt(M:Vm);
<q> |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
EncodingSpecificOperations(); CheckVFPEnabled(TRUE); bits(64) fltval = D[m]; bits(32) intval = FPToFixedJS(fltval, FPSCR, FALSE); S[d] = intval;
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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