Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register.
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 and T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | (0) | (0) | (0) | (0) | Rd | imm5 | 1 | 0 | 0 | Rm | |||||||||||||
cond | S | type |
ASR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 0 | imm5 | Rm | Rd | ||||||||
op |
ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> // (Inside IT block)
is equivalent to
MOV<c>{<q>} <Rd>, <Rm>, ASR #<imm>
and is the preferred disassembly when InITBlock().
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 1 | 0 | Rm | |||||||||
S | type |
ASR<c>.W {<Rd>,} <Rm>, #<imm> // (Inside IT block, and <Rd>, <Rm>, <imm> can be represented in T2)
ASR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>
and is always the preferred disassembly.
<c> |
<q> |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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