1 | 2 | 3 | 4 | A | B | C | D | E | F | G | H | I | J | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z |
VLD1 (single element to all lanes): Load single
VLD1 (single element to one lane): Load single
1-element structure to one lane of one register.
VLD1 (multiple single elements): Load multiple single
1-element structures to one, two, three, or four registers.
VLD2 (single 2-element structure to all lanes): Load single
VST2 (single 2-element structure from one lane): Store single
2-element structure from one lane of two registers.
2-element structure from one lane): Store single 2-element structure from one lane of two registers.
2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.
VLD2 (single 2-element structure to one lane): Load single
2-element structure to one lane of two registers.
2-element structure to one lane): Load single 2-element structure to one lane of two registers.
VST2 (multiple 2-element structures): Store multiple
2-element structures from two or four registers.
VLD2 (multiple 2-element structures): Load multiple
2-element structures to two or four registers.
2-element structures): Load multiple 2-element structures to two or four registers.
2-element structures): Store multiple 2-element structures from two or four registers.
VLD3 (single 3-element structure to all lanes): Load single
VST3 (single 3-element structure from one lane): Store single
3-element structure from one lane of three registers.
3-element structure from one lane): Store single 3-element structure from one lane of three registers.
3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.
VLD3 (single 3-element structure to one lane): Load single
3-element structure to one lane of three registers.
3-element structure to one lane): Load single 3-element structure to one lane of three registers.
VST3 (multiple 3-element structures): Store multiple
3-element structures from three registers.
VLD3 (multiple 3-element structures): Load multiple
3-element structures to three registers.
3-element structures): Load multiple 3-element structures to three registers.
3-element structures): Store multiple 3-element structures from three registers.
VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a
32-bit SIMD&FP register.
VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a
32-bit SIMD&FP register.
VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of
32-bit SIMD&FP registers.
VLD4 (single 4-element structure to all lanes): Load single
VST4 (single 4-element structure from one lane): Store single
4-element structure from one lane of four registers.
4-element structure from one lane): Store single 4-element structure from one lane of four registers.
4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.
VLD4 (single 4-element structure to one lane): Load single
4-element structure to one lane of four registers.
4-element structure to one lane): Load single 4-element structure to one lane of four registers.
VST4 (multiple 4-element structures): Store multiple
4-element structures from four registers.
VLD4 (multiple 4-element structures): Load multiple
4-element structures to four registers.
4-element structures): Load multiple 4-element structures to four registers.
4-element structures): Store multiple 4-element structures from four registers.
VACGT: Vector
Absolute Compare Greater Than.
VACLE: Vector
Absolute Compare Less Than or Equal: an alias of VACGE.
VACLT: Vector
Absolute Compare Less Than: an alias of VACGT.
VABD (floating-point): Vector
Absolute Difference (floating-point).
VABD (integer): Vector
Absolute Difference (integer).
VABAL: Vector
Absolute Difference and Accumulate Long.
VABA: Vector
Absolute Difference and Accumulate.
VABDL (integer): Vector
Absolute Difference Long (integer).
USADA8: Unsigned Sum of
Absolute Differences and Accumulate.
USAD8: Unsigned Sum of
Absolute Differences.
VABS: Vector
Absolute.
VQABS: Vector Saturating
Absolute.
SETPAN: Set Privileged
Access Never.
VCMLA (by element): Vector Complex Multiply
Accumulate (by element).
VMLA (by scalar): Vector Multiply
Accumulate (by scalar).
VMLA (floating-point): Vector Multiply
Accumulate (floating-point).
SMLABB, SMLABT, SMLATB, SMLATT: Signed Multiply
Accumulate (halfwords).
VMLA (integer): Vector Multiply
Accumulate (integer).
SMLAWB, SMLAWT: Signed Multiply
Accumulate (word by halfword).
UMAAL: Unsigned Multiply
Accumulate Accumulate Long.
SMLAD, SMLADX: Signed Multiply
Accumulate Dual.
VMLAL (by scalar): Vector Multiply
Accumulate Long (by scalar).
SMLALBB, SMLALBT, SMLALTB, SMLALTT: Signed Multiply
Accumulate Long (halfwords).
VMLAL (integer): Vector Multiply
Accumulate Long (integer).
SMLALD, SMLALDX: Signed Multiply
Accumulate Long Dual.
SMLAL, SMLALS: Signed Multiply
Accumulate Long.
UMAAL: Unsigned Multiply Accumulate
Accumulate Long.
UMLAL, UMLALS: Unsigned Multiply
Accumulate Long.
VABAL: Vector Absolute Difference and
Accumulate Long.
VPADAL: Vector Pairwise Add and
Accumulate Long.
VQDMLAL: Vector Saturating Doubling Multiply
Accumulate Long.
VQRDMLAH: Vector Saturating Rounding Doubling Multiply
Accumulate Returning High Half.
MLA, MLAS: Multiply
Accumulate.
SMMLA, SMMLAR: Signed Most Significant Word Multiply
Accumulate.
USADA8: Unsigned Sum of Absolute Differences and
Accumulate.
VABA: Vector Absolute Difference and
Accumulate.
VCMLA: Vector Complex Multiply
Accumulate.
VFMA: Vector Fused Multiply
Accumulate.
VFNMA: Vector Fused Negate Multiply
Accumulate.
VNMLA: Vector Negate Multiply
Accumulate.
VRSRA: Vector Rounding Shift Right and
Accumulate.
VSRA: Vector Shift Right and
Accumulate.
VFMAL (by scalar): Vector Floating-point Multiply-Add Long to
accumulator (by scalar).
VFMSL (by scalar): Vector Floating-point Multiply-Subtract Long from
accumulator (by scalar).
VFMAL (vector): Vector Floating-point Multiply-Add Long to
accumulator (vector).
VFMSL (vector): Vector Floating-point Multiply-Subtract Long from
accumulator (vector).
LDAB: Load-
Acquire Byte.
LDAEXB: Load-
Acquire Exclusive Byte.
LDAEXD: Load-
Acquire Exclusive Doubleword.
LDAEXH: Load-
Acquire Exclusive Halfword.
LDAEX: Load-
Acquire Exclusive Word.
LDAH: Load-
Acquire Halfword.
LDA: Load-
Acquire Word.
ADC, ADCS (immediate): Add with Carry (immediate).
ADC, ADCS (register): Add with Carry (register).
ADC, ADCS (register-shifted register): Add with Carry (register-shifted register).
ADCS (immediate): Add with Carry (immediate).
ADCS (register): Add with Carry (register).
ADCS (register-shifted register): Add with Carry (register-shifted register).
VADD (floating-point): Vector
Add (floating-point).
VPADD (floating-point): Vector Pairwise
Add (floating-point).
Add (immediate).
ADD (immediate, to PC): Add to PC: an alias of ADR.
VADD (integer): Vector
Add (integer).
VPADD (integer): Vector Pairwise
Add (integer).
Add (register).
Add (register-shifted register).
QADD16: Saturating
Add 16.
SADD16: Signed
Add 16.
SHADD16: Signed Halving
Add 16.
UADD16: Unsigned
Add 16.
UHADD16: Unsigned Halving
Add 16.
UQADD16: Unsigned Saturating
Add 16.
QADD8: Saturating
Add 8.
SADD8: Signed
Add 8.
SHADD8: Signed Halving
Add 8.
UADD8: Unsigned
Add 8.
UHADD8: Unsigned Halving
Add 8.
UQADD8: Unsigned Saturating
Add 8.
VPADAL: Vector Pairwise
Add and Accumulate Long.
VADDHN: Vector
Add and Narrow, returning High Half.
VRADDHN: Vector Rounding
Add and Narrow, returning High Half.
QASX: Saturating
Add and Subtract with Exchange.
SASX: Signed
Add and Subtract with Exchange.
SHASX: Signed Halving
Add and Subtract with Exchange.
UASX: Unsigned
Add and Subtract with Exchange.
UHASX: Unsigned Halving
Add and Subtract with Exchange.
UQASX: Unsigned Saturating
Add and Subtract with Exchange.
SXTAB16: Signed Extend and
Add Byte 16.
UXTAB16: Unsigned Extend and
Add Byte 16.
SXTAB: Signed Extend and
Add Byte.
UXTAB: Unsigned Extend and
Add Byte.
SXTAH: Signed Extend and
Add Halfword.
UXTAH: Unsigned Extend and
Add Halfword.
VFMAL (by scalar): Vector Floating-point Multiply-
Add Long to accumulator (by scalar).
VFMAL (vector): Vector Floating-point Multiply-
Add Long to accumulator (vector).
VADDL: Vector
Add Long.
VPADDL: Vector Pairwise
Add Long.
Add to PC: an alias of ADR.
Add to SP (immediate).
Add to SP (register).
VADDW: Vector
Add Wide.
Add with Carry (immediate).
Add with Carry (register).
Add with Carry (register-shifted register).
QSAX: Saturating Subtract and
Add with Exchange.
SHSAX: Signed Halving Subtract and
Add with Exchange.
SSAX: Signed Subtract and
Add with Exchange.
UHSAX: Unsigned Halving Subtract and
Add with Exchange.
UQSAX: Unsigned Saturating Subtract and
Add with Exchange.
USAX: Unsigned Subtract and
Add with Exchange.
ADD, ADDS (immediate): Add (immediate).
ADD, ADDS (register): Add (register).
ADD, ADDS (register-shifted register): Add (register-shifted register).
ADD, ADDS (SP plus immediate): Add to SP (immediate).
ADD, ADDS (SP plus register): Add to SP (register).
QADD: Saturating
Add.
QDADD: Saturating Double and
Add.
SMUAD, SMUADX: Signed Dual Multiply
Add.
VCADD: Vector Complex
Add.
VHADD: Vector Halving
Add.
VQADD: Vector Saturating
Add.
VRHADD: Vector Rounding Halving
Add.
ADR: Form PC-relative
address.
ADDS (immediate): Add (immediate).
ADDS (register): Add (register).
ADDS (register-shifted register): Add (register-shifted register).
ADDS (SP plus immediate): Add to SP (immediate).
ADDS (SP plus register): Add to SP (register).
ADD (immediate, to PC): Add to PC: an alias of
ADR.
SUB (immediate, from PC): Subtract from PC: an alias of
ADR.
ADR: Form PC-relative address.
Advanced SIMD): Vector Convert between floating-point and fixed-point.
Advanced SIMD): Vector Convert between floating-point and integer.
Advanced SIMD): Vector Convert between half-precision and single-precision.
Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to Away.
Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest.
Advanced SIMD): Vector Convert floating-point to integer with Round towards +Infinity.
Advanced SIMD): Vector Convert floating-point to integer with Round towards -Infinity.
Advanced SIMD): Vector round floating-point to integer inexact.
Advanced SIMD): Vector Round floating-point to integer to Nearest.
Advanced SIMD): Vector Round floating-point to integer towards +Infinity.
Advanced SIMD): Vector Round floating-point to integer towards -Infinity.
Advanced SIMD): Vector Round floating-point to integer towards Nearest with Ties to Away.
Advanced SIMD): Vector round floating-point to integer towards Zero.
AES inverse mix columns.
AES mix columns.
AESD:
AES single round decryption.
AESE:
AES single round encryption.
AESD: AES single round decryption.
AESE: AES single round encryption.
AESIMC: AES inverse mix columns.
AESMC: AES mix columns.
STMDA, STMED: Store Multiple Decrement
After (Empty Descending).
LDMDA, LDMFA: Load Multiple Decrement
After (Full Ascending).
STM, STMIA, STMEA: Store Multiple (Increment
After, Empty Ascending).
LDM, LDMIA, LDMFD: Load Multiple (Increment
After, Full Descending).
ADD (immediate, to PC): Add to PC: an
alias of ADR.
SUB (immediate, from PC): Subtract from PC: an
alias of ADR.
POP (multiple registers): Pop Multiple Registers from Stack: an
alias of LDM, LDMIA, LDMFD.
POP (single register): Pop Single Register from Stack: an
alias of LDR (immediate).
ASR (immediate): Arithmetic Shift Right (immediate): an
alias of MOV, MOVS (register).
ASRS (immediate): Arithmetic Shift Right, setting flags (immediate): an
alias of MOV, MOVS (register).
LSL (immediate): Logical Shift Left (immediate): an
alias of MOV, MOVS (register).
LSLS (immediate): Logical Shift Left, setting flags (immediate): an
alias of MOV, MOVS (register).
LSR (immediate): Logical Shift Right (immediate): an
alias of MOV, MOVS (register).
LSRS (immediate): Logical Shift Right, setting flags (immediate): an
alias of MOV, MOVS (register).
ROR (immediate): Rotate Right (immediate): an
alias of MOV, MOVS (register).
RORS (immediate): Rotate Right, setting flags (immediate): an
alias of MOV, MOVS (register).
RRX: Rotate Right with Extend: an
alias of MOV, MOVS (register).
RRXS: Rotate Right with Extend, setting flags: an
alias of MOV, MOVS (register).
ASR (register): Arithmetic Shift Right (register): an
alias of MOV, MOVS (register-shifted register).
ASRS (register): Arithmetic Shift Right, setting flags (register): an
alias of MOV, MOVS (register-shifted register).
LSL (register): Logical Shift Left (register): an
alias of MOV, MOVS (register-shifted register).
LSLS (register): Logical Shift Left, setting flags (register): an
alias of MOV, MOVS (register-shifted register).
LSR (register): Logical Shift Right (register): an
alias of MOV, MOVS (register-shifted register).
LSRS (register): Logical Shift Right, setting flags (register): an
alias of MOV, MOVS (register-shifted register).
ROR (register): Rotate Right (register): an
alias of MOV, MOVS (register-shifted register).
RORS (register): Rotate Right, setting flags (register): an
alias of MOV, MOVS (register-shifted register).
PUSH (multiple registers): Push multiple registers to Stack: an
alias of STMDB, STMFD.
PUSH (single register): Push Single Register to Stack: an
alias of STR (immediate).
VACLE: Vector Absolute Compare Less Than or Equal: an
alias of VACGE.
VACLT: Vector Absolute Compare Less Than: an
alias of VACGT.
VAND (immediate): Vector Bitwise AND (immediate): an
alias of VBIC (immediate).
VCLE (register): Vector Compare Less Than or Equal: an
alias of VCGE (register).
VCLT (register): Vector Compare Less Than: an
alias of VCGT (register).
VEXT (multibyte elements): Vector Extract: an
alias of VEXT (byte elements).
VPOP: Pop SIMD&FP registers from Stack: an
alias of VLDM, VLDMDB, VLDMIA.
VRSHRN (zero): Vector Rounding Shift Right and Narrow: an
alias of VMOVN.
VSHRN (zero): Vector Shift Right Narrow: an
alias of VMOVN.
VORN (immediate): Vector Bitwise OR NOT (immediate): an
alias of VORR (immediate).
VMOV (register, SIMD): Copy between SIMD registers: an
alias of VORR (register).
VRSHR (zero): Vector Rounding Shift Right: an
alias of VORR (register).
VSHR (zero): Vector Shift Right: an
alias of VORR (register).
VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an
alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an
alias of VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating Shift Right, Narrow: an
alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an
alias of VQMOVN, VQMOVUN.
VPUSH: Push SIMD&FP registers to Stack: an
alias of VSTM, VSTMDB, VSTMIA.
VUZP (alias): Vector Unzip: an
alias of VTRN.
VZIP (alias): Vector Zip: an
alias of VTRN.
VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to
all lanes of four registers.
VLD1 (single element to all lanes): Load single 1-element structure and replicate to
all lanes of one register.
VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to
all lanes of three registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to
all lanes of two registers.
all lanes): Load single 1-element structure and replicate to all lanes of one register.
all lanes): Load single 2-element structure and replicate to all lanes of two registers.
all lanes): Load single 3-element structure and replicate to all lanes of three registers.
all lanes): Load single 4-element structure and replicate to all lanes of four registers.
ADD (immediate, to PC): Add to PC:
an alias of ADR.
SUB (immediate, from PC): Subtract from PC:
an alias of ADR.
POP (multiple registers): Pop Multiple Registers from Stack:
an alias of LDM, LDMIA, LDMFD.
POP (single register): Pop Single Register from Stack:
an alias of LDR (immediate).
ASR (immediate): Arithmetic Shift Right (immediate):
an alias of MOV, MOVS (register).
ASRS (immediate): Arithmetic Shift Right, setting flags (immediate):
an alias of MOV, MOVS (register).
LSL (immediate): Logical Shift Left (immediate):
an alias of MOV, MOVS (register).
LSLS (immediate): Logical Shift Left, setting flags (immediate):
an alias of MOV, MOVS (register).
LSR (immediate): Logical Shift Right (immediate):
an alias of MOV, MOVS (register).
LSRS (immediate): Logical Shift Right, setting flags (immediate):
an alias of MOV, MOVS (register).
ROR (immediate): Rotate Right (immediate):
an alias of MOV, MOVS (register).
RORS (immediate): Rotate Right, setting flags (immediate):
an alias of MOV, MOVS (register).
RRX: Rotate Right with Extend:
an alias of MOV, MOVS (register).
RRXS: Rotate Right with Extend, setting flags:
an alias of MOV, MOVS (register).
ASR (register): Arithmetic Shift Right (register):
an alias of MOV, MOVS (register-shifted register).
ASRS (register): Arithmetic Shift Right, setting flags (register):
an alias of MOV, MOVS (register-shifted register).
LSL (register): Logical Shift Left (register):
an alias of MOV, MOVS (register-shifted register).
LSLS (register): Logical Shift Left, setting flags (register):
an alias of MOV, MOVS (register-shifted register).
LSR (register): Logical Shift Right (register):
an alias of MOV, MOVS (register-shifted register).
LSRS (register): Logical Shift Right, setting flags (register):
an alias of MOV, MOVS (register-shifted register).
ROR (register): Rotate Right (register):
an alias of MOV, MOVS (register-shifted register).
RORS (register): Rotate Right, setting flags (register):
an alias of MOV, MOVS (register-shifted register).
PUSH (multiple registers): Push multiple registers to Stack:
an alias of STMDB, STMFD.
PUSH (single register): Push Single Register to Stack:
an alias of STR (immediate).
VACLE: Vector Absolute Compare Less Than or Equal:
an alias of VACGE.
VACLT: Vector Absolute Compare Less Than:
an alias of VACGT.
VAND (immediate): Vector Bitwise AND (immediate):
an alias of VBIC (immediate).
VCLE (register): Vector Compare Less Than or Equal:
an alias of VCGE (register).
VCLT (register): Vector Compare Less Than:
an alias of VCGT (register).
VEXT (multibyte elements): Vector Extract:
an alias of VEXT (byte elements).
VPOP: Pop SIMD&FP registers from Stack:
an alias of VLDM, VLDMDB, VLDMIA.
VRSHRN (zero): Vector Rounding Shift Right and Narrow:
an alias of VMOVN.
VSHRN (zero): Vector Shift Right Narrow:
an alias of VMOVN.
VORN (immediate): Vector Bitwise OR NOT (immediate):
an alias of VORR (immediate).
VMOV (register, SIMD): Copy between SIMD registers:
an alias of VORR (register).
VRSHR (zero): Vector Rounding Shift Right:
an alias of VORR (register).
VSHR (zero): Vector Shift Right:
an alias of VORR (register).
VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow:
an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow:
an alias of VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating Shift Right, Narrow:
an alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift Right, Narrow:
an alias of VQMOVN, VQMOVUN.
VPUSH: Push SIMD&FP registers to Stack:
an alias of VSTM, VSTMDB, VSTMIA.
VUZP (alias): Vector Unzip:
an alias of VTRN.
VZIP (alias): Vector Zip:
an alias of VTRN.
AND, ANDS (immediate): Bitwise
AND (immediate).
VAND (immediate): Vector Bitwise
AND (immediate): an alias of VBIC (immediate).
AND, ANDS (register): Bitwise
AND (register).
VAND (register): Vector Bitwise
AND (register).
AND (register-shifted register).
AND, ANDS (immediate): Bitwise AND (immediate).
AND, ANDS (register): Bitwise AND (register).
AND, ANDS (register-shifted register): Bitwise AND (register-shifted register).
ANDS (immediate): Bitwise AND (immediate).
ANDS (register): Bitwise AND (register).
ANDS (register-shifted register): Bitwise AND (register-shifted register).
Arithmetic Shift Right (immediate): an alias of MOV, MOVS (register).
Arithmetic Shift Right (register): an alias of MOV, MOVS (register-shifted register).
Arithmetic Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
Arithmetic Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
LDMDA, LDMFA: Load Multiple Decrement After (Full
Ascending).
LDMDB, LDMEA: Load Multiple Decrement Before (Empty
Ascending).
STM, STMIA, STMEA: Store Multiple (Increment After, Empty
Ascending).
STMIB, STMFA: Store Multiple Increment Before (Full
Ascending).
ASR (immediate): Arithmetic Shift Right (immediate): an alias of MOV, MOVS (register).
ASR (register): Arithmetic Shift Right (register): an alias of MOV, MOVS (register-shifted register).
ASRS (immediate): Arithmetic Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
ASRS (register): Arithmetic Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to
Away.
VCVTA (floating-point): Convert floating-point to integer with Round to Nearest with Ties to
Away.
VRINTA (Advanced SIMD): Vector Round floating-point to integer towards Nearest with Ties to
Away.
VRINTA (floating-point): Round floating-point to integer to Nearest with Ties to
Away.
MRS (Banked register): Move
Banked or Special register to general-purpose register.
MSR (Banked register): Move general-purpose register to
Banked or Special register.
Banked register): Move Banked or Special register to general-purpose register.
Banked register): Move general-purpose register to Banked or Special register.
DMB: Data Memory
Barrier.
DSB: Data Synchronization
Barrier.
ESB: Error Synchronization
Barrier.
ISB: Instruction Synchronization
Barrier.
LDMDB, LDMEA: Load Multiple Decrement
Before (Empty Ascending).
LDMIB, LDMED: Load Multiple Increment
Before (Empty Descending).
STMIB, STMFA: Store Multiple Increment
Before (Full Ascending).
STMDB, STMFD: Store Multiple Decrement
Before (Full Descending).
between double-precision and single-precision): Convert between double-precision and single-precision.
between double-precision and single-precision.
between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
between floating-point and fixed-point, floating-point): Convert between floating-point and fixed-point.
VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert
between floating-point and fixed-point.
between floating-point and fixed-point.
between floating-point and integer, Advanced SIMD): Vector Convert between floating-point and integer.
VCVT (between floating-point and integer, Advanced SIMD): Vector Convert
between floating-point and integer.
VMOV (register): Copy
between FP registers.
between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
between half-precision and single-precision.
VMOV (register, SIMD): Copy
between SIMD registers: an alias of VORR (register).
between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
BFC: Bit Field Clear.
BFI: Bit Field Insert.
BIC, BICS (immediate): Bitwise Bit Clear (immediate).
BIC, BICS (register): Bitwise Bit Clear (register).
BIC, BICS (register-shifted register): Bitwise Bit Clear (register-shifted register).
BICS (immediate): Bitwise Bit Clear (immediate).
BICS (register): Bitwise Bit Clear (register).
BICS (register-shifted register): Bitwise Bit Clear (register-shifted register).
BIC, BICS (immediate): Bitwise
Bit Clear (immediate).
VBIC (immediate): Vector Bitwise
Bit Clear (immediate).
BIC, BICS (register): Bitwise
Bit Clear (register).
VBIC (register): Vector Bitwise
Bit Clear (register).
Bit Clear (register-shifted register).
BFC:
Bit Field Clear.
SBFX: Signed
Bit Field Extract.
UBFX: Unsigned
Bit Field Extract.
BFI:
Bit Field Insert.
bits of a general-purpose register to or from a 32-bit SIMD&FP register.
RBIT: Reverse
Bits.
VCLS: Vector Count Leading Sign
Bits.
VCNT: Vector Count Set
Bits.
VTST: Vector Test
Bits.
Bitwise AND (immediate).
VAND (immediate): Vector
Bitwise AND (immediate): an alias of VBIC (immediate).
Bitwise AND (register).
VAND (register): Vector
Bitwise AND (register).
Bitwise AND (register-shifted register).
Bitwise Bit Clear (immediate).
VBIC (immediate): Vector
Bitwise Bit Clear (immediate).
Bitwise Bit Clear (register).
VBIC (register): Vector
Bitwise Bit Clear (register).
Bitwise Bit Clear (register-shifted register).
Bitwise Exclusive OR (immediate).
Bitwise Exclusive OR (register).
Bitwise Exclusive OR (register-shifted register).
VEOR: Vector
Bitwise Exclusive OR.
VBIF: Vector
Bitwise Insert if False.
VBIT: Vector
Bitwise Insert if True.
Bitwise NOT (immediate).
VMVN (immediate): Vector
Bitwise NOT (immediate).
Bitwise NOT (register).
VMVN (register): Vector
Bitwise NOT (register).
Bitwise NOT (register-shifted register).
Bitwise OR (immediate).
VORR (immediate): Vector
Bitwise OR (immediate).
Bitwise OR (register).
VORR (register): Vector
bitwise OR (register).
Bitwise OR (register-shifted register).
Bitwise OR NOT (immediate).
VORN (immediate): Vector
Bitwise OR NOT (immediate): an alias of VORR (immediate).
Bitwise OR NOT (register).
VORN (register): Vector
bitwise OR NOT (register).
VBSL: Vector
Bitwise Select.
BKPT: Breakpoint.
BL, BLX (immediate): Branch with Link and optional Exchange (immediate).
BLX (immediate): Branch with Link and optional Exchange (immediate).
BLX (register): Branch with Link and Exchange (register).
VCVTB: Convert to or from a half-precision value in the
bottom half of a single-precision register.
BXJ: Branch and Exchange, previously
Branch and Exchange Jazelle.
BXJ:
Branch and Exchange, previously Branch and Exchange Jazelle.
BX:
Branch and Exchange.
TBB, TBH: Table
Branch Byte or Halfword.
CBNZ, CBZ: Compare and
Branch on Nonzero or Zero.
Branch with Link and Exchange (register).
Branch with Link and optional Exchange (immediate).
B:
Branch.
BKPT:
Breakpoint.
HLT: Halting
Breakpoint.
BX: Branch and Exchange.
BXJ: Branch and Exchange, previously Branch and Exchange Jazelle.
LDRB (immediate): Load Register
Byte (immediate).
LDRSB (immediate): Load Register Signed
Byte (immediate).
STRB (immediate): Store Register
Byte (immediate).
LDRB (literal): Load Register
Byte (literal).
LDRSB (literal): Load Register Signed
Byte (literal).
LDRB (register): Load Register
Byte (register).
LDRSB (register): Load Register Signed
Byte (register).
STRB (register): Store Register
Byte (register).
SXTAB16: Signed Extend and Add
Byte 16.
SXTB16: Signed Extend
Byte 16.
UXTAB16: Unsigned Extend and Add
Byte 16.
UXTB16: Unsigned Extend
Byte 16.
VEXT (multibyte elements): Vector Extract: an alias of VEXT (
byte elements).
byte elements): Vector Extract.
TBB, TBH: Table Branch
Byte or Halfword.
LDRBT: Load Register
Byte Unprivileged.
LDRSBT: Load Register Signed
Byte Unprivileged.
STRBT: Store Register
Byte Unprivileged.
Byte-Reverse Packed Halfword.
Byte-Reverse Signed Halfword.
REV:
Byte-Reverse Word.
LDAB: Load-Acquire
Byte.
LDAEXB: Load-Acquire Exclusive
Byte.
LDREXB: Load Register Exclusive
Byte.
STLB: Store-Release
Byte.
STLEXB: Store-Release Exclusive
Byte.
STREXB: Store Register Exclusive
Byte.
SXTAB: Signed Extend and Add
Byte.
SXTB: Signed Extend
Byte.
UXTAB: Unsigned Extend and Add
Byte.
UXTB: Unsigned Extend
Byte.
SEL: Select
Bytes.
SMC: Secure Monitor
Call.
SVC: Supervisor
Call.
ADC, ADCS (immediate): Add with
Carry (immediate).
RSC, RSCS (immediate): Reverse Subtract with
Carry (immediate).
SBC, SBCS (immediate): Subtract with
Carry (immediate).
ADC, ADCS (register): Add with
Carry (register).
RSC, RSCS (register): Reverse Subtract with
Carry (register).
SBC, SBCS (register): Subtract with
Carry (register).
ADC, ADCS (register-shifted register): Add with
Carry (register-shifted register).
SBC, SBCS (register-shifted register): Subtract with
Carry (register-shifted register).
CBNZ, CBZ: Compare and Branch on Nonzero or Zero.
Change PE State.
DCPS1, DCPS2, DCPS3: Debug
Change PE State.
SHA1C: SHA1 hash update (
choose).
BIC, BICS (immediate): Bitwise Bit
Clear (immediate).
VBIC (immediate): Vector Bitwise Bit
Clear (immediate).
BIC, BICS (register): Bitwise Bit
Clear (register).
VBIC (register): Vector Bitwise Bit
Clear (register).
BIC, BICS (register-shifted register): Bitwise Bit
Clear (register-shifted register).
Clear-Exclusive.
BFC: Bit Field
Clear.
CLREX: Clear-Exclusive.
CLZ: Count Leading Zeros.
CMN (immediate): Compare Negative (immediate).
CMN (register): Compare Negative (register).
CMN (register-shifted register): Compare Negative (register-shifted register).
CMP (immediate): Compare (immediate).
CMP (register): Compare (register).
CMP (register-shifted register): Compare (register-shifted register).
AESIMC: AES inverse mix
columns.
AESMC: AES mix
columns.
Compare (immediate).
Compare (register).
Compare (register-shifted register).
Compare and Branch on Nonzero or Zero.
VCEQ (immediate #0): Vector
Compare Equal to Zero.
VCEQ (register): Vector
Compare Equal.
VCGE (immediate #0): Vector
Compare Greater Than or Equal to Zero.
VACGE: Vector Absolute
Compare Greater Than or Equal.
VCGE (register): Vector
Compare Greater Than or Equal.
VCGT (immediate #0): Vector
Compare Greater Than Zero.
VACGT: Vector Absolute
Compare Greater Than.
VCGT (register): Vector
Compare Greater Than.
VCLE (immediate #0): Vector
Compare Less Than or Equal to Zero.
VACLE: Vector Absolute
Compare Less Than or Equal: an alias of VACGE.
VCLE (register): Vector
Compare Less Than or Equal: an alias of VCGE (register).
VCLT (immediate #0): Vector
Compare Less Than Zero.
VACLT: Vector Absolute
Compare Less Than: an alias of VACGT.
VCLT (register): Vector
Compare Less Than: an alias of VCGT (register).
Compare Negative (immediate).
Compare Negative (register).
Compare Negative (register-shifted register).
VCMPE: Vector
Compare, raising Invalid Operation on NaN.
VCMP: Vector
Compare.
VCADD: Vector
Complex Add.
VCMLA (by element): Vector
Complex Multiply Accumulate (by element).
VCMLA: Vector
Complex Multiply Accumulate.
VSELEQ, VSELGE, VSELGT, VSELVS: Floating-point
conditional select.
Convert between double-precision and single-precision.
Convert between floating-point and fixed-point.
Convert between floating-point and fixed-point.
Convert between floating-point and integer.
Convert between half-precision and single-precision.
VCVTA (Advanced SIMD): Vector
Convert floating-point to integer with Round to Nearest with Ties to Away.
Convert floating-point to integer with Round to Nearest with Ties to Away.
VCVTN (Advanced SIMD): Vector
Convert floating-point to integer with Round to Nearest.
Convert floating-point to integer with Round to Nearest.
VCVTP (Advanced SIMD): Vector
Convert floating-point to integer with Round towards +Infinity.
Convert floating-point to integer with Round towards +Infinity.
VCVTM (Advanced SIMD): Vector
Convert floating-point to integer with Round towards -Infinity.
Convert floating-point to integer with Round towards -Infinity.
Convert floating-point to integer with Round towards Zero.
Convert floating-point to integer.
Convert integer to floating-point.
Convert to or from a half-precision value in the bottom half of a single-precision register.
Convert to or from a half-precision value in the top half of a single-precision register.
VJCVT: Javascript
Convert to signed fixed-point, rounding toward Zero.
Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
Copy a general-purpose register to a vector element.
Copy a general-purpose register to or from a 32-bit SIMD&FP register.
Copy a vector element to a general-purpose register with sign or zero extension.
Copy between FP registers.
Copy between SIMD registers: an alias of VORR (register).
Copy immediate value to a SIMD&FP register.
Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
Copy two general-purpose registers to or from a SIMD&FP register.
VCLS: Vector
Count Leading Sign Bits.
CLZ:
Count Leading Zeros.
VCLZ: Vector
Count Leading Zeros.
VCNT: Vector
Count Set Bits.
CPS, CPSID, CPSIE: Change PE State.
CPSID, CPSIE: Change PE State.
CPSIE: Change PE State.
CRC32.
CRC32: CRC32.
CRC32C.
CRC32C: CRC32C.
PLD, PLDW (immediate): Preload
PLD (literal): Preload
Data (literal).
PLD, PLDW (register): Preload
Data (register).
DMB:
Data Memory Barrier.
DSB:
Data Synchronization Barrier.
LDC (immediate): Load
data to System register (immediate).
LDC (literal): Load
data to System register (literal).
STC: Store
data to System register.
DBG: Debug hint.
DCPS1, DCPS2, DCPS3: Debug Change PE State.
DCPS2, DCPS3: Debug Change PE State.
DCPS3: Debug Change PE State.
Debug Change PE State.
DBG:
Debug hint.
STMDA, STMED: Store Multiple
Decrement After (Empty Descending).
LDMDA, LDMFA: Load Multiple
Decrement After (Full Ascending).
LDMDB, LDMEA: Load Multiple
Decrement Before (Empty Ascending).
STMDB, STMFD: Store Multiple
Decrement Before (Full Descending).
AESD: AES single round
decryption.
LDM, LDMIA, LDMFD: Load Multiple (Increment After, Full
Descending).
LDMIB, LDMED: Load Multiple Increment Before (Empty
Descending).
STMDA, STMED: Store Multiple Decrement After (Empty
Descending).
STMDB, STMFD: Store Multiple Decrement Before (Full
Descending).
VABD (floating-point): Vector Absolute
Difference (floating-point).
VABD (integer): Vector Absolute
Difference (integer).
VABAL: Vector Absolute
Difference and Accumulate Long.
VABA: Vector Absolute
Difference and Accumulate.
VABDL (integer): Vector Absolute
Difference Long (integer).
USADA8: Unsigned Sum of Absolute
Differences and Accumulate.
USAD8: Unsigned Sum of Absolute
Differences.
SDIV: Signed
Divide.
UDIV: Unsigned
Divide.
VDIV:
Divide.
DMB: Data Memory Barrier.
Dot Product index form with signed integers..
Dot Product index form with unsigned integers..
Dot Product vector form with signed integers..
Dot Product vector form with unsigned integers..
QDADD: Saturating
Double and Add.
QDSUB: Saturating
Double and Subtract.
double-precision and single-precision): Convert between double-precision and single-precision.
VCVT (between double-precision and single-precision): Convert between
double-precision and single-precision.
doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
LDAEXD: Load-Acquire Exclusive
Doubleword.
LDREXD: Load Register Exclusive
Doubleword.
STLEXD: Store-Release Exclusive
Doubleword.
STREXD: Store Register Exclusive
Doubleword.
VREV64: Vector Reverse in
doublewords.
VQDMLAL: Vector Saturating
Doubling Multiply Accumulate Long.
VQRDMLAH: Vector Saturating Rounding
Doubling Multiply Accumulate Returning High Half.
VQDMULL: Vector Saturating
Doubling Multiply Long.
VQDMULH: Vector Saturating
Doubling Multiply Returning High Half.
VQRDMULH: Vector Saturating Rounding
Doubling Multiply Returning High Half.
VQDMLSL: Vector Saturating
Doubling Multiply Subtract Long.
VQRDMLSH: Vector Saturating Rounding
Doubling Multiply Subtract Returning High Half.
DSB: Data Synchronization Barrier.
LDRD (immediate): Load Register
Dual (immediate).
STRD (immediate): Store Register
Dual (immediate).
LDRD (literal): Load Register
Dual (literal).
LDRD (register): Load Register
Dual (register).
STRD (register): Store Register
Dual (register).
SMUAD, SMUADX: Signed
Dual Multiply Add.
SMLAD, SMLADX: Signed Multiply Accumulate
Dual.
SMLALD, SMLALDX: Signed Multiply Accumulate Long
Dual.
SMLSD, SMLSDX: Signed Multiply Subtract
Dual.
SMLSLD, SMLSLDX: Signed Multiply Subtract Long
Dual.
SMUSD, SMUSDX: Signed Multiply Subtract
Dual.
Duplicate general-purpose register to vector.
Duplicate vector element to vector.
element from one lane): Store single element from one lane of one register.
VMOV (scalar to general-purpose register): Copy a vector
element to a general-purpose register with sign or zero extension.
element to all lanes): Load single 1-element structure and replicate to all lanes of one register.
element to one lane): Load single 1-element structure to one lane of one register.
VDUP (scalar): Duplicate vector
element to vector.
VCMLA (by element): Vector Complex Multiply Accumulate (by
element).
VMOV (general-purpose register to scalar): Copy a general-purpose register to a vector
element.
VST1 (multiple single elements): Store multiple single
elements from one, two, three, or four registers.
VEXT (multibyte elements): Vector Extract: an alias of VEXT (byte
elements).
elements): Load multiple single 1-element structures to one, two, three, or four registers.
elements): Store multiple single elements from one, two, three, or four registers.
elements): Vector Extract.
elements): Vector Extract: an alias of VEXT (byte elements).
LDMDB, LDMEA: Load Multiple Decrement Before (
Empty Ascending).
STM, STMIA, STMEA: Store Multiple (Increment After,
Empty Ascending).
LDMIB, LDMED: Load Multiple Increment Before (
Empty Descending).
STMDA, STMED: Store Multiple Decrement After (
Empty Descending).
AESE: AES single round
encryption.
SETEND: Set
Endianness.
EOR, EORS (immediate): Bitwise Exclusive OR (immediate).
EOR, EORS (register): Bitwise Exclusive OR (register).
EOR, EORS (register-shifted register): Bitwise Exclusive OR (register-shifted register).
EORS (immediate): Bitwise Exclusive OR (immediate).
EORS (register): Bitwise Exclusive OR (register).
EORS (register-shifted register): Bitwise Exclusive OR (register-shifted register).
VCEQ (immediate #0): Vector Compare
Equal to Zero.
VCGE (immediate #0): Vector Compare Greater Than or
Equal to Zero.
VCLE (immediate #0): Vector Compare Less Than or
Equal to Zero.
VACGE: Vector Absolute Compare Greater Than or
Equal.
VCEQ (register): Vector Compare
Equal.
VCGE (register): Vector Compare Greater Than or
Equal.
VACLE: Vector Absolute Compare Less Than or
Equal: an alias of VACGE.
VCLE (register): Vector Compare Less Than or
Equal: an alias of VCGE (register).
TEQ (immediate): Test
Equivalence (immediate).
TEQ (register): Test
Equivalence (register).
Equivalence (register-shifted register).
ERET: Exception Return.
ESB:
Error Synchronization Barrier.
ESB: Error Synchronization Barrier.
VRECPE: Vector Reciprocal
Estimate.
VRSQRTE: Vector Reciprocal Square Root
Estimate.
SEVL: Send
Event Local.
SEV: Send
Event.
WFE: Wait For
Event.
LDM (exception return): Load Multiple (
exception return).
exception return): Load Multiple (exception return).
ERET:
Exception Return.
RFE, RFEDA, RFEDB, RFEIA, RFEIB: Return From
Exception.
BL, BLX (immediate): Branch with Link and optional
Exchange (immediate).
BLX (register): Branch with Link and
Exchange (register).
BXJ: Branch and Exchange, previously Branch and
Exchange Jazelle.
BXJ: Branch and
Exchange, previously Branch and Exchange Jazelle.
BX: Branch and
Exchange.
QASX: Saturating Add and Subtract with
Exchange.
QSAX: Saturating Subtract and Add with
Exchange.
SASX: Signed Add and Subtract with
Exchange.
SHASX: Signed Halving Add and Subtract with
Exchange.
SHSAX: Signed Halving Subtract and Add with
Exchange.
SSAX: Signed Subtract and Add with
Exchange.
UASX: Unsigned Add and Subtract with
Exchange.
UHASX: Unsigned Halving Add and Subtract with
Exchange.
UHSAX: Unsigned Halving Subtract and Add with
Exchange.
UQASX: Unsigned Saturating Add and Subtract with
Exchange.
UQSAX: Unsigned Saturating Subtract and Add with
Exchange.
USAX: Unsigned Subtract and Add with
Exchange.
LDAEXB: Load-Acquire
Exclusive Byte.
LDREXB: Load Register
Exclusive Byte.
STLEXB: Store-Release
Exclusive Byte.
STREXB: Store Register
Exclusive Byte.
LDAEXD: Load-Acquire
Exclusive Doubleword.
LDREXD: Load Register
Exclusive Doubleword.
STLEXD: Store-Release
Exclusive Doubleword.
STREXD: Store Register
Exclusive Doubleword.
LDAEXH: Load-Acquire
Exclusive Halfword.
LDREXH: Load Register
Exclusive Halfword.
STLEXH: Store-Release
Exclusive Halfword.
STREXH: Store Register
Exclusive Halfword.
EOR, EORS (immediate): Bitwise
Exclusive OR (immediate).
EOR, EORS (register): Bitwise
Exclusive OR (register).
Exclusive OR (register-shifted register).
VEOR: Vector Bitwise
Exclusive OR.
LDAEX: Load-Acquire
Exclusive Word.
STLEX: Store-Release
Exclusive Word.
CLREX: Clear-
Exclusive.
LDREX: Load Register
Exclusive.
STREX: Store Register
Exclusive.
MCR: Move to System register from general-purpose register or
execute a System instruction.
SXTAB16: Signed
Extend and Add Byte 16.
UXTAB16: Unsigned
Extend and Add Byte 16.
SXTAB: Signed
Extend and Add Byte.
UXTAB: Unsigned
Extend and Add Byte.
SXTAH: Signed
Extend and Add Halfword.
UXTAH: Unsigned
Extend and Add Halfword.
SXTB16: Signed
Extend Byte 16.
UXTB16: Unsigned
Extend Byte 16.
SXTB: Signed
Extend Byte.
UXTB: Unsigned
Extend Byte.
SXTH: Signed
Extend Halfword.
UXTH: Unsigned
Extend Halfword.
RRXS: Rotate Right with
Extend, setting flags: an alias of MOV, MOVS (register).
RRX: Rotate Right with
Extend: an alias of MOV, MOVS (register).
VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or zero
extension.
VTBL, VTBX: Vector Table Lookup and
Extension.
SBFX: Signed Bit Field
Extract.
UBFX: Unsigned Bit Field
Extract.
VEXT (byte elements): Vector
Extract.
VEXT (multibyte elements): Vector
Extract: an alias of VEXT (byte elements).
VMOVX: Vector Move
extraction.
BFC: Bit
Field Clear.
SBFX: Signed Bit
Field Extract.
UBFX: Unsigned Bit
Field Extract.
BFI: Bit
Field Insert.
SHA1H: SHA1
fixed rotate.
fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
fixed-point, floating-point): Convert between floating-point and fixed-point.
VJCVT: Javascript Convert to signed
fixed-point, rounding toward Zero.
VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and
fixed-point.
VCVT (between floating-point and fixed-point, floating-point): Convert between floating-point and
fixed-point.
ASRS (immediate): Arithmetic Shift Right, setting
flags (immediate): an alias of MOV, MOVS (register).
LSLS (immediate): Logical Shift Left, setting
flags (immediate): an alias of MOV, MOVS (register).
LSRS (immediate): Logical Shift Right, setting
flags (immediate): an alias of MOV, MOVS (register).
RORS (immediate): Rotate Right, setting
flags (immediate): an alias of MOV, MOVS (register).
ASRS (register): Arithmetic Shift Right, setting
flags (register): an alias of MOV, MOVS (register-shifted register).
LSLS (register): Logical Shift Left, setting
flags (register): an alias of MOV, MOVS (register-shifted register).
LSRS (register): Logical Shift Right, setting
flags (register): an alias of MOV, MOVS (register-shifted register).
RORS (register): Rotate Right, setting
flags (register): an alias of MOV, MOVS (register-shifted register).
RRXS: Rotate Right with Extend, setting
flags: an alias of MOV, MOVS (register).
FLDM*X (FLDMDBX, FLDMIAX): FLDM*X.
FLDM*X.
FLDMDBX, FLDMIAX): FLDM*X.
FLDMIAX): FLDM*X.
floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
floating-point and fixed-point, floating-point): Convert between floating-point and fixed-point.
VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between
floating-point and fixed-point.
VCVT (between floating-point and fixed-point, floating-point): Convert between
floating-point and fixed-point.
floating-point and integer, Advanced SIMD): Vector Convert between floating-point and integer.
VCVT (between floating-point and integer, Advanced SIMD): Vector Convert between
floating-point and integer.
Floating-point conditional select.
Floating-point Maximum Number.
Floating-point Minimum Number.
VFMAL (by scalar): Vector
Floating-point Multiply-Add Long to accumulator (by scalar).
VFMAL (vector): Vector
Floating-point Multiply-Add Long to accumulator (vector).
VFMSL (by scalar): Vector
Floating-point Multiply-Subtract Long from accumulator (by scalar).
VFMSL (vector): Vector
Floating-point Multiply-Subtract Long from accumulator (vector).
floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
VRINTX (Advanced SIMD): Vector round
floating-point to integer inexact.
VRINTX (floating-point): Round
floating-point to integer inexact.
VRINTA (floating-point): Round
floating-point to integer to Nearest with Ties to Away.
VRINTN (Advanced SIMD): Vector Round
floating-point to integer to Nearest.
VRINTN (floating-point): Round
floating-point to integer to Nearest.
VRINTP (Advanced SIMD): Vector Round
floating-point to integer towards +Infinity.
VRINTP (floating-point): Round
floating-point to integer towards +Infinity.
VRINTM (Advanced SIMD): Vector Round
floating-point to integer towards -Infinity.
VRINTM (floating-point): Round
floating-point to integer towards -Infinity.
VRINTA (Advanced SIMD): Vector Round
floating-point to integer towards Nearest with Ties to Away.
VRINTZ (Advanced SIMD): Vector round
floating-point to integer towards Zero.
VRINTZ (floating-point): Round
floating-point to integer towards Zero.
VCVTA (Advanced SIMD): Vector Convert
floating-point to integer with Round to Nearest with Ties to Away.
VCVTA (floating-point): Convert
floating-point to integer with Round to Nearest with Ties to Away.
VCVTN (Advanced SIMD): Vector Convert
floating-point to integer with Round to Nearest.
VCVTN (floating-point): Convert
floating-point to integer with Round to Nearest.
VCVTP (Advanced SIMD): Vector Convert
floating-point to integer with Round towards +Infinity.
VCVTP (floating-point): Convert
floating-point to integer with Round towards +Infinity.
VCVTM (Advanced SIMD): Vector Convert
floating-point to integer with Round towards -Infinity.
VCVTM (floating-point): Convert
floating-point to integer with Round towards -Infinity.
floating-point to integer with Round towards Zero.
floating-point to integer, floating-point): Convert floating-point to integer with Round towards Zero.
VCVTR: Convert
floating-point to integer.
VRINTR: Round
floating-point to integer.
VABD (floating-point): Vector Absolute Difference (
floating-point).
VADD (floating-point): Vector Add (
floating-point).
VMAX (floating-point): Vector Maximum (
floating-point).
VMIN (floating-point): Vector Minimum (
floating-point).
VMLA (floating-point): Vector Multiply Accumulate (
floating-point).
VMLS (floating-point): Vector Multiply Subtract (
floating-point).
VMUL (floating-point): Vector Multiply (
floating-point).
VPADD (floating-point): Vector Pairwise Add (
floating-point).
VPMAX (floating-point): Vector Pairwise Maximum (
floating-point).
VPMIN (floating-point): Vector Pairwise Minimum (
floating-point).
VSUB (floating-point): Vector Subtract (
floating-point).
floating-point): Convert between floating-point and fixed-point.
floating-point): Convert floating-point to integer with Round to Nearest with Ties to Away.
floating-point): Convert floating-point to integer with Round to Nearest.
floating-point): Convert floating-point to integer with Round towards +Infinity.
floating-point): Convert floating-point to integer with Round towards -Infinity.
floating-point): Convert floating-point to integer with Round towards Zero.
floating-point): Convert integer to floating-point.
floating-point): Round floating-point to integer inexact.
floating-point): Round floating-point to integer to Nearest with Ties to Away.
floating-point): Round floating-point to integer to Nearest.
floating-point): Round floating-point to integer towards +Infinity.
floating-point): Round floating-point to integer towards -Infinity.
floating-point): Round floating-point to integer towards Zero.
floating-point): Vector Absolute Difference (floating-point).
floating-point): Vector Add (floating-point).
floating-point): Vector Maximum (floating-point).
floating-point): Vector Minimum (floating-point).
floating-point): Vector Multiply (floating-point).
floating-point): Vector Multiply Accumulate (floating-point).
floating-point): Vector Multiply Subtract (floating-point).
floating-point): Vector Pairwise Add (floating-point).
floating-point): Vector Pairwise Maximum (floating-point).
floating-point): Vector Pairwise Minimum (floating-point).
floating-point): Vector Subtract (floating-point).
floating-point, floating-point): Convert integer to floating-point.
VCVT (integer to floating-point, floating-point): Convert integer to
floating-point.
WFE: Wait
For Event.
WFI: Wait
For Interrupt.
ADR:
Form PC-relative address.
VSDOT (by element): Dot Product index
form with signed integers..
VSDOT (vector): Dot Product vector
form with signed integers..
VUDOT (by element): Dot Product index
form with unsigned integers..
VUDOT (vector): Dot Product vector
form with unsigned integers..
VLD1 (multiple single elements): Load multiple single 1-element structures to one, two, three, or
four registers.
VLD2 (multiple 2-element structures): Load multiple 2-element structures to two or
four registers.
VLD4 (multiple 4-element structures): Load multiple 4-element structures to
four registers.
VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of
four registers.
VLD4 (single 4-element structure to one lane): Load single 4-element structure to one lane of
four registers.
VST1 (multiple single elements): Store multiple single elements from one, two, three, or
four registers.
VST2 (multiple 2-element structures): Store multiple 2-element structures from two or
four registers.
VST4 (multiple 4-element structures): Store multiple 4-element structures from
four registers.
VST4 (single 4-element structure from one lane): Store single 4-element structure from one lane of
four registers.
VLDR (immediate): Load SIMD&
FP register (immediate).
VLDR (literal): Load SIMD&
FP register (literal).
VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&
FP register.
VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&
FP register.
VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&
FP register.
VMOV (immediate): Copy immediate value to a SIMD&
FP register.
VSTR: Store SIMD&
FP register.
VPOP: Pop SIMD&
FP registers from Stack: an alias of VLDM, VLDMDB, VLDMIA.
VPUSH: Push SIMD&
FP registers to Stack: an alias of VSTM, VSTMDB, VSTMIA.
VLDM, VLDMDB, VLDMIA: Load Multiple SIMD&
FP registers.
VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&
FP registers.
VMOV (register): Copy between
FP registers.
VSTM, VSTMDB, VSTMIA: Store multiple SIMD&
FP registers.
VMRS: Move SIMD&
FP Special register to general-purpose register.
VMSR: Move general-purpose register to SIMD&
FP Special register.
RFE, RFEDA, RFEDB, RFEIA, RFEIB: Return
From Exception.
FSTMDBX, FSTMIAX: FSTMX.
FSTMX.
LDMDA, LDMFA: Load Multiple Decrement After (
Full Ascending).
STMIB, STMFA: Store Multiple Increment Before (
Full Ascending).
LDM, LDMIA, LDMFD: Load Multiple (Increment After,
Full Descending).
STMDB, STMFD: Store Multiple Decrement Before (
Full Descending).
VFMA: Vector
Fused Multiply Accumulate.
VFMS: Vector
Fused Multiply Subtract.
VFNMA: Vector
Fused Negate Multiply Accumulate.
VFNMS: Vector
Fused Negate Multiply Subtract.
general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
MRC: Move to
general-purpose register from System register.
MCR: Move to System register from
general-purpose register or execute a System instruction.
general-purpose register to a vector element.
MSR (Banked register): Move
general-purpose register to Banked or Special register.
VMOV (between general-purpose register and half-precision): Copy 16 bits of a
general-purpose register to or from a 32-bit SIMD&FP register.
general-purpose register to or from a 32-bit SIMD&FP register.
general-purpose register to scalar): Copy a general-purpose register to a vector element.
VMSR: Move
general-purpose register to SIMD&FP Special register.
MSR (register): Move
general-purpose register to Special register.
VDUP (general-purpose register): Duplicate
general-purpose register to vector.
VMOV (scalar to general-purpose register): Copy a vector element to a
general-purpose register with sign or zero extension.
general-purpose register): Copy a vector element to a general-purpose register with sign or zero extension.
general-purpose register): Duplicate general-purpose register to vector.
MRS (Banked register): Move Banked or Special register to
general-purpose register.
MRS: Move Special register to
general-purpose register.
VMRS: Move SIMD&FP Special register to
general-purpose register.
general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
MRRC: Move to two
general-purpose registers from System register.
general-purpose registers to a pair of 32-bit SIMD&FP registers.
general-purpose registers to or from a SIMD&FP register.
MCRR: Move to System register from two
general-purpose registers.
VCGE (immediate #0): Vector Compare
Greater Than or Equal to Zero.
VACGE: Vector Absolute Compare
Greater Than or Equal.
VCGE (register): Vector Compare
Greater Than or Equal.
VCGT (immediate #0): Vector Compare
Greater Than Zero.
VACGT: Vector Absolute Compare
Greater Than.
VCGT (register): Vector Compare
Greater Than.
VCVTB: Convert to or from a half-precision value in the bottom
VCVTT: Convert to or from a half-precision value in the top
half of a single-precision register.
half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between
half-precision and single-precision.
VCVTB: Convert to or from a
half-precision value in the bottom half of a single-precision register.
VCVTT: Convert to or from a
half-precision value in the top half of a single-precision register.
half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
VADDHN: Vector Add and Narrow, returning High
Half.
VQDMULH: Vector Saturating Doubling Multiply Returning High
Half.
VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High
Half.
VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High
Half.
VQRDMULH: Vector Saturating Rounding Doubling Multiply Returning High
Half.
VRADDHN: Vector Rounding Add and Narrow, returning High
Half.
VRSUBHN: Vector Rounding Subtract and Narrow, returning High
Half.
VSUBHN: Vector Subtract and Narrow, returning High
Half.
LDRH (immediate): Load Register
Halfword (immediate).
LDRSH (immediate): Load Register Signed
Halfword (immediate).
STRH (immediate): Store Register
Halfword (immediate).
LDRH (literal): Load Register
Halfword (literal).
LDRSH (literal): Load Register Signed
Halfword (literal).
LDRH (register): Load Register
Halfword (register).
LDRSH (register): Load Register Signed
Halfword (register).
STRH (register): Store Register
Halfword (register).
LDRHT: Load Register
Halfword Unprivileged.
LDRSHT: Load Register Signed
Halfword Unprivileged.
STRHT: Store Register
Halfword Unprivileged.
SMLAWB, SMLAWT: Signed Multiply Accumulate (word by
halfword).
SMULWB, SMULWT: Signed Multiply (word by
halfword).
LDAEXH: Load-Acquire Exclusive
Halfword.
LDAH: Load-Acquire
Halfword.
LDREXH: Load Register Exclusive
Halfword.
PKHBT, PKHTB: Pack
Halfword.
REV16: Byte-Reverse Packed
Halfword.
REVSH: Byte-Reverse Signed
Halfword.
STLEXH: Store-Release Exclusive
Halfword.
STLH: Store-Release
Halfword.
STREXH: Store Register Exclusive
Halfword.
SXTAH: Signed Extend and Add
Halfword.
SXTH: Signed Extend
Halfword.
TBB, TBH: Table Branch Byte or
Halfword.
UXTAH: Unsigned Extend and Add
Halfword.
UXTH: Unsigned Extend
Halfword.
SMLABB, SMLABT, SMLATB, SMLATT: Signed Multiply Accumulate (
halfwords).
SMLALBB, SMLALBT, SMLALTB, SMLALTT: Signed Multiply Accumulate Long (
halfwords).
SMULBB, SMULBT, SMULTB, SMULTT: Signed Multiply (
halfwords).
VREV16: Vector Reverse in
halfwords.
HLT:
Halting Breakpoint.
SHADD16: Signed
Halving Add 16.
UHADD16: Unsigned
Halving Add 16.
SHADD8: Signed
Halving Add 8.
UHADD8: Unsigned
Halving Add 8.
SHASX: Signed
Halving Add and Subtract with Exchange.
UHASX: Unsigned
Halving Add and Subtract with Exchange.
VHADD: Vector
Halving Add.
VRHADD: Vector Rounding
Halving Add.
SHSUB16: Signed
Halving Subtract 16.
UHSUB16: Unsigned
Halving Subtract 16.
SHSUB8: Signed
Halving Subtract 8.
UHSUB8: Unsigned
Halving Subtract 8.
SHSAX: Signed
Halving Subtract and Add with Exchange.
UHSAX: Unsigned
Halving Subtract and Add with Exchange.
VHSUB: Vector
Halving Subtract.
SHA1C: SHA1
hash update (choose).
SHA1M: SHA1
hash update (majority).
SHA1P: SHA1
hash update (parity).
SHA256H: SHA256
hash update part 1.
SHA256H2: SHA256
hash update part 2.
VADDHN: Vector Add and Narrow, returning
High Half.
VQDMULH: Vector Saturating Doubling Multiply Returning
High Half.
VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning
High Half.
VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning
High Half.
VQRDMULH: Vector Saturating Rounding Doubling Multiply Returning
High Half.
VRADDHN: Vector Rounding Add and Narrow, returning
High Half.
VRSUBHN: Vector Rounding Subtract and Narrow, returning
High Half.
VSUBHN: Vector Subtract and Narrow, returning
High Half.
DBG: Debug
hint.
YIELD: Yield
hint.
HLT: Halting Breakpoint.
HVC: Hypervisor Call.
HVC:
Hypervisor Call.
immediate #0): Vector Compare Equal to Zero.
immediate #0): Vector Compare Greater Than or Equal to Zero.
immediate #0): Vector Compare Greater Than Zero.
immediate #0): Vector Compare Less Than or Equal to Zero.
immediate #0): Vector Compare Less Than Zero.
VMOV (immediate): Copy
immediate value to a SIMD&FP register.
MSR (immediate): Move
immediate value to Special register.
ADC, ADCS (immediate): Add with Carry (
immediate).
ADD, ADDS (immediate): Add (
immediate).
ADD, ADDS (SP plus immediate): Add to SP (
immediate).
AND, ANDS (immediate): Bitwise AND (
immediate).
BIC, BICS (immediate): Bitwise Bit Clear (
immediate).
BL, BLX (immediate): Branch with Link and optional Exchange (
immediate).
CMN (immediate): Compare Negative (
immediate).
CMP (immediate): Compare (
immediate).
EOR, EORS (immediate): Bitwise Exclusive OR (
immediate).
LDC (immediate): Load data to System register (
immediate).
LDR (immediate): Load Register (
immediate).
LDRB (immediate): Load Register Byte (
immediate).
LDRD (immediate): Load Register Dual (
immediate).
LDRH (immediate): Load Register Halfword (
immediate).
LDRSB (immediate): Load Register Signed Byte (
immediate).
LDRSH (immediate): Load Register Signed Halfword (
immediate).
MOV, MOVS (immediate): Move (
immediate).
MVN, MVNS (immediate): Bitwise NOT (
immediate).
ORN, ORNS (immediate): Bitwise OR NOT (
immediate).
ORR, ORRS (immediate): Bitwise OR (
immediate).
PLD, PLDW (immediate): Preload Data (
immediate).
POP (single register): Pop Single Register from Stack: an alias of LDR (
immediate).
PUSH (single register): Push Single Register to Stack: an alias of STR (
immediate).
RSB, RSBS (immediate): Reverse Subtract (
immediate).
RSC, RSCS (immediate): Reverse Subtract with Carry (
immediate).
SBC, SBCS (immediate): Subtract with Carry (
immediate).
STR (immediate): Store Register (
immediate).
STRB (immediate): Store Register Byte (
immediate).
STRD (immediate): Store Register Dual (
immediate).
STRH (immediate): Store Register Halfword (
immediate).
SUB, SUBS (immediate): Subtract (
immediate).
SUB, SUBS (SP minus immediate): Subtract from SP (
immediate).
TEQ (immediate): Test Equivalence (
immediate).
TST (immediate): Test (
immediate).
VAND (immediate): Vector Bitwise AND (immediate): an alias of VBIC (
immediate).
VBIC (immediate): Vector Bitwise Bit Clear (
immediate).
VLDR (immediate): Load SIMD&FP register (
immediate).
VMVN (immediate): Vector Bitwise NOT (
immediate).
VORN (immediate): Vector Bitwise OR NOT (immediate): an alias of VORR (
immediate).
VORR (immediate): Vector Bitwise OR (
immediate).
VQSHL, VQSHLU (immediate): Vector Saturating Shift Left (
immediate).
VSHL (immediate): Vector Shift Left (
immediate).
immediate): Add (immediate).
immediate): Add to SP (immediate).
immediate): Add with Carry (immediate).
ASR (immediate): Arithmetic Shift Right (
immediate): an alias of MOV, MOVS (register).
ASRS (immediate): Arithmetic Shift Right, setting flags (
immediate): an alias of MOV, MOVS (register).
LSL (immediate): Logical Shift Left (
immediate): an alias of MOV, MOVS (register).
LSLS (immediate): Logical Shift Left, setting flags (
immediate): an alias of MOV, MOVS (register).
LSR (immediate): Logical Shift Right (
immediate): an alias of MOV, MOVS (register).
LSRS (immediate): Logical Shift Right, setting flags (
immediate): an alias of MOV, MOVS (register).
ROR (immediate): Rotate Right (
immediate): an alias of MOV, MOVS (register).
RORS (immediate): Rotate Right, setting flags (
immediate): an alias of MOV, MOVS (register).
VAND (immediate): Vector Bitwise AND (
immediate): an alias of VBIC (immediate).
VORN (immediate): Vector Bitwise OR NOT (
immediate): an alias of VORR (immediate).
immediate): Arithmetic Shift Right (immediate): an alias of MOV, MOVS (register).
immediate): Arithmetic Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
immediate): Bitwise AND (immediate).
immediate): Bitwise Bit Clear (immediate).
immediate): Bitwise Exclusive OR (immediate).
immediate): Bitwise NOT (immediate).
immediate): Bitwise OR (immediate).
immediate): Bitwise OR NOT (immediate).
immediate): Branch with Link and optional Exchange (immediate).
immediate): Compare (immediate).
immediate): Compare Negative (immediate).
immediate): Copy immediate value to a SIMD&FP register.
immediate): Load data to System register (immediate).
immediate): Load Register (immediate).
immediate): Load Register Byte (immediate).
immediate): Load Register Dual (immediate).
immediate): Load Register Halfword (immediate).
immediate): Load Register Signed Byte (immediate).
immediate): Load Register Signed Halfword (immediate).
immediate): Load SIMD&FP register (immediate).
immediate): Logical Shift Left (immediate): an alias of MOV, MOVS (register).
immediate): Logical Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).
immediate): Logical Shift Right (immediate): an alias of MOV, MOVS (register).
immediate): Logical Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
immediate): Move (immediate).
immediate): Move immediate value to Special register.
immediate): Preload Data (immediate).
immediate): Reverse Subtract (immediate).
immediate): Reverse Subtract with Carry (immediate).
immediate): Rotate Right (immediate): an alias of MOV, MOVS (register).
immediate): Rotate Right, setting flags (immediate): an alias of MOV, MOVS (register).
immediate): Store Register (immediate).
immediate): Store Register Byte (immediate).
immediate): Store Register Dual (immediate).
immediate): Store Register Halfword (immediate).
immediate): Subtract (immediate).
immediate): Subtract from SP (immediate).
immediate): Subtract with Carry (immediate).
immediate): Test (immediate).
immediate): Test Equivalence (immediate).
immediate): Vector Bitwise AND (immediate): an alias of VBIC (immediate).
immediate): Vector Bitwise Bit Clear (immediate).
immediate): Vector Bitwise NOT (immediate).
immediate): Vector Bitwise OR (immediate).
immediate): Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).
immediate): Vector Saturating Shift Left (immediate).
immediate): Vector Shift Left (immediate).
immediate, from PC): Subtract from PC: an alias of ADR.
PLI (immediate, literal): Preload Instruction (
immediate, literal).
immediate, literal): Preload Instruction (immediate, literal).
immediate, to PC): Add to PC: an alias of ADR.
STM, STMIA, STMEA: Store Multiple (
Increment After, Empty Ascending).
LDM, LDMIA, LDMFD: Load Multiple (
Increment After, Full Descending).
LDMIB, LDMED: Load Multiple
Increment Before (Empty Descending).
STMIB, STMFA: Store Multiple
Increment Before (Full Ascending).
VSDOT (by element): Dot Product
index form with signed integers..
VUDOT (by element): Dot Product
index form with unsigned integers..
VRINTX (Advanced SIMD): Vector round floating-point to integer
inexact.
VRINTX (floating-point): Round floating-point to integer
inexact.
VCVTM (Advanced SIMD): Vector Convert floating-point to integer with Round towards -
Infinity.
VCVTM (floating-point): Convert floating-point to integer with Round towards -
Infinity.
VCVTP (Advanced SIMD): Vector Convert floating-point to integer with Round towards +
Infinity.
VCVTP (floating-point): Convert floating-point to integer with Round towards +
Infinity.
VRINTM (Advanced SIMD): Vector Round floating-point to integer towards -
Infinity.
VRINTM (floating-point): Round floating-point to integer towards -
Infinity.
VRINTP (Advanced SIMD): Vector Round floating-point to integer towards +
Infinity.
VRINTP (floating-point): Round floating-point to integer towards +
Infinity.
VBIF: Vector Bitwise
Insert if False.
VBIT: Vector Bitwise
Insert if True.
BFI: Bit Field
Insert.
VSLI: Vector Shift Left and
Insert.
VSRI: Vector Shift Right and
Insert.
VINS: Vector move
Insertion.
PLI (immediate, literal): Preload
Instruction (immediate, literal).
PLI (register): Preload
Instruction (register).
ISB:
Instruction Synchronization Barrier.
MCR: Move to System register from general-purpose register or execute a System
instruction.
VMUL (integer and polynomial): Vector Multiply (
integer and polynomial).
VMULL (integer and polynomial): Vector Multiply Long (
integer and polynomial).
integer and polynomial): Vector Multiply (integer and polynomial).
integer and polynomial): Vector Multiply Long (integer and polynomial).
VRINTX (Advanced SIMD): Vector round floating-point to
integer inexact.
VRINTX (floating-point): Round floating-point to
integer inexact.
integer to floating-point, floating-point): Convert integer to floating-point.
integer to floating-point.
VRINTA (floating-point): Round floating-point to
integer to Nearest with Ties to Away.
VRINTN (Advanced SIMD): Vector Round floating-point to
integer to Nearest.
VRINTN (floating-point): Round floating-point to
integer to Nearest.
VRINTP (Advanced SIMD): Vector Round floating-point to
integer towards +Infinity.
VRINTP (floating-point): Round floating-point to
integer towards +Infinity.
VRINTM (Advanced SIMD): Vector Round floating-point to
integer towards -Infinity.
VRINTM (floating-point): Round floating-point to
integer towards -Infinity.
VRINTA (Advanced SIMD): Vector Round floating-point to
integer towards Nearest with Ties to Away.
VRINTZ (Advanced SIMD): Vector round floating-point to
integer towards Zero.
VRINTZ (floating-point): Round floating-point to
integer towards Zero.
VCVTA (Advanced SIMD): Vector Convert floating-point to
integer with Round to Nearest with Ties to Away.
VCVTA (floating-point): Convert floating-point to
integer with Round to Nearest with Ties to Away.
VCVTN (Advanced SIMD): Vector Convert floating-point to
integer with Round to Nearest.
VCVTN (floating-point): Convert floating-point to
integer with Round to Nearest.
VCVTP (Advanced SIMD): Vector Convert floating-point to
integer with Round towards +Infinity.
VCVTP (floating-point): Convert floating-point to
integer with Round towards +Infinity.
VCVTM (Advanced SIMD): Vector Convert floating-point to
integer with Round towards -Infinity.
VCVTM (floating-point): Convert floating-point to
integer with Round towards -Infinity.
VCVT (floating-point to integer, floating-point): Convert floating-point to
integer with Round towards Zero.
VABD (integer): Vector Absolute Difference (
integer).
VABDL (integer): Vector Absolute Difference Long (
integer).
VADD (integer): Vector Add (
integer).
VMAX (integer): Vector Maximum (
integer).
VMIN (integer): Vector Minimum (
integer).
VMLA (integer): Vector Multiply Accumulate (
integer).
VMLAL (integer): Vector Multiply Accumulate Long (
integer).
VMLS (integer): Vector Multiply Subtract (
integer).
VMLSL (integer): Vector Multiply Subtract Long (
integer).
VPADD (integer): Vector Pairwise Add (
integer).
VPMAX (integer): Vector Pairwise Maximum (
integer).
VPMIN (integer): Vector Pairwise Minimum (
integer).
VSUB (integer): Vector Subtract (
integer).
integer, Advanced SIMD): Vector Convert between floating-point and integer.
integer, floating-point): Convert floating-point to integer with Round towards Zero.
VCVT (between floating-point and integer, Advanced SIMD): Vector Convert between floating-point and
integer.
VCVTR: Convert floating-point to
integer.
VRINTR: Round floating-point to
integer.
VSDOT (by element): Dot Product index form with signed
integers..
VSDOT (vector): Dot Product vector form with signed
integers..
VUDOT (by element): Dot Product index form with unsigned
integers..
VUDOT (vector): Dot Product vector form with unsigned
integers..
WFI: Wait For
Interrupt.
VCMPE: Vector Compare, raising
Invalid Operation on NaN.
AESIMC: AES
inverse mix columns.
ISB: Instruction Synchronization Barrier.
IT: If-Then.
BXJ: Branch and Exchange, previously Branch and Exchange
Jazelle.
VLD4 (single 4-element structure to one lane): Load single 4-element structure to one
VST4 (single 4-element structure from one lane): Store single 4-element structure from one
lane of four registers.
VLD1 (single element to one lane): Load single 1-element structure to one
lane of one register.
VST1 (single element from one lane): Store single element from one
lane of one register.
VLD3 (single 3-element structure to one lane): Load single 3-element structure to one
lane of three registers.
VST3 (single 3-element structure from one lane): Store single 3-element structure from one
lane of three registers.
VLD2 (single 2-element structure to one lane): Load single 2-element structure to one
lane of two registers.
VST2 (single 2-element structure from one lane): Store single 2-element structure from one
lane of two registers.
lane): Load single 1-element structure to one lane of one register.
lane): Load single 2-element structure to one lane of two registers.
lane): Load single 3-element structure to one lane of three registers.
lane): Load single 4-element structure to one lane of four registers.
lane): Store single 2-element structure from one lane of two registers.
lane): Store single 3-element structure from one lane of three registers.
lane): Store single 4-element structure from one lane of four registers.
lane): Store single element from one lane of one register.
VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to all
lanes of four registers.
VLD1 (single element to all lanes): Load single 1-element structure and replicate to all
lanes of one register.
VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to all
lanes of three registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to all
lanes of two registers.
lanes): Load single 1-element structure and replicate to all lanes of one register.
lanes): Load single 2-element structure and replicate to all lanes of two registers.
lanes): Load single 3-element structure and replicate to all lanes of three registers.
lanes): Load single 4-element structure and replicate to all lanes of four registers.
LDA: Load-Acquire Word.
LDAB: Load-Acquire Byte.
LDAEX: Load-Acquire Exclusive Word.
LDAEXB: Load-Acquire Exclusive Byte.
LDAEXD: Load-Acquire Exclusive Doubleword.
LDAEXH: Load-Acquire Exclusive Halfword.
LDAH: Load-Acquire Halfword.
LDC (immediate): Load data to System register (immediate).
LDC (literal): Load data to System register (literal).
LDM (exception return): Load Multiple (exception return).
LDM (User registers): Load Multiple (User registers).
POP (multiple registers): Pop Multiple Registers from Stack: an alias of
LDM, LDMIA, LDMFD.
LDM, LDMIA, LDMFD: Load Multiple (Increment After, Full Descending).
LDMDA, LDMFA: Load Multiple Decrement After (Full Ascending).
LDMDB, LDMEA: Load Multiple Decrement Before (Empty Ascending).
POP (multiple registers): Pop Multiple Registers from Stack: an alias of LDM, LDMIA,
LDMFD.
LDMFD: Load Multiple (Increment After, Full Descending).
POP (multiple registers): Pop Multiple Registers from Stack: an alias of LDM,
LDMIA, LDMFD.
LDMIA, LDMFD: Load Multiple (Increment After, Full Descending).
LDMIB, LDMED: Load Multiple Increment Before (Empty Descending).
POP (single register): Pop Single Register from Stack: an alias of
LDR (immediate).
LDR (immediate): Load Register (immediate).
LDR (literal): Load Register (literal).
LDR (register): Load Register (register).
LDRB (immediate): Load Register Byte (immediate).
LDRB (literal): Load Register Byte (literal).
LDRB (register): Load Register Byte (register).
LDRBT: Load Register Byte Unprivileged.
LDRD (immediate): Load Register Dual (immediate).
LDRD (literal): Load Register Dual (literal).
LDRD (register): Load Register Dual (register).
LDREX: Load Register Exclusive.
LDREXB: Load Register Exclusive Byte.
LDREXD: Load Register Exclusive Doubleword.
LDREXH: Load Register Exclusive Halfword.
LDRH (immediate): Load Register Halfword (immediate).
LDRH (literal): Load Register Halfword (literal).
LDRH (register): Load Register Halfword (register).
LDRHT: Load Register Halfword Unprivileged.
LDRSB (immediate): Load Register Signed Byte (immediate).
LDRSB (literal): Load Register Signed Byte (literal).
LDRSB (register): Load Register Signed Byte (register).
LDRSBT: Load Register Signed Byte Unprivileged.
LDRSH (immediate): Load Register Signed Halfword (immediate).
LDRSH (literal): Load Register Signed Halfword (literal).
LDRSH (register): Load Register Signed Halfword (register).
LDRSHT: Load Register Signed Halfword Unprivileged.
LDRT: Load Register Unprivileged.
VCLS: Vector Count
Leading Sign Bits.
CLZ: Count
Leading Zeros.
VCLZ: Vector Count
Leading Zeros.
VQSHL, VQSHLU (immediate): Vector Saturating Shift
Left (immediate).
VSHL (immediate): Vector Shift
Left (immediate).
LSL (immediate): Logical Shift
Left (immediate): an alias of MOV, MOVS (register).
VQSHL (register): Vector Saturating Shift
Left (register).
VSHL (register): Vector Shift
Left (register).
LSL (register): Logical Shift
Left (register): an alias of MOV, MOVS (register-shifted register).
VSLI: Vector Shift
Left and Insert.
VSHLL: Vector Shift
Left Long.
LSLS (immediate): Logical Shift
Left, setting flags (immediate): an alias of MOV, MOVS (register).
LSLS (register): Logical Shift
Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VQRSHL: Vector Saturating Rounding Shift
Left.
VRSHL: Vector Rounding Shift
Left.
VCLE (immediate #0): Vector Compare
Less Than or Equal to Zero.
VACLE: Vector Absolute Compare
Less Than or Equal: an alias of VACGE.
VCLE (register): Vector Compare
Less Than or Equal: an alias of VCGE (register).
VCLT (immediate #0): Vector Compare
Less Than Zero.
VACLT: Vector Absolute Compare
Less Than: an alias of VACGT.
VCLT (register): Vector Compare
Less Than: an alias of VCGT (register).
BLX (register): Branch with
Link and Exchange (register).
BL, BLX (immediate): Branch with
Link and optional Exchange (immediate).
LDC (literal): Load data to System register (
literal).
LDR (literal): Load Register (
literal).
LDRB (literal): Load Register Byte (
literal).
LDRD (literal): Load Register Dual (
literal).
LDRH (literal): Load Register Halfword (
literal).
LDRSB (literal): Load Register Signed Byte (
literal).
LDRSH (literal): Load Register Signed Halfword (
literal).
PLD (literal): Preload Data (
literal).
PLI (immediate, literal): Preload Instruction (immediate,
literal).
VLDR (literal): Load SIMD&FP register (
literal).
literal): Preload Instruction (immediate, literal).
Load data to System register (immediate).
Load data to System register (literal).
Load Multiple (exception return).
Load Multiple (Increment After, Full Descending).
Load Multiple (User registers).
Load multiple 2-element structures to two or four registers.
Load multiple 3-element structures to three registers.
Load multiple 4-element structures to four registers.
Load Multiple Decrement After (Full Ascending).
Load Multiple Decrement Before (Empty Ascending).
Load Multiple Increment Before (Empty Descending).
Load Multiple SIMD&FP registers.
Load multiple single 1-element structures to one, two, three, or four registers.
Load Register (immediate).
Load Register (literal).
Load Register (register).
Load Register Byte (immediate).
Load Register Byte (literal).
Load Register Byte (register).
Load Register Byte Unprivileged.
Load Register Dual (immediate).
Load Register Dual (literal).
Load Register Dual (register).
Load Register Exclusive Byte.
Load Register Exclusive Doubleword.
Load Register Exclusive Halfword.
Load Register Exclusive.
Load Register Halfword (immediate).
Load Register Halfword (literal).
Load Register Halfword (register).
Load Register Halfword Unprivileged.
Load Register Signed Byte (immediate).
Load Register Signed Byte (literal).
Load Register Signed Byte (register).
Load Register Signed Byte Unprivileged.
Load Register Signed Halfword (immediate).
Load Register Signed Halfword (literal).
Load Register Signed Halfword (register).
Load Register Signed Halfword Unprivileged.
LDRT:
Load Register Unprivileged.
Load SIMD&FP register (immediate).
Load SIMD&FP register (literal).
Load single 1-element structure and replicate to all lanes of one register.
Load single 1-element structure to one lane of one register.
Load single 2-element structure and replicate to all lanes of two registers.
Load single 2-element structure to one lane of two registers.
Load single 3-element structure and replicate to all lanes of three registers.
Load single 3-element structure to one lane of three registers.
Load single 4-element structure and replicate to all lanes of four registers.
Load single 4-element structure to one lane of four registers.
LDAB:
Load-Acquire Byte.
Load-Acquire Exclusive Byte.
Load-Acquire Exclusive Doubleword.
Load-Acquire Exclusive Halfword.
Load-Acquire Exclusive Word.
LDAH:
Load-Acquire Halfword.
LDA:
Load-Acquire Word.
SEVL: Send Event
Local.
Logical Shift Left (immediate): an alias of MOV, MOVS (register).
Logical Shift Left (register): an alias of MOV, MOVS (register-shifted register).
Logical Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).
Logical Shift Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).
Logical Shift Right (immediate): an alias of MOV, MOVS (register).
Logical Shift Right (register): an alias of MOV, MOVS (register-shifted register).
Logical Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
Logical Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VMLAL (by scalar): Vector Multiply Accumulate
Long (by scalar).
VMLSL (by scalar): Vector Multiply Subtract
Long (by scalar).
VMULL (by scalar): Vector Multiply
Long (by scalar).
SMLALBB, SMLALBT, SMLALTB, SMLALTT: Signed Multiply Accumulate
Long (halfwords).
VMULL (integer and polynomial): Vector Multiply
Long (integer and polynomial).
VABDL (integer): Vector Absolute Difference
Long (integer).
VMLAL (integer): Vector Multiply Accumulate
Long (integer).
VMLSL (integer): Vector Multiply Subtract
Long (integer).
SMLALD, SMLALDX: Signed Multiply Accumulate
Long Dual.
SMLSLD, SMLSLDX: Signed Multiply Subtract
Long Dual.
VFMSL (by scalar): Vector Floating-point Multiply-Subtract
Long from accumulator (by scalar).
VFMSL (vector): Vector Floating-point Multiply-Subtract
Long from accumulator (vector).
VFMAL (by scalar): Vector Floating-point Multiply-Add
Long to accumulator (by scalar).
VFMAL (vector): Vector Floating-point Multiply-Add
Long to accumulator (vector).
SMLAL, SMLALS: Signed Multiply Accumulate
Long.
SMULL, SMULLS: Signed Multiply
Long.
UMAAL: Unsigned Multiply Accumulate Accumulate
Long.
UMLAL, UMLALS: Unsigned Multiply Accumulate
Long.
UMULL, UMULLS: Unsigned Multiply
Long.
VABAL: Vector Absolute Difference and Accumulate
Long.
VADDL: Vector Add
Long.
VMOVL: Vector Move
Long.
VPADAL: Vector Pairwise Add and Accumulate
Long.
VPADDL: Vector Pairwise Add
Long.
VQDMLAL: Vector Saturating Doubling Multiply Accumulate
Long.
VQDMLSL: Vector Saturating Doubling Multiply Subtract
Long.
VQDMULL: Vector Saturating Doubling Multiply
Long.
VSHLL: Vector Shift Left
Long.
VSUBL: Vector Subtract
Long.
VTBL, VTBX: Vector Table
Lookup and Extension.
LSL (immediate): Logical Shift Left (immediate): an alias of MOV, MOVS (register).
LSL (register): Logical Shift Left (register): an alias of MOV, MOVS (register-shifted register).
LSLS (immediate): Logical Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).
LSLS (register): Logical Shift Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).
LSR (immediate): Logical Shift Right (immediate): an alias of MOV, MOVS (register).
LSR (register): Logical Shift Right (register): an alias of MOV, MOVS (register-shifted register).
LSRS (immediate): Logical Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
LSRS (register): Logical Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
SHA1M: SHA1 hash update (
VMAX (floating-point): Vector
Maximum (floating-point).
VPMAX (floating-point): Vector Pairwise
Maximum (floating-point).
VMAX (integer): Vector
Maximum (integer).
VPMAX (integer): Vector Pairwise
Maximum (integer).
VMAXNM: Floating-point
Maximum Number.
MCR: Move to System register from general-purpose register or execute a System instruction.
MCRR: Move to System register from two general-purpose registers.
DMB: Data
Memory Barrier.
VMIN (floating-point): Vector
Minimum (floating-point).
VPMIN (floating-point): Vector Pairwise
Minimum (floating-point).
VMIN (integer): Vector
Minimum (integer).
VPMIN (integer): Vector Pairwise
Minimum (integer).
VMINNM: Floating-point
Minimum Number.
minus immediate): Subtract from SP (immediate).
minus register): Subtract from SP (register).
AESIMC: AES inverse
mix columns.
AESMC: AES
mix columns.
MLA, MLAS: Multiply Accumulate.
MLS: Multiply and Subtract.
SMC: Secure
Monitor Call.
SMMLA, SMMLAR: Signed
Most Significant Word Multiply Accumulate.
SMMLS, SMMLSR: Signed
Most Significant Word Multiply Subtract.
SMMUL, SMMULR: Signed
Most Significant Word Multiply.
MOV, MOVS (immediate): Move (immediate).
ASR (immediate): Arithmetic Shift Right (immediate): an alias of
MOV, MOVS (register).
ASRS (immediate): Arithmetic Shift Right, setting flags (immediate): an alias of
MOV, MOVS (register).
LSL (immediate): Logical Shift Left (immediate): an alias of
MOV, MOVS (register).
LSLS (immediate): Logical Shift Left, setting flags (immediate): an alias of
MOV, MOVS (register).
LSR (immediate): Logical Shift Right (immediate): an alias of
MOV, MOVS (register).
LSRS (immediate): Logical Shift Right, setting flags (immediate): an alias of
MOV, MOVS (register).
ROR (immediate): Rotate Right (immediate): an alias of
MOV, MOVS (register).
RORS (immediate): Rotate Right, setting flags (immediate): an alias of
MOV, MOVS (register).
RRX: Rotate Right with Extend: an alias of
MOV, MOVS (register).
RRXS: Rotate Right with Extend, setting flags: an alias of
MOV, MOVS (register).
MOV, MOVS (register): Move (register).
ASR (register): Arithmetic Shift Right (register): an alias of
MOV, MOVS (register-shifted register).
ASRS (register): Arithmetic Shift Right, setting flags (register): an alias of
MOV, MOVS (register-shifted register).
LSL (register): Logical Shift Left (register): an alias of
MOV, MOVS (register-shifted register).
LSLS (register): Logical Shift Left, setting flags (register): an alias of
MOV, MOVS (register-shifted register).
LSR (register): Logical Shift Right (register): an alias of
MOV, MOVS (register-shifted register).
LSRS (register): Logical Shift Right, setting flags (register): an alias of
MOV, MOVS (register-shifted register).
ROR (register): Rotate Right (register): an alias of
MOV, MOVS (register-shifted register).
RORS (register): Rotate Right, setting flags (register): an alias of
MOV, MOVS (register-shifted register).
MOV, MOVS (register-shifted register): Move (register-shifted register).
Move (immediate).
Move (register).
Move (register-shifted register).
VMOVN: Vector
Move and Narrow.
VQMOVN, VQMOVUN: Vector Saturating
Move and Narrow.
Move Banked or Special register to general-purpose register.
VMOVX: Vector
Move extraction.
Move general-purpose register to Banked or Special register.
VMSR:
Move general-purpose register to SIMD&FP Special register.
Move general-purpose register to Special register.
Move immediate value to Special register.
VINS: Vector
move Insertion.
VMOVL: Vector
Move Long.
VMRS:
Move SIMD&FP Special register to general-purpose register.
MRS:
Move Special register to general-purpose register.
MRC:
Move to general-purpose register from System register.
MCR:
Move to System register from general-purpose register or execute a System instruction.
MCRR:
Move to System register from two general-purpose registers.
MRRC:
Move to two general-purpose registers from System register.
MOVT:
Move Top.
MOVS (immediate): Move (immediate).
ASR (immediate): Arithmetic Shift Right (immediate): an alias of MOV,
MOVS (register).
ASRS (immediate): Arithmetic Shift Right, setting flags (immediate): an alias of MOV,
MOVS (register).
LSL (immediate): Logical Shift Left (immediate): an alias of MOV,
MOVS (register).
LSLS (immediate): Logical Shift Left, setting flags (immediate): an alias of MOV,
MOVS (register).
LSR (immediate): Logical Shift Right (immediate): an alias of MOV,
MOVS (register).
LSRS (immediate): Logical Shift Right, setting flags (immediate): an alias of MOV,
MOVS (register).
ROR (immediate): Rotate Right (immediate): an alias of MOV,
MOVS (register).
RORS (immediate): Rotate Right, setting flags (immediate): an alias of MOV,
MOVS (register).
RRX: Rotate Right with Extend: an alias of MOV,
MOVS (register).
RRXS: Rotate Right with Extend, setting flags: an alias of MOV,
MOVS (register).
MOVS (register): Move (register).
ASR (register): Arithmetic Shift Right (register): an alias of MOV,
MOVS (register-shifted register).
ASRS (register): Arithmetic Shift Right, setting flags (register): an alias of MOV,
MOVS (register-shifted register).
LSL (register): Logical Shift Left (register): an alias of MOV,
MOVS (register-shifted register).
LSLS (register): Logical Shift Left, setting flags (register): an alias of MOV,
MOVS (register-shifted register).
LSR (register): Logical Shift Right (register): an alias of MOV,
MOVS (register-shifted register).
LSRS (register): Logical Shift Right, setting flags (register): an alias of MOV,
MOVS (register-shifted register).
ROR (register): Rotate Right (register): an alias of MOV,
MOVS (register-shifted register).
RORS (register): Rotate Right, setting flags (register): an alias of MOV,
MOVS (register-shifted register).
MOVS (register-shifted register): Move (register-shifted register).
MOVT: Move Top.
MRC: Move to general-purpose register from System register.
MRRC: Move to two general-purpose registers from System register.
MRS (Banked register): Move Banked or Special register to general-purpose register.
MRS: Move Special register to general-purpose register.
MSR (Banked register): Move general-purpose register to Banked or Special register.
MSR (immediate): Move immediate value to Special register.
MSR (register): Move general-purpose register to Special register.
MUL, MULS: Multiply.
multibyte elements): Vector Extract: an alias of VEXT (byte elements).
LDM (exception return): Load
Multiple (exception return).
STM, STMIA, STMEA: Store
Multiple (Increment After, Empty Ascending).
LDM, LDMIA, LDMFD: Load
Multiple (Increment After, Full Descending).
LDM (User registers): Load
Multiple (User registers).
STM (User registers): Store
Multiple (User registers).
multiple 2-element structures from two or four registers.
multiple 2-element structures to two or four registers.
multiple 2-element structures): Load multiple 2-element structures to two or four registers.
multiple 2-element structures): Store multiple 2-element structures from two or four registers.
multiple 3-element structures from three registers.
multiple 3-element structures to three registers.
multiple 3-element structures): Load multiple 3-element structures to three registers.
multiple 3-element structures): Store multiple 3-element structures from three registers.
multiple 4-element structures from four registers.
multiple 4-element structures to four registers.
multiple 4-element structures): Load multiple 4-element structures to four registers.
multiple 4-element structures): Store multiple 4-element structures from four registers.
STMDA, STMED: Store
Multiple Decrement After (Empty Descending).
LDMDA, LDMFA: Load
Multiple Decrement After (Full Ascending).
LDMDB, LDMEA: Load
Multiple Decrement Before (Empty Ascending).
STMDB, STMFD: Store
Multiple Decrement Before (Full Descending).
LDMIB, LDMED: Load
Multiple Increment Before (Empty Descending).
STMIB, STMFA: Store
Multiple Increment Before (Full Ascending).
POP: Pop
Multiple Registers from Stack.
Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.
PUSH: Push
Multiple Registers to Stack.
multiple registers to Stack: an alias of STMDB, STMFD.
multiple registers): Pop Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.
multiple registers): Push multiple registers to Stack: an alias of STMDB, STMFD.
VLDM, VLDMDB, VLDMIA: Load
Multiple SIMD&FP registers.
VSTM, VSTMDB, VSTMIA: Store
multiple SIMD&FP registers.
multiple single 1-element structures to one, two, three, or four registers.
multiple single elements from one, two, three, or four registers.
multiple single elements): Load multiple single 1-element structures to one, two, three, or four registers.
multiple single elements): Store multiple single elements from one, two, three, or four registers.
VMUL (by scalar): Vector
Multiply (by scalar).
VMUL (floating-point): Vector
Multiply (floating-point).
SMULBB, SMULBT, SMULTB, SMULTT: Signed
Multiply (halfwords).
VMUL (integer and polynomial): Vector
Multiply (integer and polynomial).
SMULWB, SMULWT: Signed
Multiply (word by halfword).
VCMLA (by element): Vector Complex
Multiply Accumulate (by element).
VMLA (by scalar): Vector
Multiply Accumulate (by scalar).
VMLA (floating-point): Vector
Multiply Accumulate (floating-point).
SMLABB, SMLABT, SMLATB, SMLATT: Signed
Multiply Accumulate (halfwords).
VMLA (integer): Vector
Multiply Accumulate (integer).
SMLAWB, SMLAWT: Signed
Multiply Accumulate (word by halfword).
UMAAL: Unsigned
Multiply Accumulate Accumulate Long.
SMLAD, SMLADX: Signed
Multiply Accumulate Dual.
VMLAL (by scalar): Vector
Multiply Accumulate Long (by scalar).
Multiply Accumulate Long (halfwords).
VMLAL (integer): Vector
Multiply Accumulate Long (integer).
SMLALD, SMLALDX: Signed
Multiply Accumulate Long Dual.
SMLAL, SMLALS: Signed
Multiply Accumulate Long.
UMLAL, UMLALS: Unsigned
Multiply Accumulate Long.
VQDMLAL: Vector Saturating Doubling
Multiply Accumulate Long.
VQRDMLAH: Vector Saturating Rounding Doubling
Multiply Accumulate Returning High Half.
Multiply Accumulate.
SMMLA, SMMLAR: Signed Most Significant Word
Multiply Accumulate.
VCMLA: Vector Complex
Multiply Accumulate.
VFMA: Vector Fused
Multiply Accumulate.
VFNMA: Vector Fused Negate
Multiply Accumulate.
VNMLA: Vector Negate
Multiply Accumulate.
SMUAD, SMUADX: Signed Dual
Multiply Add.
MLS:
Multiply and Subtract.
VMULL (by scalar): Vector
Multiply Long (by scalar).
VMULL (integer and polynomial): Vector
Multiply Long (integer and polynomial).
SMULL, SMULLS: Signed
Multiply Long.
UMULL, UMULLS: Unsigned
Multiply Long.
VQDMULL: Vector Saturating Doubling
Multiply Long.
VQDMULH: Vector Saturating Doubling
Multiply Returning High Half.
VQRDMULH: Vector Saturating Rounding Doubling
Multiply Returning High Half.
VMLS (by scalar): Vector
Multiply Subtract (by scalar).
VMLS (floating-point): Vector
Multiply Subtract (floating-point).
VMLS (integer): Vector
Multiply Subtract (integer).
SMLSD, SMLSDX: Signed
Multiply Subtract Dual.
SMUSD, SMUSDX: Signed
Multiply Subtract Dual.
VMLSL (by scalar): Vector
Multiply Subtract Long (by scalar).
VMLSL (integer): Vector
Multiply Subtract Long (integer).
SMLSLD, SMLSLDX: Signed
Multiply Subtract Long Dual.
VQDMLSL: Vector Saturating Doubling
Multiply Subtract Long.
VQRDMLSH: Vector Saturating Rounding Doubling
Multiply Subtract Returning High Half.
SMMLS, SMMLSR: Signed Most Significant Word
Multiply Subtract.
VFMS: Vector Fused
Multiply Subtract.
VFNMS: Vector Fused Negate
Multiply Subtract.
VNMLS: Vector Negate
Multiply Subtract.
VFMAL (by scalar): Vector Floating-point
Multiply-Add Long to accumulator (by scalar).
VFMAL (vector): Vector Floating-point
Multiply-Add Long to accumulator (vector).
VFMSL (by scalar): Vector Floating-point
Multiply-Subtract Long from accumulator (by scalar).
VFMSL (vector): Vector Floating-point
Multiply-Subtract Long from accumulator (vector).
Multiply.
SMMUL, SMMULR: Signed Most Significant Word
Multiply.
VNMUL: Vector Negate
Multiply.
MVN, MVNS (immediate): Bitwise NOT (immediate).
MVN, MVNS (register): Bitwise NOT (register).
MVN, MVNS (register-shifted register): Bitwise NOT (register-shifted register).
MVNS (immediate): Bitwise NOT (immediate).
MVNS (register): Bitwise NOT (register).
MVNS (register-shifted register): Bitwise NOT (register-shifted register).
VADDHN: Vector Add and
Narrow, returning High Half.
VRADDHN: Vector Rounding Add and
Narrow, returning High Half.
VRSUBHN: Vector Rounding Subtract and
Narrow, returning High Half.
VSUBHN: Vector Subtract and
Narrow, returning High Half.
VMOVN: Vector Move and
Narrow.
VQMOVN, VQMOVUN: Vector Saturating Move and
Narrow.
VQRSHRN, VQRSHRUN: Vector Saturating Rounding Shift Right,
Narrow.
VQSHRN, VQSHRUN: Vector Saturating Shift Right,
Narrow.
VRSHRN: Vector Rounding Shift Right and
Narrow.
VSHRN: Vector Shift Right
Narrow.
VRSHRN (zero): Vector Rounding Shift Right and
Narrow: an alias of VMOVN.
VSHRN (zero): Vector Shift Right
Narrow: an alias of VMOVN.
VQRSHRN (zero): Vector Saturating Rounding Shift Right,
Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right,
Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating Shift Right,
Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift Right,
Narrow: an alias of VQMOVN, VQMOVUN.
VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to
Nearest with Ties to Away.
VCVTA (floating-point): Convert floating-point to integer with Round to
Nearest with Ties to Away.
VRINTA (Advanced SIMD): Vector Round floating-point to integer towards
Nearest with Ties to Away.
VRINTA (floating-point): Round floating-point to integer to
Nearest with Ties to Away.
VCVTN (Advanced SIMD): Vector Convert floating-point to integer with Round to
Nearest.
VCVTN (floating-point): Convert floating-point to integer with Round to
Nearest.
VRINTN (Advanced SIMD): Vector Round floating-point to integer to
Nearest.
VRINTN (floating-point): Round floating-point to integer to
Nearest.
VFNMA: Vector Fused
Negate Multiply Accumulate.
VNMLA: Vector
Negate Multiply Accumulate.
VFNMS: Vector Fused
Negate Multiply Subtract.
VNMLS: Vector
Negate Multiply Subtract.
VNMUL: Vector
Negate Multiply.
VNEG: Vector
Negate.
VQNEG: Vector Saturating
Negate.
CMN (immediate): Compare
Negative (immediate).
CMN (register): Compare
Negative (register).
CMN (register-shifted register): Compare
Negative (register-shifted register).
SETPAN: Set Privileged Access
Never.
NOP:
No Operation.
CBNZ, CBZ: Compare and Branch on
Nonzero or Zero.
NOP: No Operation.
MVN, MVNS (immediate): Bitwise
NOT (immediate).
ORN, ORNS (immediate): Bitwise OR
NOT (immediate).
VMVN (immediate): Vector Bitwise
NOT (immediate).
VORN (immediate): Vector Bitwise OR
NOT (immediate): an alias of VORR (immediate).
MVN, MVNS (register): Bitwise
NOT (register).
ORN, ORNS (register): Bitwise OR
NOT (register).
VMVN (register): Vector Bitwise
NOT (register).
VORN (register): Vector bitwise OR
NOT (register).
NOT (register-shifted register).
VMAXNM: Floating-point Maximum
Number.
VMINNM: Floating-point Minimum
Number.
CBNZ, CBZ: Compare and Branch
on Nonzero or Zero.
VLD4 (single 4-element structure to one lane): Load single 4-element structure to
one lane of four registers.
VST4 (single 4-element structure from one lane): Store single 4-element structure from
one lane of four registers.
VLD1 (single element to one lane): Load single 1-element structure to
one lane of one register.
VST1 (single element from one lane): Store single element from
one lane of one register.
VLD3 (single 3-element structure to one lane): Load single 3-element structure to
one lane of three registers.
VST3 (single 3-element structure from one lane): Store single 3-element structure from
one lane of three registers.
VLD2 (single 2-element structure to one lane): Load single 2-element structure to
one lane of two registers.
VST2 (single 2-element structure from one lane): Store single 2-element structure from
one lane of two registers.
one lane): Load single 1-element structure to one lane of one register.
one lane): Load single 2-element structure to one lane of two registers.
one lane): Load single 3-element structure to one lane of three registers.
one lane): Load single 4-element structure to one lane of four registers.
one lane): Store single 2-element structure from one lane of two registers.
one lane): Store single 3-element structure from one lane of three registers.
one lane): Store single 4-element structure from one lane of four registers.
one lane): Store single element from one lane of one register.
VLD1 (single element to all lanes): Load single 1-element structure and replicate to all lanes of
one register.
VLD1 (single element to one lane): Load single 1-element structure to one lane of
one register.
VST1 (single element from one lane): Store single element from one lane of
one register.
VLD1 (multiple single elements): Load multiple single 1-element structures to
one, two, three, or four registers.
VST1 (multiple single elements): Store multiple single elements from
one, two, three, or four registers.
VCMPE: Vector Compare, raising Invalid
Operation on NaN.
NOP: No
Operation.
BL, BLX (immediate): Branch with Link and
optional Exchange (immediate).
EOR, EORS (immediate): Bitwise Exclusive
OR (immediate).
ORR, ORRS (immediate): Bitwise
OR (immediate).
VORR (immediate): Vector Bitwise
OR (immediate).
EOR, EORS (register): Bitwise Exclusive
OR (register).
ORR, ORRS (register): Bitwise
OR (register).
VORR (register): Vector bitwise
OR (register).
EOR, EORS (register-shifted register): Bitwise Exclusive
OR (register-shifted register).
OR (register-shifted register).
ORN, ORNS (immediate): Bitwise
OR NOT (immediate).
VORN (immediate): Vector Bitwise
OR NOT (immediate): an alias of VORR (immediate).
ORN, ORNS (register): Bitwise
OR NOT (register).
VORN (register): Vector bitwise
OR NOT (register).
VEOR: Vector Bitwise Exclusive
OR.
ORN, ORNS (immediate): Bitwise OR NOT (immediate).
ORN, ORNS (register): Bitwise OR NOT (register).
ORNS (immediate): Bitwise OR NOT (immediate).
ORNS (register): Bitwise OR NOT (register).
ORR, ORRS (immediate): Bitwise OR (immediate).
ORR, ORRS (register): Bitwise OR (register).
ORR, ORRS (register-shifted register): Bitwise OR (register-shifted register).
ORRS (immediate): Bitwise OR (immediate).
ORRS (register): Bitwise OR (register).
ORRS (register-shifted register): Bitwise OR (register-shifted register).
REV16: Byte-Reverse
Packed Halfword.
VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a
pair of 32-bit SIMD&FP registers.
VPADD (floating-point): Vector
Pairwise Add (floating-point).
VPADD (integer): Vector
Pairwise Add (integer).
VPADAL: Vector
Pairwise Add and Accumulate Long.
VPADDL: Vector
Pairwise Add Long.
VPMAX (floating-point): Vector
Pairwise Maximum (floating-point).
VPMAX (integer): Vector
Pairwise Maximum (integer).
VPMIN (floating-point): Vector
Pairwise Minimum (floating-point).
VPMIN (integer): Vector
Pairwise Minimum (integer).
SHA1P: SHA1 hash update (
parity).
SHA256H: SHA256 hash update
part 1.
SHA256H2: SHA256 hash update
part 2.
PC): Add to PC: an alias of ADR.
PC): Subtract from PC: an alias of ADR.
ADR: Form
PC-relative address.
ADD (immediate, to PC): Add to
PC: an alias of ADR.
SUB (immediate, from PC): Subtract from
PC: an alias of ADR.
CPS, CPSID, CPSIE: Change
PE State.
DCPS1, DCPS2, DCPS3: Debug Change
PE State.
UDF:
Permanently Undefined.
PKHBT, PKHTB: Pack Halfword.
PLD (literal): Preload Data (literal).
PLD, PLDW (immediate): Preload Data (immediate).
PLD, PLDW (register): Preload Data (register).
PLDW (immediate): Preload Data (immediate).
PLDW (register): Preload Data (register).
PLI (immediate, literal): Preload Instruction (immediate, literal).
PLI (register): Preload Instruction (register).
plus immediate): Add to SP (immediate).
plus register): Add to SP (register).
VSELEQ, VSELGE, VSELGT, VSELVS: Floating-
point conditional select.
VMAXNM: Floating-
point Maximum Number.
VMINNM: Floating-
point Minimum Number.
VFMAL (by scalar): Vector Floating-
point Multiply-Add Long to accumulator (by scalar).
VFMAL (vector): Vector Floating-
point Multiply-Add Long to accumulator (vector).
VFMSL (by scalar): Vector Floating-
point Multiply-Subtract Long from accumulator (by scalar).
VFMSL (vector): Vector Floating-
point Multiply-Subtract Long from accumulator (vector).
point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
point, floating-point): Convert between floating-point and fixed-point.
VJCVT: Javascript Convert to signed fixed-
point, rounding toward Zero.
VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-
point.
VCVT (between floating-point and fixed-point, floating-point): Convert between floating-point and fixed-
point.
VMUL (integer and polynomial): Vector Multiply (integer and
polynomial).
VMULL (integer and polynomial): Vector Multiply Long (integer and
polynomial).
polynomial): Vector Multiply (integer and polynomial).
polynomial): Vector Multiply Long (integer and polynomial).
POP (multiple registers): Pop Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.
POP (single register): Pop Single Register from Stack: an alias of LDR (immediate).
POP:
Pop Multiple Registers from Stack.
Pop Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.
VPOP:
Pop SIMD&FP registers from Stack: an alias of VLDM, VLDMDB, VLDMIA.
Pop Single Register from Stack: an alias of LDR (immediate).
POP: Pop Multiple Registers from Stack.
precision and single-precision): Convert between double-precision and single-precision.
precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
VCVT (between double-precision and single-precision): Convert between double-
precision and single-precision.
VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-
precision and single-precision.
VCVTB: Convert to or from a half-precision value in the bottom half of a single-
precision register.
VCVTT: Convert to or from a half-precision value in the top half of a single-
precision register.
precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
VCVTB: Convert to or from a half-
precision value in the bottom half of a single-precision register.
VCVTT: Convert to or from a half-
precision value in the top half of a single-precision register.
precision): Convert between double-precision and single-precision.
precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
VCVT (between double-precision and single-precision): Convert between double-precision and single-
precision.
VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-
precision.
Preload Data (immediate).
Preload Data (literal).
Preload Data (register).
Preload Instruction (immediate, literal).
Preload Instruction (register).
BXJ: Branch and Exchange,
previously Branch and Exchange Jazelle.
SETPAN: Set
Privileged Access Never.
VSDOT (by element): Dot
Product index form with signed integers..
VUDOT (by element): Dot
Product index form with unsigned integers..
VSDOT (vector): Dot
Product vector form with signed integers..
VUDOT (vector): Dot
Product vector form with unsigned integers..
purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
MRC: Move to general-
purpose register from System register.
MCR: Move to System register from general-
purpose register or execute a System instruction.
VMOV (general-purpose register to scalar): Copy a general-
purpose register to a vector element.
MSR (Banked register): Move general-
purpose register to Banked or Special register.
VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-
purpose register to or from a 32-bit SIMD&FP register.
VMOV (between general-purpose register and single-precision): Copy a general-
purpose register to or from a 32-bit SIMD&FP register.
purpose register to scalar): Copy a general-purpose register to a vector element.
VMSR: Move general-
purpose register to SIMD&FP Special register.
MSR (register): Move general-
purpose register to Special register.
VDUP (general-purpose register): Duplicate general-
purpose register to vector.
VMOV (scalar to general-purpose register): Copy a vector element to a general-
purpose register with sign or zero extension.
purpose register): Copy a vector element to a general-purpose register with sign or zero extension.
purpose register): Duplicate general-purpose register to vector.
MRS (Banked register): Move Banked or Special register to general-
purpose register.
MRS: Move Special register to general-
purpose register.
VMRS: Move SIMD&FP Special register to general-
purpose register.
purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
MRRC: Move to two general-
purpose registers from System register.
purpose registers to a pair of 32-bit SIMD&FP registers.
VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-
purpose registers to or from a SIMD&FP register.
MCRR: Move to System register from two general-
purpose registers.
PUSH (multiple registers): Push multiple registers to Stack: an alias of STMDB, STMFD.
PUSH (single register): Push Single Register to Stack: an alias of STR (immediate).
PUSH:
Push Multiple Registers to Stack.
Push multiple registers to Stack: an alias of STMDB, STMFD.
Push SIMD&FP registers to Stack: an alias of VSTM, VSTMDB, VSTMIA.
Push Single Register to Stack: an alias of STR (immediate).
PUSH: Push Multiple Registers to Stack.
QADD8: Saturating Add 8.
QADD: Saturating Add.
QASX: Saturating Add and Subtract with Exchange.
QDADD: Saturating Double and Add.
QDSUB: Saturating Double and Subtract.
QSAX: Saturating Subtract and Add with Exchange.
QSUB16: Saturating Subtract 16.
QSUB8: Saturating Subtract 8.
QSUB: Saturating Subtract.
VCMPE: Vector Compare,
RBIT: Reverse Bits.
VRECPE: Vector
Reciprocal Estimate.
VRSQRTE: Vector
Reciprocal Square Root Estimate.
VRSQRTS: Vector
Reciprocal Square Root Step.
VRECPS: Vector
Reciprocal Step.
LDR (immediate): Load
Register (immediate).
STR (immediate): Store
Register (immediate).
LDR (literal): Load
Register (literal).
LDR (register): Load
Register (register).
STR (register): Store
Register (register).
LDRB (immediate): Load
Register Byte (immediate).
STRB (immediate): Store
Register Byte (immediate).
LDRB (literal): Load
Register Byte (literal).
LDRB (register): Load
Register Byte (register).
STRB (register): Store
Register Byte (register).
LDRBT: Load
Register Byte Unprivileged.
STRBT: Store
Register Byte Unprivileged.
LDRD (immediate): Load
Register Dual (immediate).
STRD (immediate): Store
Register Dual (immediate).
LDRD (literal): Load
Register Dual (literal).
LDRD (register): Load
Register Dual (register).
STRD (register): Store
Register Dual (register).
LDREXB: Load
Register Exclusive Byte.
STREXB: Store
Register Exclusive Byte.
LDREXD: Load
Register Exclusive Doubleword.
STREXD: Store
Register Exclusive Doubleword.
LDREXH: Load
Register Exclusive Halfword.
STREXH: Store
Register Exclusive Halfword.
LDREX: Load
Register Exclusive.
STREX: Store
Register Exclusive.
POP (single register): Pop Single
Register from Stack: an alias of LDR (immediate).
LDRH (immediate): Load
Register Halfword (immediate).
STRH (immediate): Store
Register Halfword (immediate).
LDRH (literal): Load
Register Halfword (literal).
LDRH (register): Load
Register Halfword (register).
STRH (register): Store
Register Halfword (register).
LDRHT: Load
Register Halfword Unprivileged.
STRHT: Store
Register Halfword Unprivileged.
LDRSB (immediate): Load
Register Signed Byte (immediate).
LDRSB (literal): Load
Register Signed Byte (literal).
LDRSB (register): Load
Register Signed Byte (register).
LDRSBT: Load
Register Signed Byte Unprivileged.
LDRSH (immediate): Load
Register Signed Halfword (immediate).
LDRSH (literal): Load
Register Signed Halfword (literal).
LDRSH (register): Load
Register Signed Halfword (register).
LDRSHT: Load
Register Signed Halfword Unprivileged.
PUSH (single register): Push Single
Register to Stack: an alias of STR (immediate).
LDRT: Load
Register Unprivileged.
STRT: Store
Register Unprivileged.
POP: Pop Multiple
Registers from Stack.
POP (multiple registers): Pop Multiple
Registers from Stack: an alias of LDM, LDMIA, LDMFD.
PUSH: Push Multiple
Registers to Stack.
STLB: Store-
Release Byte.
STLEXB: Store-
Release Exclusive Byte.
STLEXD: Store-
Release Exclusive Doubleword.
STLEXH: Store-
Release Exclusive Halfword.
STLEX: Store-
Release Exclusive Word.
STLH: Store-
Release Halfword.
STL: Store-
Release Word.
VLD4 (single 4-element structure to all lanes): Load single 4-element structure and
replicate to all lanes of four registers.
VLD1 (single element to all lanes): Load single 1-element structure and
replicate to all lanes of one register.
VLD3 (single 3-element structure to all lanes): Load single 3-element structure and
replicate to all lanes of three registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element structure and
replicate to all lanes of two registers.
Return From Exception.
Return State.
LDM (exception return): Load Multiple (exception
return).
return): Load Multiple (exception return).
ERET: Exception
Return.
VADDHN: Vector Add and Narrow,
returning High Half.
VQDMULH: Vector Saturating Doubling Multiply
Returning High Half.
VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate
Returning High Half.
VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract
Returning High Half.
VQRDMULH: Vector Saturating Rounding Doubling Multiply
Returning High Half.
VRADDHN: Vector Rounding Add and Narrow,
returning High Half.
VRSUBHN: Vector Rounding Subtract and Narrow,
returning High Half.
VSUBHN: Vector Subtract and Narrow,
returning High Half.
REV16: Byte-Reverse Packed Halfword.
REV: Byte-Reverse Word.
RBIT:
Reverse Bits.
VREV64: Vector
Reverse in doublewords.
VREV16: Vector
Reverse in halfwords.
VREV32: Vector
Reverse in words.
REV16: Byte-
Reverse Packed Halfword.
REVSH: Byte-
Reverse Signed Halfword.
Reverse Subtract (immediate).
Reverse Subtract (register).
Reverse Subtract (register-shifted register).
Reverse Subtract (register-shifted register).
Reverse Subtract with Carry (immediate).
Reverse Subtract with Carry (register).
REV: Byte-
Reverse Word.
REVSH: Byte-Reverse Signed Halfword.
RFE, RFEDA, RFEDB, RFEIA, RFEIB: Return From Exception.
RFEDA, RFEDB, RFEIA, RFEIB: Return From Exception.
RFEDB, RFEIA, RFEIB: Return From Exception.
RFEIA, RFEIB: Return From Exception.
RFEIB: Return From Exception.
ASR (immediate): Arithmetic Shift
Right (immediate): an alias of MOV, MOVS (register).
LSR (immediate): Logical Shift
Right (immediate): an alias of MOV, MOVS (register).
ROR (immediate): Rotate
Right (immediate): an alias of MOV, MOVS (register).
ASR (register): Arithmetic Shift
Right (register): an alias of MOV, MOVS (register-shifted register).
LSR (register): Logical Shift
Right (register): an alias of MOV, MOVS (register-shifted register).
ROR (register): Rotate
Right (register): an alias of MOV, MOVS (register-shifted register).
VRSRA: Vector Rounding Shift
Right and Accumulate.
VSRA: Vector Shift
Right and Accumulate.
VSRI: Vector Shift
Right and Insert.
VRSHRN: Vector Rounding Shift
Right and Narrow.
VRSHRN (zero): Vector Rounding Shift
Right and Narrow: an alias of VMOVN.
VSHRN: Vector Shift
Right Narrow.
VSHRN (zero): Vector Shift
Right Narrow: an alias of VMOVN.
RRXS: Rotate
Right with Extend, setting flags: an alias of MOV, MOVS (register).
RRX: Rotate
Right with Extend: an alias of MOV, MOVS (register).
VQRSHRN, VQRSHRUN: Vector Saturating Rounding Shift
Right, Narrow.
VQSHRN, VQSHRUN: Vector Saturating Shift
Right, Narrow.
VQRSHRN (zero): Vector Saturating Rounding Shift
Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift
Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating Shift
Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift
Right, Narrow: an alias of VQMOVN, VQMOVUN.
ASRS (immediate): Arithmetic Shift
Right, setting flags (immediate): an alias of MOV, MOVS (register).
LSRS (immediate): Logical Shift
Right, setting flags (immediate): an alias of MOV, MOVS (register).
RORS (immediate): Rotate
Right, setting flags (immediate): an alias of MOV, MOVS (register).
ASRS (register): Arithmetic Shift
Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
LSRS (register): Logical Shift
Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
RORS (register): Rotate
Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VRSHR: Vector Rounding Shift
Right.
VSHR: Vector Shift
Right.
VRSHR (zero): Vector Rounding Shift
Right: an alias of VORR (register).
VSHR (zero): Vector Shift
Right: an alias of VORR (register).
VRSQRTE: Vector Reciprocal Square
Root Estimate.
VRSQRTS: Vector Reciprocal Square
Root Step.
VSQRT: Square
Root.
ROR (immediate): Rotate Right (immediate): an alias of MOV, MOVS (register).
ROR (register): Rotate Right (register): an alias of MOV, MOVS (register-shifted register).
RORS (immediate): Rotate Right, setting flags (immediate): an alias of MOV, MOVS (register).
RORS (register): Rotate Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
Rotate Right (immediate): an alias of MOV, MOVS (register).
Rotate Right (register): an alias of MOV, MOVS (register-shifted register).
RRXS:
Rotate Right with Extend, setting flags: an alias of MOV, MOVS (register).
RRX:
Rotate Right with Extend: an alias of MOV, MOVS (register).
Rotate Right, setting flags (immediate): an alias of MOV, MOVS (register).
Rotate Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
SHA1H: SHA1 fixed
rotate.
AESD: AES single
round decryption.
AESE: AES single
round encryption.
VRINTX (Advanced SIMD): Vector
round floating-point to integer inexact.
Round floating-point to integer inexact.
Round floating-point to integer to Nearest with Ties to Away.
VRINTN (Advanced SIMD): Vector
Round floating-point to integer to Nearest.
Round floating-point to integer to Nearest.
VRINTP (Advanced SIMD): Vector
Round floating-point to integer towards +Infinity.
Round floating-point to integer towards +Infinity.
VRINTM (Advanced SIMD): Vector
Round floating-point to integer towards -Infinity.
Round floating-point to integer towards -Infinity.
VRINTA (Advanced SIMD): Vector
Round floating-point to integer towards Nearest with Ties to Away.
VRINTZ (Advanced SIMD): Vector
round floating-point to integer towards Zero.
Round floating-point to integer towards Zero.
Round floating-point to integer.
VCVTA (Advanced SIMD): Vector Convert floating-point to integer with
Round to Nearest with Ties to Away.
VCVTA (floating-point): Convert floating-point to integer with
Round to Nearest with Ties to Away.
VCVTN (Advanced SIMD): Vector Convert floating-point to integer with
Round to Nearest.
VCVTN (floating-point): Convert floating-point to integer with
Round to Nearest.
VCVTP (Advanced SIMD): Vector Convert floating-point to integer with
Round towards +Infinity.
VCVTP (floating-point): Convert floating-point to integer with
Round towards +Infinity.
VCVTM (Advanced SIMD): Vector Convert floating-point to integer with
Round towards -Infinity.
VCVTM (floating-point): Convert floating-point to integer with
Round towards -Infinity.
VCVT (floating-point to integer, floating-point): Convert floating-point to integer with
Round towards Zero.
VRADDHN: Vector
Rounding Add and Narrow, returning High Half.
VQRDMLAH: Vector Saturating
Rounding Doubling Multiply Accumulate Returning High Half.
VQRDMULH: Vector Saturating
Rounding Doubling Multiply Returning High Half.
VQRDMLSH: Vector Saturating
Rounding Doubling Multiply Subtract Returning High Half.
VRHADD: Vector
Rounding Halving Add.
VQRSHL: Vector Saturating
Rounding Shift Left.
VRSHL: Vector
Rounding Shift Left.
VRSRA: Vector
Rounding Shift Right and Accumulate.
VRSHRN: Vector
Rounding Shift Right and Narrow.
VRSHRN (zero): Vector
Rounding Shift Right and Narrow: an alias of VMOVN.
VQRSHRN, VQRSHRUN: Vector Saturating
Rounding Shift Right, Narrow.
VQRSHRN (zero): Vector Saturating
Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating
Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VRSHR: Vector
Rounding Shift Right.
VRSHR (zero): Vector
Rounding Shift Right: an alias of VORR (register).
VRSUBHN: Vector
Rounding Subtract and Narrow, returning High Half.
VJCVT: Javascript Convert to signed fixed-point,
rounding toward Zero.
RRX: Rotate Right with Extend: an alias of MOV, MOVS (register).
RRXS: Rotate Right with Extend, setting flags: an alias of MOV, MOVS (register).
RSB, RSBS (immediate): Reverse Subtract (immediate).
RSB, RSBS (register): Reverse Subtract (register).
RSB, RSBS (register-shifted register): Reverse Subtract (register-shifted register).
RSBS (immediate): Reverse Subtract (immediate).
RSBS (register): Reverse Subtract (register).
RSBS (register-shifted register): Reverse Subtract (register-shifted register).
RSC, RSCS (immediate): Reverse Subtract with Carry (immediate).
RSC, RSCS (register): Reverse Subtract with Carry (register).
RSC, RSCS (register-shifted register): Reverse Subtract (register-shifted register).
RSCS (immediate): Reverse Subtract with Carry (immediate).
RSCS (register): Reverse Subtract with Carry (register).
RSCS (register-shifted register): Reverse Subtract (register-shifted register).
SADD8: Signed Add 8.
SASX: Signed Add and Subtract with Exchange.
SSAT16: Signed
Saturate 16.
USAT16: Unsigned
Saturate 16.
SSAT: Signed
Saturate.
USAT: Unsigned
Saturate.
VQABS: Vector
Saturating Absolute.
Saturating Add 16.
UQADD16: Unsigned
Saturating Add 16.
Saturating Add 8.
UQADD8: Unsigned
Saturating Add 8.
QASX:
Saturating Add and Subtract with Exchange.
UQASX: Unsigned
Saturating Add and Subtract with Exchange.
QADD:
Saturating Add.
VQADD: Vector
Saturating Add.
Saturating Double and Add.
Saturating Double and Subtract.
VQDMLAL: Vector
Saturating Doubling Multiply Accumulate Long.
VQDMULL: Vector
Saturating Doubling Multiply Long.
VQDMULH: Vector
Saturating Doubling Multiply Returning High Half.
VQDMLSL: Vector
Saturating Doubling Multiply Subtract Long.
VQMOVN, VQMOVUN: Vector
Saturating Move and Narrow.
VQNEG: Vector
Saturating Negate.
VQRDMLAH: Vector
Saturating Rounding Doubling Multiply Accumulate Returning High Half.
VQRDMULH: Vector
Saturating Rounding Doubling Multiply Returning High Half.
VQRDMLSH: Vector
Saturating Rounding Doubling Multiply Subtract Returning High Half.
VQRSHL: Vector
Saturating Rounding Shift Left.
VQRSHRN, VQRSHRUN: Vector
Saturating Rounding Shift Right, Narrow.
VQRSHRN (zero): Vector
Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector
Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHL, VQSHLU (immediate): Vector
Saturating Shift Left (immediate).
VQSHL (register): Vector
Saturating Shift Left (register).
VQSHRN, VQSHRUN: Vector
Saturating Shift Right, Narrow.
VQSHRN (zero): Vector
Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector
Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
Saturating Subtract 16.
UQSUB16: Unsigned
Saturating Subtract 16.
Saturating Subtract 8.
UQSUB8: Unsigned
Saturating Subtract 8.
QSAX:
Saturating Subtract and Add with Exchange.
UQSAX: Unsigned
Saturating Subtract and Add with Exchange.
QSUB:
Saturating Subtract.
VQSUB: Vector
Saturating Subtract.
SBC, SBCS (immediate): Subtract with Carry (immediate).
SBC, SBCS (register): Subtract with Carry (register).
SBC, SBCS (register-shifted register): Subtract with Carry (register-shifted register).
SBCS (immediate): Subtract with Carry (immediate).
SBCS (register): Subtract with Carry (register).
SBCS (register-shifted register): Subtract with Carry (register-shifted register).
SBFX: Signed Bit Field Extract.
scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or zero extension.
VFMAL (by scalar): Vector Floating-point Multiply-Add Long to accumulator (by
scalar).
VFMSL (by scalar): Vector Floating-point Multiply-Subtract Long from accumulator (by
scalar).
VMLA (by scalar): Vector Multiply Accumulate (by
scalar).
VMLAL (by scalar): Vector Multiply Accumulate Long (by
scalar).
VMLS (by scalar): Vector Multiply Subtract (by
scalar).
VMLSL (by scalar): Vector Multiply Subtract Long (by
scalar).
VMUL (by scalar): Vector Multiply (by
scalar).
VMULL (by scalar): Vector Multiply Long (by
scalar).
scalar): Copy a general-purpose register to a vector element.
SHA1SU0: SHA1
schedule update 0.
SHA256SU0: SHA256
schedule update 0.
SHA1SU1: SHA1
schedule update 1.
SHA256SU1: SHA256
schedule update 1.
SDIV: Signed Divide.
SMC:
Secure Monitor Call.
SEL: Select Bytes.
SEL:
Select Bytes.
VBSL: Vector Bitwise
Select.
VSELEQ, VSELGE, VSELGT, VSELVS: Floating-point conditional
select.
SEVL:
Send Event Local.
SEV:
Send Event.
VCNT: Vector Count
Set Bits.
Set Endianness.
Set Privileged Access Never.
SETEND: Set Endianness.
SETPAN: Set Privileged Access Never.
SEV: Send Event.
SEVL: Send Event Local.
SHA1 fixed rotate.
SHA1 hash update (choose).
SHA1 hash update (majority).
SHA1 hash update (parity).
SHA1 schedule update 0.
SHA1 schedule update 1.
SHA1C: SHA1 hash update (choose).
SHA1H: SHA1 fixed rotate.
SHA1M: SHA1 hash update (majority).
SHA1P: SHA1 hash update (parity).
SHA1SU0: SHA1 schedule update 0.
SHA1SU1: SHA1 schedule update 1.
SHA256 hash update part 1.
SHA256 hash update part 2.
SHA256 schedule update 0.
SHA256 schedule update 1.
SHA256H2: SHA256 hash update part 2.
SHA256H: SHA256 hash update part 1.
SHA256SU0: SHA256 schedule update 0.
SHA256SU1: SHA256 schedule update 1.
SHADD16: Signed Halving Add 16.
SHADD8: Signed Halving Add 8.
SHASX: Signed Halving Add and Subtract with Exchange.
VQSHL, VQSHLU (immediate): Vector Saturating
Shift Left (immediate).
VSHL (immediate): Vector
Shift Left (immediate).
LSL (immediate): Logical
Shift Left (immediate): an alias of MOV, MOVS (register).
VQSHL (register): Vector Saturating
Shift Left (register).
VSHL (register): Vector
Shift Left (register).
LSL (register): Logical
Shift Left (register): an alias of MOV, MOVS (register-shifted register).
VSLI: Vector
Shift Left and Insert.
VSHLL: Vector
Shift Left Long.
LSLS (immediate): Logical
Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).
LSLS (register): Logical
Shift Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VQRSHL: Vector Saturating Rounding
Shift Left.
VRSHL: Vector Rounding
Shift Left.
ASR (immediate): Arithmetic
Shift Right (immediate): an alias of MOV, MOVS (register).
LSR (immediate): Logical
Shift Right (immediate): an alias of MOV, MOVS (register).
ASR (register): Arithmetic
Shift Right (register): an alias of MOV, MOVS (register-shifted register).
LSR (register): Logical
Shift Right (register): an alias of MOV, MOVS (register-shifted register).
VRSRA: Vector Rounding
Shift Right and Accumulate.
VSRA: Vector
Shift Right and Accumulate.
VSRI: Vector
Shift Right and Insert.
VRSHRN: Vector Rounding
Shift Right and Narrow.
VRSHRN (zero): Vector Rounding
Shift Right and Narrow: an alias of VMOVN.
VSHRN: Vector
Shift Right Narrow.
VSHRN (zero): Vector
Shift Right Narrow: an alias of VMOVN.
VQRSHRN, VQRSHRUN: Vector Saturating Rounding
Shift Right, Narrow.
VQSHRN, VQSHRUN: Vector Saturating
Shift Right, Narrow.
VQRSHRN (zero): Vector Saturating Rounding
Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding
Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating
Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating
Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
ASRS (immediate): Arithmetic
Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
LSRS (immediate): Logical
Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).
ASRS (register): Arithmetic
Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
LSRS (register): Logical
Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).
VRSHR: Vector Rounding
Shift Right.
VSHR: Vector
Shift Right.
VRSHR (zero): Vector Rounding
Shift Right: an alias of VORR (register).
VSHR (zero): Vector
Shift Right: an alias of VORR (register).
ADC, ADCS (register-shifted register): Add with Carry (register-
shifted register).
ADD, ADDS (register-shifted register): Add (register-
shifted register).
AND, ANDS (register-shifted register): Bitwise AND (register-
shifted register).
ASR (register): Arithmetic Shift Right (register): an alias of MOV, MOVS (register-
shifted register).
ASRS (register): Arithmetic Shift Right, setting flags (register): an alias of MOV, MOVS (register-
shifted register).
BIC, BICS (register-shifted register): Bitwise Bit Clear (register-
shifted register).
CMN (register-shifted register): Compare Negative (register-
shifted register).
CMP (register-shifted register): Compare (register-
shifted register).
EOR, EORS (register-shifted register): Bitwise Exclusive OR (register-
shifted register).
LSL (register): Logical Shift Left (register): an alias of MOV, MOVS (register-
shifted register).
LSLS (register): Logical Shift Left, setting flags (register): an alias of MOV, MOVS (register-
shifted register).
LSR (register): Logical Shift Right (register): an alias of MOV, MOVS (register-
shifted register).
LSRS (register): Logical Shift Right, setting flags (register): an alias of MOV, MOVS (register-
shifted register).
MOV, MOVS (register-shifted register): Move (register-
shifted register).
MVN, MVNS (register-shifted register): Bitwise NOT (register-
shifted register).
ORR, ORRS (register-shifted register): Bitwise OR (register-
shifted register).
ROR (register): Rotate Right (register): an alias of MOV, MOVS (register-
shifted register).
RORS (register): Rotate Right, setting flags (register): an alias of MOV, MOVS (register-
shifted register).
RSB, RSBS (register-shifted register): Reverse Subtract (register-
shifted register).
RSC, RSCS (register-shifted register): Reverse Subtract (register-
shifted register).
SBC, SBCS (register-shifted register): Subtract with Carry (register-
shifted register).
SUB, SUBS (register-shifted register): Subtract (register-
shifted register).
TEQ (register-shifted register): Test Equivalence (register-
shifted register).
TST (register-shifted register): Test (register-
shifted register).
shifted register): Add (register-shifted register).
shifted register): Add with Carry (register-shifted register).
shifted register): Bitwise AND (register-shifted register).
shifted register): Bitwise Bit Clear (register-shifted register).
shifted register): Bitwise Exclusive OR (register-shifted register).
shifted register): Bitwise NOT (register-shifted register).
shifted register): Bitwise OR (register-shifted register).
shifted register): Compare (register-shifted register).
shifted register): Compare Negative (register-shifted register).
shifted register): Move (register-shifted register).
shifted register): Reverse Subtract (register-shifted register).
shifted register): Reverse Subtract (register-shifted register).
shifted register): Subtract (register-shifted register).
shifted register): Subtract with Carry (register-shifted register).
shifted register): Test (register-shifted register).
shifted register): Test Equivalence (register-shifted register).
SHSAX: Signed Halving Subtract and Add with Exchange.
SHSUB16: Signed Halving Subtract 16.
SHSUB8: Signed Halving Subtract 8.
VCLS: Vector Count Leading
Sign Bits.
VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with
sign or zero extension.
Signed Add 16.
Signed Add 8.
SASX:
Signed Add and Subtract with Exchange.
SBFX:
Signed Bit Field Extract.
LDRSB (immediate): Load Register
Signed Byte (immediate).
LDRSB (literal): Load Register
Signed Byte (literal).
LDRSB (register): Load Register
Signed Byte (register).
LDRSBT: Load Register
Signed Byte Unprivileged.
SDIV:
Signed Divide.
Signed Dual Multiply Add.
Signed Extend and Add Byte 16.
Signed Extend and Add Byte.
Signed Extend and Add Halfword.
Signed Extend Byte 16.
SXTB:
Signed Extend Byte.
SXTH:
Signed Extend Halfword.
VJCVT: Javascript Convert to
signed fixed-point, rounding toward Zero.
LDRSH (immediate): Load Register
Signed Halfword (immediate).
LDRSH (literal): Load Register
Signed Halfword (literal).
LDRSH (register): Load Register
Signed Halfword (register).
LDRSHT: Load Register
Signed Halfword Unprivileged.
REVSH: Byte-Reverse
Signed Halfword.
Signed Halving Add 16.
Signed Halving Add 8.
Signed Halving Add and Subtract with Exchange.
Signed Halving Subtract 16.
Signed Halving Subtract 8.
Signed Halving Subtract and Add with Exchange.
VSDOT (by element): Dot Product index form with
signed integers..
VSDOT (vector): Dot Product vector form with
signed integers..
Signed Most Significant Word Multiply Accumulate.
Signed Most Significant Word Multiply Subtract.
Signed Most Significant Word Multiply.
Signed Multiply (halfwords).
Signed Multiply (word by halfword).
Signed Multiply Accumulate (halfwords).
Signed Multiply Accumulate (word by halfword).
Signed Multiply Accumulate Dual.
Signed Multiply Accumulate Long (halfwords).
Signed Multiply Accumulate Long Dual.
Signed Multiply Accumulate Long.
Signed Multiply Long.
Signed Multiply Subtract Dual.
Signed Multiply Subtract Dual.
Signed Multiply Subtract Long Dual.
Signed Saturate 16.
SSAT:
Signed Saturate.
Signed Subtract 16.
Signed Subtract 8.
SSAX:
Signed Subtract and Add with Exchange.
SMMLA, SMMLAR: Signed Most
Significant Word Multiply Accumulate.
SMMLS, SMMLSR: Signed Most
Significant Word Multiply Subtract.
SMMUL, SMMULR: Signed Most
Significant Word Multiply.
VMOV (register, SIMD): Copy between
SIMD registers: an alias of VORR (register).
VLDR (immediate): Load
SIMD&FP register (immediate).
VLDR (literal): Load
SIMD&FP register (literal).
VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit
SIMD&FP register.
VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit
SIMD&FP register.
VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a
SIMD&FP register.
VMOV (immediate): Copy immediate value to a
SIMD&FP register.
VSTR: Store
SIMD&FP register.
VPOP: Pop
SIMD&FP registers from Stack: an alias of VLDM, VLDMDB, VLDMIA.
VPUSH: Push
SIMD&FP registers to Stack: an alias of VSTM, VSTMDB, VSTMIA.
VLDM, VLDMDB, VLDMIA: Load Multiple
SIMD&FP registers.
VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit
SIMD&FP registers.
VSTM, VSTMDB, VSTMIA: Store multiple
SIMD&FP registers.
VMRS: Move
SIMD&FP Special register to general-purpose register.
VMSR: Move general-purpose register to
SIMD&FP Special register.
SIMD): Copy between SIMD registers: an alias of VORR (register).
SIMD): Vector Convert between floating-point and fixed-point.
SIMD): Vector Convert between floating-point and integer.
SIMD): Vector Convert between half-precision and single-precision.
SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to Away.
SIMD): Vector Convert floating-point to integer with Round to Nearest.
SIMD): Vector Convert floating-point to integer with Round towards +Infinity.
SIMD): Vector Convert floating-point to integer with Round towards -Infinity.
SIMD): Vector round floating-point to integer inexact.
SIMD): Vector Round floating-point to integer to Nearest.
SIMD): Vector Round floating-point to integer towards +Infinity.
SIMD): Vector Round floating-point to integer towards -Infinity.
SIMD): Vector Round floating-point to integer towards Nearest with Ties to Away.
SIMD): Vector round floating-point to integer towards Zero.
single 1-element structure and replicate to all lanes of one register.
single 1-element structure to one lane of one register.
VLD1 (multiple single elements): Load multiple
single 1-element structures to one, two, three, or four registers.
single 2-element structure and replicate to all lanes of two registers.
single 2-element structure from one lane of two registers.
single 2-element structure from one lane): Store single 2-element structure from one lane of two registers.
single 2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.
single 2-element structure to one lane of two registers.
single 2-element structure to one lane): Load single 2-element structure to one lane of two registers.
single 3-element structure and replicate to all lanes of three registers.
single 3-element structure from one lane of three registers.
single 3-element structure from one lane): Store single 3-element structure from one lane of three registers.
single 3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.
single 3-element structure to one lane of three registers.
single 3-element structure to one lane): Load single 3-element structure to one lane of three registers.
single 4-element structure and replicate to all lanes of four registers.
single 4-element structure from one lane of four registers.
single 4-element structure from one lane): Store single 4-element structure from one lane of four registers.
single 4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.
single 4-element structure to one lane of four registers.
single 4-element structure to one lane): Load single 4-element structure to one lane of four registers.
single element from one lane of one register.
single element from one lane): Store single element from one lane of one register.
single element to all lanes): Load single 1-element structure and replicate to all lanes of one register.
single element to one lane): Load single 1-element structure to one lane of one register.
VST1 (multiple single elements): Store multiple
single elements from one, two, three, or four registers.
single elements): Load multiple single 1-element structures to one, two, three, or four registers.
single elements): Store multiple single elements from one, two, three, or four registers.
Single Register from Stack: an alias of LDR (immediate).
PUSH (single register): Push
Single Register to Stack: an alias of STR (immediate).
single register): Pop Single Register from Stack: an alias of LDR (immediate).
single register): Push Single Register to Stack: an alias of STR (immediate).
AESD: AES
single round decryption.
AESE: AES
single round encryption.
VCVTB: Convert to or from a half-precision value in the bottom half of a
single-precision register.
VCVTT: Convert to or from a half-precision value in the top half of a
single-precision register.
single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
single-precision): Convert between double-precision and single-precision.
single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
VCVT (between double-precision and single-precision): Convert between double-precision and
single-precision.
VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and
single-precision.
SMC: Secure Monitor Call.
SMLABB, SMLABT, SMLATB, SMLATT: Signed Multiply Accumulate (halfwords).
SMLABT, SMLATB, SMLATT: Signed Multiply Accumulate (halfwords).
SMLAD, SMLADX: Signed Multiply Accumulate Dual.
SMLAL, SMLALS: Signed Multiply Accumulate Long.
SMLALBB, SMLALBT, SMLALTB, SMLALTT: Signed Multiply Accumulate Long (halfwords).
SMLALBT, SMLALTB, SMLALTT: Signed Multiply Accumulate Long (halfwords).
SMLALD, SMLALDX: Signed Multiply Accumulate Long Dual.
SMLALTB, SMLALTT: Signed Multiply Accumulate Long (halfwords).
SMLALTT: Signed Multiply Accumulate Long (halfwords).
SMLATB, SMLATT: Signed Multiply Accumulate (halfwords).
SMLATT: Signed Multiply Accumulate (halfwords).
SMLAWB, SMLAWT: Signed Multiply Accumulate (word by halfword).
SMLSD, SMLSDX: Signed Multiply Subtract Dual.
SMLSLD, SMLSLDX: Signed Multiply Subtract Long Dual.
SMMLA, SMMLAR: Signed Most Significant Word Multiply Accumulate.
SMMLS, SMMLSR: Signed Most Significant Word Multiply Subtract.
SMMUL, SMMULR: Signed Most Significant Word Multiply.
SMUAD, SMUADX: Signed Dual Multiply Add.
SMULBB, SMULBT, SMULTB, SMULTT: Signed Multiply (halfwords).
SMULBT, SMULTB, SMULTT: Signed Multiply (halfwords).
SMULL, SMULLS: Signed Multiply Long.
SMULTB, SMULTT: Signed Multiply (halfwords).
SMULTT: Signed Multiply (halfwords).
SMULWB, SMULWT: Signed Multiply (word by halfword).
SMUSD, SMUSDX: Signed Multiply Subtract Dual.
ADD, ADDS (SP plus immediate): Add to
SP (immediate).
SUB, SUBS (SP minus immediate): Subtract from
SP (immediate).
ADD, ADDS (SP plus register): Add to
SP (register).
SUB, SUBS (SP minus register): Subtract from
SP (register).
SP minus immediate): Subtract from SP (immediate).
SP minus register): Subtract from SP (register).
SP plus immediate): Add to SP (immediate).
SP plus register): Add to SP (register).
MRS (Banked register): Move Banked or
Special register to general-purpose register.
MRS: Move
Special register to general-purpose register.
VMRS: Move SIMD&FP
Special register to general-purpose register.
MSR (Banked register): Move general-purpose register to Banked or
Special register.
MSR (immediate): Move immediate value to
Special register.
MSR (register): Move general-purpose register to
Special register.
VMSR: Move general-purpose register to SIMD&FP
Special register.
VRSQRTE: Vector Reciprocal
Square Root Estimate.
VRSQRTS: Vector Reciprocal
Square Root Step.
Square Root.
SRS, SRSDA, SRSDB, SRSIA, SRSIB: Store Return State.
SRSDA, SRSDB, SRSIA, SRSIB: Store Return State.
SRSDB, SRSIA, SRSIB: Store Return State.
SRSIA, SRSIB: Store Return State.
SRSIB: Store Return State.
SSAT16: Signed Saturate 16.
SSAT: Signed Saturate.
SSAX: Signed Subtract and Add with Exchange.
SSUB16: Signed Subtract 16.
SSUB8: Signed Subtract 8.
POP: Pop Multiple Registers from
Stack.
PUSH: Push Multiple Registers to
Stack.
POP (multiple registers): Pop Multiple Registers from
Stack: an alias of LDM, LDMIA, LDMFD.
POP (single register): Pop Single Register from
Stack: an alias of LDR (immediate).
PUSH (multiple registers): Push multiple registers to
Stack: an alias of STMDB, STMFD.
PUSH (single register): Push Single Register to
Stack: an alias of STR (immediate).
VPOP: Pop SIMD&FP registers from
Stack: an alias of VLDM, VLDMDB, VLDMIA.
VPUSH: Push SIMD&FP registers to
Stack: an alias of VSTM, VSTMDB, VSTMIA.
CPS, CPSID, CPSIE: Change PE
State.
DCPS1, DCPS2, DCPS3: Debug Change PE
State.
SRS, SRSDA, SRSDB, SRSIA, SRSIB: Store Return
State.
STC: Store data to System register.
VRECPS: Vector Reciprocal
Step.
VRSQRTS: Vector Reciprocal Square Root
Step.
STL: Store-Release Word.
STLB: Store-Release Byte.
STLEX: Store-Release Exclusive Word.
STLEXB: Store-Release Exclusive Byte.
STLEXD: Store-Release Exclusive Doubleword.
STLEXH: Store-Release Exclusive Halfword.
STLH: Store-Release Halfword.
STM (User registers): Store Multiple (User registers).
STM, STMIA, STMEA: Store Multiple (Increment After, Empty Ascending).
STMDA, STMED: Store Multiple Decrement After (Empty Descending).
PUSH (multiple registers): Push multiple registers to Stack: an alias of
STMDB, STMFD.
STMDB, STMFD: Store Multiple Decrement Before (Full Descending).
STMEA: Store Multiple (Increment After, Empty Ascending).
PUSH (multiple registers): Push multiple registers to Stack: an alias of STMDB,
STMFD.
STMIA, STMEA: Store Multiple (Increment After, Empty Ascending).
STMIB, STMFA: Store Multiple Increment Before (Full Ascending).
STC:
Store data to System register.
Store Multiple (Increment After, Empty Ascending).
Store Multiple (User registers).
Store multiple 2-element structures from two or four registers.
Store multiple 3-element structures from three registers.
Store multiple 4-element structures from four registers.
Store Multiple Decrement After (Empty Descending).
Store Multiple Decrement Before (Full Descending).
Store Multiple Increment Before (Full Ascending).
Store multiple SIMD&FP registers.
Store multiple single elements from one, two, three, or four registers.
Store Register (immediate).
Store Register (register).
Store Register Byte (immediate).
Store Register Byte (register).
Store Register Byte Unprivileged.
Store Register Dual (immediate).
Store Register Dual (register).
Store Register Exclusive Byte.
Store Register Exclusive Doubleword.
Store Register Exclusive Halfword.
Store Register Exclusive.
Store Register Halfword (immediate).
Store Register Halfword (register).
Store Register Halfword Unprivileged.
STRT:
Store Register Unprivileged.
Store Return State.
VSTR:
Store SIMD&FP register.
Store single 2-element structure from one lane of two registers.
Store single 3-element structure from one lane of three registers.
Store single 4-element structure from one lane of four registers.
Store single element from one lane of one register.
STLB:
Store-Release Byte.
Store-Release Exclusive Byte.
Store-Release Exclusive Doubleword.
Store-Release Exclusive Halfword.
Store-Release Exclusive Word.
STLH:
Store-Release Halfword.
STL:
Store-Release Word.
PUSH (single register): Push Single Register to Stack: an alias of
STR (immediate).
STR (immediate): Store Register (immediate).
STR (register): Store Register (register).
STRB (immediate): Store Register Byte (immediate).
STRB (register): Store Register Byte (register).
STRBT: Store Register Byte Unprivileged.
STRD (immediate): Store Register Dual (immediate).
STRD (register): Store Register Dual (register).
STREX: Store Register Exclusive.
STREXB: Store Register Exclusive Byte.
STREXD: Store Register Exclusive Doubleword.
STREXH: Store Register Exclusive Halfword.
STRH (immediate): Store Register Halfword (immediate).
STRH (register): Store Register Halfword (register).
STRHT: Store Register Halfword Unprivileged.
STRT: Store Register Unprivileged.
VLD4 (single 4-element structure to all lanes): Load single 4-element
structure and replicate to all lanes of four registers.
VLD1 (single element to all lanes): Load single 1-element
structure and replicate to all lanes of one register.
VLD3 (single 3-element structure to all lanes): Load single 3-element
structure and replicate to all lanes of three registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element
structure and replicate to all lanes of two registers.
VST4 (single 4-element structure from one lane): Store single 4-element
structure from one lane of four registers.
VST3 (single 3-element structure from one lane): Store single 3-element
structure from one lane of three registers.
VST2 (single 2-element structure from one lane): Store single 2-element
structure from one lane of two registers.
structure from one lane): Store single 2-element structure from one lane of two registers.
structure from one lane): Store single 3-element structure from one lane of three registers.
structure from one lane): Store single 4-element structure from one lane of four registers.
structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.
structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.
structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.
VLD4 (single 4-element structure to one lane): Load single 4-element
structure to one lane of four registers.
VLD1 (single element to one lane): Load single 1-element
structure to one lane of one register.
VLD3 (single 3-element structure to one lane): Load single 3-element
structure to one lane of three registers.
VLD2 (single 2-element structure to one lane): Load single 2-element
structure to one lane of two registers.
structure to one lane): Load single 2-element structure to one lane of two registers.
structure to one lane): Load single 3-element structure to one lane of three registers.
structure to one lane): Load single 4-element structure to one lane of four registers.
VST4 (multiple 4-element structures): Store multiple 4-element
structures from four registers.
VST3 (multiple 3-element structures): Store multiple 3-element
structures from three registers.
VST2 (multiple 2-element structures): Store multiple 2-element
structures from two or four registers.
VLD4 (multiple 4-element structures): Load multiple 4-element
structures to four registers.
VLD1 (multiple single elements): Load multiple single 1-element
structures to one, two, three, or four registers.
VLD3 (multiple 3-element structures): Load multiple 3-element
structures to three registers.
VLD2 (multiple 2-element structures): Load multiple 2-element
structures to two or four registers.
structures): Load multiple 2-element structures to two or four registers.
structures): Load multiple 3-element structures to three registers.
structures): Load multiple 4-element structures to four registers.
structures): Store multiple 2-element structures from two or four registers.
structures): Store multiple 3-element structures from three registers.
structures): Store multiple 4-element structures from four registers.
SUB (immediate, from PC): Subtract from PC: an alias of ADR.
SUB, SUBS (immediate): Subtract (immediate).
SUB, SUBS (register): Subtract (register).
SUB, SUBS (register-shifted register): Subtract (register-shifted register).
SUB, SUBS (SP minus immediate): Subtract from SP (immediate).
SUB, SUBS (SP minus register): Subtract from SP (register).
SUBS (immediate): Subtract (immediate).
SUBS (register): Subtract (register).
SUBS (register-shifted register): Subtract (register-shifted register).
SUBS (SP minus immediate): Subtract from SP (immediate).
SUBS (SP minus register): Subtract from SP (register).
VMLS (by scalar): Vector Multiply
Subtract (by scalar).
VMLS (floating-point): Vector Multiply
Subtract (floating-point).
VSUB (floating-point): Vector
Subtract (floating-point).
RSB, RSBS (immediate): Reverse
Subtract (immediate).
Subtract (immediate).
VMLS (integer): Vector Multiply
Subtract (integer).
VSUB (integer): Vector
Subtract (integer).
RSB, RSBS (register): Reverse
Subtract (register).
Subtract (register).
Subtract (register-shifted register).
Subtract (register-shifted register).
Subtract (register-shifted register).
QSUB16: Saturating
Subtract 16.
SHSUB16: Signed Halving
Subtract 16.
SSUB16: Signed
Subtract 16.
UHSUB16: Unsigned Halving
Subtract 16.
UQSUB16: Unsigned Saturating
Subtract 16.
USUB16: Unsigned
Subtract 16.
QSUB8: Saturating
Subtract 8.
SHSUB8: Signed Halving
Subtract 8.
SSUB8: Signed
Subtract 8.
UHSUB8: Unsigned Halving
Subtract 8.
UQSUB8: Unsigned Saturating
Subtract 8.
USUB8: Unsigned
Subtract 8.
QSAX: Saturating
Subtract and Add with Exchange.
SHSAX: Signed Halving
Subtract and Add with Exchange.
SSAX: Signed
Subtract and Add with Exchange.
UHSAX: Unsigned Halving
Subtract and Add with Exchange.
UQSAX: Unsigned Saturating
Subtract and Add with Exchange.
USAX: Unsigned
Subtract and Add with Exchange.
VRSUBHN: Vector Rounding
Subtract and Narrow, returning High Half.
VSUBHN: Vector
Subtract and Narrow, returning High Half.
SMLSD, SMLSDX: Signed Multiply
Subtract Dual.
SMUSD, SMUSDX: Signed Multiply
Subtract Dual.
Subtract from PC: an alias of ADR.
Subtract from SP (immediate).
Subtract from SP (register).
VMLSL (by scalar): Vector Multiply
Subtract Long (by scalar).
VMLSL (integer): Vector Multiply
Subtract Long (integer).
SMLSLD, SMLSLDX: Signed Multiply
Subtract Long Dual.
VFMSL (by scalar): Vector Floating-point Multiply-
Subtract Long from accumulator (by scalar).
VFMSL (vector): Vector Floating-point Multiply-
Subtract Long from accumulator (vector).
VQDMLSL: Vector Saturating Doubling Multiply
Subtract Long.
VSUBL: Vector
Subtract Long.
VQRDMLSH: Vector Saturating Rounding Doubling Multiply
Subtract Returning High Half.
VSUBW: Vector
Subtract Wide.
RSC, RSCS (immediate): Reverse
Subtract with Carry (immediate).
Subtract with Carry (immediate).
RSC, RSCS (register): Reverse
Subtract with Carry (register).
Subtract with Carry (register).
Subtract with Carry (register-shifted register).
QASX: Saturating Add and
Subtract with Exchange.
SASX: Signed Add and
Subtract with Exchange.
SHASX: Signed Halving Add and
Subtract with Exchange.
UASX: Unsigned Add and
Subtract with Exchange.
UHASX: Unsigned Halving Add and
Subtract with Exchange.
UQASX: Unsigned Saturating Add and
Subtract with Exchange.
MLS: Multiply and
Subtract.
QDSUB: Saturating Double and
Subtract.
QSUB: Saturating
Subtract.
SMMLS, SMMLSR: Signed Most Significant Word Multiply
Subtract.
VFMS: Vector Fused Multiply
Subtract.
VFNMS: Vector Fused Negate Multiply
Subtract.
VHSUB: Vector Halving
Subtract.
VNMLS: Vector Negate Multiply
Subtract.
VQSUB: Vector Saturating
Subtract.
USADA8: Unsigned
Sum of Absolute Differences and Accumulate.
USAD8: Unsigned
Sum of Absolute Differences.
SVC:
Supervisor Call.
SVC: Supervisor Call.
VSWP: Vector
Swap.
SXTAB16: Signed Extend and Add Byte 16.
SXTAB: Signed Extend and Add Byte.
SXTAH: Signed Extend and Add Halfword.
SXTB16: Signed Extend Byte 16.
SXTB: Signed Extend Byte.
SXTH: Signed Extend Halfword.
DSB: Data
Synchronization Barrier.
ESB: Error
Synchronization Barrier.
ISB: Instruction
Synchronization Barrier.
MCR: Move to System register from general-purpose register or execute a
System instruction.
LDC (immediate): Load data to
System register (immediate).
LDC (literal): Load data to
System register (literal).
MCR: Move to
System register from general-purpose register or execute a System instruction.
MCRR: Move to
System register from two general-purpose registers.
MRC: Move to general-purpose register from
System register.
MRRC: Move to two general-purpose registers from
System register.
STC: Store data to
System register.
VTBL, VTBX: Vector
Table Lookup and Extension.
TBB, TBH: Table Branch Byte or Halfword.
TEQ (immediate): Test Equivalence (immediate).
TEQ (register): Test Equivalence (register).
TEQ (register-shifted register): Test Equivalence (register-shifted register).
Test (immediate).
Test (register).
Test (register-shifted register).
VTST: Vector
Test Bits.
Test Equivalence (immediate).
Test Equivalence (register).
Test Equivalence (register-shifted register).
VCGE (immediate #0): Vector Compare Greater
Than or Equal to Zero.
VCLE (immediate #0): Vector Compare Less
Than or Equal to Zero.
VACGE: Vector Absolute Compare Greater
Than or Equal.
VCGE (register): Vector Compare Greater
Than or Equal.
VACLE: Vector Absolute Compare Less
Than or Equal: an alias of VACGE.
VCLE (register): Vector Compare Less
Than or Equal: an alias of VCGE (register).
VCGT (immediate #0): Vector Compare Greater
Than Zero.
VCLT (immediate #0): Vector Compare Less
Than Zero.
VACGT: Vector Absolute Compare Greater
Than.
VCGT (register): Vector Compare Greater
Than.
VACLT: Vector Absolute Compare Less
Than: an alias of VACGT.
VCLT (register): Vector Compare Less
Than: an alias of VCGT (register).
IT: If-
Then.
VLD3 (multiple 3-element structures): Load multiple 3-element structures to
three registers.
VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of
three registers.
VLD3 (single 3-element structure to one lane): Load single 3-element structure to one lane of
three registers.
VST3 (multiple 3-element structures): Store multiple 3-element structures from
three registers.
VST3 (single 3-element structure from one lane): Store single 3-element structure from one lane of
three registers.
VLD1 (multiple single elements): Load multiple single 1-element structures to one, two,
three, or four registers.
VST1 (multiple single elements): Store multiple single elements from one, two,
three, or four registers.
VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with
Ties to Away.
VCVTA (floating-point): Convert floating-point to integer with Round to Nearest with
Ties to Away.
VRINTA (Advanced SIMD): Vector Round floating-point to integer towards Nearest with
Ties to Away.
VRINTA (floating-point): Round floating-point to integer to Nearest with
Ties to Away.
VCVTT: Convert to or from a half-precision value in the
top half of a single-precision register.
MOVT: Move
Top.
VJCVT: Javascript Convert to signed fixed-point, rounding
toward Zero.
VCVTP (Advanced SIMD): Vector Convert floating-point to integer with Round
towards +Infinity.
VCVTP (floating-point): Convert floating-point to integer with Round
towards +Infinity.
VRINTP (Advanced SIMD): Vector Round floating-point to integer
towards +Infinity.
VRINTP (floating-point): Round floating-point to integer
towards +Infinity.
VCVTM (Advanced SIMD): Vector Convert floating-point to integer with Round
towards -Infinity.
VCVTM (floating-point): Convert floating-point to integer with Round
towards -Infinity.
VRINTM (Advanced SIMD): Vector Round floating-point to integer
towards -Infinity.
VRINTM (floating-point): Round floating-point to integer
towards -Infinity.
VRINTA (Advanced SIMD): Vector Round floating-point to integer
towards Nearest with Ties to Away.
VCVT (floating-point to integer, floating-point): Convert floating-point to integer with Round
towards Zero.
VRINTZ (Advanced SIMD): Vector round floating-point to integer
towards Zero.
VRINTZ (floating-point): Round floating-point to integer
towards Zero.
VTRN: Vector
Transpose.
VBIT: Vector Bitwise Insert if
True.
TST (immediate): Test (immediate).
TST (register): Test (register).
TST (register-shifted register): Test (register-shifted register).
two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
MRRC: Move to
two general-purpose registers from System register.
two general-purpose registers to a pair of 32-bit SIMD&FP registers.
two general-purpose registers to or from a SIMD&FP register.
MCRR: Move to System register from
two general-purpose registers.
VLD2 (multiple 2-element structures): Load multiple 2-element structures to
two or four registers.
VST2 (multiple 2-element structures): Store multiple 2-element structures from
two or four registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of
two registers.
VLD2 (single 2-element structure to one lane): Load single 2-element structure to one lane of
two registers.
VST2 (single 2-element structure from one lane): Store single 2-element structure from one lane of
two registers.
two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
VLD1 (multiple single elements): Load multiple single 1-element structures to one,
two, three, or four registers.
VST1 (multiple single elements): Store multiple single elements from one,
two, three, or four registers.
UADD8: Unsigned Add 8.
UASX: Unsigned Add and Subtract with Exchange.
UBFX: Unsigned Bit Field Extract.
UDF: Permanently Undefined.
UDIV: Unsigned Divide.
UHADD16: Unsigned Halving Add 16.
UHADD8: Unsigned Halving Add 8.
UHASX: Unsigned Halving Add and Subtract with Exchange.
UHSAX: Unsigned Halving Subtract and Add with Exchange.
UHSUB16: Unsigned Halving Subtract 16.
UHSUB8: Unsigned Halving Subtract 8.
UMAAL: Unsigned Multiply Accumulate Accumulate Long.
UMLAL, UMLALS: Unsigned Multiply Accumulate Long.
UMULL, UMULLS: Unsigned Multiply Long.
UDF: Permanently
Undefined.
LDRBT: Load Register Byte
Unprivileged.
LDRHT: Load Register Halfword
Unprivileged.
LDRSBT: Load Register Signed Byte
Unprivileged.
LDRSHT: Load Register Signed Halfword
Unprivileged.
LDRT: Load Register
Unprivileged.
STRBT: Store Register Byte
Unprivileged.
STRHT: Store Register Halfword
Unprivileged.
STRT: Store Register
Unprivileged.
Unsigned Add 16.
Unsigned Add 8.
UASX:
Unsigned Add and Subtract with Exchange.
UBFX:
Unsigned Bit Field Extract.
UDIV:
Unsigned Divide.
Unsigned Extend and Add Byte 16.
Unsigned Extend and Add Byte.
Unsigned Extend and Add Halfword.
Unsigned Extend Byte 16.
UXTB:
Unsigned Extend Byte.
UXTH:
Unsigned Extend Halfword.
Unsigned Halving Add 16.
Unsigned Halving Add 8.
Unsigned Halving Add and Subtract with Exchange.
Unsigned Halving Subtract 16.
Unsigned Halving Subtract 8.
Unsigned Halving Subtract and Add with Exchange.
VUDOT (by element): Dot Product index form with
unsigned integers..
VUDOT (vector): Dot Product vector form with
unsigned integers..
Unsigned Multiply Accumulate Accumulate Long.
Unsigned Multiply Accumulate Long.
Unsigned Multiply Long.
Unsigned Saturate 16.
USAT:
Unsigned Saturate.
Unsigned Saturating Add 16.
Unsigned Saturating Add 8.
Unsigned Saturating Add and Subtract with Exchange.
Unsigned Saturating Subtract 16.
Unsigned Saturating Subtract 8.
Unsigned Saturating Subtract and Add with Exchange.
Unsigned Subtract 16.
Unsigned Subtract 8.
USAX:
Unsigned Subtract and Add with Exchange.
Unsigned Sum of Absolute Differences and Accumulate.
Unsigned Sum of Absolute Differences.
VUZP: Vector
Unzip.
VUZP (alias): Vector
Unzip: an alias of VTRN.
SHA1C: SHA1 hash
update (choose).
SHA1M: SHA1 hash
update (majority).
SHA1P: SHA1 hash
update (parity).
SHA1SU0: SHA1 schedule
update 0.
SHA256SU0: SHA256 schedule
update 0.
SHA1SU1: SHA1 schedule
update 1.
SHA256SU1: SHA256 schedule
update 1.
SHA256H: SHA256 hash
update part 1.
SHA256H2: SHA256 hash
update part 2.
UQADD16: Unsigned Saturating Add 16.
UQADD8: Unsigned Saturating Add 8.
UQASX: Unsigned Saturating Add and Subtract with Exchange.
UQSAX: Unsigned Saturating Subtract and Add with Exchange.
UQSUB16: Unsigned Saturating Subtract 16.
UQSUB8: Unsigned Saturating Subtract 8.
USAD8: Unsigned Sum of Absolute Differences.
USADA8: Unsigned Sum of Absolute Differences and Accumulate.
USAT16: Unsigned Saturate 16.
USAT: Unsigned Saturate.
USAX: Unsigned Subtract and Add with Exchange.
LDM (User registers): Load Multiple (
User registers).
STM (User registers): Store Multiple (
User registers).
User registers): Load Multiple (User registers).
User registers): Store Multiple (User registers).
USUB16: Unsigned Subtract 16.
USUB8: Unsigned Subtract 8.
UXTAB16: Unsigned Extend and Add Byte 16.
UXTAB: Unsigned Extend and Add Byte.
UXTAH: Unsigned Extend and Add Halfword.
UXTB16: Unsigned Extend Byte 16.
UXTB: Unsigned Extend Byte.
UXTH: Unsigned Extend Halfword.
VABAL: Vector Absolute Difference and Accumulate Long.
VABD (floating-point): Vector Absolute Difference (floating-point).
VABD (integer): Vector Absolute Difference (integer).
VABDL (integer): Vector Absolute Difference Long (integer).
VABS: Vector Absolute.
VACLE: Vector Absolute Compare Less Than or Equal: an alias of
VACGE.
VACGE: Vector Absolute Compare Greater Than or Equal.
VACLT: Vector Absolute Compare Less Than: an alias of
VACGT.
VACGT: Vector Absolute Compare Greater Than.
VACLE: Vector Absolute Compare Less Than or Equal: an alias of VACGE.
VACLT: Vector Absolute Compare Less Than: an alias of VACGT.
VADD (floating-point): Vector Add (floating-point).
VADD (integer): Vector Add (integer).
VADDHN: Vector Add and Narrow, returning High Half.
VADDL: Vector Add Long.
VADDW: Vector Add Wide.
VAND (immediate): Vector Bitwise AND (immediate): an alias of VBIC (immediate).
VAND (register): Vector Bitwise AND (register).
VAND (immediate): Vector Bitwise AND (immediate): an alias of
VBIC (immediate).
VBIC (immediate): Vector Bitwise Bit Clear (immediate).
VBIC (register): Vector Bitwise Bit Clear (register).
VBIF: Vector Bitwise Insert if False.
VBIT: Vector Bitwise Insert if True.
VBSL: Vector Bitwise Select.
VCADD: Vector Complex Add.
VCEQ (immediate #0): Vector Compare Equal to Zero.
VCEQ (register): Vector Compare Equal.
VCGE (immediate #0): Vector Compare Greater Than or Equal to Zero.
VCLE (register): Vector Compare Less Than or Equal: an alias of
VCGE (register).
VCGE (register): Vector Compare Greater Than or Equal.
VCGT (immediate #0): Vector Compare Greater Than Zero.
VCLT (register): Vector Compare Less Than: an alias of
VCGT (register).
VCGT (register): Vector Compare Greater Than.
VCLE (immediate #0): Vector Compare Less Than or Equal to Zero.
VCLE (register): Vector Compare Less Than or Equal: an alias of VCGE (register).
VCLS: Vector Count Leading Sign Bits.
VCLT (immediate #0): Vector Compare Less Than Zero.
VCLT (register): Vector Compare Less Than: an alias of VCGT (register).
VCLZ: Vector Count Leading Zeros.
VCMLA (by element): Vector Complex Multiply Accumulate (by element).
VCMLA: Vector Complex Multiply Accumulate.
VCMP: Vector Compare.
VCMPE: Vector Compare, raising Invalid Operation on NaN.
VCNT: Vector Count Set Bits.
VCVT (between double-precision and single-precision): Convert between double-precision and single-precision.
VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.
VCVT (between floating-point and fixed-point, floating-point): Convert between floating-point and fixed-point.
VCVT (between floating-point and integer, Advanced SIMD): Vector Convert between floating-point and integer.
VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.
VCVT (floating-point to integer, floating-point): Convert floating-point to integer with Round towards Zero.
VCVT (integer to floating-point, floating-point): Convert integer to floating-point.
VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to Away.
VCVTA (floating-point): Convert floating-point to integer with Round to Nearest with Ties to Away.
VCVTB: Convert to or from a half-precision value in the bottom half of a single-precision register.
VCVTM (Advanced SIMD): Vector Convert floating-point to integer with Round towards -Infinity.
VCVTM (floating-point): Convert floating-point to integer with Round towards -Infinity.
VCVTN (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest.
VCVTN (floating-point): Convert floating-point to integer with Round to Nearest.
VCVTP (Advanced SIMD): Vector Convert floating-point to integer with Round towards +Infinity.
VCVTP (floating-point): Convert floating-point to integer with Round towards +Infinity.
VCVTR: Convert floating-point to integer.
VCVTT: Convert to or from a half-precision value in the top half of a single-precision register.
VDIV: Divide.
VDUP (general-purpose register): Duplicate general-purpose register to vector.
VDUP (scalar): Duplicate vector element to vector.
Vector Absolute Compare Greater Than or Equal.
Vector Absolute Compare Greater Than.
Vector Absolute Compare Less Than or Equal: an alias of VACGE.
Vector Absolute Compare Less Than: an alias of VACGT.
Vector Absolute Difference (floating-point).
Vector Absolute Difference (integer).
Vector Absolute Difference and Accumulate Long.
VABA:
Vector Absolute Difference and Accumulate.
Vector Absolute Difference Long (integer).
VABS:
Vector Absolute.
Vector Add (floating-point).
Vector Add (integer).
Vector Add and Narrow, returning High Half.
Vector Add Long.
Vector Add Wide.
Vector Bitwise AND (immediate): an alias of VBIC (immediate).
Vector Bitwise AND (register).
Vector Bitwise Bit Clear (immediate).
Vector Bitwise Bit Clear (register).
VEOR:
Vector Bitwise Exclusive OR.
VBIF:
Vector Bitwise Insert if False.
VBIT:
Vector Bitwise Insert if True.
Vector Bitwise NOT (immediate).
Vector Bitwise NOT (register).
Vector Bitwise OR (immediate).
Vector bitwise OR (register).
Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).
Vector bitwise OR NOT (register).
VBSL:
Vector Bitwise Select.
Vector Compare Equal to Zero.
Vector Compare Equal.
Vector Compare Greater Than or Equal to Zero.
Vector Compare Greater Than or Equal.
Vector Compare Greater Than Zero.
Vector Compare Greater Than.
Vector Compare Less Than or Equal to Zero.
Vector Compare Less Than or Equal: an alias of VCGE (register).
Vector Compare Less Than Zero.
Vector Compare Less Than: an alias of VCGT (register).
Vector Compare, raising Invalid Operation on NaN.
VCMP:
Vector Compare.
Vector Complex Add.
Vector Complex Multiply Accumulate (by element).
Vector Complex Multiply Accumulate.
Vector Convert between floating-point and fixed-point.
Vector Convert between floating-point and integer.
Vector Convert between half-precision and single-precision.
Vector Convert floating-point to integer with Round to Nearest with Ties to Away.
Vector Convert floating-point to integer with Round to Nearest.
Vector Convert floating-point to integer with Round towards +Infinity.
Vector Convert floating-point to integer with Round towards -Infinity.
VCLS:
Vector Count Leading Sign Bits.
VCLZ:
Vector Count Leading Zeros.
VCNT:
Vector Count Set Bits.
vector element to a general-purpose register with sign or zero extension.
VDUP (scalar): Duplicate
vector element to vector.
VMOV (general-purpose register to scalar): Copy a general-purpose register to a
vector element.
Vector Extract.
Vector Extract: an alias of VEXT (byte elements).
Vector Floating-point Multiply-Add Long to accumulator (by scalar).
Vector Floating-point Multiply-Add Long to accumulator (vector).
Vector Floating-point Multiply-Subtract Long from accumulator (by scalar).
Vector Floating-point Multiply-Subtract Long from accumulator (vector).
VSDOT (vector): Dot Product
vector form with signed integers..
VUDOT (vector): Dot Product
vector form with unsigned integers..
VFMA:
Vector Fused Multiply Accumulate.
VFMS:
Vector Fused Multiply Subtract.
Vector Fused Negate Multiply Accumulate.
Vector Fused Negate Multiply Subtract.
Vector Halving Add.
Vector Halving Subtract.
Vector Maximum (floating-point).
Vector Maximum (integer).
Vector Minimum (floating-point).
Vector Minimum (integer).
Vector Move and Narrow.
Vector Move extraction.
VINS:
Vector move Insertion.
Vector Move Long.
Vector Multiply (by scalar).
Vector Multiply (floating-point).
Vector Multiply (integer and polynomial).
Vector Multiply Accumulate (by scalar).
Vector Multiply Accumulate (floating-point).
Vector Multiply Accumulate (integer).
Vector Multiply Accumulate Long (by scalar).
Vector Multiply Accumulate Long (integer).
Vector Multiply Long (by scalar).
Vector Multiply Long (integer and polynomial).
Vector Multiply Subtract (by scalar).
Vector Multiply Subtract (floating-point).
Vector Multiply Subtract (integer).
Vector Multiply Subtract Long (by scalar).
Vector Multiply Subtract Long (integer).
Vector Negate Multiply Accumulate.
Vector Negate Multiply Subtract.
Vector Negate Multiply.
VNEG:
Vector Negate.
Vector Pairwise Add (floating-point).
Vector Pairwise Add (integer).
Vector Pairwise Add and Accumulate Long.
Vector Pairwise Add Long.
Vector Pairwise Maximum (floating-point).
Vector Pairwise Maximum (integer).
Vector Pairwise Minimum (floating-point).
Vector Pairwise Minimum (integer).
Vector Reciprocal Estimate.
Vector Reciprocal Square Root Estimate.
Vector Reciprocal Square Root Step.
Vector Reciprocal Step.
Vector Reverse in doublewords.
Vector Reverse in halfwords.
Vector Reverse in words.
Vector round floating-point to integer inexact.
Vector Round floating-point to integer to Nearest.
Vector Round floating-point to integer towards +Infinity.
Vector Round floating-point to integer towards -Infinity.
Vector Round floating-point to integer towards Nearest with Ties to Away.
Vector round floating-point to integer towards Zero.
Vector Rounding Add and Narrow, returning High Half.
Vector Rounding Halving Add.
Vector Rounding Shift Left.
Vector Rounding Shift Right and Accumulate.
Vector Rounding Shift Right and Narrow.
Vector Rounding Shift Right and Narrow: an alias of VMOVN.
Vector Rounding Shift Right.
Vector Rounding Shift Right: an alias of VORR (register).
Vector Rounding Subtract and Narrow, returning High Half.
Vector Saturating Absolute.
Vector Saturating Add.
Vector Saturating Doubling Multiply Accumulate Long.
Vector Saturating Doubling Multiply Long.
Vector Saturating Doubling Multiply Returning High Half.
Vector Saturating Doubling Multiply Subtract Long.
Vector Saturating Move and Narrow.
Vector Saturating Negate.
Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.
Vector Saturating Rounding Doubling Multiply Returning High Half.
Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.
Vector Saturating Rounding Shift Left.
Vector Saturating Rounding Shift Right, Narrow.
Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
Vector Saturating Shift Left (immediate).
Vector Saturating Shift Left (register).
Vector Saturating Shift Right, Narrow.
Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
Vector Saturating Subtract.
Vector Shift Left (immediate).
Vector Shift Left (register).
VSLI:
Vector Shift Left and Insert.
Vector Shift Left Long.
VSRA:
Vector Shift Right and Accumulate.
VSRI:
Vector Shift Right and Insert.
Vector Shift Right Narrow.
Vector Shift Right Narrow: an alias of VMOVN.
VSHR:
Vector Shift Right.
Vector Shift Right: an alias of VORR (register).
Vector Subtract (floating-point).
Vector Subtract (integer).
Vector Subtract and Narrow, returning High Half.
Vector Subtract Long.
Vector Subtract Wide.
VSWP:
Vector Swap.
Vector Table Lookup and Extension.
VTST:
Vector Test Bits.
VTRN:
Vector Transpose.
VUZP:
Vector Unzip.
Vector Unzip: an alias of VTRN.
VZIP:
Vector Zip.
Vector Zip: an alias of VTRN.
VFMAL (vector): Vector Floating-point Multiply-Add Long to accumulator (
vector).
VFMSL (vector): Vector Floating-point Multiply-Subtract Long from accumulator (
vector).
VDUP (general-purpose register): Duplicate general-purpose register to
vector.
VDUP (scalar): Duplicate vector element to
vector.
VEOR: Vector Bitwise Exclusive OR.
VEXT (multibyte elements): Vector Extract: an alias of
VEXT (byte elements).
VEXT (byte elements): Vector Extract.
VEXT (multibyte elements): Vector Extract: an alias of VEXT (byte elements).
VFMA: Vector Fused Multiply Accumulate.
VFMAL (by scalar): Vector Floating-point Multiply-Add Long to accumulator (by scalar).
VFMAL (vector): Vector Floating-point Multiply-Add Long to accumulator (vector).
VFMS: Vector Fused Multiply Subtract.
VFMSL (by scalar): Vector Floating-point Multiply-Subtract Long from accumulator (by scalar).
VFMSL (vector): Vector Floating-point Multiply-Subtract Long from accumulator (vector).
VFNMA: Vector Fused Negate Multiply Accumulate.
VFNMS: Vector Fused Negate Multiply Subtract.
VHADD: Vector Halving Add.
VHSUB: Vector Halving Subtract.
VINS: Vector move Insertion.
VJCVT: Javascript Convert to signed fixed-point, rounding toward Zero.
VLD1 (multiple single elements): Load multiple single 1-element structures to one, two, three, or four registers.
VLD1 (single element to all lanes): Load single 1-element structure and replicate to all lanes of one register.
VLD1 (single element to one lane): Load single 1-element structure to one lane of one register.
VLD2 (multiple 2-element structures): Load multiple 2-element structures to two or four registers.
VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.
VLD2 (single 2-element structure to one lane): Load single 2-element structure to one lane of two registers.
VLD3 (multiple 3-element structures): Load multiple 3-element structures to three registers.
VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.
VLD3 (single 3-element structure to one lane): Load single 3-element structure to one lane of three registers.
VLD4 (multiple 4-element structures): Load multiple 4-element structures to four registers.
VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.
VLD4 (single 4-element structure to one lane): Load single 4-element structure to one lane of four registers.
VPOP: Pop SIMD&FP registers from Stack: an alias of
VLDM, VLDMDB, VLDMIA.
VLDM, VLDMDB, VLDMIA: Load Multiple SIMD&FP registers.
VPOP: Pop SIMD&FP registers from Stack: an alias of VLDM,
VLDMDB, VLDMIA.
VLDMDB, VLDMIA: Load Multiple SIMD&FP registers.
VPOP: Pop SIMD&FP registers from Stack: an alias of VLDM, VLDMDB,
VLDMIA.
VLDMIA: Load Multiple SIMD&FP registers.
VLDR (immediate): Load SIMD&FP register (immediate).
VLDR (literal): Load SIMD&FP register (literal).
VMAX (floating-point): Vector Maximum (floating-point).
VMAX (integer): Vector Maximum (integer).
VMAXNM: Floating-point Maximum Number.
VMIN (floating-point): Vector Minimum (floating-point).
VMIN (integer): Vector Minimum (integer).
VMINNM: Floating-point Minimum Number.
VMLA (by scalar): Vector Multiply Accumulate (by scalar).
VMLA (floating-point): Vector Multiply Accumulate (floating-point).
VMLA (integer): Vector Multiply Accumulate (integer).
VMLAL (by scalar): Vector Multiply Accumulate Long (by scalar).
VMLAL (integer): Vector Multiply Accumulate Long (integer).
VMLS (by scalar): Vector Multiply Subtract (by scalar).
VMLS (floating-point): Vector Multiply Subtract (floating-point).
VMLS (integer): Vector Multiply Subtract (integer).
VMLSL (by scalar): Vector Multiply Subtract Long (by scalar).
VMLSL (integer): Vector Multiply Subtract Long (integer).
VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.
VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.
VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.
VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.
VMOV (general-purpose register to scalar): Copy a general-purpose register to a vector element.
VMOV (immediate): Copy immediate value to a SIMD&FP register.
VMOV (register): Copy between FP registers.
VMOV (register, SIMD): Copy between SIMD registers: an alias of VORR (register).
VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or zero extension.
VMOVL: Vector Move Long.
VRSHRN (zero): Vector Rounding Shift Right and Narrow: an alias of
VMOVN.
VSHRN (zero): Vector Shift Right Narrow: an alias of
VMOVN.
VMOVN: Vector Move and Narrow.
VMOVX: Vector Move extraction.
VMRS: Move SIMD&FP Special register to general-purpose register.
VMSR: Move general-purpose register to SIMD&FP Special register.
VMUL (by scalar): Vector Multiply (by scalar).
VMUL (floating-point): Vector Multiply (floating-point).
VMUL (integer and polynomial): Vector Multiply (integer and polynomial).
VMULL (by scalar): Vector Multiply Long (by scalar).
VMULL (integer and polynomial): Vector Multiply Long (integer and polynomial).
VMVN (immediate): Vector Bitwise NOT (immediate).
VMVN (register): Vector Bitwise NOT (register).
VNEG: Vector Negate.
VNMLA: Vector Negate Multiply Accumulate.
VNMLS: Vector Negate Multiply Subtract.
VNMUL: Vector Negate Multiply.
VORN (immediate): Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).
VORN (register): Vector bitwise OR NOT (register).
VORN (immediate): Vector Bitwise OR NOT (immediate): an alias of
VORR (immediate).
VORR (immediate): Vector Bitwise OR (immediate).
VMOV (register, SIMD): Copy between SIMD registers: an alias of
VORR (register).
VRSHR (zero): Vector Rounding Shift Right: an alias of
VORR (register).
VSHR (zero): Vector Shift Right: an alias of
VORR (register).
VORR (register): Vector bitwise OR (register).
VPADAL: Vector Pairwise Add and Accumulate Long.
VPADD (floating-point): Vector Pairwise Add (floating-point).
VPADD (integer): Vector Pairwise Add (integer).
VPADDL: Vector Pairwise Add Long.
VPMAX (floating-point): Vector Pairwise Maximum (floating-point).
VPMAX (integer): Vector Pairwise Maximum (integer).
VPMIN (floating-point): Vector Pairwise Minimum (floating-point).
VPMIN (integer): Vector Pairwise Minimum (integer).
VPOP: Pop SIMD&FP registers from Stack: an alias of VLDM, VLDMDB, VLDMIA.
VPUSH: Push SIMD&FP registers to Stack: an alias of VSTM, VSTMDB, VSTMIA.
VQABS: Vector Saturating Absolute.
VQADD: Vector Saturating Add.
VQDMLAL: Vector Saturating Doubling Multiply Accumulate Long.
VQDMLSL: Vector Saturating Doubling Multiply Subtract Long.
VQDMULH: Vector Saturating Doubling Multiply Returning High Half.
VQDMULL: Vector Saturating Doubling Multiply Long.
VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of
VQMOVN, VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of
VQMOVN, VQMOVUN.
VQSHRN (zero): Vector Saturating Shift Right, Narrow: an alias of
VQMOVN, VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an alias of
VQMOVN, VQMOVUN.
VQMOVN, VQMOVUN: Vector Saturating Move and Narrow.
VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN,
VQMOVUN.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN,
VQMOVUN.
VQSHRN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN,
VQMOVUN.
VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN,
VQMOVUN.
VQNEG: Vector Saturating Negate.
VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.
VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.
VQRDMULH: Vector Saturating Rounding Doubling Multiply Returning High Half.
VQRSHL: Vector Saturating Rounding Shift Left.
VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQRSHRN, VQRSHRUN: Vector Saturating Rounding Shift Right, Narrow.
VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHL (register): Vector Saturating Shift Left (register).
VQSHL, VQSHLU (immediate): Vector Saturating Shift Left (immediate).
VQSHLU (immediate): Vector Saturating Shift Left (immediate).
VQSHRN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSHRN, VQSHRUN: Vector Saturating Shift Right, Narrow.
VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
VQSUB: Vector Saturating Subtract.
VRADDHN: Vector Rounding Add and Narrow, returning High Half.
VRECPE: Vector Reciprocal Estimate.
VRECPS: Vector Reciprocal Step.
VREV16: Vector Reverse in halfwords.
VREV32: Vector Reverse in words.
VREV64: Vector Reverse in doublewords.
VRHADD: Vector Rounding Halving Add.
VRINTA (Advanced SIMD): Vector Round floating-point to integer towards Nearest with Ties to Away.
VRINTA (floating-point): Round floating-point to integer to Nearest with Ties to Away.
VRINTM (Advanced SIMD): Vector Round floating-point to integer towards -Infinity.
VRINTM (floating-point): Round floating-point to integer towards -Infinity.
VRINTN (Advanced SIMD): Vector Round floating-point to integer to Nearest.
VRINTN (floating-point): Round floating-point to integer to Nearest.
VRINTP (Advanced SIMD): Vector Round floating-point to integer towards +Infinity.
VRINTP (floating-point): Round floating-point to integer towards +Infinity.
VRINTR: Round floating-point to integer.
VRINTX (Advanced SIMD): Vector round floating-point to integer inexact.
VRINTX (floating-point): Round floating-point to integer inexact.
VRINTZ (Advanced SIMD): Vector round floating-point to integer towards Zero.
VRINTZ (floating-point): Round floating-point to integer towards Zero.
VRSHL: Vector Rounding Shift Left.
VRSHR (zero): Vector Rounding Shift Right: an alias of VORR (register).
VRSHR: Vector Rounding Shift Right.
VRSHRN (zero): Vector Rounding Shift Right and Narrow: an alias of VMOVN.
VRSHRN: Vector Rounding Shift Right and Narrow.
VRSQRTE: Vector Reciprocal Square Root Estimate.
VRSQRTS: Vector Reciprocal Square Root Step.
VRSRA: Vector Rounding Shift Right and Accumulate.
VRSUBHN: Vector Rounding Subtract and Narrow, returning High Half.
VSDOT (by element): Dot Product index form with signed integers..
VSDOT (vector): Dot Product vector form with signed integers..
VSELEQ, VSELGE, VSELGT, VSELVS: Floating-point conditional select.
VSELGE, VSELGT, VSELVS: Floating-point conditional select.
VSELGT, VSELVS: Floating-point conditional select.
VSELVS: Floating-point conditional select.
VSHL (immediate): Vector Shift Left (immediate).
VSHL (register): Vector Shift Left (register).
VSHLL: Vector Shift Left Long.
VSHR (zero): Vector Shift Right: an alias of VORR (register).
VSHR: Vector Shift Right.
VSHRN (zero): Vector Shift Right Narrow: an alias of VMOVN.
VSHRN: Vector Shift Right Narrow.
VSLI: Vector Shift Left and Insert.
VSQRT: Square Root.
VSRA: Vector Shift Right and Accumulate.
VSRI: Vector Shift Right and Insert.
VST1 (multiple single elements): Store multiple single elements from one, two, three, or four registers.
VST1 (single element from one lane): Store single element from one lane of one register.
VST2 (multiple 2-element structures): Store multiple 2-element structures from two or four registers.
VST2 (single 2-element structure from one lane): Store single 2-element structure from one lane of two registers.
VST3 (multiple 3-element structures): Store multiple 3-element structures from three registers.
VST3 (single 3-element structure from one lane): Store single 3-element structure from one lane of three registers.
VST4 (multiple 4-element structures): Store multiple 4-element structures from four registers.
VST4 (single 4-element structure from one lane): Store single 4-element structure from one lane of four registers.
VPUSH: Push SIMD&FP registers to Stack: an alias of
VSTM, VSTMDB, VSTMIA.
VSTM, VSTMDB, VSTMIA: Store multiple SIMD&FP registers.
VPUSH: Push SIMD&FP registers to Stack: an alias of VSTM,
VSTMDB, VSTMIA.
VSTMDB, VSTMIA: Store multiple SIMD&FP registers.
VPUSH: Push SIMD&FP registers to Stack: an alias of VSTM, VSTMDB,
VSTMIA.
VSTMIA: Store multiple SIMD&FP registers.
VSTR: Store SIMD&FP register.
VSUB (floating-point): Vector Subtract (floating-point).
VSUB (integer): Vector Subtract (integer).
VSUBHN: Vector Subtract and Narrow, returning High Half.
VSUBL: Vector Subtract Long.
VSUBW: Vector Subtract Wide.
VSWP: Vector Swap.
VTBL, VTBX: Vector Table Lookup and Extension.
VUZP (alias): Vector Unzip: an alias of
VTRN.
VZIP (alias): Vector Zip: an alias of
VTRN.
VTRN: Vector Transpose.
VTST: Vector Test Bits.
VUDOT (by element): Dot Product index form with unsigned integers..
VUDOT (vector): Dot Product vector form with unsigned integers..
VUZP (alias): Vector Unzip: an alias of VTRN.
VUZP: Vector Unzip.
VZIP (alias): Vector Zip: an alias of VTRN.
VZIP: Vector Zip.
WFI:
Wait For Interrupt.
WFE: Wait For Event.
WFI: Wait For Interrupt.
VADDW: Vector Add
Wide.
VSUBW: Vector Subtract
Wide.
SMLAWB, SMLAWT: Signed Multiply Accumulate (
word by halfword).
SMULWB, SMULWT: Signed Multiply (
word by halfword).
SMMLA, SMMLAR: Signed Most Significant
Word Multiply Accumulate.
SMMLS, SMMLSR: Signed Most Significant
Word Multiply Subtract.
SMMUL, SMMULR: Signed Most Significant
Word Multiply.
LDA: Load-Acquire
Word.
LDAEX: Load-Acquire Exclusive
Word.
REV: Byte-Reverse
Word.
STL: Store-Release
Word.
STLEX: Store-Release Exclusive
Word.
VREV32: Vector Reverse in
words.
FLDM*X (FLDMDBX, FLDMIAX): FLDM*
X.
YIELD: Yield hint.
VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or
zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.
CBNZ, CBZ: Compare and Branch on Nonzero or
Zero.
VCEQ (immediate #0): Vector Compare Equal to
Zero.
VCGE (immediate #0): Vector Compare Greater Than or Equal to
Zero.
VCGT (immediate #0): Vector Compare Greater Than
Zero.
VCLE (immediate #0): Vector Compare Less Than or Equal to
Zero.
VCLT (immediate #0): Vector Compare Less Than
Zero.
VCVT (floating-point to integer, floating-point): Convert floating-point to integer with Round towards
Zero.
VJCVT: Javascript Convert to signed fixed-point, rounding toward
Zero.
VRINTZ (Advanced SIMD): Vector round floating-point to integer towards
Zero.
VRINTZ (floating-point): Round floating-point to integer towards
Zero.
CLZ: Count Leading
Zeros.
VCLZ: Vector Count Leading
Zeros.
VZIP: Vector
Zip.
VZIP (alias): Vector
Zip: an alias of VTRN.
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.