Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | (0) | (0) | (0) | (0) | Rd | != 00000 | 1 | 1 | 0 | Rm | |||||||||||||
cond | S | imm5 | type |
ROR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 1 | 1 | Rm | |||||||||
S | type |
ROR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>
and is always the preferred disassembly.
<c> |
<q> |
<imm> |
For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field. |
For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field. |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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