Copy between FP registers copies the contents of one FP register to another.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A2 ) and T32 ( T2 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | x | 0 | 1 | M | 0 | Vm | |||||||||
cond | size |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; single_register = (size == '10'); advsimd = FALSE; if single_register then d = UInt(Vd:D); m = UInt(Vm:M); else d = UInt(D:Vd); m = UInt(M:Vm); regs = 1;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | x | 0 | 1 | M | 0 | Vm | ||||||
size |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; single_register = (size == '10'); advsimd = FALSE; if single_register then d = UInt(Vd:D); m = UInt(Vm:M); else d = UInt(D:Vd); m = UInt(M:Vm); regs = 1;
<c> |
<q> |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if single_register then S[d] = S[m]; else for r = 0 to regs-1 D[d+r] = D[m+r];
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.