ISA_v83A_AArch32_xml_00bet6 (old)htmldiff from-ISA_v83A_AArch32_xml_00bet6(new) ISA_v83A_AArch32_xml_00bet6.1

Top-level encodings for A32

313029282726252423222120191817161514131211109876543210
condop0op1
Decode fields Instruction details
condop0op1
!= 1111 00x Data-processing and miscellaneous instructions
!= 1111 010 Load/Store Word, Unsigned Byte (immediate, literal)
!= 1111 011 0 Load/Store Word, Unsigned Byte (register)
!= 1111 011 1 Media instructions
10x Branch, branch with link, and block data transfer
11x System register access, Advanced SIMD, floating-point, and Supervisor call
1111 0xx Unconditional instructions

Data-processing and miscellaneous instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
!= 111100op0op1op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0 1 != 00 1 Extra load/store
0 0xxxx 1 00 1 Multiply and Accumulate
0 1xxxx 1 00 1 Synchronization primitives and Load-Acquire/Store-Release
0 10xx0 0 Miscellaneous
0 10xx0 1 0 Halfword Multiply and Accumulate
0 != 10xx0 0 Data-processing register (immediate shift)
0 != 10xx0 0 1 Data-processing register (register shift)
1 Data-processing immediate

Extra load/store

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op01!= 001
Decode fields Instruction details
op0
0 Load/Store Dual, Half, Signed Byte (register)
1 Load/Store Dual, Half, Signed Byte (immediate, literal)

Load/Store Dual, Half, Signed Byte (register)

These instructions are under Extra load/store.

313029282726252423222120191817161514131211109876543210
!= 1111000PU0Wo1RnRt(0)(0)(0)(0)1!= 001Rm
condop2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
PWo1op2
00001STRH (register)post-indexed
00010LDRD (register)post-indexed
00011STRD (register)post-indexed
00101LDRH (register)post-indexed
00110LDRSB (register)post-indexed
00111LDRSH (register)post-indexed
01001STRHT
01010UNALLOCATED
01011UNALLOCATED
01101LDRHT
01110LDRSBT
01111LDRSHT
1001STRH (register)pre-indexed
1010LDRD (register)pre-indexed
1011STRD (register)pre-indexed
1101LDRH (register)pre-indexed
1110LDRSB (register)pre-indexed
1111LDRSH (register)pre-indexed

Load/Store Dual, Half, Signed Byte (immediate, literal)

These instructions are under Extra load/store.

313029282726252423222120191817161514131211109876543210
!= 1111000PU1Wo1RnRtimm4H1!= 001imm4L
condop2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P:Wo1Rnop2
0111110LDRD (literal)
!= 011111101LDRH (literal)
!= 011111110LDRSB (literal)
!= 011111111LDRSH (literal)
000!= 111110LDRD (immediate)post-indexed
00001STRH (immediate)post-indexed
00011STRD (immediate)post-indexed
001!= 111101LDRH (immediate)post-indexed
001!= 111110LDRSB (immediate)post-indexed
001!= 111111LDRSH (immediate)post-indexed
010!= 111110UNALLOCATED
01001STRHT
01011UNALLOCATED
01101LDRHT
01110LDRSBT
01111LDRSHT
100!= 111110LDRD (immediate)offset
10001STRH (immediate)offset
10011STRD (immediate)offset
101!= 111101LDRH (immediate)offset
101!= 111110LDRSB (immediate)offset
101!= 111111LDRSH (immediate)offset
110!= 111110LDRD (immediate)pre-indexed
11001STRH (immediate)pre-indexed
11011STRD (immediate)pre-indexed
111!= 111101LDRH (immediate)pre-indexed
111!= 111110LDRSB (immediate)pre-indexed
111!= 111111LDRSH (immediate)pre-indexed

Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRdHiRdLoRm1001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcS
000MUL, MULS
001MLA, MLAS
0100UMAAL
0101UNALLOCATED
0110MLS
0111UNALLOCATED
100UMULL, UMULLS
101UMLAL, UMLALS
110SMULL, SMULLS
111SMLAL, SMLALS

Synchronization primitives and Load-Acquire/Store-Release

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 11110001op0111001
Decode fields Instruction details
op0
0 UNALLOCATED
1 Load/Store Exclusive and Load-Acquire/Store-Release

Load/Store Exclusive and Load-Acquire/Store-Release

These instructions are under Synchronization primitives and Load-Acquire/Store-Release.

313029282726252423222120191817161514131211109876543210
!= 111100011typeLRnxRd(1)(1)exord1001xRt
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
typeLexord
00000STL
00001UNALLOCATED
00010STLEX
00011STREX
00100LDA
00101UNALLOCATED
00110LDAEX
00111LDREX
0100UNALLOCATED
01010STLEXD
01011STREXD
0110UNALLOCATED
01110LDAEXD
01111LDREXD
10000STLB
10001UNALLOCATED
10010STLEXB
10011STREXB
10100LDAB
10101UNALLOCATED
10110LDAEXB
10111LDREXB
11000STLH
11001UNALLOCATED
11010STLEXH
11011STREXH
11100LDAH
11101UNALLOCATED
11110LDAEXH
11111LDREXH

Miscellaneous

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 111100010op000op1
Decode fields Instruction details
op0op1
00 001 UNALLOCATED
00 010 UNALLOCATED
00 011 UNALLOCATED
00 110 UNALLOCATED
01 001 BX
01 010 BXJ
01 011 BLX (register)
01 110 UNALLOCATED
10 001 UNALLOCATED
10 010 UNALLOCATED
10 011 UNALLOCATED
10 110 UNALLOCATED
11 001 CLZ
11 010 UNALLOCATED
11 011 UNALLOCATED
11 110 ERET
111 Exception Generation
000 Move special register (register)
100 Cyclic Redundancy Check
101 Integer Saturating Arithmetic

Exception Generation

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0imm120111imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00HLT
01BKPT
10HVC
11SMC

Move special register (register)

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0maskRd(0)(0)Bm0000Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcB
x00MRS
x01MRS (Banked register)
x10MSR (register)
x11MSR (Banked register)

Cyclic Redundancy Check

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010sz0RnRd(0)(0)C(0)0100Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
szC
000CRC32CRC32B
001CRC32CCRC32CB
010CRC32CRC32H
011CRC32CCRC32CH
100CRC32CRC32W
101CRC32CCRC32CW
11CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Integer Saturating Arithmetic

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0RnRd(0)(0)(0)(0)0101Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00QADD
01QSUB
10QDADD
11QDSUB

Halfword Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0RdRaRm1MN0Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcMN
00SMLABB, SMLABT, SMLATB, SMLATT
0100SMLAWB, SMLAWTSMLAWB
0101SMULWB, SMULWTSMULWB
0110SMLAWB, SMLAWTSMLAWT
0111SMULWB, SMULWTSMULWT
10SMLALBB, SMLALBT, SMLALTB, SMLALTT
11SMULBB, SMULBT, SMULTB, SMULTT

Data-processing register (immediate shift)

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op0op10

The following constraints also apply to this encoding: op0:op1 != 100

Decode fields Instruction details
op0op1
0x Integer Data Processing (three register, immediate shift)
10 1 Integer Test and Compare (two register, immediate shift)
11 Logical Arithmetic (three register, immediate shift)

Integer Data Processing (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRnRdimm5type0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcSRn
000AND, ANDS (register)
001EOR, EORS (register)
0100!= 1101SUB, SUBS (register)SUB
01001101SUB, SUBS (SP minus register)SUB
0101!= 1101SUB, SUBS (register)SUBS
01011101SUB, SUBS (SP minus register)SUBS
011RSB, RSBS (register)
1000!= 1101ADD, ADDS (register)ADD
10001101ADD, ADDS (SP plus register)ADD
1001!= 1101ADD, ADDS (register)ADDS
10011101ADD, ADDS (SP plus register)ADDS
101ADC, ADCS (register)
110SBC, SBCS (register)
111RSC, RSCS (register)

Integer Test and Compare (two register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 111100010opc1Rn(0)(0)(0)(0)imm5type0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00TST (register)
01TEQ (register)
10CMP (register)
11CMN (register)

Logical Arithmetic (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 111100011opcSRnRdimm5type0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00ORR, ORRS (register)
01MOV, MOVS (register)
10BIC, BICS (register)
11MVN, MVNS (register)

Data-processing register (register shift)

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op0op101

The following constraints also apply to this encoding: op0:op1 != 100

Decode fields Instruction details
op0op1
0x Integer Data Processing (three register, register shift)
10 1 Integer Test and Compare (two register, register shift)
11 Logical Arithmetic (three register, register shift)

Integer Data Processing (three register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRnRdRs0type1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
000AND, ANDS (register-shifted register)
001EOR, EORS (register-shifted register)
010SUB, SUBS (register-shifted register)
011RSB, RSBS (register-shifted register)
100ADD, ADDS (register-shifted register)
101ADC, ADCS (register-shifted register)
110SBC, SBCS (register-shifted register)
111RSC, RSCS (register-shifted register)

Integer Test and Compare (two register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 111100010opc1Rn(0)(0)(0)(0)Rs0type1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00TST (register-shifted register)
01TEQ (register-shifted register)
10CMP (register-shifted register)
11CMN (register-shifted register)

Logical Arithmetic (three register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 111100011opcSRnRdRs0type1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00ORR, ORRS (register-shifted register)
01MOV, MOVS (register-shifted register)
10BIC, BICS (register-shifted register)
11MVN, MVNS (register-shifted register)

Data-processing immediate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111001op0op1
Decode fields Instruction details
op0op1
0x Integer Data Processing (two register and immediate)
10 00 Move Halfword (immediate)
10 10 Move Special Register and Hints (immediate)
10 x1 Integer Test and Compare (one register and immediate)
11 Logical Arithmetic (two register and immediate)

Integer Data Processing (two register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 11110010opcSRnRdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcSRn
000AND, ANDS (immediate)
001EOR, EORS (immediate)
0100!= 11x1SUB, SUBS (immediate)SUB
01001101SUB, SUBS (SP minus immediate)SUB
01001111ADRA2
0101!= 1101SUB, SUBS (immediate)SUBS
01011101SUB, SUBS (SP minus immediate)SUBS
011RSB, RSBS (immediate)
1000!= 11x1ADD, ADDS (immediate)ADD
10001101ADD, ADDS (SP plus immediate)ADD
10001111ADRA1
1001!= 1101ADD, ADDS (immediate)ADDS
10011101ADD, ADDS (SP plus immediate)ADDS
101ADC, ADCS (immediate)
110SBC, SBCS (immediate)
111RSC, RSCS (immediate)

Move Halfword (immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110H00imm4Rdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
H
0MOV, MOVS (immediate)
1MOVT

Move Special Register and Hints (immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110R10imm4(1)(1)(1)(1)imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
R:imm4imm12
!= 00000MSR (immediate)-
00000xxxx00000000NOP-
00000xxxx00000001YIELD-
00000xxxx00000010WFE-
00000xxxx00000011WFI-
00000xxxx00000100SEV-
00000xxxx00000101SEVL-
00000xxxx0000011xReserved hint, behaves as NOP-
00000xxxx00001xxxReserved hint, behaves as NOP-
00000xxxx00010000ESBARMv8.2
00000xxxx00010001Reserved hint, behaves as NOP-
00000xxxx00010011xxxx0001001xReserved hint, behaves as NOP-
00000xxxx00010100xxxx000101xxReserved hint, behaves as NOPCSDB-
00000xxxx00010101xxxx00011xxxReserved hint, behaves as NOP-
00000xxxx00011xxxxxxx001xxxxxReserved hint, behaves as NOP-
00000xxxx0001111xxxxx01xxxxxxReserved hint, behaves as NOP-
00000xxxx001xxxxxxxxx10xxxxxxReserved hint, behaves as NOP-
00000xxxx01xxxxxxxxxx110xxxxxReserved hint, behaves as NOP-
00000xxxx10xxxxxxxxxx1110xxxxReserved hint, behaves as NOP-
00000xxxx110xxxxxxxxx1111xxxxDBGReserved hint, behaves as NOP-
00000xxxx1110xxxxReserved hint, behaves as NOP-
00000xxxx1111xxxxDBG-

Integer Test and Compare (one register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110opc1Rn(0)(0)(0)(0)imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00TST (immediate)
01TEQ (immediate)
10CMP (immediate)
11CMN (immediate)

Logical Arithmetic (two register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100111opcSRnRdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00ORR, ORRS (immediate)
01MOV, MOVS (immediate)
10BIC, BICS (immediate)
11MVN, MVNS (immediate)

Load/Store Word, Unsigned Byte (immediate, literal)

313029282726252423222120191817161514131211109876543210
!= 1111010PUo2Wo1RnRtimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
P:Wo2o1Rn
!= 01011111LDR (literal)
!= 01111111LDRB (literal)
0000STR (immediate)post-indexed
0001!= 1111LDR (immediate)post-indexed
0010STRB (immediate)post-indexed
0011!= 1111LDRB (immediate)post-indexed
0100STRT
0101LDRT
0110STRBT
0111LDRBT
1000STR (immediate)offset
1001!= 1111LDR (immediate)offset
1010STRB (immediate)offset
1011!= 1111LDRB (immediate)offset
1100STR (immediate)pre-indexed
1101!= 1111LDR (immediate)pre-indexed
1110STRB (immediate)pre-indexed
1111!= 1111LDRB (immediate)pre-indexed

Load/Store Word, Unsigned Byte (register)

313029282726252423222120191817161514131211109876543210
!= 1111011PUo2Wo1RnRtimm5type0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Po2Wo1
0000STR (register)post-indexed
0001LDR (register)post-indexed
0010STRT
0011LDRT
0100STRB (register)post-indexed
0101LDRB (register)post-indexed
0110STRBT
0111LDRBT
100STR (register)pre-indexed
101LDR (register)pre-indexed
110STRB (register)pre-indexed
111LDRB (register)pre-indexed

Media instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
!= 1111011op0op11
Decode fields Instruction details
op0op1
00xxx Parallel Arithmetic
01000 101 SEL
01000 001 UNALLOCATED
01000 xx0 PKHBT, PKHTB
01001 x01 UNALLOCATED
01001 xx0 UNALLOCATED
0110x x01 UNALLOCATED
0110x xx0 UNALLOCATED
01x10 001 Saturate 16-bit
01x10 101 UNALLOCATED
01x11 x01 Reverse Bit/Byte
01x1x xx0 Saturate 32-bit
01xxx 111 UNALLOCATED
01xxx 011 Extend and Add
10xxx Signed multiply, Divide
11000 000 Unsigned Sum of Absolute Differences
11000 100 UNALLOCATED
11001 x00 UNALLOCATED
1101x x00 UNALLOCATED
110xx 111 UNALLOCATED
1110x 111 UNALLOCATED
1110x x00 Bitfield Insert
11110 111 UNALLOCATED
11111 111 Permanently UNDEFINED
1111x x00 UNALLOCATED
11x0x x10 UNALLOCATED
11x1x x10 Bitfield Extract
11xxx 011 UNALLOCATED
11xxx x01 UNALLOCATED

Parallel Arithmetic

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101100op1RnRd(1)(1)(1)(1)Bop21Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1Bop2
000UNALLOCATED
001000SADD16
001001SASX
001010SSAX
001011SSUB16
001100SADD8
001101UNALLOCATED
001110UNALLOCATED
001111SSUB8
010000QADD16
010001QASX
010010QSAX
010011QSUB16
010100QADD8
010101UNALLOCATED
010110UNALLOCATED
010111QSUB8
011000SHADD16
011001SHASX
011010SHSAX
011011SHSUB16
011100SHADD8
011101UNALLOCATED
011110UNALLOCATED
011111SHSUB8
100UNALLOCATED
101000UADD16
101001UASX
101010USAX
101011USUB16
101100UADD8
101101UNALLOCATED
101110UNALLOCATED
101111USUB8
110000UQADD16
110001UQASX
110010UQSAX
110011UQSUB16
110100UQADD8
110101UNALLOCATED
110110UNALLOCATED
110111UQSUB8
111000UHADD16
111001UHASX
111010UHSAX
111011UHSUB16
111100UHADD8
111101UNALLOCATED
111110UNALLOCATED
111111UHSUB8

Saturate 16-bit

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101U10sat_immRd(1)(1)(1)(1)0011Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SSAT16
1USAT16

Reverse Bit/Byte

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101o111(1)(1)(1)(1)Rd(1)(1)(1)(1)o2011Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
o1o2
00REV
01REV16
10RBIT
11REVSH

Saturate 32-bit

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101U1sat_immRdimm5sh01Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SSAT
1USAT

Extend and Add

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101UopRnRdrotate(0)(0)0111Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
UopRn
000!= 1111SXTAB16
0001111SXTB16
010!= 1111SXTAB
0101111SXTB
011!= 1111SXTAH
0111111SXTH
100!= 1111UXTAB16
1001111UXTB16
110!= 1111UXTAB
1101111UXTB
111!= 1111UXTAH
1111111UXTH

Signed multiply, Divide

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101110op1RdRaRmop21Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1Raop2
000!= 1111000SMLAD, SMLADXSMLAD
000!= 1111001SMLAD, SMLADXSMLADX
000!= 1111010SMLSD, SMLSDXSMLSD
000!= 1111011SMLSD, SMLSDXSMLSDX
0001xxUNALLOCATED
0001111000SMUAD, SMUADXSMUAD
0001111001SMUAD, SMUADXSMUADX
0001111010SMUSD, SMUSDXSMUSD
0001111011SMUSD, SMUSDXSMUSDX
001000SDIV
001!= 000UNALLOCATED
010UNALLOCATED
011000UDIV
011!= 000UNALLOCATED
100000SMLALD, SMLALDXSMLALD
100001SMLALD, SMLALDXSMLALDX
100010SMLSLD, SMLSLDXSMLSLD
100011SMLSLD, SMLSLDXSMLSLDX
1001xxUNALLOCATED
101!= 1111000SMMLA, SMMLARSMMLA
101!= 1111001SMMLA, SMMLARSMMLAR
10101xUNALLOCATED
10110xUNALLOCATED
101110SMMLS, SMMLSRSMMLS
101111SMMLS, SMMLSRSMMLSR
1011111000SMMUL, SMMULRSMMUL
1011111001SMMUL, SMMULRSMMULR
11xUNALLOCATED

Unsigned Sum of Absolute Differences

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111000RdRaRm0001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Ra
!= 1111USADA8
1111USAD8

Bitfield Insert

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 11110111110msbRdlsb001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Rn
!= 1111BFI
1111BFC

Permanently UNDEFINED

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111111imm121111imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
cond
0xxxUNALLOCATED
10xxUNALLOCATED
110xUNALLOCATED
1110UDF

Bitfield Extract

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111U1widthm1Rdlsb101Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SBFX
1UBFX

Branch, branch with link, and block data transfer

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
cond10op0
Decode fields Instruction details
condop0
1111 0 Exception Save/Restore
!= 1111 0 Load/Store Multiple
1 Branch (immediate)

Exception Save/Restore

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
1111100PUSWLRnopmode
Decode fields Instruction Details
PUSL
00UNALLOCATED
0001RFE, RFEDA, RFEDB, RFEIA, RFEIBDecrement After
0010SRS, SRSDA, SRSDB, SRSIA, SRSIBDecrement After
0101RFE, RFEDA, RFEDB, RFEIA, RFEIBIncrement After
0110SRS, SRSDA, SRSDB, SRSIA, SRSIBIncrement After
1001RFE, RFEDA, RFEDB, RFEIA, RFEIBDecrement Before
1010SRS, SRSDA, SRSDB, SRSIA, SRSIBDecrement Before
11UNALLOCATED
1101RFE, RFEDA, RFEDB, RFEIA, RFEIBIncrement Before
1110SRS, SRSDA, SRSDB, SRSIA, SRSIBIncrement Before

Load/Store Multiple

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
!= 1111100PUopWLRnregister_list
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
PUopLregister_list
0000STMDA, STMED
0001LDMDA, LDMFA
0100STM, STMIA, STMEA
0101LDM, LDMIA, LDMFD
10STM (User registers)
1000STMDB, STMFD
1001LDMDB, LDMEA
110xxxxxxxxxxxxxxxLDM (User registers)
1100STMIB, STMFA
1101LDMIB, LDMED
111xxxxxxxxxxxxxxxLDM (exception return)

Branch (immediate)

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
cond101Himm24
Decode fields Instruction Details
condH
!= 11110B
!= 11111BL, BLX (immediate)A1
1111BL, BLX (immediate)A2

System register access, Advanced SIMD, floating-point, and Supervisor call

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
cond11op0op1op2
Decode fields Instruction details
condop0op1op2
0x 111 System register load/store and 64-bit move
10 10x 0 Floating-point data-processing
10 111 1 System register 32-bit move
11 Supervisor call
1111 0x 1x0 Advanced SIMD three registers of the same length extension
1111 10 1x0 Advanced SIMD two registers and a scalar extension
!= 1111 0x 10x Advanced SIMD load/store and 64-bit move
!= 1111 10 10x 1 Advanced SIMD and floating-point 32-bit move

System register load/store and 64-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
110op0111
Decode fields Instruction details
op0
00x0 System register 64-bit move
!= 00x0 System register load/store

System register 64-bit move

These instructions are under System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
cond11000D0LRt2Rt111cp15opc1CRm
Decode fields Instruction Details
condDL
!= 111110MCRR
!= 111111MRRC
0UNALLOCATED
11111UNALLOCATED

System register load/store

These instructions are under System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
cond110PUDWLRnCRd111cp15imm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
condP:U:WDLRnCRdcp15
!= 1111!= 0000!= 01010UNALLOCATED
!= 1111!= 00001111101010LDC (literal)
!= 1111!= 0001UNALLOCATED
!= 1111!= 000101010UNALLOCATED
!= 11110x10001010STCpost-indexed
!= 11110x101!= 111101010LDC (immediate)post-indexed
!= 11110100001010STCunindexed
!= 111101001!= 111101010LDC (immediate)unindexed
!= 11111x00001010STCoffset
!= 11111x001!= 111101010LDC (immediate)offset
!= 11111x10001010STCpre-indexed
!= 11111x101!= 111101010LDC (immediate)pre-indexed
1111!= 000UNALLOCATED

Floating-point data-processing

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
cond1110op0op110op2op30
Decode fields Instruction details
condop0op1op2op3
1111 0xxx != 00 0 Floating-point conditional select
1111 1x00 != 00 Floating-point minNum/maxNum
1111 1x11 0000 != 00 1 Floating-point extraction and insertion
1111 1x11 1xxx != 00 1 Floating-point directed convert to integer
!= 1111 1x11 1 Floating-point data-processing (two registers)
!= 1111 1x11 0 Floating-point move immediate
!= 1111 != 1x11 Floating-point data-processing (three registers)

Floating-point conditional select

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
111111100DccVnVd10!= 00N0M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
ccsize
00VSELEQ, VSELGE, VSELGT, VSELVSVSELEQ
01VSELEQ, VSELGE, VSELGT, VSELVSVSELVS
01UNALLOCATED
10VSELEQ, VSELGE, VSELGT, VSELVSVSELGE
11VSELEQ, VSELGE, VSELGT, VSELVSVSELGT

Floating-point minNum/maxNum

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
111111101D00VnVd10!= 00NopM0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
sizeop
0VMAXNM
01UNALLOCATED
1VMINNM

Floating-point extraction and insertion

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
111111101D110000Vd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Architecture Version
sizeop
01UNALLOCATED-
100VMOVXARMv8.2
101VINSARMv8.2
11UNALLOCATED-

Floating-point directed convert to integer

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
111111101D111o1RMVd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
o1RMsize
000VRINTA (floating-point)
001VRINTN (floating-point)
01UNALLOCATED
010VRINTP (floating-point)
011VRINTM (floating-point)
100VCVTA (floating-point)
101VCVTN (floating-point)
110VCVTP (floating-point)
111VCVTM (floating-point)

Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 111111101D11o1opc2Vd10sizeo31M0Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
o1opc2sizeo3
00UNALLOCATED-
0000010UNALLOCATED-
00001VABS-
0000100VMOV (register)single-precision scalar-
0000110VMOV (register)double-precision scalar-
00010VNEG-
00011VSQRT-
001x01UNALLOCATED-
00100VCVTBhalf-precision to double-precision-
00101VCVTThalf-precision to double-precision-
00110VCVTBdouble-precision to half-precision-
00111VCVTTdouble-precision to half-precision-
01000VCMPA1-
01001VCMPEA1-
01010VCMPA2-
01011VCMPEA2-
01100VRINTR-
01101VRINTZ (floating-point)-
01110VRINTX (floating-point)-
0111011UNALLOCATED-
0111101VCVT (between double-precision and single-precision)single-precision to double-precision-
0111111VCVT (between double-precision and single-precision)double-precision to single-precision-
1000VCVT (integer to floating-point, floating-point)-
100101UNALLOCATED-
100110UNALLOCATED-
1001110UNALLOCATED-
1001111VJCVTARMv8.3
101xVCVT (between floating-point and fixed-point, floating-point)-
11000VCVTR-
11001VCVT (floating-point to integer, floating-point)-
11010VCVTR-
11011VCVT (floating-point to integer, floating-point)-
111xVCVT (between floating-point and fixed-point, floating-point)-

Floating-point move immediate

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 111111101D11imm4HVd10size(0)0(0)0imm4L
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Architecture Version
size
00UNALLOCATED-
01VMOV (immediate)half-precision scalarARMv8.2
10VMOV (immediate)single-precision scalar-
11VMOV (immediate)double-precision scalar-

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 11111110o0Do1VnVd10sizeNo2M0Vm
cond

The following constraints also apply to this encoding: cond != 1111 && o0:D:o1 != 1x11 && cond != 1111

Decode fields Instruction Details
o0:o1sizeo2
!= 11100UNALLOCATED
0000VMLA (floating-point)
0001VMLS (floating-point)
0010VNMLS
0011VNMLA
0100VMUL (floating-point)
0101VNMUL
0110VADD (floating-point)
0111VSUB (floating-point)
1000VDIV
1010VFNMS
1011VFNMA
1100VFMA
1101VFMS

System register 32-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
cond1110opc1LCRnRt111cp15opc21CRm
Decode fields Instruction Details
condL
!= 11110MCR
!= 11111MRC
1111UNALLOCATED

Supervisor call

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
cond1111
Decode fields Instruction details
cond
1111 UNALLOCATED
!= 1111 SVC

Advanced SIMD three registers of the same length extension

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
1111110op1Dop2VnVd1op30op4NQMUVm
Decode fields Instruction Details Architecture Version
op1op2op3op4QU
x10x000VCADDARMv8.3
0010001VFMAL (vector)ARMv8.2
00101100VSDOT (vector)64-bit SIMD vectorARMv8.2
00101101VUDOT (vector)64-bit SIMD vectorARMv8.2
00101110VSDOT (vector)128-bit SIMD vectorARMv8.2
00101111VUDOT (vector)128-bit SIMD vectorARMv8.2
0110001VFMSL (vector)ARMv8.2
1x000VCMLAARMv8.3

Advanced SIMD two registers and a scalar extension

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
11111110op1Dop2VnVd1op30op4NQMUVm
Decode fields Instruction Details Architecture Version
op1op2op3op4QU
0000VCMLA (by element)half-precision scalarARMv8.3
000001VFMAL (by scalar)ARMv8.2
001001VFMSL (by scalar)ARMv8.2
0101100VSDOT (by element)64-bit SIMD vectorARMv8.2
0101101VUDOT (by element)64-bit SIMD vectorARMv8.2
0101110VSDOT (by element)128-bit SIMD vectorARMv8.2
0101111VUDOT (by element)128-bit SIMD vectorARMv8.2
1000VCMLA (by element)single-precision scalarARMv8.3

Advanced SIMD load/store and 64-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
!= 1111110op010
Decode fields Instruction details
op0
00x0 Advanced SIMD and floating-point 64-bit move
!= 00x0 Advanced SIMD and floating-point load/store

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 111111000D0opRt2Rt10sizeopc2Mo3Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Dopsizeopc2o3
0UNALLOCATED
10UNALLOCATED
10x001UNALLOCATED
101UNALLOCATED
1010001VMOV (between two general-purpose registers and two single-precision registers)from general-purpose registers
1011001VMOV (between two general-purpose registers and a doubleword floating-point register)from general-purpose registers
11xUNALLOCATED
1110001VMOV (between two general-purpose registers and two single-precision registers)to general-purpose registers
1111001VMOV (between two general-purpose registers and a doubleword floating-point register)to general-purpose registers

Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 1111110PUDWLRnVd10sizeimm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details
PUWLRnsizeimm8
001UNALLOCATED
010xUNALLOCATED
01010VSTM, VSTMDB, VSTMIA
01011xxxxxxx0VSTM, VSTMDB, VSTMIA
01011xxxxxxx1FSTMDBX, FSTMIAXIncrement After
01110VLDM, VLDMDB, VLDMIA
01111xxxxxxx0VLDM, VLDMDB, VLDMIA
01111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Increment After
100VSTR
1000UNALLOCATED
101!= 1111VLDR (immediate)
1010xUNALLOCATED
101010VSTM, VSTMDB, VSTMIA
101011xxxxxxx0VSTM, VSTMDB, VSTMIA
101011xxxxxxx1FSTMDBX, FSTMIAXDecrement Before
101110VLDM, VLDMDB, VLDMIA
101111xxxxxxx0VLDM, VLDMDB, VLDMIA
101111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Decrement Before
1011111VLDR (literal)
111UNALLOCATED

Advanced SIMD and floating-point 32-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
!= 11111110op0101op111111
Decode fields Instruction details
op0op1
000 0 VMOV (between general-purpose register and single-precision)
111 0 Floating-point move special register
1 Advanced SIMD 8/16/32-bit element move/duplicate

Floating-point move special register

These instructions are under Advanced SIMD and floating-point 32-bit move.

313029282726252423222120191817161514131211109876543210
!= 11111110111LregRt1010(0)(0)(0)1(0)(0)(0)(0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0VMSR
1VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and floating-point 32-bit move.

313029282726252423222120191817161514131211109876543210
!= 11111110opc1LVnRt1011Nopc21(0)(0)(0)(0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc1Lopc2
0xx0VMOV (general-purpose register to scalar)
1VMOV (scalar to general-purpose register)
1xx00xVDUP (general-purpose register)
1xx01xUNALLOCATED

Unconditional instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
11110op0op1
Decode fields Instruction details
op0op1
00 Miscellaneous
01 Advanced SIMD data-processing
1x 1 Memory hints and barriers
10 0 Advanced SIMD element or structure load/store
11 0 UNALLOCATED

Miscellaneous

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
1111000op0op1
Decode fields Instruction details Architecture version
op0op1
0xxxx UNALLOCATED-
10000 xx0x Change Process State-
10001 1000 UNALLOCATED-
10001 x100 UNALLOCATED-
10001 xx01 UNALLOCATED-
10001 0000 SETPANARMv8.1
1000x 0111 UNALLOCATED-
10010 0111 CONSTRAINED UNPREDICTABLE-
10011 0111 UNALLOCATED-
1001x xx0x UNALLOCATED-
100xx 0011 UNALLOCATED-
100xx 0x10 UNALLOCATED-
100xx 1x1x UNALLOCATED-
101xx UNALLOCATED-
11xxx UNALLOCATED-

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Change Process State

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
111100010000imodMop(0)(0)(0)(0)(0)(0)EAIF0mode
Decode fields Instruction Details
imodMopmode
10xxxxSETEND
0CPS, CPSID, CPSIE
11xxxxUNALLOCATED

Advanced SIMD data-processing

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
1111001op0op1
Decode fields Instruction details
op0op1
0 Advanced SIMD three registers of the same length
1 0 Advanced SIMD two registers, or three registers of different lengths
1 1 Advanced SIMD shifts and immediate generation

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
1111001U0DsizeVnVdopcNQMo1Vm
Decode fields Instruction Details Architecture Version
UsizeopcQo1
00x11001VFMA-
00x11010VADD (floating-point)-
00x11011VMLA (floating-point)-
00x11100VCEQ (register)A2-
00x11110VMAX (floating-point)-
00x11111VRECPS-
00000VHADD-
00000011VAND (register)-
00001VQADD-
00010VRHADD-
00011000SHA1C-
00100VHSUB-
00100011VBIC (register)-
00101VQSUB-
00110VCGT (register)A1-
00111VCGE (register)A1-
00111000SHA1P-
01x11001VFMS-
01x11010VSUB (floating-point)-
01x11011VMLS (floating-point)-
01x11100UNALLOCATED-
01x11110VMIN (floating-point)-
01x11111VRSQRTS-
01000VSHL (register)-
010000VADD (integer)-
01000011VORR (register)-
010001VTST-
01001VQSHL (register)-
010010VMLA (integer)-
01010VRSHL-
01011VQRSHL-
010110VQDMULH-
01011000SHA1M-
010111VPADD (integer)-
01100VMAX (integer)-
01100011VORN (register)-
01101VMIN (integer)-
01110VABD (integer)-
01111VABA-
01111000SHA1SU0-
10x11010VPADD (floating-point)-
10x11011VMUL (floating-point)-
10x11100VCGE (register)A2-
10x11101VACGE-
10x111100VPMAX (floating-point)-
10x11111VMAXNM-
10000011VEOR-
10011VMUL (integer and polynomial)-
10011000SHA256H-
101000VPMAX (integer)-
10100011VBSL-
101001VPMIN (integer)-
10101UNALLOCATED-
10111000SHA256H2-
11x11010VABD (floating-point)-
11x11100VCGT (register)A2-
11x11101VACGT-
11x111100VPMIN (floating-point)-
11x11111VMINNM-
110000VSUB (integer)-
11000011VBIT-
110001VCEQ (register)A1-
110010VMLS (integer)-
110110VQRDMULH-
11011000SHA256SU1-
110111VQRDMLAHARMv8.1
11100011VBIF-
111001VQRDMLSHARMv8.1
1111110UNALLOCATED-

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
1111001op01op1op2op30
Decode fields Instruction details
op0op1op2op3
0 11 VEXT (byte elements)
1 11 0x Advanced SIMD two registers misc
1 11 10 VTBL, VTBX
1 11 11 Advanced SIMD duplicate (scalar)
!= 11 0 Advanced SIMD three registers of different lengths
!= 11 1 Advanced SIMD two registers and a scalar

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
111100111D11sizeopc1Vd0opc2QM0Vm
Decode fields Instruction Details
sizeopc1opc2Q
000000VREV64
000001VREV32
000010VREV16
000011UNALLOCATED
00010xVPADDL
0001100AESE
0001101AESD
0001110AESMC
0001111AESIMC
001000VCLS
00100000VSWP
001001VCLZ
001010VCNT
001011VMVN (register)
00110xVPADAL
001110VQABS
001111VQNEG
01x000VCGT (immediate #0)
01x001VCGE (immediate #0)
01x010VCEQ (immediate #0)
01x011VCLE (immediate #0)
01x100VCLT (immediate #0)
01x110VABS
01x111VNEG
0101011SHA1H
100001VTRN
100010VUZP
100011VZIP
1001000VMOVN
1001001VQMOVN, VQMOVUNVQMOVUN
100101VQMOVN, VQMOVUNVQMOVN
1001100VSHLL
1001110SHA1SU1
1001111SHA256SU0
101000VRINTN (Advanced SIMD)
101001VRINTX (Advanced SIMD)
101010VRINTA (Advanced SIMD)
101011VRINTZ (Advanced SIMD)
1011000VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision
1011001UNALLOCATED
101101VRINTM (Advanced SIMD)
1011100VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision
1011101UNALLOCATED
101111VRINTP (Advanced SIMD)
11000xVCVTA (Advanced SIMD)
11001xVCVTN (Advanced SIMD)
11010xVCVTP (Advanced SIMD)
11011xVCVTM (Advanced SIMD)
1110x0VRECPE
1110x1VRSQRTE
1111xxVCVT (between floating-point and integer, Advanced SIMD)

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
111100111D11imm4Vd11opcQM0Vm
Decode fields Instruction Details
opc
000VDUP (scalar)
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
1111001U1D!= 11VnVdopcN0M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
Uopc
0000VADDL
0001VADDW
0010VSUBL
00100VADDHN
0011VSUBW
00110VSUBHN
01001VQDMLAL
0101VABAL
01011VQDMLSL
01101VQDMULL
0111VABDL (integer)
1000VMLAL (integer)
1010VMLSL (integer)
10100VRADDHN
10110VRSUBHN
11x0VMULL (integer and polynomial)
11001UNALLOCATED
11011UNALLOCATED
11101UNALLOCATED
1111UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
1111001Q1D!= 11VnVdopcN1M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Architecture Version
Qopc
000xVMLA (by scalar)-
00011VQDMLAL-
0010VMLAL (by scalar)-
00111VQDMLSL-
010xVMLS (by scalar)-
01011VQDMULL-
0110VMLSL (by scalar)-
100xVMUL (by scalar)-
10011UNALLOCATED-
1010VMULL (by scalar)-
10111UNALLOCATED-
1100VQDMULH-
1101VQRDMULH-
11011UNALLOCATED-
1110VQRDMLAHARMv8.1
1111VQRDMLSHARMv8.1

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
11110011op01
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

313029282726252423222120191817161514131211109876543210
1111001i1D000imm3Vdcmode0Qop1imm4
Decode fields Instruction Details
cmodeop
0xx00VMOV (immediate)A1
0xx01VMVN (immediate)A1
0xx10VORR (immediate)A1
0xx11VBIC (immediate)A1
10x00VMOV (immediate)A3
10x01VMVN (immediate)A2
10x10VORR (immediate)A2
10x11VBIC (immediate)A2
11xx0VMOV (immediate)A4
110x1VMVN (immediate)A3
11101VMOV (immediate)A5
11111UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

313029282726252423222120191817161514131211109876543210
1111001U1Dimm3Himm3LVdopcLQM1Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
Uimm3H:Limm3LopcQ
!= 00000000VSHR
!= 00000001VSRA
!= 000000010100VMOVL
!= 00000010VRSHR
!= 00000011VRSRA
!= 00000111VQSHL, VQSHLU (immediate)VQSHL
!= 000010010VQSHRN, VQSHRUNVQSHRN
!= 000010011VQRSHRN, VQRSHRUNVQRSHRN
!= 000010100VSHLL
!= 000011xxVCVT (between floating-point and fixed-point, Advanced SIMD)
0!= 00000101VSHL (immediate)
0!= 000010000VSHRN
0!= 000010001VRSHRN
1!= 00000100VSRI
1!= 00000101VSLI
1!= 00000110VQSHL, VQSHLU (immediate)VQSHLU
1!= 000010000VQSHRN, VQSHRUNVQSHRUN
1!= 000010001VQRSHRN, VQRSHRUNVQRSHRUN

Memory hints and barriers

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
111101op01op1
Decode fields Instruction details
op0op1
00xx1 CONSTRAINED UNPREDICTABLE
01001 CONSTRAINED UNPREDICTABLE
01011 Barriers
011x1 CONSTRAINED UNPREDICTABLE
0xxx0 Preload (immediate)
1xxx0 0 Preload (register)
1xxx1 0 CONSTRAINED UNPREDICTABLE
1xxxx 1 UNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Barriers

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)opcodeoption
Decode fields Instruction Details
opcode
0000CONSTRAINED UNPREDICTABLE
0001CLREX
001xCONSTRAINED UNPREDICTABLE
0100DSB
0101DMB
0110ISB
0111CONSTRAINED UNPREDICTABLE
1xxxCONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Preload (immediate)

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
1111010DUR01Rn(1)(1)(1)(1)imm12
Decode fields Instruction Details
DRRn
00Reserved hint, behaves as NOP
01PLI (immediate, literal)
11111PLD (literal)
10!= 1111PLD, PLDW (immediate)preload write
11!= 1111PLD, PLDW (immediate)preload read

Preload (register)

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
1111011DUo201Rn(1)(1)(1)(1)imm5type0Rm
Decode fields Instruction Details
Do2
00Reserved hint, behaves as NOP
01PLI (register)
10PLD, PLDW (register)preload write
11PLD, PLDW (register)preload read

Advanced SIMD element or structure load/store

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
11110100op00op1
Decode fields Instruction details
op0op1
0 Advanced SIMD load/store multiple structures
1 11 Advanced SIMD load single structure to all lanes
1 != 11 Advanced SIMD load/store single structure to one lane

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101000DL0RnVdtypesizealignRm
Decode fields Instruction Details
Ltype
0000xVST4 (multiple 4-element structures)
00010VST1 (multiple single elements)A4
00011VST2 (multiple 2-element structures)A2
0010xVST3 (multiple 3-element structures)
00110VST1 (multiple single elements)A3
00111VST1 (multiple single elements)A1
0100xVST2 (multiple 2-element structures)A1
01010VST1 (multiple single elements)A2
1000xVLD4 (multiple 4-element structures)
10010VLD1 (multiple single elements)A4
10011VLD2 (multiple 2-element structures)A2
1010xVLD3 (multiple 3-element structures)
1011UNALLOCATED
10110VLD1 (multiple single elements)A3
10111VLD1 (multiple single elements)A1
11xxUNALLOCATED
1100xVLD2 (multiple 2-element structures)A1
11010VLD1 (multiple single elements)A2

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101001DL0RnVd11NsizeTaRm
Decode fields Instruction Details
LNa
0UNALLOCATED
100VLD1 (single element to all lanes)
101VLD2 (single 2-element structure to all lanes)
1100VLD3 (single 3-element structure to all lanes)
1101UNALLOCATED
111VLD4 (single 4-element structure to all lanes)

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101001DL0RnVd!= 11Nindex_alignRm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
LsizeN
00000VST1 (single element from one lane)A1
00001VST2 (single 2-element structure from one lane)A1
00010VST3 (single 3-element structure from one lane)A1
00011VST4 (single 4-element structure from one lane)A1
00100VST1 (single element from one lane)A2
00101VST2 (single 2-element structure from one lane)A2
00110VST3 (single 3-element structure from one lane)A2
00111VST4 (single 4-element structure from one lane)A2
01000VST1 (single element from one lane)A3
01001VST2 (single 2-element structure from one lane)A3
01010VST3 (single 3-element structure from one lane)A3
01011VST4 (single 4-element structure from one lane)A3
10000VLD1 (single element to one lane)A1
10001VLD2 (single 2-element structure to one lane)A1
10010VLD3 (single 3-element structure to one lane)A1
10011VLD4 (single 4-element structure to one lane)A1
10100VLD1 (single element to one lane)A2
10101VLD2 (single 2-element structure to one lane)A2
10110VLD3 (single 3-element structure to one lane)A2
10111VLD4 (single 4-element structure to one lane)A2
11000VLD1 (single element to one lane)A3
11001VLD2 (single 2-element structure to one lane)A3
11010VLD3 (single 3-element structure to one lane)A3
11011VLD4 (single 4-element structure to one lane)A3

Internal version only: isa v00_81v00_79, pseudocode v34.2.2v34.2 ; Build timestamp: 2018-03-28T202017-12-19T15:4342

Copyright © 2010-20182010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

ISA_v83A_AArch32_xml_00bet6 (old)htmldiff from-ISA_v83A_AArch32_xml_00bet6(new) ISA_v83A_AArch32_xml_00bet6.1