Pop SIMD&FP registers from Stack loads multiple consecutive Advanced SIMD and floating-point register file registers from the stack.
This is an alias of VLDM, VLDMDB, VLDMIA. This means:
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 0 | 0 | 1 | D | 1 | 1 | 1 | 1 | 0 | 1 | Vd | 1 | 0 | 1 | 1 | imm8<7:1> | 0 | ||||||||||||
cond | P | U | W | Rn | imm8<0> |
VPOP{<c>}{<q>}{.<size>} <dreglist>
is equivalent to
VLDM{<c>}{<q>}{.<size>} SP!, <dreglist>
and is always the preferred disassembly.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 0 | 0 | 1 | D | 1 | 1 | 1 | 1 | 0 | 1 | Vd | 1 | 0 | 1 | 0 | imm8 | |||||||||||||
cond | P | U | W | Rn |
VPOP{<c>}{<q>}{.<size>} <sreglist>
is equivalent to
VLDM{<c>}{<q>}{.<size>} SP!, <sreglist>
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | D | 1 | 1 | 1 | 1 | 0 | 1 | Vd | 1 | 0 | 1 | 1 | imm8<7:1> | 0 | |||||||||
P | U | W | Rn | imm8<0> |
VPOP{<c>}{<q>}{.<size>} <dreglist>
is equivalent to
VLDM{<c>}{<q>}{.<size>} SP!, <dreglist>
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | D | 1 | 1 | 1 | 1 | 0 | 1 | Vd | 1 | 0 | 1 | 0 | imm8 | ||||||||||
P | U | W | Rn |
VPOP{<c>}{<q>}{.<size>} <sreglist>
is equivalent to
VLDM{<c>}{<q>}{.<size>} SP!, <sreglist>
and is always the preferred disassembly.
<c> |
<q> |
<size> |
An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred. |
The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
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