ISA_v83A_AArch32_xml_00bet6 (old)htmldiff from-ISA_v83A_AArch32_xml_00bet6(new) ISA_v83A_AArch32_xml_00bet6.1

Top-level encodings for T32

15141312111098765432101514131211109876543210
op0op1
Decode fields Instruction details
op0op1
!= 111 16-bit
111 00 BT2
111 != 00 32-bit

16-bit

These instructions are under the top-level.

1514131211109876543210
op0

The following constraints also apply to this encoding: op0<5:3> != 111

Decode fields Instruction details
op0
00xxxx Shift (immediate), add, subtract, move, and compare
010000 Data-processing (two low registers)
010001 Special data instructions and branch and exchange
01001x LDR (literal)T1
0101xx Load/store (register offset)
011xxx Load/store word/byte (immediate offset)
1000xx Load/store halfword (immediate offset)
1001xx Load/store (SP-relative)
1010xx Add PC/SP (immediate)
1011xx Miscellaneous 16-bit instructions
1100xx Load/store multiple
1101xx Conditional branch, and Supervisor Call

Shift (immediate), add, subtract, move, and compare

These instructions are under 16-bit.

1514131211109876543210
00op0op1op2
Decode fields Instruction details
op0op1op2
0 11 0 Add, subtract (three low registers)
0 11 1 Add, subtract (two low registers and immediate)
0 != 11 MOV, MOVS (register)T2
1 Add, subtract, compare, move (one low register and immediate)

Add, subtract (three low registers)

These instructions are under Shift (immediate), add, subtract, move, and compare.

1514131211109876543210
000110SRmRnRd
Decode fields Instruction Details
S
0ADD, ADDS (register)
1SUB, SUBS (register)

Add, subtract (two low registers and immediate)

These instructions are under Shift (immediate), add, subtract, move, and compare.

1514131211109876543210
000111Simm3RnRd
Decode fields Instruction Details
S
0ADD, ADDS (immediate)
1SUB, SUBS (immediate)

Add, subtract, compare, move (one low register and immediate)

These instructions are under Shift (immediate), add, subtract, move, and compare.

1514131211109876543210
001opRdimm8
Decode fields Instruction Details
op
00MOV, MOVS (immediate)
01CMP (immediate)
10ADD, ADDS (immediate)
11SUB, SUBS (immediate)

Data-processing (two low registers)

These instructions are under 16-bit.

1514131211109876543210
010000opRsRd
Decode fields Instruction Details
op
0000AND, ANDS (register)
0001EOR, EORS (register)
0010MOV, MOVS (register-shifted register)logical shift left
0011MOV, MOVS (register-shifted register)logical shift right
0100MOV, MOVS (register-shifted register)arithmetic shift right
0101ADC, ADCS (register)
0110SBC, SBCS (register)
0111MOV, MOVS (register-shifted register)rotate right
1000TST (register)
1001RSB, RSBS (immediate)
1010CMP (register)
1011CMN (register)
1100ORR, ORRS (register)
1101MUL, MULS
1110BIC, BICS (register)
1111MVN, MVNS (register)

Special data instructions and branch and exchange

These instructions are under 16-bit.

1514131211109876543210
010001op0
Decode fields Instruction details
op0
11 Branch and exchange
!= 11 Add, subtract, compare, move (two high registers)

Branch and exchange

These instructions are under Special data instructions and branch and exchange.

1514131211109876543210
01000111LRm(0)(0)(0)
Decode fields Instruction Details
L
0BX
1BLX (register)

Add, subtract, compare, move (two high registers)

These instructions are under Special data instructions and branch and exchange.

1514131211109876543210
010001!= 11DRsRd
op

The following constraints also apply to this encoding: op != 11 && op != 11

Decode fields Instruction Details
opD:RdRs
00!= 1101!= 1101ADD, ADDS (register)
001101ADD, ADDS (SP plus register)T1
001101!= 1101ADD, ADDS (SP plus register)T2
01CMP (register)
10MOV, MOVS (register)

Load/store (register offset)

These instructions are under 16-bit.

1514131211109876543210
0101LBHRmRnRt
Decode fields Instruction Details
LBH
000STR (register)
001STRH (register)
010STRB (register)
011LDRSB (register)
100LDR (register)
101LDRH (register)
110LDRB (register)
111LDRSH (register)

Load/store word/byte (immediate offset)

These instructions are under 16-bit.

1514131211109876543210
011BLimm5RnRt
Decode fields Instruction Details
BL
00STR (immediate)
01LDR (immediate)
10STRB (immediate)
11LDRB (immediate)

Load/store halfword (immediate offset)

These instructions are under 16-bit.

1514131211109876543210
1000Limm5RnRt
Decode fields Instruction Details
L
0STRH (immediate)
1LDRH (immediate)

Load/store (SP-relative)

These instructions are under 16-bit.

1514131211109876543210
1001LRtimm8
Decode fields Instruction Details
L
0STR (immediate)
1LDR (immediate)

Add PC/SP (immediate)

These instructions are under 16-bit.

1514131211109876543210
1010SPRdimm8
Decode fields Instruction Details
SP
0ADR
1ADD, ADDS (SP plus immediate)

Miscellaneous 16-bit instructions

These instructions are under 16-bit.

1514131211109876543210
1011op0op1op2op3
Decode fields Instruction details Architecture version
op0op1op2op3
0000 Adjust SP (immediate)-
0010 Extend-
0110 00 0 SETPANARMv8.1
0110 00 1 UNALLOCATED-
0110 01 Change Processor State-
0110 1x UNALLOCATED-
0111 UNALLOCATED-
1000 UNALLOCATED-
1010 10 HLT-
1010 != 10 Reverse bytes-
1110 BKPT-
1111 0000 Hints-
1111 != 0000 IT-
x0x1 CBNZ, CBZ-
x10x Push and Pop-

Adjust SP (immediate)

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
10110000Simm7
Decode fields Instruction Details
S
0ADD, ADDS (SP plus immediate)
1SUB, SUBS (SP minus immediate)

Extend

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
10110010UBRmRd
Decode fields Instruction Details
UB
00SXTH
01SXTB
10UXTH
11UXTB

Change Processor State

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
1011011001opflags
Decode fields Instruction Details
opflags
0SETEND
1CPS, CPSID, CPSIE

Reverse bytes

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
10111010!= 10RmRd
op

The following constraints also apply to this encoding: op != 10 && op != 10

Decode fields Instruction Details
op
00REV
01REV16
11REVSH

Hints

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
10111111hint0000
Decode fields Instruction Details
hint
0000NOP
0001YIELD
0010WFE
0011WFI
0100SEV
0101SEVL
011xReserved hint, behaves as NOP
1xxxReserved hint, behaves as NOP

Push and Pop

These instructions are under Miscellaneous 16-bit instructions.

1514131211109876543210
1011L10Pregister_list
Decode fields Instruction Details
L
0PUSH
1POP

Load/store multiple

These instructions are under 16-bit.

1514131211109876543210
1100LRnregister_list
Decode fields Instruction Details
L
0STM, STMIA, STMEA
1LDM, LDMIA, LDMFD

Conditional branch, and Supervisor Call

These instructions are under 16-bit.

1514131211109876543210
1101op0
Decode fields Instruction details
op0
111x Exception generation
!= 111x BT1

Exception generation

These instructions are under Conditional branch, and Supervisor Call.

1514131211109876543210
1101111Simm8
Decode fields Instruction Details
S
0UDF
1SVC

32-bit

These instructions are under the top-level.

15141312111098765432101514131211109876543210
111op0op1op3

The following constraints also apply to this encoding: op0<3:2> != 00

Decode fields Instruction details
op0op1op3
x11x System register access, Advanced SIMD, and floating-point
0100 xx0xx Load/store multiple
0100 xx1xx Load/store dual, load/store exclusive, load-acquire/store-release, and table branch
0101 Data-processing (shifted register)
10xx 1 Branches and miscellaneous control
10x0 0 Data-processing (modified immediate)
10x1 0 Data-processing (plain binary immediate)
1100 1xxx0 Advanced SIMD element or structure load/store
1100 != 1xxx0 Load/store single
1101 0xxxx Data-processing (register)
1101 10xxx Multiply, multiply accumulate, and absolute difference
1101 11xxx Long multiply and divide

System register access, Advanced SIMD, and floating-point

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
111op011op1op2op3
Decode fields Instruction details
op0op1op2op3
0x 111 System register load/store and 64-bit move
10 10x 0 Floating-point data-processing
10 111 1 System register 32-bit move
11 Advanced SIMD data-processing
0 0x 10x Advanced SIMD load/store and 64-bit move
0 10 10x 1 Advanced SIMD and floating-point 32-bit move
1 0x 1x0 Advanced SIMD three registers of the same length extension
1 10 1x0 Advanced SIMD two registers and a scalar extension

System register load/store and 64-bit move

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
111110op0111
Decode fields Instruction details
op0
00x0 System register 64-bit move
!= 00x0 System register Load/Store

System register 64-bit move

These instructions are under System register load/store and 64-bit move.

15141312111098765432101514131211109876543210
111o011000D0LRt2Rt111cp15opc1CRm
Decode fields Instruction Details
o0DL
00UNALLOCATED
010MCRR
011MRRC
10UNALLOCATED
11UNALLOCATED

System register Load/Store

These instructions are under System register load/store and 64-bit move.

15141312111098765432101514131211109876543210
111o0110PUDWLRnCRd111cp15imm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
o0P:U:WDLRnCRdcp15
!= 000!= 01010UNALLOCATED
!= 0001UNALLOCATED
!= 000101010UNALLOCATED
0!= 00001111101010LDC (literal)
00x10001010STCpost-indexed
00x101!= 111101010LDC (immediate)post-indexed
00100001010STCunindexed
001001!= 111101010LDC (immediate)unindexed
01x00001010STCoffset
01x001!= 111101010LDC (immediate)offset
01x10001010STCpre-indexed
01x101!= 111101010LDC (immediate)pre-indexed
1!= 000001010UNALLOCATED

Floating-point data-processing

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
111op01110op1op210op3op40
Decode fields Instruction details
op0op1op2op3op4
0 1x11 1 Floating-point data-processing (two registers)
0 1x11 0 Floating-point move immediate
0 != 1x11 Floating-point data-processing (three registers)
1 0xxx != 00 0 Floating-point conditional select
1 1x00 != 00 Floating-point minNum/maxNum
1 1x11 0000 != 00 1 Floating-point extraction and insertion
1 1x11 1xxx != 00 1 Floating-point directed convert to integer

Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111011101D11o1opc2Vd10sizeo31M0Vm
Decode fields Instruction Details Architecture Version
o1opc2sizeo3
00UNALLOCATED-
0000010UNALLOCATED-
00001VABS-
0000100VMOV (register)single-precision scalar-
0000110VMOV (register)double-precision scalar-
00010VNEG-
00011VSQRT-
001x01UNALLOCATED-
00100VCVTBhalf-precision to double-precision-
00101VCVTThalf-precision to double-precision-
00110VCVTBdouble-precision to half-precision-
00111VCVTTdouble-precision to half-precision-
01000VCMPT1-
01001VCMPET1-
01010VCMPT2-
01011VCMPET2-
01100VRINTR-
01101VRINTZ (floating-point)-
01110VRINTX (floating-point)-
0111011UNALLOCATED-
0111101VCVT (between double-precision and single-precision)single-precision to double-precision-
0111111VCVT (between double-precision and single-precision)double-precision to single-precision-
1000VCVT (integer to floating-point, floating-point)-
100101UNALLOCATED-
100110UNALLOCATED-
1001110UNALLOCATED-
1001111VJCVTARMv8.3
101xVCVT (between floating-point and fixed-point, floating-point)-
11000VCVTR-
11001VCVT (floating-point to integer, floating-point)-
11010VCVTR-
11011VCVT (floating-point to integer, floating-point)-
111xVCVT (between floating-point and fixed-point, floating-point)-

Floating-point move immediate

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111011101D11imm4HVd10size(0)0(0)0imm4L
Decode fields Instruction Details Architecture Version
size
00UNALLOCATED-
01VMOV (immediate)half-precision scalarARMv8.2
10VMOV (immediate)single-precision scalar-
11VMOV (immediate)double-precision scalar-

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
11101110o0Do1VnVd10sizeNo2M0Vm

The following constraints also apply to this encoding: o0:D:o1 != 1x11

Decode fields Instruction Details
o0:o1sizeo2
!= 11100UNALLOCATED
0000VMLA (floating-point)
0001VMLS (floating-point)
0010VNMLS
0011VNMLA
0100VMUL (floating-point)
0101VNMUL
0110VADD (floating-point)
0111VSUB (floating-point)
1000VDIV
1010VFNMS
1011VFNMA
1100VFMA
1101VFMS

Floating-point conditional select

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111111100DccVnVd10!= 00N0M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
ccsize
00VSELEQ, VSELGE, VSELGT, VSELVSVSELEQ
01VSELEQ, VSELGE, VSELGT, VSELVSVSELVS
01UNALLOCATED
10VSELEQ, VSELGE, VSELGT, VSELVSVSELGE
11VSELEQ, VSELGE, VSELGT, VSELVSVSELGT

Floating-point minNum/maxNum

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111111101D00VnVd10!= 00NopM0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
sizeop
0VMAXNM
01UNALLOCATED
1VMINNM

Floating-point extraction and insertion

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111111101D110000Vd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Architecture Version
sizeop
01UNALLOCATED-
100VMOVXARMv8.2
101VINSARMv8.2
11UNALLOCATED-

Floating-point directed convert to integer

These instructions are under Floating-point data-processing.

15141312111098765432101514131211109876543210
111111101D111o1RMVd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details
o1RMsize
000VRINTA (floating-point)
001VRINTN (floating-point)
01UNALLOCATED
010VRINTP (floating-point)
011VRINTM (floating-point)
100VCVTA (floating-point)
101VCVTN (floating-point)
110VCVTP (floating-point)
111VCVTM (floating-point)

System register 32-bit move

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
111o01110opc1LCRnRt111cp15opc21CRm
Decode fields Instruction Details
o0L
00MCR
01MRC
1UNALLOCATED

Advanced SIMD data-processing

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
1111111op0op1
Decode fields Instruction details
op0op1
0 Advanced SIMD three registers of the same length
1 0 Advanced SIMD two registers, or three registers of different lengths
1 1 Advanced SIMD shifts and immediate generation

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

15141312111098765432101514131211109876543210
111U11110DsizeVnVdopcNQMo1Vm
Decode fields Instruction Details Architecture Version
UsizeopcQo1
00x11001VFMA-
00x11010VADD (floating-point)-
00x11011VMLA (floating-point)-
00x11100VCEQ (register)T2-
00x11110VMAX (floating-point)-
00x11111VRECPS-
00000VHADD-
00000011VAND (register)-
00001VQADD-
00010VRHADD-
00011000SHA1C-
00100VHSUB-
00100011VBIC (register)-
00101VQSUB-
00110VCGT (register)T1-
00111VCGE (register)T1-
00111000SHA1P-
01x11001VFMS-
01x11010VSUB (floating-point)-
01x11011VMLS (floating-point)-
01x11100UNALLOCATED-
01x11110VMIN (floating-point)-
01x11111VRSQRTS-
01000VSHL (register)-
010000VADD (integer)-
01000011VORR (register)-
010001VTST-
01001VQSHL (register)-
010010VMLA (integer)-
01010VRSHL-
01011VQRSHL-
010110VQDMULH-
01011000SHA1M-
010111VPADD (integer)-
01100VMAX (integer)-
01100011VORN (register)-
01101VMIN (integer)-
01110VABD (integer)-
01111VABA-
01111000SHA1SU0-
10x11010VPADD (floating-point)-
10x11011VMUL (floating-point)-
10x11100VCGE (register)T2-
10x11101VACGE-
10x111100VPMAX (floating-point)-
10x11111VMAXNM-
10000011VEOR-
10011VMUL (integer and polynomial)-
10011000SHA256H-
101000VPMAX (integer)-
10100011VBSL-
101001VPMIN (integer)-
10101UNALLOCATED-
10111000SHA256H2-
11x11010VABD (floating-point)-
11x11100VCGT (register)T2-
11x11101VACGT-
11x111100VPMIN (floating-point)-
11x11111VMINNM-
110000VSUB (integer)-
11000011VBIT-
110001VCEQ (register)T1-
110010VMLS (integer)-
110110VQRDMULH-
11011000SHA256SU1-
110111VQRDMLAHARMv8.1
11100011VBIF-
111001VQRDMLSHARMv8.1
1111110UNALLOCATED-

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

15141312111098765432101514131211109876543210
111op011111op1op2op30
Decode fields Instruction details
op0op1op2op3
0 11 VEXT (byte elements)
1 11 0x Advanced SIMD two registers misc
1 11 10 VTBL, VTBX
1 11 11 Advanced SIMD duplicate (scalar)
!= 11 0 Advanced SIMD three registers of different lengths
!= 11 1 Advanced SIMD two registers and a scalar

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15141312111098765432101514131211109876543210
111111111D11sizeopc1Vd0opc2QM0Vm
Decode fields Instruction Details
sizeopc1opc2Q
000000VREV64
000001VREV32
000010VREV16
000011UNALLOCATED
00010xVPADDL
0001100AESE
0001101AESD
0001110AESMC
0001111AESIMC
001000VCLS
00100000VSWP
001001VCLZ
001010VCNT
001011VMVN (register)
00110xVPADAL
001110VQABS
001111VQNEG
01x000VCGT (immediate #0)
01x001VCGE (immediate #0)
01x010VCEQ (immediate #0)
01x011VCLE (immediate #0)
01x100VCLT (immediate #0)
01x110VABS
01x111VNEG
0101011SHA1H
100001VTRN
100010VUZP
100011VZIP
1001000VMOVN
1001001VQMOVN, VQMOVUNVQMOVUN
100101VQMOVN, VQMOVUNVQMOVN
1001100VSHLL
1001110SHA1SU1
1001111SHA256SU0
101000VRINTN (Advanced SIMD)
101001VRINTX (Advanced SIMD)
101010VRINTA (Advanced SIMD)
101011VRINTZ (Advanced SIMD)
1011000VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision
1011001UNALLOCATED
101101VRINTM (Advanced SIMD)
1011100VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision
1011101UNALLOCATED
101111VRINTP (Advanced SIMD)
11000xVCVTA (Advanced SIMD)
11001xVCVTN (Advanced SIMD)
11010xVCVTP (Advanced SIMD)
11011xVCVTM (Advanced SIMD)
1110x0VRECPE
1110x1VRSQRTE
1111xxVCVT (between floating-point and integer, Advanced SIMD)

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15141312111098765432101514131211109876543210
111111111D11imm4Vd11opcQM0Vm
Decode fields Instruction Details
opc
000VDUP (scalar)
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15141312111098765432101514131211109876543210
111U11111D!= 11VnVdopcN0M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
Uopc
0000VADDL
0001VADDW
0010VSUBL
00100VADDHN
0011VSUBW
00110VSUBHN
01001VQDMLAL
0101VABAL
01011VQDMLSL
01101VQDMULL
0111VABDL (integer)
1000VMLAL (integer)
1010VMLSL (integer)
10100VRADDHN
10110VRSUBHN
11x0VMULL (integer and polynomial)
11001UNALLOCATED
11011UNALLOCATED
11101UNALLOCATED
1111UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

15141312111098765432101514131211109876543210
111Q11111D!= 11VnVdopcN1M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Architecture Version
Qopc
000xVMLA (by scalar)-
00011VQDMLAL-
0010VMLAL (by scalar)-
00111VQDMLSL-
010xVMLS (by scalar)-
01011VQDMULL-
0110VMLSL (by scalar)-
100xVMUL (by scalar)-
10011UNALLOCATED-
1010VMULL (by scalar)-
10111UNALLOCATED-
1100VQDMULH-
1101VQRDMULH-
11011UNALLOCATED-
1110VQRDMLAHARMv8.1
1111VQRDMLSHARMv8.1

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

15141312111098765432101514131211109876543210
11111111op01
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

15141312111098765432101514131211109876543210
111i11111D000imm3Vdcmode0Qop1imm4
Decode fields Instruction Details
cmodeop
0xx00VMOV (immediate)T1
0xx01VMVN (immediate)T1
0xx10VORR (immediate)T1
0xx11VBIC (immediate)T1
10x00VMOV (immediate)T3
10x01VMVN (immediate)T2
10x10VORR (immediate)T2
10x11VBIC (immediate)T2
11xx0VMOV (immediate)T4
110x1VMVN (immediate)T3
11101VMOV (immediate)T5
11111UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

15141312111098765432101514131211109876543210
111U11111Dimm3Himm3LVdopcLQM1Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
Uimm3H:Limm3LopcQ
!= 00000000VSHR
!= 00000001VSRA
!= 000000010100VMOVL
!= 00000010VRSHR
!= 00000011VRSRA
!= 00000111VQSHL, VQSHLU (immediate)VQSHL
!= 000010010VQSHRN, VQSHRUNVQSHRN
!= 000010011VQRSHRN, VQRSHRUNVQRSHRN
!= 000010100VSHLL
!= 000011xxVCVT (between floating-point and fixed-point, Advanced SIMD)
0!= 00000101VSHL (immediate)
0!= 000010000VSHRN
0!= 000010001VRSHRN
1!= 00000100VSRI
1!= 00000101VSLI
1!= 00000110VQSHL, VQSHLU (immediate)VQSHLU
1!= 000010000VQSHRN, VQSHRUNVQSHRUN
1!= 000010001VQRSHRN, VQRSHRUNVQRSHRUN

Advanced SIMD load/store and 64-bit move

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
1110110op010
Decode fields Instruction details
op0
00x0 Advanced SIMD and floating-point 64-bit move
!= 00x0 Advanced SIMD and floating-point load/store

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD load/store and 64-bit move.

15141312111098765432101514131211109876543210
111011000D0opRt2Rt10sizeopc2Mo3Vm
Decode fields Instruction Details
Dopsizeopc2o3
0UNALLOCATED
10UNALLOCATED
10x001UNALLOCATED
101UNALLOCATED
1010001VMOV (between two general-purpose registers and two single-precision registers)from general-purpose registers
1011001VMOV (between two general-purpose registers and a doubleword floating-point register)from general-purpose registers
11xUNALLOCATED
1110001VMOV (between two general-purpose registers and two single-precision registers)to general-purpose registers
1111001VMOV (between two general-purpose registers and a doubleword floating-point register)to general-purpose registers

Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD load/store and 64-bit move.

15141312111098765432101514131211109876543210
1110110PUDWLRnVd10sizeimm8

The following constraints also apply to this encoding: P:U:D:W != 00x0

Decode fields Instruction Details
PUWLRnsizeimm8
001UNALLOCATED
010xUNALLOCATED
01010VSTM, VSTMDB, VSTMIA
01011xxxxxxx0VSTM, VSTMDB, VSTMIA
01011xxxxxxx1FSTMDBX, FSTMIAXIncrement After
01110VLDM, VLDMDB, VLDMIA
01111xxxxxxx0VLDM, VLDMDB, VLDMIA
01111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Increment After
100VSTR
1000UNALLOCATED
101!= 1111VLDR (immediate)
1010xUNALLOCATED
101010VSTM, VSTMDB, VSTMIA
101011xxxxxxx0VSTM, VSTMDB, VSTMIA
101011xxxxxxx1FSTMDBX, FSTMIAXDecrement Before
101110VLDM, VLDMDB, VLDMIA
101111xxxxxxx0VLDM, VLDMDB, VLDMIA
101111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Decrement Before
1011111VLDR (literal)
111UNALLOCATED

Advanced SIMD and floating-point 32-bit move

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
11101110op0101op111111
Decode fields Instruction details
op0op1
000 0 VMOV (between general-purpose register and single-precision)
111 0 Floating-point move special register
1 Advanced SIMD 8/16/32-bit element move/duplicate

Floating-point move special register

These instructions are under Advanced SIMD and floating-point 32-bit move.

15141312111098765432101514131211109876543210
11101110111LregRt1010(0)(0)(0)1(0)(0)(0)(0)
Decode fields Instruction Details
L
0VMSR
1VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and floating-point 32-bit move.

15141312111098765432101514131211109876543210
11101110opc1LVnRt1011Nopc21(0)(0)(0)(0)
Decode fields Instruction Details
opc1Lopc2
0xx0VMOV (general-purpose register to scalar)
1VMOV (scalar to general-purpose register)
1xx00xVDUP (general-purpose register)
1xx01xUNALLOCATED

Advanced SIMD three registers of the same length extension

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
1111110op1Dop2VnVd1op30op4NQMUVm
Decode fields Instruction Details Architecture Version
op1op2op3op4QU
x10x000VCADDARMv8.3
0010001VFMAL (vector)ARMv8.2
00101100VSDOT (vector)64-bit SIMD vectorARMv8.2
00101101VUDOT (vector)64-bit SIMD vectorARMv8.2
00101110VSDOT (vector)128-bit SIMD vectorARMv8.2
00101111VUDOT (vector)128-bit SIMD vectorARMv8.2
0110001VFMSL (vector)ARMv8.2
1x000VCMLAARMv8.3

Advanced SIMD two registers and a scalar extension

These instructions are under System register access, Advanced SIMD, and floating-point.

15141312111098765432101514131211109876543210
11111110op1Dop2VnVd1op30op4NQMUVm
Decode fields Instruction Details Architecture Version
op1op2op3op4QU
0000VCMLA (by element)half-precision scalarARMv8.3
000001VFMAL (by scalar)ARMv8.2
001001VFMSL (by scalar)ARMv8.2
0101100VSDOT (by element)64-bit SIMD vectorARMv8.2
0101101VUDOT (by element)64-bit SIMD vectorARMv8.2
0101110VSDOT (by element)128-bit SIMD vectorARMv8.2
0101111VUDOT (by element)128-bit SIMD vectorARMv8.2
1000VCMLA (by element)single-precision scalarARMv8.3

Load/store multiple

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
1110100opc0WLRnPM(0)register_list
Decode fields Instruction Details
opcL
000SRS, SRSDA, SRSDB, SRSIA, SRSIBT1
001RFE, RFEDA, RFEDB, RFEIA, RFEIBT1
010STM, STMIA, STMEA
011LDM, LDMIA, LDMFD
100STMDB, STMFD
101LDMDB, LDMEA
110SRS, SRSDA, SRSDB, SRSIA, SRSIBT2
111RFE, RFEDA, RFEDB, RFEIA, RFEIBT2

Load/store dual, load/store exclusive, load-acquire/store-release, and table branch

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
1110100op0op1op2op3

The following constraints also apply to this encoding: op0<1> == 1

Decode fields Instruction details
op0op1op2op3
0010 Load/store exclusive
0110 0 000 UNALLOCATED
0110 1 000 TBB, TBH
0110 01x Load/store exclusive byte/half/dual
0110 1xx Load-acquire / Store-release
0x11 != 1111 Load/store dual (immediate, post-indexed)
1x10 != 1111 Load/store dual (immediate)
1x11 != 1111 Load/store dual (immediate, pre-indexed)
!= 0xx0 1111 LDRD (literal)

Load/store exclusive

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101000010LRnRtRdimm8
Decode fields Instruction Details
L
0STREX
1LDREX

Load/store exclusive byte/half/dual

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101000110LRnRtRt201szRd
Decode fields Instruction Details
Lsz
000STREXB
001STREXH
010UNALLOCATED
011STREXD
100LDREXB
101LDREXH
110UNALLOCATED
111LDREXD

Load-acquire / Store-release

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101000110LRnRtRt21opszRd
Decode fields Instruction Details
Lopsz
0000STLB
0001STLH
0010STL
0011UNALLOCATED
0100STLEXB
0101STLEXH
0110STLEX
0111STLEXD
1000LDAB
1001LDAH
1010LDA
1011UNALLOCATED
1100LDAEXB
1101LDAEXH
1110LDAEX
1111LDAEXD

Load/store dual (immediate, post-indexed)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101000U11L!= 1111RtRt2imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0STRD (immediate)
1LDRD (immediate)

Load/store dual (immediate)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101001U10L!= 1111RtRt2imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0STRD (immediate)
1LDRD (immediate)

Load/store dual (immediate, pre-indexed)

These instructions are under Load/store dual, load/store exclusive, load-acquire/store-release, and table branch.

15141312111098765432101514131211109876543210
11101001U11L!= 1111RtRt2imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
L
0STRD (immediate)
1LDRD (immediate)

Data-processing (shifted register)

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
1110101op1SRn(0)imm3Rdimm2typeRm
Decode fields Instruction Details
op1SRnimm3:imm2:typeRd
00000AND, ANDS (register)AND, rotate right with extend
00001!= 0000011!= 1111AND, ANDS (register)ANDS, shift or rotate by value
00001!= 00000111111TST (register)shift or rotate by value
000010000011!= 1111AND, ANDS (register)ANDS, rotate right with extend
0000100000111111TST (register)rotate right with extend
0001BIC, BICS (register)
00100!= 1111ORR, ORRS (register)ORR
001001111MOV, MOVS (register)MOV
00101!= 1111ORR, ORRS (register)ORRS
001011111MOV, MOVS (register)MOVS
00110!= 1111ORN, ORNS (register)not flag setting
001101111MVN, MVNS (register)MVN
00111!= 1111ORN, ORNS (register)flag setting
001111111MVN, MVNS (register)MVNS
01000EOR, EORS (register)EOR, rotate right with extend
01001!= 0000011!= 1111EOR, EORS (register)EORS, shift or rotate by value
01001!= 00000111111TEQ (register)shift or rotate by value
010010000011!= 1111EOR, EORS (register)EORS, rotate right with extend
0100100000111111TEQ (register)rotate right with extend
0101UNALLOCATED
01100xxxxx00PKHBT, PKHTBPKHBT
01100xxxxx01UNALLOCATED
01100xxxxx10PKHBT, PKHTBPKHTB
01100xxxxx11UNALLOCATED
0111UNALLOCATED
10000!= 1101ADD, ADDS (register)ADD
100001101ADD, ADDS (SP plus register)ADD
10001!= 1101!= 1111ADD, ADDS (register)ADDS
100011101!= 1111ADD, ADDS (SP plus register)ADDS
100011111CMN (register)
1001UNALLOCATED
1010ADC, ADCS (register)
1011SBC, SBCS (register)
1100UNALLOCATED
11010!= 1101SUB, SUBS (register)SUB
110101101SUB, SUBS (SP minus register)SUB
11011!= 1101!= 1111SUB, SUBS (register)SUBS
110111101!= 1111SUB, SUBS (SP minus register)SUBS
110111111CMP (register)
1110RSB, RSBS (register)
1111UNALLOCATED

Branches and miscellaneous control

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
11110op0op1op21op3op4op5
Decode fields Instruction details
op0op1op2op3op4op5
0 1110 0x 0x0 0 MSR (register)
0 1110 0x 0x0 1 MSR (Banked register)
0 1110 10 0x0 000 Hints
0 1110 10 0x0 != 000 Change processor state
0 1110 11 0x0 Miscellaneous system
0 1111 00 0x0 BXJ
0 1111 01 0x0 Exception return
0 1111 1x 0x0 0 MRS
0 1111 1x 0x0 1 MRS (Banked register)
1 1110 00 000 DCPS
1 1110 00 010 UNALLOCATED
1 1110 01 0x0 UNALLOCATED
1 1110 1x 0x0 UNALLOCATED
1 1111 0x 0x0 UNALLOCATED
1 1111 1x 0x0 Exception generation
!= 111x 0x0 BT3
0x1 BT4
1x0 BL, BLX (immediate)T2
1x1 BL, BLX (immediate)T1

Hints

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)000hintoption
Decode fields Instruction Details Architecture Version
hintoption
00000000NOP-
00000001YIELD-
00000010WFE-
00000011WFI-
00000100SEV-
00000101SEVL-
0000011xReserved hint, behaves as NOP-
00001xxxReserved hint, behaves as NOP-
0001!= 0000Reserved hint, behaves as NOPESBARMv8.2-
000100010000ESBReserved hint, behaves as NOP-ARMv8.2
0001001x0011Reserved hint, behaves as NOP-
00010100CSDB-
01xxReserved hint, behaves as NOP-
000110xx0101Reserved hint, behaves as NOP-
0001110x011xReserved hint, behaves as NOP-
000111101xxxReserved hint, behaves as NOP-
001x1111DBGReserved hint, behaves as NOP-
01xxReserved hint, behaves as NOP-
10xxReserved hint, behaves as NOP-
110xReserved hint, behaves as NOP-
1110Reserved hint, behaves as NOP-
1111DBG-

Change processor state

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)imodMAIFmode

The following constraints also apply to this encoding: imod:M != 000

Decode fields Instruction Details
imodM
001CPS, CPSID, CPSIECPS
01UNALLOCATED
10CPS, CPSID, CPSIECPSIE
11CPS, CPSID, CPSIECPSID

Miscellaneous system

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
111100111011(1)(1)(1)(1)10(0)0(1)(1)(1)(1)opcoption
Decode fields Instruction Details
opc
000xUNALLOCATED
0010CLREX
0011UNALLOCATED
0100DSB
0101DMB
0110ISB
0111UNALLOCATED
1xxxUNALLOCATED

Exception return

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
111100111101Rn10(0)0(1)(1)(1)(1)imm8
Decode fields Instruction Details
Rnimm8
!= 00000000SUB, SUBS (immediate)
111000000000ERET

DCPS

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
111101111000imm41000imm10opt
Decode fields Instruction Details
imm4imm10opt
!= 1111UNALLOCATED
1111!= 0000000000UNALLOCATED
1111000000000000UNALLOCATED
1111000000000001DCPS1, DCPS2, DCPS3DCPS1
1111000000000010DCPS1, DCPS2, DCPS3DCPS2
1111000000000011DCPS1, DCPS2, DCPS3DCPS3

Exception generation

These instructions are under Branches and miscellaneous control.

15141312111098765432101514131211109876543210
11110111111o1imm410o20imm12
Decode fields Instruction Details
o1o2
00HVC
01UNALLOCATED
10SMC
11UDF

Data-processing (modified immediate)

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
11110i0op1SRn0imm3Rdimm8
Decode fields Instruction Details
op1SRnRd
00000AND, ANDS (immediate)AND
00001!= 1111AND, ANDS (immediate)ANDS
000011111TST (immediate)
0001BIC, BICS (immediate)
00100!= 1111ORR, ORRS (immediate)ORR
001001111MOV, MOVS (immediate)MOV
00101!= 1111ORR, ORRS (immediate)ORRS
001011111MOV, MOVS (immediate)MOVS
00110!= 1111ORN, ORNS (immediate)not flag setting
001101111MVN, MVNS (immediate)MVN
00111!= 1111ORN, ORNS (immediate)flag setting
001111111MVN, MVNS (immediate)MVNS
01000EOR, EORS (immediate)EOR
01001!= 1111EOR, EORS (immediate)EORS
010011111TEQ (immediate)
0101UNALLOCATED
011xUNALLOCATED
10000!= 1101ADD, ADDS (immediate)ADD
100001101ADD, ADDS (SP plus immediate)ADD
10001!= 1101!= 1111ADD, ADDS (immediate)ADDS
100011101!= 1111ADD, ADDS (SP plus immediate)ADDS
100011111CMN (immediate)
1001UNALLOCATED
1010ADC, ADCS (immediate)
1011SBC, SBCS (immediate)
1100UNALLOCATED
11010!= 1101SUB, SUBS (immediate)SUB
110101101SUB, SUBS (SP minus immediate)SUB
11011!= 1101!= 1111SUB, SUBS (immediate)SUBS
110111101!= 1111SUB, SUBS (SP minus immediate)SUBS
110111111CMP (immediate)
1110RSB, RSBS (immediate)
1111UNALLOCATED

Data-processing (plain binary immediate)

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
111101op0op100
Decode fields Instruction details
op0op1
0 0x Data-processing (simple immediate)
0 10 Move Wide (16-bit immediate)
0 11 UNALLOCATED
1 Saturate, Bitfield

Data-processing (simple immediate)

These instructions are under Data-processing (plain binary immediate).

15141312111098765432101514131211109876543210
11110i10o10o20Rn0imm3Rdimm8
Decode fields Instruction Details
o1o2Rn
00!= 11x1ADD, ADDS (immediate)
001101ADD, ADDS (SP plus immediate)
001111ADRT3
01UNALLOCATED
10UNALLOCATED
11!= 11x1SUB, SUBS (immediate)
111101SUB, SUBS (SP minus immediate)
111111ADRT2

Move Wide (16-bit immediate)

These instructions are under Data-processing (plain binary immediate).

15141312111098765432101514131211109876543210
11110i10o1100imm40imm3Rdimm8
Decode fields Instruction Details
o1
0MOV, MOVS (immediate)
1MOVT

Saturate, Bitfield

These instructions are under Data-processing (plain binary immediate).

15141312111098765432101514131211109876543210
11110(0)11op10Rn0imm3Rdimm2(0)widthm1
Decode fields Instruction Details
op1Rnimm3:imm2
000SSATlogical shift left
001!= 00000SSATarithmetic shift right
00100000SSAT16
010SBFX
011!= 1111BFI
0111111BFC
100USATlogical shift left
101!= 00000USATarithmetic shift right
10100000USAT16
110UBFX
111UNALLOCATED

Advanced SIMD element or structure load/store

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
11111001op00op1
Decode fields Instruction details
op0op1
0 Advanced SIMD load/store multiple structures
1 11 Advanced SIMD load single structure to all lanes
1 != 11 Advanced SIMD load/store single structure to one lane

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

15141312111098765432101514131211109876543210
111110010DL0RnVdtypesizealignRm
Decode fields Instruction Details
Ltype
0000xVST4 (multiple 4-element structures)
00010VST1 (multiple single elements)T4
00011VST2 (multiple 2-element structures)T2
0010xVST3 (multiple 3-element structures)
00110VST1 (multiple single elements)T3
00111VST1 (multiple single elements)T1
0100xVST2 (multiple 2-element structures)T1
01010VST1 (multiple single elements)T2
1000xVLD4 (multiple 4-element structures)
10010VLD1 (multiple single elements)T4
10011VLD2 (multiple 2-element structures)T2
1010xVLD3 (multiple 3-element structures)
1011UNALLOCATED
10110VLD1 (multiple single elements)T3
10111VLD1 (multiple single elements)T1
11xxUNALLOCATED
1100xVLD2 (multiple 2-element structures)T1
11010VLD1 (multiple single elements)T2

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

15141312111098765432101514131211109876543210
111110011DL0RnVd11NsizeTaRm
Decode fields Instruction Details
LNa
0UNALLOCATED
100VLD1 (single element to all lanes)
101VLD2 (single 2-element structure to all lanes)
1100VLD3 (single 3-element structure to all lanes)
1101UNALLOCATED
111VLD4 (single 4-element structure to all lanes)

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

15141312111098765432101514131211109876543210
111110011DL0RnVd!= 11Nindex_alignRm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
LsizeN
00000VST1 (single element from one lane)T1
00001VST2 (single 2-element structure from one lane)T1
00010VST3 (single 3-element structure from one lane)T1
00011VST4 (single 4-element structure from one lane)T1
00100VST1 (single element from one lane)T2
00101VST2 (single 2-element structure from one lane)T2
00110VST3 (single 3-element structure from one lane)T2
00111VST4 (single 4-element structure from one lane)T2
01000VST1 (single element from one lane)T3
01001VST2 (single 2-element structure from one lane)T3
01010VST3 (single 3-element structure from one lane)T3
01011VST4 (single 4-element structure from one lane)T3
10000VLD1 (single element to one lane)T1
10001VLD2 (single 2-element structure to one lane)T1
10010VLD3 (single 3-element structure to one lane)T1
10011VLD4 (single 4-element structure to one lane)T1
10100VLD1 (single element to one lane)T2
10101VLD2 (single 2-element structure to one lane)T2
10110VLD3 (single 3-element structure to one lane)T2
10111VLD4 (single 4-element structure to one lane)T2
11000VLD1 (single element to one lane)T3
11001VLD2 (single 2-element structure to one lane)T3
11010VLD3 (single 3-element structure to one lane)T3
11011VLD4 (single 4-element structure to one lane)T3

Load/store single

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
1111100op0op1op2op3

The following constraints also apply to this encoding: op0<1>:op1 != 10

Decode fields Instruction details
op0op1op2op3
00 != 1111 000000 Load/store, unsigned (register offset)
00 != 1111 000001 UNALLOCATED
00 != 1111 00001x UNALLOCATED
00 != 1111 0001xx UNALLOCATED
00 != 1111 001xxx UNALLOCATED
00 != 1111 01xxxx UNALLOCATED
00 != 1111 10x0xx UNALLOCATED
00 != 1111 10x1xx Load/store, unsigned (immediate, post-indexed)
00 != 1111 1100xx Load/store, unsigned (negative immediate)
00 != 1111 1110xx Load/store, unsigned (unprivileged)
00 != 1111 11x1xx Load/store, unsigned (immediate, pre-indexed)
01 != 1111 Load/store, unsigned (positive immediate)
0x 1111 Load, unsigned (literal)
10 1 != 1111 000000 Load/store, signed (register offset)
10 1 != 1111 000001 UNALLOCATED
10 1 != 1111 00001x UNALLOCATED
10 1 != 1111 0001xx UNALLOCATED
10 1 != 1111 001xxx UNALLOCATED
10 1 != 1111 01xxxx UNALLOCATED
10 1 != 1111 10x0xx UNALLOCATED
10 1 != 1111 10x1xx Load/store, signed (immediate, post-indexed)
10 1 != 1111 1100xx Load/store, signed (negative immediate)
10 1 != 1111 1110xx Load/store, signed (unprivileged)
10 1 != 1111 11x1xx Load/store, signed (immediate, pre-indexed)
11 1 != 1111 Load/store, signed (positive immediate)
1x 1 1111 Load, signed (literal)

Load/store, unsigned (register offset)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110000sizeL!= 1111Rt000000imm2Rm
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeLRt
000STRB (register)
001!= 1111LDRB (register)
0011111PLD, PLDW (register)preload read
010STRH (register)
011!= 1111LDRH (register)
0111111PLD, PLDW (register)preload write
100STR (register)
101LDR (register)
11UNALLOCATED

Load/store, unsigned (immediate, post-indexed)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110000sizeL!= 1111Rt10U1imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeL
000STRB (immediate)
001LDRB (immediate)
010STRH (immediate)
011LDRH (immediate)
100STR (immediate)
101LDR (immediate)
11UNALLOCATED

Load/store, unsigned (negative immediate)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110000sizeL!= 1111Rt1100imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeLRt
000STRB (immediate)
001!= 1111LDRB (immediate)
0011111PLD, PLDW (immediate)preload read
010STRH (immediate)
011!= 1111LDRH (immediate)
0111111PLD, PLDW (immediate)preload write
100STR (immediate)
101LDR (immediate)
11UNALLOCATED

Load/store, unsigned (unprivileged)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110000sizeL!= 1111Rt1110imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeL
000STRBT
001LDRBT
010STRHT
011LDRHT
100STRT
101LDRT
11UNALLOCATED

Load/store, unsigned (immediate, pre-indexed)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110000sizeL!= 1111Rt11U1imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeL
000STRB (immediate)
001LDRB (immediate)
010STRH (immediate)
011LDRH (immediate)
100STR (immediate)
101LDR (immediate)
11UNALLOCATED

Load/store, unsigned (positive immediate)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110001sizeL!= 1111Rtimm12
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeLRt
000STRB (immediate)
001!= 1111LDRB (immediate)
0011111PLD, PLDW (immediate)preload read
010STRH (immediate)
011!= 1111LDRH (immediate)
0111111PLD, PLDW (immediate)preload write
100STR (immediate)
101LDR (immediate)

Load, unsigned (literal)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
11111000UsizeL1111Rtimm12
Decode fields Instruction Details
sizeLRt
0x11111PLD (literal)
001!= 1111LDRB (literal)
011!= 1111LDRH (literal)
101LDR (literal)
11UNALLOCATED

Load/store, signed (register offset)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110010size1!= 1111Rt000000imm2Rm
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeRt
00!= 1111LDRSB (register)
001111PLI (register)
01!= 1111LDRSH (register)
011111Reserved hint, behaves as NOP
1xUNALLOCATED

Load/store, signed (immediate, post-indexed)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110010size1!= 1111Rt10U1imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00LDRSB (immediate)
01LDRSH (immediate)
1xUNALLOCATED

Load/store, signed (negative immediate)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110010size1!= 1111Rt1100imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeRt
00!= 1111LDRSB (immediate)
001111PLI (immediate, literal)
01!= 1111LDRSH (immediate)
011111Reserved hint, behaves as NOP
1xUNALLOCATED

Load/store, signed (unprivileged)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110010size1!= 1111Rt1110imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00LDRSBT
01LDRSHT
1xUNALLOCATED

Load/store, signed (immediate, pre-indexed)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110010size1!= 1111Rt11U1imm8
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
size
00LDRSB (immediate)
01LDRSH (immediate)
1xUNALLOCATED

Load/store, signed (positive immediate)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
111110011size1!= 1111Rtimm12
Rn

The following constraints also apply to this encoding: Rn != 1111 && Rn != 1111

Decode fields Instruction Details
sizeRt
00!= 1111LDRSB (immediate)
001111PLI (immediate, literal)
01!= 1111LDRSH (immediate)
011111Reserved hint, behaves as NOP

Load, signed (literal)

These instructions are under Load/store single.

15141312111098765432101514131211109876543210
11111001Usize11111Rtimm12
Decode fields Instruction Details
sizeRt
00!= 1111LDRSB (literal)
001111PLI (immediate, literal)
01!= 1111LDRSH (literal)
011111Reserved hint, behaves as NOP
1xUNALLOCATED

Data-processing (register)

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
11111010op01111op1
Decode fields Instruction details
op0op1
0 0000 MOV, MOVS (register-shifted register)T2, Flag setting
0 0001 UNALLOCATED
0 001x UNALLOCATED
0 01xx UNALLOCATED
0 1xxx Register extends
1 0xxx Parallel add-subtract
1 10xx Data-processing (two source registers)
1 11xx UNALLOCATED

Register extends

These instructions are under Data-processing (register).

15141312111098765432101514131211109876543210
111110100op1URn1111Rd1(0)rotateRm
Decode fields Instruction Details
op1URn
000!= 1111SXTAH
0001111SXTH
001!= 1111UXTAH
0011111UXTH
010!= 1111SXTAB16
0101111SXTB16
011!= 1111UXTAB16
0111111UXTB16
100!= 1111SXTAB
1001111SXTB
101!= 1111UXTAB
1011111UXTB
11UNALLOCATED

Parallel add-subtract

These instructions are under Data-processing (register).

15141312111098765432101514131211109876543210
111110101op1Rn1111Rd0UHSRm
Decode fields Instruction Details
op1UHS
000000SADD8
000001QADD8
000010SHADD8
000011UNALLOCATED
000100UADD8
000101UQADD8
000110UHADD8
000111UNALLOCATED
001000SADD16
001001QADD16
001010SHADD16
001011UNALLOCATED
001100UADD16
001101UQADD16
001110UHADD16
001111UNALLOCATED
010000SASX
010001QASX
010010SHASX
010011UNALLOCATED
010100UASX
010101UQASX
010110UHASX
010111UNALLOCATED
100000SSUB8
100001QSUB8
100010SHSUB8
100011UNALLOCATED
100100USUB8
100101UQSUB8
100110UHSUB8
100111UNALLOCATED
101000SSUB16
101001QSUB16
101010SHSUB16
101011UNALLOCATED
101100USUB16
101101UQSUB16
101110UHSUB16
101111UNALLOCATED
110000SSAX
110001QSAX
110010SHSAX
110011UNALLOCATED
110100USAX
110101UQSAX
110110UHSAX
110111UNALLOCATED
111UNALLOCATED

Data-processing (two source registers)

These instructions are under Data-processing (register).

15141312111098765432101514131211109876543210
111110101op1Rn1111Rd10op2Rm
Decode fields Instruction Details
op1op2
00000QADD
00001QDADD
00010QSUB
00011QDSUB
00100REV
00101REV16
00110RBIT
00111REVSH
01000SEL
01001UNALLOCATED
0101xUNALLOCATED
01100CLZ
01101UNALLOCATED
0111xUNALLOCATED
10000CRC32CRC32B
10001CRC32CRC32H
10010CRC32CRC32W
10011CONSTRAINED UNPREDICTABLE
10100CRC32CCRC32CB
10101CRC32CCRC32CH
10110CRC32CCRC32CW
10111CONSTRAINED UNPREDICTABLE
11xUNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Multiply, multiply accumulate, and absolute difference

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
111110110op0
Decode fields Instruction details
op0
00 Multiply and absolute difference
01 UNALLOCATED
1x UNALLOCATED

Multiply and absolute difference

These instructions are under Multiply, multiply accumulate, and absolute difference.

15141312111098765432101514131211109876543210
111110110op1RnRaRd00op2Rm
Decode fields Instruction Details
op1Raop2
000!= 111100MLA, MLAS
00001MLS
0001xUNALLOCATED
000111100MUL, MULS
001!= 111100SMLABB, SMLABT, SMLATB, SMLATTSMLABB
001!= 111101SMLABB, SMLABT, SMLATB, SMLATTSMLABT
001!= 111110SMLABB, SMLABT, SMLATB, SMLATTSMLATB
001!= 111111SMLABB, SMLABT, SMLATB, SMLATTSMLATT
001111100SMULBB, SMULBT, SMULTB, SMULTTSMULBB
001111101SMULBB, SMULBT, SMULTB, SMULTTSMULBT
001111110SMULBB, SMULBT, SMULTB, SMULTTSMULTB
001111111SMULBB, SMULBT, SMULTB, SMULTTSMULTT
010!= 111100SMLAD, SMLADXSMLAD
010!= 111101SMLAD, SMLADXSMLADX
0101xUNALLOCATED
010111100SMUAD, SMUADXSMUAD
010111101SMUAD, SMUADXSMUADX
011!= 111100SMLAWB, SMLAWTSMLAWB
011!= 111101SMLAWB, SMLAWTSMLAWT
0111xUNALLOCATED
011111100SMULWB, SMULWTSMULWB
011111101SMULWB, SMULWTSMULWT
100!= 111100SMLSD, SMLSDXSMLSD
100!= 111101SMLSD, SMLSDXSMLSDX
1001xUNALLOCATED
100111100SMUSD, SMUSDXSMUSD
100111101SMUSD, SMUSDXSMUSDX
101!= 111100SMMLA, SMMLARSMMLA
101!= 111101SMMLA, SMMLARSMMLAR
1011xUNALLOCATED
101111100SMMUL, SMMULRSMMUL
101111101SMMUL, SMMULRSMMULR
11000SMMLS, SMMLSRSMMLS
11001SMMLS, SMMLSRSMMLSR
1101xUNALLOCATED
111!= 111100USADA8
11101UNALLOCATED
1111xUNALLOCATED
111111100USAD8

Long multiply and divide

These instructions are under 32-bit.

15141312111098765432101514131211109876543210
111110111op1RnRdLoRdHiop2Rm
Decode fields Instruction Details
op1op2
000!= 0000UNALLOCATED
0000000SMULL, SMULLS
001!= 1111UNALLOCATED
0011111SDIV
010!= 0000UNALLOCATED
0100000UMULL, UMULLS
011!= 1111UNALLOCATED
0111111UDIV
1000000SMLAL, SMLALS
1000001UNALLOCATED
100001xUNALLOCATED
10001xxUNALLOCATED
1001000SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALBB
1001001SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALBT
1001010SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALTB
1001011SMLALBB, SMLALBT, SMLALTB, SMLALTTSMLALTT
1001100SMLALD, SMLALDXSMLALD
1001101SMLALD, SMLALDXSMLALDX
100111xUNALLOCATED
1010xxxUNALLOCATED
10110xxUNALLOCATED
1011100SMLSLD, SMLSLDXSMLSLD
1011101SMLSLD, SMLSLDXSMLSLDX
101111xUNALLOCATED
1100000UMLAL, UMLALS
1100001UNALLOCATED
110001xUNALLOCATED
110010xUNALLOCATED
1100110UMAAL
1100111UNALLOCATED
1101xxxUNALLOCATED
111UNALLOCATED

Internal version only: isa v00_81v00_79, pseudocode v34.2.2v34.2 ; Build timestamp: 2018-03-28T202017-12-19T15:4342

Copyright © 2010-20182010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

ISA_v83A_AArch32_xml_00bet6 (old)htmldiff from-ISA_v83A_AArch32_xml_00bet6(new) ISA_v83A_AArch32_xml_00bet6.1