1. Introduction

This is the 00bet6.1 release of the AArch32 ISA XML for ARMv8.3.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

If you have comments on the content of this package, please send them by e-mail to support-aarchv8@arm.com. Give:

• The title, "AArch32 ISA XML for ARMv8.3".
• The version, "00bet6.1".
• A concise explanation of your comments.

2. Contents

3. Release Notes

Change history

The following general changes are made:

• The CSDB instruction is added. See https://developer.arm.com/support/security-update for more details.

Known issues

• The table for the "Advanced SIMD two registers and shift amount" class within the A32 and T32 encoding index page includes a column "imm3H:L" with the value "!= 0000" for all rows. This condition applies to all instructions in this table, and so is removed.
• The encoding diagram for the "Advanced SIMD and floating-point 32-bit move" class within the A32 and T32 encoding index page shows bits[3:0] as "1111". This is incorrect, as the next level of decode shows these bits as "(0)(0)(0)(0)".