BFC

Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110111110msbRdlsb0011111
cond

A1

BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>

d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(lsb); if d == 15 then UNPREDICTABLE;

T1

15141312111098765432101514131211109876543210
11110(0)11011011110imm3Rdimm2(0)msb

T1

BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>

d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(imm3:imm2); if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<lsb>

For encoding A1: is the least significant bit to be cleared, in the range 0 to 31, encoded in the "lsb" field.

For encoding T1: is the least significant bit that is to be cleared, in the range 0 to 31, encoded in the "imm3:imm2" field.

<width>

Is the number of bits to be cleared, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if msbit >= lsbit then R[d]<msbit:lsbit> = Replicate('0', msbit-lsbit+1); // Other bits of R[d] are unchanged else UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If msbit < lsbit, then one of the following behaviors must occur:


Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.