Vector Convert between floating-point and fixed-point converts each element in a vector from floating-point to fixed-point, or from fixed-point to floating-point, and places the results in a second vector.
The vector elements are the same type, and are floating-point numbers or integers. Signed and unsigned integers are distinct.
The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | U | 1 | D | imm6 | Vd | 1 | 1 | op | 0 | Q | M | 1 | Vm |
if imm6 == '000xxx' then SEE "Related encodings"; if op<1> == '0' && !HaveFP16Ext() then UNDEFINED; if op<1> == '0' && imm6 == '10xxxx' then UNDEFINED; if imm6 == '0xxxxx' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; to_fixed = (op<0> == '1'); frac_bits = 64 - UInt(imm6); unsigned = (U == '1'); case op<1> of when '0' esize = 16; elements = 4; when '1' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | U | 1 | 1 | 1 | 1 | 1 | D | imm6 | Vd | 1 | 1 | op | 0 | Q | M | 1 | Vm |
if imm6 == '000xxx' then SEE "Related encodings"; if op<1> == '0' && !HaveFP16Ext() then UNDEFINED; if op<1> == '0' && imm6 == '10xxxx' then UNDEFINED; if imm6 == '0xxxxx' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; to_fixed = (op<0> == '1'); frac_bits = 64 - UInt(imm6); unsigned = (U == '1'); case op<1> of when '0' esize = 16; elements = 4; when '1' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
<c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
<dt1> |
Is the data type for the elements of the destination vector,
encoded in
op:U:
|
<dt2> |
Is the data type for the elements of the source vector,
encoded in
op:U:
|
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qm> |
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); bits(esize) result; for r = 0 to regs-1 for e = 0 to elements-1 op1 = Elem[D[m+r],e,esize]; if to_fixed then result = FPToFixed(op1, frac_bits, unsigned, StandardFPSCRValue(), FPRounding_ZERO); else result = FixedToFP(op1, frac_bits, unsigned, StandardFPSCRValue(), FPRounding_TIEEVEN); Elem[D[d+r],e,esize] = result;
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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