Rotate Right with Extend, setting flags provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31].
If the destination register is not the PC, this instruction updates the condition flags based on the result, and bit[0] is shifted into the Carry flag.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | (0) | (0) | (0) | (0) | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Rm | |||||||||
cond | S | imm5 | type |
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, RRX
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | (0) | 0 | 0 | 0 | Rd | 0 | 0 | 1 | 1 | Rm | ||||||
S | imm3 | imm2 | type |
is equivalent to
MOVS{<c>}{<q>} <Rd>, <Rm>, RRX
and is always the preferred disassembly.
<c> |
<q> |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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