Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.
If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | S | Rn | Rd | imm12 | ||||||||||||||||||||
cond |
d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | i | 0 | 0 | 0 | 0 | 0 | S | Rn | 0 | imm3 | Rd | imm8 |
if Rd == '1111' && S == '1' then SEE "TST (immediate)"; d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C); if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
if ConditionPassed() then EncodingSpecificOperations(); result = R[n] AND imm32; if d == 15 then // Can only occur for A32 encoding if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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