Copy two general-purpose registers to or from a SIMD&FP register copies two words from two general-purpose registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword register in the Advanced SIMD and floating-point register file to two general-purpose registers.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | op | Rt2 | Rt | 1 | 0 | 1 | 1 | 0 | 0 | M | 1 | Vm | ||||||||||||
cond |
to_arm_registers = (op == '1'); t = UInt(Rt); t2 = UInt(Rt2); m = UInt(M:Vm); if t == 15 || t2 == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13 if to_arm_registers && t == t2 then UNPREDICTABLE;
If to_arm_registers && t == t2, then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | op | Rt2 | Rt | 1 | 0 | 1 | 1 | 0 | 0 | M | 1 | Vm |
to_arm_registers = (op == '1'); t = UInt(Rt); t2 = UInt(Rt2); m = UInt(M:Vm); if t == 15 || t2 == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13 if to_arm_registers && t == t2 then UNPREDICTABLE;
If to_arm_registers && t == t2, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMOV (between two general-purpose registers and a doubleword floating-point register).
<Dm> |
Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "M:Vm" field. |
<Rt2> |
Is the second general-purpose register that <Dm>[63:32] will be transferred to or from, encoded in the "Rt2" field. |
<Rt> |
Is the first general-purpose register that <Dm>[31:0] will be transferred to or from, encoded in the "Rt" field. |
<c> |
<q> |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_arm_registers then R[t] = D[m]<31:0>; R[t2] = D[m]<63:32>; else D[m]<31:0> = R[t]; D[m]<63:32> = R[t2];
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
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