ORN, ORNS (immediate)

Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result.

T1

15141312111098765432101514131211109876543210
11110i00011S!= 11110imm3Rdimm8
Rn

Flag setting (S == 1)

ORNS{<c>}{<q>} {<Rd>,} <Rn>, #<const>

Not flag setting (S == 0)

ORN{<c>}{<q>} {<Rd>,} <Rn>, #<const>

if Rn == '1111' then SEE "MVN (immediate)"; d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C); if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>.

<Rn>

Is the general-purpose source register, encoded in the "Rn" field.

<const>

An immediate value. See Modified immediate constants in T32 instructions for the range of values.

Operation

if ConditionPassed() then EncodingSpecificOperations(); result = R[n] OR NOT(imm32); R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged


Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.