Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register.
This is an alias of MOV, MOVS (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T2 and T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | (0) | (0) | (0) | (0) | Rd | imm5 | 0 | 1 | 0 | Rm | |||||||||||||
cond | S | type |
LSR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, LSR #<imm>
and is always the preferred disassembly.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 1 | imm5 | Rm | Rd | ||||||||
op |
LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> // (Inside IT block)
is equivalent to
MOV<c>{<q>} <Rd>, <Rm>, LSR #<imm>
and is the preferred disassembly when InITBlock().
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | 0 | 1 | Rm | |||||||||
S | type |
LSR<c>.W {<Rd>,} <Rm>, #<imm> // (Inside IT block, and <Rd>, <Rm>, <imm> can be represented in T2)
LSR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>
is equivalent to
MOV{<c>}{<q>} <Rd>, <Rm>, LSR #<imm>
and is always the preferred disassembly.
<c> |
<q> |
The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
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