Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the APSR.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm | |||||||||||
size |
VSELEQ.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)
VSELEQ.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELEQ.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELGE.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)
VSELGE.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELGE.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELGT.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)
VSELGT.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELGT.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELVS.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)
VSELVS.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
VSELVS.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); cond = cc:(cc<1> EOR cc<0>):'0';
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm | |||||||||||
size |
VSELEQ.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)
VSELEQ.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELEQ.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELGE.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)
VSELGE.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELGE.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELGT.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)
VSELGT.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELGT.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELVS.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)
VSELVS.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VSELVS.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); cond = cc:(cc<1> EOR cc<0>):'0';
If InITBlock(), then one of the following behaviors must occur:
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
<Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. |
EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 S[d] = Zeros(16) : (if ConditionHolds(cond) then S[n] else S[m])<15:0>; when 32 S[d] = if ConditionHolds(cond) then S[n] else S[m]; when 64 D[d] = if ConditionHolds(cond) then D[n] else D[m];
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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