Copy immediate value to a SIMD&FP register places an immediate constant into every element of the destination register.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 , A2 , A3 , A4 and A5 ) and T32 ( T1 , T2 , T3 , T4 and T5 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 0 | x | x | 0 | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | imm4H | Vd | 1 | 0 | size | (0) | 0 | (0) | 0 | imm4L | |||||||||||||
cond |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; single_register = (size != '11'); advsimd = FALSE; bits(16) imm16; bits(32) imm32; bits(64) imm64; case size of when '01' d = UInt(Vd:D); imm16 = VFPExpandImm(imm4H:imm4L); imm32 = Zeros(16) : imm16; when '10' d = UInt(Vd:D); imm32 = VFPExpandImm(imm4H:imm4L); when '11' d = UInt(D:Vd); imm64 = VFPExpandImm(imm4H:imm4L); regs = 1;
If size == '01' && cond != '1110', then one of the following behaviors must occur:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 0 | x | 0 | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | x | x | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | 1 | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 0 | x | x | 0 | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | imm4H | Vd | 1 | 0 | size | (0) | 0 | (0) | 0 | imm4L |
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; single_register = (size != '11'); advsimd = FALSE; bits(16) imm16; bits(32) imm32; bits(64) imm64; case size of when '01' d = UInt(Vd:D); imm16 = VFPExpandImm(imm4H:imm4L); imm32 = Zeros(16) : imm16; when '10' d = UInt(Vd:D); imm32 = VFPExpandImm(imm4H:imm4L); when '11' d = UInt(D:Vd); imm64 = VFPExpandImm(imm4H:imm4L); regs = 1;
If size == '01' && InITBlock(), then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 0 | x | 0 | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | x | x | 0 | Q | 0 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | 1 | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
cmode | op |
if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; single_register = FALSE; advsimd = TRUE; imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
<c> |
For encoding A1, A3, A4 and A5: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding A2, T1, T2, T3, T4 and T5: see Standard assembler syntax fields. |
<q> |
<dt> |
The data type,
encoded in
cmode:
|
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if single_register then S[d] = imm32; else for r = 0 to regs-1 D[d+r] = imm64;
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.