Move (register) copies a value from a register to the destination register.
If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:
This instruction is used by the aliases ASRS (immediate), ASR (immediate), LSLS (immediate), LSL (immediate), LSRS (immediate), LSR (immediate), RORS (immediate), ROR (immediate), RRXS, and RRX.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | S | (0) | (0) | (0) | (0) | Rd | imm5 | type | 0 | Rm | ||||||||||||||
cond |
d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(type, imm5);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | D | Rm | Rd |
d = UInt(D:Rd); m = UInt(Rm); setflags = FALSE; (shift_t, shift_n) = (SRType_LSL, 0); if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | != 11 | imm5 | Rm | Rd | |||||||||
op |
MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} // (Inside IT block)
MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount>} // (Outside IT block)
d = UInt(Rd); m = UInt(Rm); setflags = !InITBlock(); (shift_t, shift_n) = DecodeImmShift(op, imm5); if op == '00' && imm5 == '00000' && InITBlock() then UNPREDICTABLE;
If op == '00' && imm5 == '00000' && InITBlock(), then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | S | 1 | 1 | 1 | 1 | (0) | imm3 | Rd | imm2 | type | Rm |
MOV{<c>}.W <Rd>, <Rm> {, LSL #0} // (<Rd>, <Rm> can be represented in T1)
MOV<c>.W <Rd>, <Rm> {, <shift> #<amount>} // (Inside IT block, and <Rd>, <Rm>, <shift>, <amount> can be represented in T2)
MOVS.W <Rd>, <Rm> {, <shift> #<amount>} // (Outside IT block, and <Rd>, <Rm>, <shift>, <amount> can be represented in T1 or T2)
d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<shift> |
For encoding A1 and T3: is the type of shift to be applied to the source register,
encoded in
type:
| ||||||||||
For encoding T2: is the type of shift to be applied to the source register,
encoded in
op:
|
Alias | Of variant | Is preferred when |
---|---|---|
ASRS (immediate) | T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value) | S == '1' && type == '10' |
ASRS (immediate) | T2 | op == '10' && !InITBlock() |
ASR (immediate) | T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value) | S == '0' && type == '10' |
ASR (immediate) | T2 | op == '10' && InITBlock() |
LSLS (immediate) | T3 (MOVS, shift or rotate by value) | S == '1' && imm3:Rd:imm2 != '000xxxx00' && type == '00' |
LSLS (immediate) | A1 (MOVS, shift or rotate by value) | S == '1' && imm5 != '00000' && type == '00' |
LSLS (immediate) | T2 | op == '00' && imm5 != '00000' && !InITBlock() |
LSL (immediate) | T3 (MOV, shift or rotate by value) | S == '0' && imm3:Rd:imm2 != '000xxxx00' && type == '00' |
LSL (immediate) | A1 (MOV, shift or rotate by value) | S == '0' && imm5 != '00000' && type == '00' |
LSL (immediate) | T2 | op == '00' && imm5 != '00000' && InITBlock() |
LSRS (immediate) | T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value) | S == '1' && type == '01' |
LSRS (immediate) | T2 | op == '01' && !InITBlock() |
LSR (immediate) | T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value) | S == '0' && type == '01' |
LSR (immediate) | T2 | op == '01' && InITBlock() |
RORS (immediate) | T3 (MOVS, shift or rotate by value) | S == '1' && imm3:Rd:imm2 != '000xxxx00' && type == '11' |
RORS (immediate) | A1 (MOVS, shift or rotate by value) | S == '1' && imm5 != '00000' && type == '11' |
ROR (immediate) | T3 (MOV, shift or rotate by value) | S == '0' && imm3:Rd:imm2 != '000xxxx00' && type == '11' |
ROR (immediate) | A1 (MOV, shift or rotate by value) | S == '0' && imm5 != '00000' && type == '11' |
RRXS | T3 (MOVS, rotate right with extend) | S == '1' && imm3 == '000' && imm2 == '00' && type == '11' |
RRXS | A1 (MOVS, rotate right with extend) | S == '1' && imm5 == '00000' && type == '11' |
RRX | T3 (MOV, rotate right with extend) | S == '0' && imm3 == '000' && imm2 == '00' && type == '11' |
RRX | A1 (MOV, rotate right with extend) | S == '0' && imm5 == '00000' && type == '11' |
if ConditionPassed() then EncodingSpecificOperations(); (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); result = shifted; if d == 15 then if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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