Subtract from SP (immediate) subtracts an immediate value from the SP value, and writes the result to the destination register.
If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | S | 1 | 1 | 0 | 1 | Rd | imm12 | |||||||||||||||||
cond |
d = UInt(Rd); setflags = (S == '1'); imm32 = A32ExpandImm(imm12);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | imm7 |
d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | i | 0 | 1 | 1 | 0 | 1 | S | 1 | 1 | 0 | 1 | 0 | imm3 | Rd | imm8 |
if Rd == '1111' && S == '1' then SEE "CMP (immediate)"; d = UInt(Rd); setflags = (S == '1'); imm32 = T32ExpandImm(i:imm3:imm8); if d == 15 && !setflags then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | i | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | imm3 | Rd | imm8 |
SUB{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> cannot be represented in T1, T2, or T3)
SUBW{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> can be represented in T1, T2, or T3)
d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32); if d == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<imm7> |
Is the unsigned immediate, a multiple of 4, in the range 0 to 508, encoded in the "imm7" field as <imm7>/4. |
<imm12> |
Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field. |
if ConditionPassed() then EncodingSpecificOperations(); (result, nzcv) = AddWithCarry(SP, NOT(imm32), '1'); if d == 15 then // Can only occur for A32 encoding if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;
Internal version only: isa v00_79, pseudocode v34.2 ; Build timestamp: 2017-12-19T15:42
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