Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | msb | Rd | lsb | 0 | 0 | 1 | 1 | 1 | 1 | 1 | ||||||||||||||
cond |
d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(lsb); if d == 15 then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | (0) | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | imm3 | Rd | imm2 | (0) | msb |
d = UInt(Rd); msbit = UInt(msb); lsbit = UInt(imm3:imm2); if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
<width> |
Is the number of bits to be cleared, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1. |
if ConditionPassed() then EncodingSpecificOperations(); if msbit >= lsbit then R[d]<msbit:lsbit> = Replicate('0', msbit-lsbit+1); // Other bits of R[d] are unchanged else UNPREDICTABLE;
If msbit < lsbit, then one of the following behaviors must occur:
Internal version only: isa v00_81, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T20:43
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