Signed integer convert to floating-point (predicated).
Convert to floating-point from the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.
If the source and destination types have a different size the smaller data type is held unpacked in the least significant bits of elements of the larger size. When the source is the smaller type the unused upper bits of the source element are ignored. When the destination is the smaller type the unused upper bits of the destination element are set to zero.
It has encodings from 7 classes: 16-bit to half-precision , 32-bit to half-precision , 32-bit to single-precision , 32-bit to double-precision , 64-bit to half-precision , 64-bit to single-precision and 64-bit to double-precision
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 16; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 16; integer d_esize = 16; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 32; integer d_esize = 16; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 32; integer d_esize = 32; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 32; integer d_esize = 64; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 16; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 32; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
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0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 64; boolean unsigned = FALSE; FPRounding rounding = FPRoundingMode(FPCR);
<Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(VL) dest = Z[d]; bits(VL) result; for e = 0 to elements-1 bits(esize) element = Elem[operand, e, esize]; if ElemP[mask, e, esize] == '1' then bits(d_esize) fpval = FixedToFP(element<s_esize-1:0>, 0, unsigned, FPCR, rounding); Elem[result, e, esize] = ZeroExtend(fpval); else Elem[result, e, esize] = Elem[dest, e, esize]; Z[d] = result;
Release: 00rel4.1-manual
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