The ESR_EL1 characteristics are:
Holds syndrome information for an exception taken to EL1.
This register is part of the Exception and fault handling registers functional group.
AArch64 System register ESR_EL1 is architecturally mapped to AArch32 System register DFSR.
RW fields in this register reset to architecturally UNKNOWN values.
ESR_EL1 is a 32-bit register.
See ESR_ELx.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ESR_EL1 | 11 | 000 | 0101 | 0010 | 000 |
ESR_EL12 | 11 | 101 | 0101 | 0010 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
ESR_EL1 | x | x | 0 | - | RW | n/a | RW |
ESR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
ESR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
ESR_EL1 | 1 | 0 | 1 | - | RW | ESR_EL2 | RW |
ESR_EL1 | 1 | 1 | 1 | - | n/a | ESR_EL2 | RW |
ESR_EL12 | x | x | 0 | - | - | n/a | - |
ESR_EL12 | 0 | 0 | 1 | - | - | - | - |
ESR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
ESR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
ESR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ESR_EL1 or ESR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 using accessor ESR_EL12 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
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