FCVT

Floating-point convert precision (predicated).

Convert the size and precision of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Since the source and destination types have a different size the smaller data type is held unpacked in the least significant bits of elements of the larger size. When the source is the smaller type the unused upper bits of the source element are ignored. When the destination is the smaller type the unused upper bits of the destination element are set to zero.

It has encodings from 6 classes: Half-precision to single-precision , Half-precision to double-precision , Single-precision to half-precision , Single-precision to double-precision , Double-precision to half-precision and Double-precision to single-precision

Half-precision to single-precision

313029282726252423222120191817161514131211109876543210
0110010110001001101PgZnZd

Half-precision to single-precision

FCVT <Zd>.S, <Pg>/M, <Zn>.H

integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 16; integer d_esize = 32;

Half-precision to double-precision

313029282726252423222120191817161514131211109876543210
0110010111001001101PgZnZd

Half-precision to double-precision

FCVT <Zd>.D, <Pg>/M, <Zn>.H

integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 16; integer d_esize = 64;

Single-precision to half-precision

313029282726252423222120191817161514131211109876543210
0110010110001000101PgZnZd

Single-precision to half-precision

FCVT <Zd>.H, <Pg>/M, <Zn>.S

integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 32; integer d_esize = 16;

Single-precision to double-precision

313029282726252423222120191817161514131211109876543210
0110010111001011101PgZnZd

Single-precision to double-precision

FCVT <Zd>.D, <Pg>/M, <Zn>.S

integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 32; integer d_esize = 64;

Double-precision to half-precision

313029282726252423222120191817161514131211109876543210
0110010111001000101PgZnZd

Double-precision to half-precision

FCVT <Zd>.H, <Pg>/M, <Zn>.D

integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 16;

Double-precision to single-precision

313029282726252423222120191817161514131211109876543210
0110010111001010101PgZnZd

Double-precision to single-precision

FCVT <Zd>.S, <Pg>/M, <Zn>.D

integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 32;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(VL) dest = Z[d]; bits(VL) result; for e = 0 to elements-1 bits(esize) element = Elem[operand, e, esize]; if ElemP[mask, e, esize] == '1' then bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR); if esize > d_esize then Elem[result, e, esize] = ZeroExtend(res); else Elem[result, e, esize] = res<esize-1:0>; else Elem[result, e, esize] = Elem[dest, e, esize]; Z[d] = result;


Release: 00rel4.1-manual

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