The ZCR_EL2 characteristics are:
The SVE Control Register for EL2 is used to control aspects of SVE visible at exception levels EL2 and Non-secure EL1 and EL0.
This register is part of the Other system control registers functional group.
If SVE is not implemented, this register is UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
ZCR_EL2 is a 64-bit register.
The ZCR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LEN | |||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RAZ/WI.
Constrains the scalable vector register length for EL2 and Non-secure EL1 and Non-secure EL0 to (LEN+1)x128 bits. For all purposes other than returning the result of a direct read of ZCR_EL2 then this field behaves as if it is set to the minimum of the stored value and the constrained length inherited from more privileged Exception levels in the current Security state, rounded down to the nearest implemented vector length.
An indirect read of ZCR_EL2.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ZCR_EL2 | 11 | 100 | 0001 | 0010 | 000 |
ZCR_EL1 | 11 | 000 | 0001 | 0010 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
ZCR_EL2 | x | x | 0 | - | - | n/a | RW |
ZCR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
ZCR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
ZCR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
ZCR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
ZCR_EL1 | x | x | 0 | - | ZCR_EL1 | n/a | ZCR_EL1 |
ZCR_EL1 | 0 | 0 | 1 | - | ZCR_EL1 | ZCR_EL1 | ZCR_EL1 |
ZCR_EL1 | 0 | 1 | 1 | - | n/a | ZCR_EL1 | ZCR_EL1 |
ZCR_EL1 | 1 | 0 | 1 | - | ZCR_EL1 | RW | ZCR_EL1 |
ZCR_EL1 | 1 | 1 | 1 | - | n/a | RW | ZCR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ZCR_EL2 or ZCR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TZ==1, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.ZEN==00, Non-secure accesses to this register from EL2 are trapped to EL2.
If CPTR_EL2.ZEN==10, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CPTR_EL2.ZEN==00, Non-secure accesses to this register from EL2 are trapped to EL2.
If CPTR_EL2.ZEN==10, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.EZ==0, accesses to this register from EL2 and EL3 are trapped to EL3.
14/12/2017 16:25
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