(old) htmldiff from-(new)

Advanced SIMD load single structure to all lanes<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1x32

Advanced SIMD load single structure to all lanes<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
11RESERVED

Advanced SIMD load/store multiple structures<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
11RESERVED

Advanced SIMD load/store multiple structures<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
1164

Advanced SIMD load/store single structure to one lane<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032

System register Load/Store+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

System register 32-bit move<coproc>

Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.

Where:

<coproc> Is the System register encoding space, encoded in coproc<0>:
coproc<0><coproc>
0p14
1p15

System register 64-bit move<coproc>

Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.

Where:

<coproc> Is the System register encoding space, encoded in coproc<0>:
coproc<0><coproc>
0p14
1p15

Change Process State<endian_specifier>

Original text: Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE

Where:

<endian_specifier> Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in E:
E<endian_specifier>
0LE
1BE

Change Processor State<endian_specifier>

Original text: Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE

Where:

<endian_specifier> Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in E:
E<endian_specifier>
0LE
1BE

Data-processing (shifted register)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Data-processing (shifted register)<shift>

Original text: Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Extend and Add<amount>

Original text: Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24

Where:

<amount> Is the rotate amount, encoded in rotate:
rotate<amount>
00(omitted)
018
1016
1124

Register extends<amount>

Original text: Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24

Where:

<amount> Is the rotate amount, encoded in rotate:
rotate<amount>
00(omitted)
018
1016
1124

Floating-point data-processing (two registers)<dt>

Original text: Is the data type for the operand, encoded in "op", where 0->U32, 1->S32

Where:

<dt> Is the data type for the operand, encoded in op:
op<dt>
0U32
1S32

Floating-point data-processing (two registers)<dt>

Original text: Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32

Where:

<dt> Is the data type for the fixed-point number, encoded in U:sx:
Usx<dt>
00S16
01S32
10U16
11U32

Floating-point move special register<spec_reg>

Original text: Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE

Where:

<spec_reg> Is the destination Advanced SIMD and floating-point System register, encoded in reg:
reg<spec_reg>
0000FPSID
0001FPSCR
001xUNPREDICTABLE
01xxUNPREDICTABLE
1000FPEXC
1001UNPREDICTABLE
101xUNPREDICTABLE
11xxUNPREDICTABLE

Floating-point move special register<spec_reg>

Original text: Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE

Where:

<spec_reg> Is the source Advanced SIMD and floating-point System register, encoded in reg:
reg<spec_reg>
0000FPSID
0001FPSCR
001xUNPREDICTABLE
0100UNPREDICTABLE
0101MVFR2
0110MVFR1
0111MVFR0
1000FPEXC
1001UNPREDICTABLE
101xUNPREDICTABLE
11xxUNPREDICTABLE

Floating-point directed convert to integer<dt>

Original text: Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:
op<dt>
0U32
1S32

Floating-point directed convert to integer<dt>

Original text: Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:
op<dt>
0U32
1S32

Floating-point data-processing (two registers)<dt>

Original text: Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32

Where:

<dt> Is the data type for the fixed-point number, encoded in U:sx:
Usx<dt>
00S16
01S32
10U16
11U32

Floating-point data-processing (two registers)<dt>

Original text: Is the data type for the operand, encoded in "op", where 0->U32, 1->S32

Where:

<dt> Is the data type for the operand, encoded in op:
op<dt>
0U32
1S32

Integer Test and Compare (two register, immediate shift)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Integer Test and Compare (two register, register shift)<type>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<type> Is the type of shift to be applied to the second source register, encoded in stype:
stype<type>
00LSL
01LSR
10ASR
11ROR

Integer Data Processing (three register, immediate shift)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Integer Data Processing (three register, register shift)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Load dual (literal)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load, signed (literal)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load, unsigned (literal)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store, signed (immediate, post-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store, signed (immediate, pre-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store, unsigned (immediate, post-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store, unsigned (immediate, pre-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

System register load/store+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store dual (immediate)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store dual (immediate, post-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/store dual (immediate, pre-indexed)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/Store Word, Unsigned Byte (immediate, literal)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/Store Word, Unsigned Byte (register)+/-

Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Advanced SIMD and floating-point load/store+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Advanced SIMD load/store multiple structures<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
1164

Advanced SIMD load/store multiple structures<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
11RESERVED

Advanced SIMD load/store single structure to one lane<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032

Load/Store Dual, Half, Signed Byte (immediate, literal)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Load/Store Dual, Half, Signed Byte (register)+/-

Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Advanced SIMD load single structure to all lanes<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1x32

Advanced SIMD load single structure to all lanes<size>

Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.

Where:

<size> Is the data size, encoded in size:
size<size>
008
0116
1032
11RESERVED

Logical Arithmetic (three register, immediate shift)<shift>

Original text: Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Logical Arithmetic (three register, immediate shift)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Logical Arithmetic (three register, register shift)<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

System register 32-bit move<coproc>

Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.

Where:

<coproc> Is the System register encoding space, encoded in coproc<0>:
coproc<0><coproc>
0p14
1p15

System register 64-bit move<coproc>

Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.

Where:

<coproc> Is the System register encoding space, encoded in coproc<0>:
coproc<0><coproc>
0p14
1p15

Floating-point move special register<spec_reg>

Original text: Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE

Where:

<spec_reg> Is the destination Advanced SIMD and floating-point System register, encoded in reg:
reg<spec_reg>
0000FPSID
0001FPSCR
001xUNPREDICTABLE
01xxUNPREDICTABLE
1000FPEXC
1001UNPREDICTABLE
101xUNPREDICTABLE
11xxUNPREDICTABLE

Floating-point move special register<spec_reg>

Original text: Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE

Where:

<spec_reg> Is the source Advanced SIMD and floating-point System register, encoded in reg:
reg<spec_reg>
0000FPSID
0001FPSCR
001xUNPREDICTABLE
0100UNPREDICTABLE
0101MVFR2
0110MVFR1
0111MVFR0
1000FPEXC
1001UNPREDICTABLE
101xUNPREDICTABLE
11xxUNPREDICTABLE

Move special register (register)<spec_reg>

Original text: Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.

Where:

<spec_reg> Is the special register to be accessed, encoded in R:
R<spec_reg>
0CPSR|APSR
1SPSR

Move special register (register)<banked_reg>

Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE

Where:

<banked_reg> Is the name of the banked register to be transferred to or from, encoded in R:M:M1:
RMM1<banked_reg>
000000R8_usr
000001R9_usr
000010R10_usr
000011R11_usr
000100R12_usr
000101SP_usr
000110LR_usr
000111UNPREDICTABLE
001000R8_fiq
001001R9_fiq
001010R10_fiq
001011R11_fiq
001100R12_fiq
001101SP_fiq
001110LR_fiq
001111UNPREDICTABLE
010000LR_irq
010001SP_irq
010010LR_svc
010011SP_svc
010100LR_abt
010101SP_abt
010110LR_und
010111SP_und
0110xxUNPREDICTABLE
011100LR_mon
011101SP_mon
011110ELR_hyp
011111SP_hyp
100xxxUNPREDICTABLE
1010xxUNPREDICTABLE
10110xUNPREDICTABLE
101110SPSR_fiq
101111UNPREDICTABLE
110000SPSR_irq
110001UNPREDICTABLE
110010SPSR_svc
110011UNPREDICTABLE
110100SPSR_abt
110101UNPREDICTABLE
110110SPSR_und
110111UNPREDICTABLE
1110xxUNPREDICTABLE
111100SPSR_mon
111101UNPREDICTABLE
111110SPSR_hyp
111111UNPREDICTABLE

MRS (banked)<banked_reg>

Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE

Where:

<banked_reg> Is the name of the banked register to be transferred to or from, encoded in R:M:M1:
RMM1<banked_reg>
000000R8_usr
000001R9_usr
000010R10_usr
000011R11_usr
000100R12_usr
000101SP_usr
000110LR_usr
000111UNPREDICTABLE
001000R8_fiq
001001R9_fiq
001010R10_fiq
001011R11_fiq
001100R12_fiq
001101SP_fiq
001110LR_fiq
001111UNPREDICTABLE
010000LR_irq
010001SP_irq
010010LR_svc
010011SP_svc
010100LR_abt
010101SP_abt
010110LR_und
010111SP_und
0110xxUNPREDICTABLE
011100LR_mon
011101SP_mon
011110ELR_hyp
011111SP_hyp
100xxxUNPREDICTABLE
1010xxUNPREDICTABLE
10110xUNPREDICTABLE
101110SPSR_fiq
101111UNPREDICTABLE
110000SPSR_irq
110001UNPREDICTABLE
110010SPSR_svc
110011UNPREDICTABLE
110100SPSR_abt
110101UNPREDICTABLE
110110SPSR_und
110111UNPREDICTABLE
1110xxUNPREDICTABLE
111100SPSR_mon
111101UNPREDICTABLE
111110SPSR_hyp
111111UNPREDICTABLE

MRS (special)<spec_reg>

Original text: Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.

Where:

<spec_reg> Is the special register to be accessed, encoded in R:
R<spec_reg>
0CPSR|APSR
1SPSR

MSR (banked)<banked_reg>

Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE

Where:

<banked_reg> Is the name of the banked register to be transferred to or from, encoded in R:M:M1:
RMM1<banked_reg>
000000R8_usr
000001R9_usr
000010R10_usr
000011R11_usr
000100R12_usr
000101SP_usr
000110LR_usr
000111UNPREDICTABLE
001000R8_fiq
001001R9_fiq
001010R10_fiq
001011R11_fiq
001100R12_fiq
001101SP_fiq
001110LR_fiq
001111UNPREDICTABLE
010000LR_irq
010001SP_irq
010010LR_svc
010011SP_svc
010100LR_abt
010101SP_abt
010110LR_und
010111SP_und
0110xxUNPREDICTABLE
011100LR_mon
011101SP_mon
011110ELR_hyp
011111SP_hyp
100xxxUNPREDICTABLE
1010xxUNPREDICTABLE
10110xUNPREDICTABLE
101110SPSR_fiq
101111UNPREDICTABLE
110000SPSR_irq
110001UNPREDICTABLE
110010SPSR_svc
110011UNPREDICTABLE
110100SPSR_abt
110101UNPREDICTABLE
110110SPSR_und
110111UNPREDICTABLE
1110xxUNPREDICTABLE
111100SPSR_mon
111101UNPREDICTABLE
111110SPSR_hyp
111111UNPREDICTABLE

Preload (immediate)+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Preload (register)<shift>

Original text: Is the type of shift to be applied to the index register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the index register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Preload (register)+/-

Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Shift (immediate)<shift>

Original text: Is the type of shift to be applied to the source register, encoded in "op", where 00->LSL, 01->LSR, 10->ASR.

Where:

<shift> Is the type of shift to be applied to the source register, encoded in op:
op<shift>
00LSL
01LSR
10ASR

Register shifts<shift>

Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.

Where:

<shift> Is the type of shift to be applied to the second source register, encoded in stype:
stype<shift>
00LSL
01LSR
10ASR
11ROR

Advanced SIMD one register and modified immediate<dt>

Original text: The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.

Where:

<dt> The data type, encoded in cmode:
cmode<dt>
110xI32
1110I8
1111F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00I8
01I16
10I32
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.

Where:

<dt> Is the data type for the elements of the operand, encoded in op<0>:size:
op<0>size<dt>
000S16
001S32
010S64
011RESERVED
100U16
101U32
110U64
111RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the vectors, encoded in F:size:
Fsize<dt>
010U32
101F16
110F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the operands, encoded in F:size:
Fsize<dt>
000I8
001I16
010I32
101F16
110F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
00I16
01I32
10I64
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
00S16
01S32
10S64
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.

Where:

<dt> Is the data type for the elements of the vectors, encoded in F:size:
Fsize<dt>
000S8
001S16
010S32
101F16
110F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
008
0116
1032
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00S8
01S16
10S32
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
008
0116
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
01F16
10F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
0116
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.

Where:

<dt> Is the data type, encoded in size:
size<dt>
008
01RESERVED
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:size:
opsize<dt>
001S16
010S32
101U16
110U32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
0116
1032
11RESERVED

Advanced SIMD two registers misc<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in size:
size<dt2>
01F16
10F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the operands, encoded in F:size:
Fsize<dt>
000S8
001S16
010S32
101F16
110F32

Advanced SIMD two registers misc<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in size:op:
sizeop<dt2>
0100S16
0101U16
011xF16
1000S32
1001U32
101xF32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
01RESERVED
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the destination, encoded in "op", where 0->S32, 1->U32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:
op<dt>
0S32
1U32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in op:size:
opsize<dt>
000S8
001S16
010S32
011RESERVED
100U8
101U16
110U32
111RESERVED

Advanced SIMD two registers misc<dt1>

Original text: Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32

Where:

<dt1> Is the data type for the elements of the destination vector, encoded in size:op:
sizeop<dt1>
010xF16
0110S16
0111U16
100xF32
1010S32
1011U32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00S8
01S16
10S32
11RESERVED

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32

Where:

<dt> Is the data type for the scalar and the elements of the operand vector, encoded in U:size:
Usize<dt>
001S16
010S32
101U16
110U32

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32

Where:

<dt> Is the data type for the scalar and the elements of the operand vector, encoded in F:size:
Fsize<dt>
001I16
010I32
101F16
110F32

Advanced SIMD two registers and a scalar extension<bt>

Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.

Where:

<bt> Is the bottom or top element specifier, encoded in T:
T<bt>
0B
1T

Advanced SIMD two registers and a scalar extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
000
0190
10180
11270

Advanced SIMD two registers and shift amount<type>

Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.

Where:

<type> Is the data type for the elements of the vectors, encoded in U:
U<type>
1S

Advanced SIMD two registers and shift amount<size>

Original text: Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.

Where:

<size> Is the data size for the elements of the vectors, encoded in imm6<5:3>:
imm6<5:3><size>
00116
01x32
1xx64

Advanced SIMD two registers and shift amount<dt1>

Original text: Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32

Where:

<dt1> Is the data type for the elements of the destination vector, encoded in op:U:
opU<dt1>
00xF16
010S16
011U16
10xF32
110S32
111U32

Advanced SIMD two registers and shift amount<size>

Original text: Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.

Where:

<size> Is the data size for the elements of the vectors, encoded in L:imm6<5:3>:
Limm6<5:3><size>
00018
001x16
01xx32
1xxx64

Advanced SIMD two registers and shift amount<type>

Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.

Where:

<type> Is the data type for the elements of the vectors, encoded in U:
U<type>
0S
1U

Advanced SIMD two registers and shift amount<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in op:U:
opU<dt2>
000S16
001U16
01xF16
100S32
101U32
11xF32

Advanced SIMD two registers and shift amount<dt>

Original text: Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32

Where:

<dt> Is the data type for the elements of the operand, encoded in U:imm3H:
Uimm3H<dt>
0001S8
0010S16
0100S32
1001U8
1010U16
1100U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the operands, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the second operand vector, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00I16
01I32
10I64

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.

Where:

<dt> Is the data type for the elements of the second operand vector, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64

Where:

<dt> Is the data type for the elements of the operands, encoded in op:U:size:
opUsize<dt>
0000S8
0001S16
0010S32
0100U8
0101U16
0110U32
1000P8
1010P64

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00I8
01I16
10I32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the operands, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.

Where:

<dt> Is the data type for the elements of the vectors, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
011S64
100U8
101U16
110U32
111U64

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00I8
01I16
10I32
11I64

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
008
0116
1032

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8

Where:

<dt> Is the data type for the elements of the operands, encoded in op:size:
opsize<dt>
000I8
001I16
010I32
100P8

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.

Where:

<dt> Is the data type for the elements of the vectors, encoded in sz:
sz<dt>
0F32
1F16

Advanced SIMD three registers of the same length extension<bt>

Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.

Where:

<bt> Is the bottom or top element specifier, encoded in T:
T<bt>
0B
1T

Advanced SIMD three registers of the same length extension<dt>

Original text: Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.

Where:

<dt> Is the data type for the elements of the vectors, encoded in S:
S<dt>
0F16
1F32

Advanced SIMD three registers of the same length extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
000
0190
10180
11270

Advanced SIMD three registers of the same length extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
090
1270

Advanced SIMD one register and modified immediate<dt>

Original text: The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.

Where:

<dt> The data type, encoded in cmode:
cmode<dt>
110xI32
1110I8
1111F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00I8
01I16
10I32
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the destination, encoded in "op", where 0->S32, 1->U32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:
op<dt>
0S32
1U32

Advanced SIMD two registers misc<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in size:op:
sizeop<dt2>
0100S16
0101U16
011xF16
1000S32
1001U32
101xF32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the destination, encoded in op:size:
opsize<dt>
001S16
010S32
101U16
110U32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
008
0116
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
0116
1032
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the operands, encoded in F:size:
Fsize<dt>
000S8
001S16
010S32
101F16
110F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00S8
01S16
10S32
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
00S16
01S32
10S64
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
01F16
10F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the operands, encoded in F:size:
Fsize<dt>
000I8
001I16
010I32
101F16
110F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.

Where:

<dt> Is the data type, encoded in size:
size<dt>
008
01RESERVED
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.

Where:

<dt> Is the data type for the elements of the operand, encoded in op<0>:size:
op<0>size<dt>
000S16
001S32
010S64
011RESERVED
100U16
101U32
110U64
111RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
008
0116
1032
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
0116
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the vectors, encoded in op:size:
opsize<dt>
000S8
001S16
010S32
011RESERVED
100U8
101U16
110U32
111RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32

Where:

<dt> Is the data type for the elements of the vectors, encoded in F:size:
Fsize<dt>
010U32
101F16
110F32

Advanced SIMD two registers misc<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in size:
size<dt2>
01F16
10F32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
008
01RESERVED
1xRESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00S8
01S16
10S32
11RESERVED

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.

Where:

<dt> Is the data type for the elements of the vectors, encoded in F:size:
Fsize<dt>
000S8
001S16
010S32
101F16
110F32

Advanced SIMD two registers misc<dt1>

Original text: Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32

Where:

<dt1> Is the data type for the elements of the destination vector, encoded in size:op:
sizeop<dt1>
010xF16
0110S16
0111U16
100xF32
1010S32
1011U32

Advanced SIMD two registers misc<dt>

Original text: Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED

Where:

<dt> Is the data type for the elements of the operand, encoded in size:
size<dt>
00I16
01I32
10I64
11RESERVED

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32

Where:

<dt> Is the data type for the scalar and the elements of the operand vector, encoded in F:size:
Fsize<dt>
001I16
010I32
101F16
110F32

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD two registers and a scalar<dt>

Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32

Where:

<dt> Is the data type for the scalar and the elements of the operand vector, encoded in U:size:
Usize<dt>
001S16
010S32
101U16
110U32

Advanced SIMD two registers and a scalar extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
000
0190
10180
11270

Advanced SIMD two registers and a scalar extension<bt>

Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.

Where:

<bt> Is the bottom or top element specifier, encoded in T:
T<bt>
0B
1T

Advanced SIMD two registers and shift amount<dt2>

Original text: Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32

Where:

<dt2> Is the data type for the elements of the source vector, encoded in op:U:
opU<dt2>
000S16
001U16
01xF16
100S32
101U32
11xF32

Advanced SIMD two registers and shift amount<dt>

Original text: Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32

Where:

<dt> Is the data type for the elements of the operand, encoded in U:imm3H:
Uimm3H<dt>
0001S8
0010S16
0100S32
1001U8
1010U16
1100U32

Advanced SIMD two registers and shift amount<size>

Original text: Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.

Where:

<size> Is the data size for the elements of the vectors, encoded in L:imm6<5:3>:
Limm6<5:3><size>
00018
001x16
01xx32
1xxx64

Advanced SIMD two registers and shift amount<type>

Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.

Where:

<type> Is the data type for the elements of the vectors, encoded in U:
U<type>
0S
1U

Advanced SIMD two registers and shift amount<type>

Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.

Where:

<type> Is the data type for the elements of the vectors, encoded in U:
U<type>
1S

Advanced SIMD two registers and shift amount<size>

Original text: Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.

Where:

<size> Is the data size for the elements of the vectors, encoded in imm6<5:3>:
imm6<5:3><size>
00116
01x32
1xx64

Advanced SIMD two registers and shift amount<dt1>

Original text: Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32

Where:

<dt1> Is the data type for the elements of the destination vector, encoded in op:U:
opU<dt1>
00xF16
010S16
011U16
10xF32
110S32
111U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the second operand vector, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the operands, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
00I16
01I32
10I64

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.

Where:

<dt> Is the data type for the elements of the second operand vector, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of different lengths<dt>

Original text: Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64

Where:

<dt> Is the data type for the elements of the operands, encoded in op:U:size:
opUsize<dt>
0000S8
0001S16
0010S32
0100U8
0101U16
0110U32
1000P8
1010P64

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.

Where:

<dt> Is the data type for the elements of the vectors, encoded in sz:
sz<dt>
0F32
1F16

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8

Where:

<dt> Is the data type for the elements of the operands, encoded in op:size:
opsize<dt>
000I8
001I16
010I32
100P8

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
008
0116
1032

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32

Where:

<dt> Is the data type for the elements of the operands, encoded in size:
size<dt>
01S16
10S32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.

Where:

<dt> Is the data type for the elements of the vectors, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
011S64
100U8
101U16
110U32
111U64

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32

Where:

<dt> Is the data type for the elements of the operands, encoded in U:size:
Usize<dt>
000S8
001S16
010S32
100U8
101U16
110U32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00I8
01I16
10I32

Advanced SIMD three registers of the same length<dt>

Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.

Where:

<dt> Is the data type for the elements of the vectors, encoded in size:
size<dt>
00I8
01I16
10I32
11I64

Advanced SIMD three registers of the same length extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
000
0190
10180
11270

Advanced SIMD three registers of the same length extension<dt>

Original text: Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.

Where:

<dt> Is the data type for the elements of the vectors, encoded in S:
S<dt>
0F16
1F32

Advanced SIMD three registers of the same length extension<bt>

Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.

Where:

<bt> Is the bottom or top element specifier, encoded in T:
T<bt>
0B
1T

Advanced SIMD three registers of the same length extension<rotate>

Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.

Where:

<rotate> Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:
rot<rotate>
090
1270

Advanced SIMD and floating-point load/store+/-

Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.

Where:

+/- Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:
U+/-
0-
1+

Internal version only: isa v01_06v01_03, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-12T172019-09-30T07:3440

Copyright © 2010-2015 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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