(old) htmldiff from-(new)

VCVTA (Advanced SIMD)

Vector Convert floating-point to integer with Round to Nearest with Ties to Away converts each element in a vector from floating-point to integer using the Round to Nearest with Ties to Away rounding mode, and places the results in a second vector.

The operand vector elements are floating-point numbers.

The result vector elements are integers,32-bit and the same size as the operand vector elements.integers. Signed and unsigned integers are distinct.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size11Vd0000opQM0Vm
RM

64-bit SIMD vector (Q == 0)

VCVTA{<q>}.<dt>.<dt2> <Dd>, <Dm>

128-bit SIMD vector (Q == 1)

VCVTA{<q>}.<dt>.<dt2> <Qd>, <Qm>

if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; if (size == '01' && !HaveFP16Ext()) || size IN {'00', '11'} then UNDEFINED; rounding = FPDecodeRM(RM); unsigned = (op == '1'); case size of when '01' esize = 16; elements = 4; when '10' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;

T1

15141312111098765432101514131211109876543210
111111111D11size11Vd0000opQM0Vm
RM

64-bit SIMD vector (Q == 0)

VCVTA{<q>}.<dt>.<dt2> <Dd>, <Dm>

128-bit SIMD vector (Q == 1)

VCVTA{<q>}.<dt>.<dt2> <Qd>, <Qm>

if InITBlock() then UNPREDICTABLE; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; if (size == '01' && !HaveFP16Ext()) || size IN {'00', '11'} then UNDEFINED; rounding = FPDecodeRM(RM); unsigned = (op == '1'); case size of when '01' esize = 16; elements = 4; when '10' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<q>

See Standard assembler syntax fields.

<dt> Is the data type for the elements of the destination, encoded in op:size:
opsize<dt>
001S32S16
0110U32S32
101U16
110U32
<dt2> Is the data type for the elements of the source vector, encoded in size:
size<dt2>
01F16
10F32
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

EncodingSpecificOperations(); CheckAdvSIMDEnabled(); bits(esize) result; for r = 0 to regs-1 for e = 0 to elements-1 Elem[D[d+r],e,esize] = FPToFixed(Elem[D[m+r],e,esize], 0, unsigned, StandardFPSCRValue(), rounding);


Internal version only: isa v01_06v01_03, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-12T172019-09-30T07:3440

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)