1. Introduction

This is the 2019-12 release of the AArch32 ISA XML for Armv8.6.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

If you have comments on the content of this package, please send them by e-mail to support-aarchv8@arm.com. Give:

• The title, "AArch32 ISA XML for Armv8.6".
• The version, "2019-12".
• A concise explanation of your comments.

2. Contents

3. Release Notes

Change history

The following general changes are made:

The following changes are made to the instruction definitions:

• The instruction descriptions for the following instructions are corrected to state that result vector elements are integers, and the same size as the operand vector elements. Signed and unsigned integers are distinct.
  
  • VCVTA (Advanced SIMD)
  • VCVTM (Advanced SIMD)
  • VCVTN (Advanced SIMD)
  • VCVTP (Advanced SIMD)
  
  The description of how <dt> is encoded is also corrected.

The following changes are made to the Shared Pseudocode:

• The functions CombineS1S2Desc() and CombineS1S2AttrHints() are refactored to remove redundancy in the code.

Known issues

• 'Alias conditions' in LDR (immediate) and STR (immediate) are incomplete.
• References to TAG_GRANULE in some ARMv8.5-MemTag instances are incorrect.
• There is an apparent clash in the following instruction encoding tables for A32 and T32:
  • System register access, Advanced SIMD, and floating-point
  • System register access, Advanced SIMD, floating-point, and Supervisor call

  There are no overlapping encodings in this part of the instruction set. The "Advanced SIMD two registers and a scalar extension" are split as follows:

  • All encodings with op3 = '0' will be moved to their own table, "Multiply with Accumulate" under the "Floating-point data-processing" group.
  • All encodings with op3 = '1' will be moved to their own table, "Advanced SIMD dot product".

Potential upcoming changes