The ERR<n>MISC0 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:
If the node that owns error record <n> implements architecturally-defined error counters (ERR<q>FR.CEC != 0b000), and error record <n> can record countable errors, then ERR<n>MISC0 implements the architecturally-defined error counter or counters.
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>MISC0 are RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>MISC0, writing zero must always be supported to return the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.
ERR<n>MISC0 is a 64-bit register.
The ERR<n>MISC0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | OF | CEC | |||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
Sticky overflow bit. Set to 1 when the Corrected error count field is incremented and wraps through zero.
OF | Meaning |
---|---|
0b0 |
Counter has not overflowed. |
0b1 |
Counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | OF | CEC | |||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
Sticky overflow bit. Set to 1 when the Corrected error count field is incremented and wraps through zero.
OF | Meaning |
---|---|
0b0 |
Counter has not overflowed. |
0b1 |
Counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
OFO | CECO | OFR | CECR | ||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Sticky overflow bit, other. Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.
OFO | Meaning |
---|---|
0b0 |
Other counter has not overflowed. |
0b1 |
Other counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing CECR.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Sticky overflow bit, repeat. Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.
OFR | Meaning |
---|---|
0b0 |
Repeat counter has not overflowed. |
0b1 |
Repeat counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.
For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. CECR is then incremented for each subsequent Corrected Error in the same set and way.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | OFO | CECO | OFR | CECR | |||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
Sticky overflow bit, other. Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.
OFO | Meaning |
---|---|
0b0 |
Other counter has not overflowed. |
0b1 |
Other counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing CECR.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Sticky overflow bit, repeat. Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.
OFR | Meaning |
---|---|
0b0 |
Repeat counter has not overflowed. |
0b1 |
Repeat counter has overflowed. |
A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.
For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. CECR is then incremented for each subsequent Corrected Error in the same set and way.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
Reads from ERR<n>MISC0 return an IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.
Arm recommends that miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.
When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error should ignore writes.
These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.
Component | Offset | Instance |
---|---|---|
RAS | 0x020 + 64n | ERR<n>MISC0 |
Accesses on this interface are RW.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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