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The DBGDTR_EL0 characteristics are:
Transfers 64 bits of data between the PE and an external debugger. Can transfer both ways using only a single register.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when written.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to External register DBGDTRTX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register DBGDTRTX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to External register DBGDTRRX_EL0[31:0] when read.
AArch64 System register DBGDTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0] when read.
DBGDTR_EL0 is a 64-bit register.
The DBGDTR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
HighWord | |||||||||||||||||||||||||||||||
LowWord | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Writes to this register set DTRRX to the value in this field and do not change RXfull.
Reads of this register:
If RXfull is set to 1, return the last value written to DTRTX.
If RXfull is set to 0, return an UNKNOWN value.
After the read, RXfull is cleared to 0.
Writes to this register set DTRTX to the value in this field and set TXfull to 1.
Reads of this register:
If RXfull is set to 1, return the last value written to DTRRX.
If RXfull is set to 0, return an UNKNOWN value.
After the read, RXfull is cleared to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b0000 | 0b0100 | 0b000 |
if Halted() then
return DBGDTR_EL0;
elsif PSTATE.EL == EL0 then
if !Halted() && !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return DBGDTR_EL0;
elsif PSTATE.EL == EL1 then
if !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return DBGDTR_EL0;
elsif PSTATE.EL == EL2 then
if !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return DBGDTR_EL0;
elsif PSTATE.EL == EL3 then
return DBGDTR_EL0;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b0000 | 0b0100 | 0b000 |
if Halted() then
DBGDTR_EL0 = X[t];
elsif PSTATE.EL == EL0 then
if !Halted() && !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTR_EL0 = X[t];
elsif PSTATE.EL == EL1 then
if !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTR_EL0 = X[t];
elsif PSTATE.EL == EL2 then
if !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTR_EL0 = X[t];
elsif PSTATE.EL == EL3 then
DBGDTR_EL0 = X[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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