The ERRERICR1 characteristics are:
Interrupt configuration register.
External register ERRERICR1 bits [31:0] are architecturally mapped to External register ERRIRQCR3[31:0] .
This register is present only when RAS is implemented. Otherwise, direct accesses to ERRERICR1 are RES0.
Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.
ERRERICR1 is a 32-bit register.
The ERRERICR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
Payload for a message signaled interrupt.
The following resets apply:
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Component | Offset | Instance |
---|---|---|
RAS | 0xE98 | ERRERICR1 |
Accesses on this interface are RW.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.