The AMDEVAFF1 characteristics are:
Copy of the high half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the AMU component relates to.
The power domain of AMDEVAFF1 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMDEVAFF1 are RES0.
AMDEVAFF1 is a 32-bit register.
The AMDEVAFF1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPIDR_EL1hi |
MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1, as seen from the highest implemented Exception level.
Component | Offset | Instance |
---|---|---|
AMU | 0xFAC | AMDEVAFF1 |
Accesses on this interface are RO.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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