The JMCR characteristics are:
A Jazelle register, which provides control of the Jazelle extension.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to JMCR are UNKNOWN.
JMCR is a 32-bit register.
The JMCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAZ/WI |
Reserved, RAZ/WI.
For accesses from EL0 it is IMPLEMENTATION DEFINED whether the register is RW or UNDEFINED.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b111 | 0b0010 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else return JMCR; elsif PSTATE.EL == EL1 then return JMCR; elsif PSTATE.EL == EL2 then return JMCR; elsif PSTATE.EL == EL3 then return JMCR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b111 | 0b0010 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JMCR UNDEFINED at EL0" then UNDEFINED; else //no operation elsif PSTATE.EL == EL1 then //no operation elsif PSTATE.EL == EL2 then //no operation elsif PSTATE.EL == EL3 then //no operation
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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