(old) | htmldiff from- | (new) |
The TPIDRPRW characteristics are:
Provides a location where software executing at EL1 or higher can store thread identifying information that is not visible to software executing at EL0, for OS management purposes.
The PE makes no use of this register.
AArch32 System register TPIDRPRW bits [31:0] are architecturally mapped to AArch64 System register TPIDR_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TPIDRPRW are UNKNOWN.
The PE never updates this register.
RW fields in this register reset to architecturally UNKNOWN values.
TPIDRPRW is a 32-bit register.
The TPIDRPRW bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Thread ID |
Thread ID. Thread identifying information stored by software running at this Exception level.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
return TPIDRPRW_S;
else
return TPIDRPRW_NS;
else
return TPIDRPRW;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
return TPIDRPRW_NS;
else
return TPIDRPRW;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
return TPIDRPRW_S;
else
return TPIDRPRW_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
TPIDRPRW_S = R[t];
else
TPIDRPRW_NS = R[t];
else
TPIDRPRW = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
TPIDRPRW_NS = R[t];
else
TPIDRPRW = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
TPIDRPRW_S = R[t];
else
TPIDRPRW_NS = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |