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ERR<n>MISC0, Error Record Miscellaneous Register 0, n = 0 - 65534

The ERR<n>MISC0 characteristics are:

Purpose

IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:

If the node <q> that owns error record <n> implements architecturally-defined error counters, (so thatERR<q>FR.CEC != 0b000),, and error record <n> can record countable errors, then ERR<n>MISC0 implements the architecturally-defined error counter or counters.

Configuration

The number of error records that are implemented is IMPLEMENTATION DEFINED.

If error record <n> is not implemented, ERR<n>MISC0 is RES0.

ThisSome registeror isall presentRW only whenfields errorof recordthis <n>register ishave implemented. Otherwise,defined directreset accesses to ERR<n>MISC0 arevalues. RES0.

ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.

For IMPLEMENTATION DEFINED fields in ERR<n>MISC0this register, writing zero must always be supported to return the error record to an initial quiescent state.

In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.

Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.

Note

Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.CTRL, where q is the index of the first error record owned by the same node as error record n. If the node owns a single record then q = n.

Attributes

ERR<n>MISC0 is a 64-bit register.

Field descriptions

The ERR<n>MISC0 bit assignments are:

When ERR<q>FR.CEC == 0b000:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

When ERR<q>FR.CEC == 0b100 and ERR<q>FR.RP == 0:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINEDOFCEC
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:48]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

OF, bit [47]

Set to 1 when the Corrected error count field is incremented and wraps through zero.

Sticky overflow bit. Set to 1 when the Corrected error count field is incremented and wraps through zero.

OFMeaning
0b0

Counter has not overflowed.

0b1

Counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CEC, bits [46:32]

Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

The following resets apply:

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

When ERR<q>FR.CEC == 0b010 and ERR<q>FR.RP == 0:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINEDOFCEC
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:40]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

OF, bit [39]

Set to 1 when the Corrected error count field is incremented and wraps through zero.

Sticky overflow bit. Set to 1 when the Corrected error count field is incremented and wraps through zero.

OFMeaning
0b0

Counter has not overflowed.

0b1

Counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CEC, bits [38:32]

Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted.

The following resets apply:

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

When ERR<q>FR.CEC == 0b100 and ERR<q>FR.RP == 1:

6362616059585756555453525150494847464544434241403938373635343332
OFOCECOOFRCECR
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

OFO, bit [63]

Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

Sticky overflow bit, other. Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

OFOMeaning
0b0

Other counter has not overflowed.

0b1

Other counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CECO, bits [62:48]

Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR.

Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing CECR.

The following resets apply:

OFR, bit [47]

Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

Sticky overflow bit, repeat. Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

OFRMeaning
0b0

Repeat counter has not overflowed.

0b1

Repeat counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CECR, bits [46:32]

Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. CECR is then incremented for each subsequent Corrected Error in the same set and way.

The following resets apply:

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

When ERR<q>FR.CEC == 0b010 and ERR<q>FR.RP == 1:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINEDOFOCECOOFRCECR
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:48]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

OFO, bit [47]

Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

Sticky overflow bit, other. Set to 1 when the Corrected error count, other, field is incremented and wraps through zero.

OFOMeaning
0b0

Other counter has not overflowed.

0b1

Other counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CECO, bits [46:40]

Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR.

Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing CECR.

The following resets apply:

OFR, bit [39]

Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

Sticky overflow bit, repeat. Set to 1 when the Corrected error count, repeat, field is incremented and wraps through zero.

OFRMeaning
0b0

Repeat counter has not overflowed.

0b1

Repeat counter has overflowed.

A direct write that modifies this bit might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this bit to an UNKNOWN value.

The following resets apply:

CECR, bits [38:32]

Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way.

Note

For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. CECR is then incremented for each subsequent Corrected Error in the same set and way.

The following resets apply:

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED syndrome.

IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.

Accessing the ERR<n>MISC0

ReadsArm fromrecommends ERR<n>MISC0that returna anmiscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write. IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.

Arm recommends that miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.WhenERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.

When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error should ignore writes.

Note

These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.

ERR<n>MISC0 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x020 + 64nERR<n>MISC0

Accesses on this interface are RW.




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