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TFSR_EL3, Tag FaultFail Status Register (EL3)

The TFSR_EL3 characteristics are:

Purpose

Holds accumulated Tag Check FaultsFails occurring in EL3 thatwhich are not taken precisely.

Configuration

This register is present only when ARMv8.5-MemTag is implemented and ID_AA64PFR1_EL1.MTE != 0b0001. Otherwise, direct accesses to TFSR_EL3 are UNDEFINED.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TFSR_EL3 is a 64-bit register.

Field descriptions

The TFSR_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0TF0
313029282726252423222120191817161514131211109876543210

Bits [63:1]

Reserved, RES0.

TF0, bit [0]

Tag Check Fault.Fail. Asynchronously set to 1 when a Tag Check Faultfail using a virtual address with bit[<55] ==>== 0b0 occurs.

This field resets to an architecturally UNKNOWN value.

Accessing the TFSR_EL3

Accesses to this register use the following encodings:

MRS <Xt>, TFSR_EL3

op0op1CRnCRmop2
0b110b1100b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return TFSR_EL3;

MSR TFSR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then TFSR_EL3 = X[t];




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

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