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The DTLBIALL characteristics are:
Invalidate all cached copies of translation table entries from data TLBs that are from any level of the translation table walk. The entries that are invalidated are as follows:
The invalidation only applies to the PE that executes this System instruction.
Arm deprecates the use of this System instruction. It is only provided for backwards compatibility with earlier versions of the Arm architecture.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DTLBIALL are UNKNOWN.
DTLBIALL is a 32-bit System instruction.
DTLBIALL ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1000 | 0b0110 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TTLB == '1' then
AArch32.TakeHypTrapException(0x03);
else
DTLBIALL();
elsif PSTATE.EL == EL2 then
DTLBIALL();
elsif PSTATE.EL == EL3 then
DTLBIALL();
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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