The ERR<n>MISC2 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>MISC2 are RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>MISC2, writing zero must always be supported to return the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
If RAS System Architecture v1.1 is not implemented, Arm recommendeds that ERR<n>MISC2 does not require zeroing to return the record to a quiescent state.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.
It is IMPLEMENTATION DEFINED whether ERR<n>MISC2 is present if RAS System Architecture v1.1 is not implemented. ERR<n>MISC2 is RES0 if not present.
ERR<n>MISC2 is a 64-bit register.
The ERR<n>MISC2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
Reads from ERR<n>MISC2 return an IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.
Arm recommends that miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.
When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error should ignore writes.
These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.
Component | Offset | Instance |
---|---|---|
RAS | 0x030 + 64n | ERR<n>MISC2 |
Accesses on this interface are RW.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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