The CTICIDR2 characteristics are:
Provides information to identify a CTI component.
For more information see 'About the Component identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
CTICIDR2 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTICIDR2 is a 32-bit register.
The CTICIDR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_2 |
Reserved, RES0.
Preamble. Must read as 0x05.
Component | Offset | Instance |
---|---|---|
CTI | 0xFF8 | CTICIDR2 |
Accesses on this interface are RO.
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