The ERRPIDR2 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
ERRPIDR2 is a 32-bit register.
The ERRPIDR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
IMPLEMENTATION DEFINED.
Component major revision. ERRPIDR2.REVISION and ERRPIDR3.REVAND together form the revision number of the component, with ERRPIDR2.REVISION being the most significant part and ERRPIDR3.REVAND the least significant part. When a component is changed, ERRPIDR2.REVISION or ERRPIDR3.REVAND must be increased to ensure that software can differentiate the different revisions of the component. If ERRPIDR2.REVISION is increased then ERRPIDR3.REVAND should be set to 0b0000.
JEDEC-assigned JEP106 implementer code is used.
This bit reads as one.
IMPLEMENTATION DEFINED.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_2 | JEDEC | DES_1 |
Reserved, RES0.
IMPLEMENTATION DEFINED.
Part number, bits [15:12].
The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number:
JEDEC-assigned JEP106 implementer code is used.
This bit reads as one.
IMPLEMENTATION DEFINED.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
Component | Offset |
---|---|
RAS | 0xFE8 |
Accesses on this interface are RO.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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