(old) | htmldiff from- | (new) |
The DBGDTRTX_EL0 characteristics are:
Transfers data from the PE to an external debugger. For example, it is used by a debug target to transfer data to the debugger. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communication Channel.
AArch64 System register DBGDTRTX_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRTXint[31:0] .
AArch64 System register DBGDTRTX_EL0 bits [31:0] are architecturally mapped to External register DBGDTRTX_EL0[31:0] .
Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into an Exception level that is using AArch64.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.
DBGDTRTX_EL0 is a 64-bit register.
The DBGDTRTX_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
Return DTRTX | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Return DTRTX.
Writes to this register:
If TXfull is set to 1, set DTRRX and DTRTX to UNKNOWN.
If TXfull is set to 0, update the value in DTRTX.
After the write, TXfull is set to 1.
For the full behavior of the Debug Communications Channel, see The Debug Communication Channel and Instruction Transfer Register.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b0000 | 0b0101 | 0b000 |
if Halted() then
DBGDTRTX_EL0 = X[t];
elsif PSTATE.EL == EL0 then
if !Halted() && !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTRTX_EL0 = X[t];
elsif PSTATE.EL == EL1 then
if !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TDCC == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTRTX_EL0 = X[t];
elsif PSTATE.EL == EL2 then
if !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDCC == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif !Halted() && HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
DBGDTRTX_EL0 = X[t];
elsif PSTATE.EL == EL3 then
DBGDTRTX_EL0 = X[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |