The CNTFID<n> characteristics are:
Indicates alternative system counter update frequencies.
The power domain of CNTFID<n> is IMPLEMENTATION DEFINED.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The possible frequencies for the system counter are stored in the Frequency modes table as 32-bit words starting with the base frequency, CNTFID0, see 'The Frequency modes table' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The number of CNTFID<n> registers is IMPLEMENTATION DEFINED, and the only required CNTFID<n> register is CNTFID0.
The final entry in the Frequency modes table must be followed by a 32-bit word of zero value, to mark the end of the table.
The architecture can support up to 1004 entries in the Frequency modes table, including the zero-word end marker, and the number of entries is IMPLEMENTATION DEFINED up to this limit. For an implementation that includes registers in the IMPLEMENTATION DEFINED register space 0x0C0-0x0FC, the maximum number of entries in the Frequency modes table is 40, including the zero-word end marker.
Typically, the Frequency modes table will be in read-only memory. However, a system implementation might use read/write memory for the table, and initialize the table entries as part of its start-up sequence.
If the Frequency modes table is in read/write memory, Arm strongly recommends that the table is not updated once the system is running.
CNTFID<n> is a 32-bit register.
The CNTFID<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Frequency |
A system counter update frequency, in Hz. Must be an exact divisor of the base frequency. Arm strongly recommends that all frequency values in the Frequency modes table are integer power-of-two divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the increment applied at each counter update is given by:
increment = (base frequency) / (selected frequency)
This field resets to an architecturally UNKNOWN value.
It is IMPLEMENTATION DEFINED whether this register is RO or RW
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes these registers, is implemented only in the Secure memory map.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTControlBase | 0x020 + 4n | CNTFID<n> |
Accesses on this interface are RO or RW.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.