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The EDESR characteristics are:
Indicates the status of internally pending Halting debug events.
EDESR is in the Core power domain.
Some or all RW fields of this register have defined reset values. The field descriptions identify when the reset values apply.
EDESR is a 32-bit register.
The EDESR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SS | RC | OSUC |
Reserved, RES0.
Halting step debug event pending. Possible values of this field are:
SS | Meaning |
---|---|
0b0 | Reading this means that a Halting step debug event is not pending. Writing this means no action. |
0b1 | Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event. |
On a Cold reset, this field resets to 0.
Halting step debug event pending. Possible values of this field are:
SS | Meaning |
---|---|
0b0 | Reading this means that a Halting step debug event is not pending. Writing this means no action. |
0b1 | Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event. |
On a Warm reset, this field resets to the value in EDECR.SS.
Reset Catch debug event pending. Possible values of this field are:
RC | Meaning |
---|---|
0b0 | Reading this means that a Reset Catch debug event is not pending. Writing this means no action. |
0b1 | Reading this means that a Reset Catch debug event is pending. Writing this clears the pending Reset Catch debug event. |
On a Warm reset, this field resets to:
OS Unlock Catch debug event pending. Possible values of this field are:
OSUC | Meaning |
---|---|
0b0 | Reading this means that an OS Unlock Catch debug event is not pending. Writing this means no action. |
0b1 | Reading this means that an OS Unlock Catch debug event is pending. Writing this clears the pending OS Unlock Catch debug event. |
On a Warm reset, this field resets to 0.
If a request to clear a pending Halting debug event is received at or about the time when halting becomes allowed, it is CONSTRAINED UNPREDICTABLE whether the event is taken.
If Core power is removed while a Halting debug event is pending, it is lost. However, it might become pending again when the Core is powered back on and Cold reset.
Component | Offset | Instance |
---|---|---|
Debug | 0x020 | EDESR |
This interface is accessible as follows:
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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