The TLBI ASIDE1IS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry.
The entry would be used for the specified ASID, and either:
Is from a level of lookup above the final level.
Is a non-global entry from the final level of lookup.
When EL2 is implemented and enabled in the Security state described by the current value of SCR_EL3.NS:
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate an address using the EL1&0 translation regime.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
There are no configuration notes.
TLBI ASIDE1IS is a 64-bit System instruction.
The TLBI ASIDE1IS input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ASID | RES0 | ||||||||||||||||||||||||||||||
RES0 | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.
If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0.
Reserved, RES0.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b1000 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIASIDE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1IS(X[t]);
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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