The ID_AA64ZFR0_EL1 characteristics are:
Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.
For general information about the interpretation of the ID registers see Principles of the ID scheme for fields in ID registers.
This register is present only when SVE is implemented. Otherwise, direct accesses to ID_AA64ZFR0_EL1 are RAZ.
ID_AA64ZFR0_EL1 is a 64-bit register.
The ID_AA64ZFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | F64MM | F32MM | RES0 | I8MM | RES0 | ||||||||||||||||||||||||||
RES0 | BF16 | RES0 | SVEver | ||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates support for SVE FP64 double-precision floating-point matrix multiplication instructions. Defined values are:
F64MM | Meaning |
---|---|
0b0000 |
FP64 matrix multiplication and related instructions are not implemented. |
0b0001 |
FMMLA, and LD1RO* instructions are implemented. The 128-bit element variations of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 are also implemented. |
All other values are reserved.
ARMv8.2-F64MM implements the functionality identified by 0b0001.
Reserved, RES0.
Indicates support for the SVE FP32 single-precision floating-point matrix multiplication instruction. Defined values are:
F32MM | Meaning |
---|---|
0b0000 |
FP32 matrix multiplication instruction is not implemented. |
0b0001 |
FMMLA instruction is implemented. |
All other values are reserved.
ARMv8.2-F32MM implements the functionality identified by 0b0001.
Reserved, RES0.
Reserved, RES0.
Indicates support for SVE Int8 matrix multiplication instructions. Defined values are:
I8MM | Meaning |
---|---|
0b0000 |
Int8 matrix multiplication instructions are not implemented. |
0b0001 |
SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented. |
All other values are reserved.
ARMv8.2-I8MM implements the functionality identified by 0b0001.
From Armv8.6, the only permitted value is 0b0001.
Reserved, RES0.
Reserved, RES0.
Indicates support for SVE BFloat16 instructions. Defined values are:
BF16 | Meaning |
---|---|
0b0000 |
BFloat16 instructions are not implemented. |
0b0001 |
BFCVT, BFCVTNT, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented. |
All other values are reserved.
ARMv8.2-BF16 implements the functionality identified by 0b0001.
From ARMv8.6, the only permitted value is 0b0001.
Reserved, RES0.
Reserved, RES0.
Scalable Vector Extension instruction set version. Defined values are:
SVEver | Meaning |
---|---|
0b0000 |
SVE instructions are implemented. |
All other values are reserved. This field is only valid if the ID_AA64PFR0_EL1.SVE field is not zero.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0100 | 0b100 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("ARMv8.4-IDST") then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_AA64ZFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64ZFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64ZFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64ZFR0_EL1;
27/09/2019 18:48; 6134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.