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The PMEVCNTR<n> characteristics are:
Holds event counter n, which counts events, where n is 0 to 30.
AArch32 System register PMEVCNTR<n> bits [31:0] are architecturally mapped to AArch64 System register PMEVCNTR<n>_EL0[31:0] .
AArch32 System register PMEVCNTR<n> bits [31:0] are architecturally mapped to External register PMEVCNTR<n>_EL0[31:0] .
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only when AArch32 is supported at any Exception level and PMUv3 is implemented. Otherwise, direct accesses to PMEVCNTR<n> are UNDEFINED.
PMEVCNTR<n> is a 32-bit register.
The PMEVCNTR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Event counter n |
Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.
If ARMv8.5-PMU is implemented, the event counter is 64 bits and only the least-significant part of the event counter is accessible in AArch32 state:
Reads from PMEVCNTR<n> return bits [31:0] of the counter.
Writes to PMEVCNTR<n> update bits [31:0] and leave bits [63:32] unchanged.
There is no means to access bits [63:32] directly from AArch32 state.
If the implementation does not support AArch64 at any Exception level, bits [63:32] are not required to be implemented.
If ARMv8.5-PMU is not implemented, the event counter is 32 bits.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
PMEVCNTR<n> can also be accessed by using PMXEVCNTR with PMSELR.SEL set to the value of <n>.
If ARMv8.6-FGT is implemented, andEL2 <n> is greaterimplemented thanand orenabled equalin to the numbercurrent ofSecurity accessible countersstate, thenand theEL1 behavioris ofusing AArch64, for permitted reads and writes ofat EL0: PMEVCNTR<n> is as follows:
If ARMv8.6-FGT is not implemented, and <n> is greater than or equal to the numberabove ofbehaviors accessibledo counters,not then reads and writes ofapply: PMEVCNTR<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
If <n> is greater than or equal to the number of accessible counters, then reads and writes of PMEVCNTR<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
In EL0, an access is permitted if it is enabled by PMUSERENR.{ER,EN} or PMUSERENR_EL0.{ER,EN}.
If EL2 is implemented and enabled in the current Security state, at EL0 and EL1:
Otherwise, the number of accessible counters is the number of implemented counters. See HDCR.HPMN and MDCR_EL2.HPMN for more details.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1110 | 0b10:n[4:3] | n[2:0] |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && PMUSERENR_EL0.<ER,EN> == '00' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.<ER,EN> == '00' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVCNTRn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)]; elsif PSTATE.EL == EL3 then return PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)];
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1110 | 0b10:n[4:3] | n[2:0] |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && PMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVCNTRn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)] = R[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)] = R[t]; elsif PSTATE.EL == EL3 then PMEVCNTR[UInt(CRm<1:0>:opc2<2:0>)] = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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