(old) htmldiff from-(new)

GICR_SYNCR, Redistributor Synchronize Register

The GICR_SYNCR characteristics are:

Purpose

Indicates completion of registerphysical based invalidateRedistributor operations.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_SYNCR is a 32-bit register.

Field descriptions

The GICR_SYNCR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0Busy

Bits [31:1]

Reserved, RES0.

Busy, bit [0]

Indicates completion of invalidationany Redistributor operations as follows:

BusyMeaning
0b0

No operations are in progress.

0b1

A write is in progress to one or more of the following registers:

This field tracksalso indicates completion of any operations initiated onby thewrites same Redistributor.toGICR_PENDBASER or GICR_PROPBASER.

Accessing the GICR_SYNCR

WhenOptionally, when this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.

This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.

GICR_SYNCR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorRD_base0x00C0GICR_SYNCR

This interface is accessible as follows:




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)