(old) | htmldiff from- | (new) |
The HAFGRTR_EL2 characteristics are:
Provides controls for traps of MRS reads of Activity Monitors System registers.
This register is present only when AMUv1 is implemented and ARMv8.6-FGT is implemented. Otherwise, direct accesses to HAFGRTR_EL2 are UNDEFINED.
Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into EL2 using AArch64.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.
HAFGRTR_EL2 is a 64-bit register.
The HAFGRTR_EL2 bit assignments are:
Reserved, RES0.
Trap MRS reads of AMEVTYPER115_EL0AMEVTYPER1<15>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER115AMEVTYPER1<15> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER115_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER115_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR115_EL0AMEVCNTR1<15>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR115AMEVCNTR1<15> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR115_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR115_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER114_EL0AMEVTYPER1<14>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER114AMEVTYPER1<14> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER114_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER114_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR114_EL0AMEVCNTR1<14>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR114AMEVCNTR1<14> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR114_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR114_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER113_EL0AMEVTYPER1<13>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER113AMEVTYPER1<13> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER113_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER113_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR113_EL0AMEVCNTR1<13>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR113AMEVCNTR1<13> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR113_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR113_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER112_EL0AMEVTYPER1<12>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER112AMEVTYPER1<12> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER112_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER112_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR112_EL0AMEVCNTR1<12>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR112AMEVCNTR1<12> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR112_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR112_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER111_EL0AMEVTYPER1<11>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER111AMEVTYPER1<11> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER111_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER111_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR111_EL0AMEVCNTR1<11>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR111AMEVCNTR1<11> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR111_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR111_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER110_EL0AMEVTYPER1<10>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER110AMEVTYPER1<10> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER110_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER110_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR110_EL0AMEVCNTR1<10>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR110AMEVCNTR1<10> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR110_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR110_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER19_EL0AMEVTYPER1<9>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER19AMEVTYPER1<9> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER19_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER19_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR19_EL0AMEVCNTR1<9>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR19AMEVCNTR1<9> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR19_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR19_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER18_EL0AMEVTYPER1<8>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER18AMEVTYPER1<8> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER18_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER18_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR18_EL0AMEVCNTR1<8>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR18AMEVCNTR1<8> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR18_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR18_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER17_EL0AMEVTYPER1<7>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER17AMEVTYPER1<7> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER17_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER17_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR17_EL0AMEVCNTR1<7>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR17AMEVCNTR1<7> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR17_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR17_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER16_EL0AMEVTYPER1<6>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER16AMEVTYPER1<6> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER16_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER16_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR16_EL0AMEVCNTR1<6>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR16AMEVCNTR1<6> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR16_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR16_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER15_EL0AMEVTYPER1<5>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER15AMEVTYPER1<5> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER15_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER15_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR15_EL0AMEVCNTR1<5>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR15AMEVCNTR1<5> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR15_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR15_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER14_EL0AMEVTYPER1<4>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER14AMEVTYPER1<4> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER14_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER14_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR14_EL0AMEVCNTR1<4>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR14AMEVCNTR1<4> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR14_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR14_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER13_EL0AMEVTYPER1<3>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER13AMEVTYPER1<3> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER13_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER13_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR13_EL0AMEVCNTR1<3>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR13AMEVCNTR1<3> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR13_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR13_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER12_EL0AMEVTYPER1<2>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER12AMEVTYPER1<2> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER12_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER12_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR12_EL0AMEVCNTR1<2>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR12AMEVCNTR1<2> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR12_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR12_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER11_EL0AMEVTYPER1<1>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER11AMEVTYPER1<1> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER11_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER11_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR11_EL0AMEVCNTR1<1>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR11AMEVCNTR1<1> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR11_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR11_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVTYPER10_EL0AMEVTYPER1<0>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER10AMEVTYPER1<0> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVTYPER10_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVTYPER10_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR10_EL0AMEVCNTR1<0>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR10AMEVCNTR1<0> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR10_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR10_EL0 |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of AMCNTENCLR1_EL0 and AMCNTENSET1_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of AMCNTENCLR1 and AMCNTENSET1.
AMCNTEN1 | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of AMEVCNTR0<x3>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<x3> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
AMEVCNTR0<x>_EL0 | Meaning |
---|---|
0b0 | MRS reads of AMEVCNTR0<x |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR0<2>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<2> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
| |
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR0<1>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<1> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
| |
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AMEVCNTR0<0>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<0> at EL0 using AArch32 when EL1 is using AArch64 to EL2.
| |
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of AMCNTENCLR0_EL0 and AMCNTENSET0_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of AMCNTENCLR0 and AMCNTENSET0.
AMCNTEN0 | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1E8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return HAFGRTR_EL2; elsif PSTATE.EL == EL3 then return HAFGRTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1E8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else HAFGRTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HAFGRTR_EL2 = X[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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