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The MPAMF_MBWUMON_IDR characteristics are:
IndicatesThe MPAMF_MBWUMON_IDR is a 32-bit read-only register that indicates the number of memory bandwidth usage monitors for this MSC. ThisMPAMF_MBWUMON_IDR_s register also indicates severalthe propertiesnumber of theSecure MBWUmemory monitors,bandwidth includingusage whethermonitor theyinstances. supportMPAMF_MBWUMON_IDR_ns capture,indicates scalingthe ornumber longof counters.Non-secure memory bandwidth usage monitor instances.
MPAMF_MBWUMON_IDR_s indicates the number of Secure memory bandwidth usage monitor instances. MPAMF_MBWUMON_IDR_ns indicates the number of Non-secure memory bandwidth usage monitor instances.
The power domain of MPAMF_MBWUMON_IDR is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_MSMON == 1 and MPAMF_MSMON_IDR.MSMON_MBWU == 1. Otherwise, direct accesses to MPAMF_MBWUMON_IDR are RES0.
MPAMF_MBWUMON_IDR is a 32-bit register.
The MPAMF_MBWUMON_IDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HAS_CAPTURE | HAS_LONG | LWD | RES0 | SCALE | NUM_MON |
The implementation of this MSC supports copying an MSMON_MBWU to the corresponding MSMON_MBWU_CAPTURE on a capture event.
HAS_CAPTURE | Meaning |
---|---|
0b0 | MSMON_MBWU_CAPTURE is not implemented and there is no support for capture events in the MBWU monitor. |
0b1 | The MSMON_MBWU_CAPTURE register is implemented and the MBWU monitor supports the capture event behavior. |
Indicates whether MSMON_MBWU_L is implemented.
If HAS_CAPTURE == 1, indicates whether MSMON_MBWU_L_CAPTURE is implemented.
HAS_LONG | Meaning |
---|---|
0b0 | Does not implement MSMON_MBWU_L or MSMON_MBWU_L_CAPTURE. |
0b1 | Implements MSMON_MBWU_L. If HAS_CAPTURE == 1, MSMON_MBWU_L_CAPTURE is also implemented. |
Reserved, RES0.
Long register VALUE width.
If MPAMF_MBWUMON_IDR.HAS_LONG == 0, MPAMF_MBWUMON_IDR.LWD must also be 0.
LWD | Meaning |
---|---|
0b0 | If MPAMF_MBWUMON_IDR.HAS_LONG == 1, MSMON_MBWU_L has 44-bit VALUE field in bits [43:0]. Bits [62:44] are RES0. If HAS_LONG == 1 and MSMON_MBWU_IDR.HAS_CAPTURE == 1, MSMON_MBWU_L_CAPTURE also has 44-bit VALUE field in bits [43:0]. |
0b1 | MSMON_MBWU_L has 63-bit VALUE field in bits [62:0]. If MPAMF_MBWUMON_IDR.HAS_CAPTURE == 1, MSMON_MBWU_L_CAPTURE also has 63-bit VALUE field in bits [62:0]. |
Reserved, RES0.
Reserved, RES0.
Scaling of MSMON_MBWU.VALUE in bits. If scaling is enabled by MSMON_CFG_MBWU_CTL.SCLEN, the byte count in the VALUE field has been shifted by SCALE bits to the right.
SCALE | Meaning |
---|---|
0b00000 | Scaling is not implemented. |
0bxxxxx | Other values are right shift count when scaling is enabled. |
The number of memory bandwidth usage monitors implemented in this MSC.
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_MBWUMON_IDR is read-only.
MPAMF_MBWUMON_IDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_MBWUMON_IDR is permitted to have the same contents when read from either the Secure and Non-secure MPAM feature pages unless the register contents is different for Secure and Non-secure versions, when there must be separate registers in the Secure (MPAMF_MBWUMON_IDR_s) and Non-secure (MPAMF_MBWUMON_IDR_ns) MPAM feature pages.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0090 | MPAMF_MBWUMON_IDR_s |
Accesses on this interface are RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0090 | MPAMF_MBWUMON_IDR_ns |
Accesses on this interface are RO.
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