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The DACR characteristics are:
Defines the access permission for each of the sixteen memory domains.
AArch32 System register DACR bits [31:0] are architecturally mapped to AArch64 System register DACR32_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DACR are UNKNOWN.
This register has no function when TTBCR.EAE is set to 1, to select the Long-descriptor translation table format.
RW fields in this register reset to architecturally UNKNOWN values.
DACR is a 32-bit register.
The DACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Domain n access permission, where n = 0 to 15. Permitted values are:
D<n> | Meaning |
---|---|
0b00 | No access. Any access to the domain generates a Domain fault. |
0b01 | Client. Accesses are checked against the permission bits in the translation tables. |
0b11 | Manager. Accesses are not checked against the permission bits in the translation tables. |
The value 0b10 is reserved.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0011 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T3 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
return DACR_S;
else
return DACR_NS;
else
return DACR;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
return DACR_NS;
else
return DACR;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
return DACR_S;
else
return DACR_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0011 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T3 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
DACR_S = R[t];
else
DACR_NS = R[t];
else
DACR = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
DACR_NS = R[t];
else
DACR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
if SCR.NS == '0' then
DACR_S = R[t];
else
DACR_NS = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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