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The CNTNSAR characteristics are:
Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.
The power domain of CNTNSAR is IMPLEMENTATION DEFINED.
The power domain of CNTNSAR is IMPLEMENTATION DEFINED.
RW fields in this register reset to architecturally UNKNOWN values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
CNTNSAR is a 32-bit register.
The CNTNSAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | NS7 | NS6 | NS5 | NS4 | NS3 | NS2 | NS1 | NS0 |
Reserved, RES0.
Non-secure access to frame n. The possible values of this bit are:
NS<n> | Meaning |
---|---|
0b0 | Secure access only. Behaves as RES0 to Non-secure accesses. |
0b1 | Secure and Non-secure accesses permitted. |
This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.
If frame CNTBase<n>:
This field resets to an architecturally UNKNOWN value.
In a system that recognizes two Security states, this register is only accessible by Secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTCTLBase | 0x004 | CNTNSAR |
Accesses on this interface are RW.
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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