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The ERR<n>ADDR characteristics are:
Software might have to reconstruct the actual physical addresses using the identity of the node and knowledge of the system.
If an addresserror ishas an associated with a detected erroraddress, then this must be written to the address register when the error is recorded. It is IMPLEMENTATION DEFINED how the recorded addresses map to the software-visible physical addresses. Software might have to reconstruct the actual physical addresses using the identity of the node and knowledge of the system.
This register is present only
when RAS is implemented.
Otherwise, direct accesses to ERR<n>ADDR are UNDEFINED.
The number of error records that are implemented is IMPLEMENTATION DEFINED.
If error record <n> is not implemented, ERR<n>ADDR is RES0.
ThisSome registeror isall presentRW only
whenfields errorof recordthis <n>register ishave implementeddefined andreset the error record includes an address associated with an error.
Otherwise, direct accesses to ERR<n>ADDR arevalues. RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
If the error record does not record the fault address, this register is RES0.
ERR<n>ADDR is a 64-bit register.
The ERR<n>ADDR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
NS | SI | AI | VA | RES0 | PADDR | ||||||||||||||||||||||||||
PADDR | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Non-secure attribute.
NS | Meaning |
---|---|
0b0 | The address is Secure. |
0b1 | The address is Non-secure. |
The following resets apply:
OnThis anbit Erroris recoverypreserved reset,on thean valueError ofRecovery this field is unchanged.reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Indicates whether the NS bit is valid.
Secure Incorrect. Indicates whether the NS bit is valid.
SI | Meaning |
---|---|
0b0 | The NS bit is correct. That is, it matches the programmers' view of the Non-secure attribute for this recorded location. |
0b1 | The NS bit might not be correct, and might not match the programmers' view of the Non-secure attribute for the recorded location. |
It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.
The following resets apply:
OnThis anbit Erroris recoverypreserved reset,on thean valueError ofRecovery this field is unchanged.reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Indicates whether the PADDR field is a valid physical address that is known to match the programmers' view of the physical address for the recorded location.
Address Incorrect. Indicates whether the PADDR field is a valid physical address that is known to match the programmers' view of the physical address for the recorded location.
AI | Meaning |
---|---|
0b0 | The PADDR field is a valid physical address. That is, it matches the programmers' view of the physical address for the recorded location. |
0b1 | The PADDR field might not be a valid physical address, and might not match the programmers' view of the physical address for the recorded location. |
It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.
The following resets apply:
OnThis anbit Erroris recoverypreserved reset,on thean valueError ofRecovery this field is unchanged.reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Indicates whether the PADDR field is a virtual address.
Virtual Address. Indicates whether the PADDR field is a virtual address.
VA | Meaning |
---|---|
0b0 | The PADDR field is not a virtual address. |
0b1 | The PADDR field is a virtual address. |
No context information is provided for the virtual address. When this bit is set to 1, ERR<n>ADDR.VAADDR.{NS,SI,AI} ==must read as {0,1,1}. 0b1, ERR<n>ADDR.{NS,SI,AI} must read as {0,1,1}.
Support for this bit is optional. If this bit is not implemented and the PADDR field is a virtual address, then ERR<n>ADDR.{NS,SI,AI} must read as {0,1,1}.
It is IMPLEMENTATION DEFINED whether this bit is read-only or read/write.
The following resets apply:
OnThis anbit Erroris recoverypreserved reset,on thean valueError ofRecovery this field is unchanged.reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
If the physical address size implemented by this component is smaller than the size of this field, then high-order bits are unimplemented and either RES0 or have a fixed read-only IMPLEMENTATION DEFINED value.
Low-order address bits might also be unimplemented and RES0, for example, if the physical address is always aligned to the size of a protection granule.
Physical Address. Address of the recorded location. If the physical address size implemented by this component is smaller than the size of this field, then high-order bits are unimplemented and either RES0 or have a fixed read-only IMPLEMENTATION DEFINED value. Low-order address bits might also be unimplemented and RES0, for example, if the physical address is always aligned to the size of a protection granule.
The following resets apply:
OnThis anfield Erroris recoverypreserved reset,on thean valueError ofRecovery this field is unchanged.reset.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
ERR<n>ADDR ignores writes if ERR<n>STATUS.AV is set to 1. ERR<n>STATUS.AV == 0b1.
Component | Offset | Instance |
---|---|---|
RAS | 0x018 + 64n | ERR<n>ADDR |
Accesses on this interface are RW.
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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