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The ERRCIDR3 characteristics are:
Provides discovery information aboutfor the component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
This register is present only
when RAS is implemented.
Otherwise, direct accesses to ERRCIDR3 are RES0.
ERRCIDR3 is a 32-bit register.
The ERRCIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_3 |
Reserved, RES0.
Component identification preamble, segment 3.
Component identification preamble, segment 3. This field reads as 0xB1.
This field reads as 0xB1.
Component | Offset |
---|---|
RAS | 0xFFC |
Accesses on this interface are RO.
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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