The ERRCIDR1 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
ERRCIDR1 is a 32-bit register.
The ERRCIDR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class.
CLASS | Meaning |
---|---|
0b1111 |
Generic peripheral with IMPLEMENTATION DEFINED register layout. |
Other values are defined by the CoreSight Architecture.
This field reads as 0xF.
Component identification preamble, segment 1.
This field reads as 0x0.
Component | Offset |
---|---|
RAS | 0xFF4 |
Accesses on this interface are RO.
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.