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The ICH_MISR characteristics are:
Indicates which maintenance interrupts are asserted.
AArch32 System register ICH_MISR bits [31:0] are architecturally mapped to AArch64 System register ICH_MISR_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICH_MISR are UNKNOWN.
If EL2 is not implemented, this register is RES0 from EL3.
Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into an Exception level that is using AArch32.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.
ICH_MISR is a 32-bit register.
The ICH_MISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | VGrp1D | VGrp1E | VGrp0D | VGrp0E | NP | LRENP | U | EOI |
Reserved, RES0.
vPE Group 1 Disabled.
VGrp1D | Meaning |
---|---|
0b0 | vPE Group 1 Disabled maintenance interrupt not asserted. |
0b1 | vPE Group 1 Disabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp1DIE is ==1 and ICH_VMCR.VENG0 is VMGrp1En==0.
This field resets to 0.
vPE Group 1 Enabled.
VGrp1E | Meaning |
---|---|
0b0 | vPE Group 1 Enabled maintenance interrupt not asserted. |
0b1 | vPE Group 1 Enabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp1EIE is ==1 and ICH_VMCR.VENG1 is VMGrp1En==1.
This field resets to 0.
vPE Group 0 Disabled.
VGrp0D | Meaning |
---|---|
0b0 | vPE Group 0 Disabled maintenance interrupt not asserted. |
0b1 | vPE Group 0 Disabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp0DIE is ==1 and ICH_VMCR.VENG0 is VMGrp0En==0.
This field resets to 0.
vPE Group 0 Enabled.
VGrp0E | Meaning |
---|---|
0b0 | vPE Group 0 Enabled maintenance interrupt not asserted. |
0b1 | vPE Group 0 Enabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp0EIE is ==1 and ICH_VMCR.VENG0 is VMGrp0En==1.
This field resets to 0.
No Pending.
NP | Meaning |
---|---|
0b0 | No Pending maintenance interrupt not asserted. |
0b1 | No Pending maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.NPIE is ==1 and no List register is in pending state.
This field resets to 0.
List Register Entry Not Present.
LRENP | Meaning |
---|---|
0b0 | List Register Entry Not Present maintenance interrupt not asserted. |
0b1 | List Register Entry Not Present maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.LRENPIE is ==1 and ICH_HCR.EOIcount is non-zero.
This field resets to 0.
Underflow.
U | Meaning |
---|---|
0b0 | Underflow maintenance interrupt not asserted. |
0b1 | Underflow maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.UIE is ==1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LRC<n>.State bits do not equal 0x0.
This field resets to 0.
End Of Interrupt.
EOI | Meaning |
---|---|
0b0 | End Of Interrupt maintenance interrupt not asserted. |
0b1 | End Of Interrupt maintenance interrupt asserted. |
This maintenance interrupt is asserted when at least one bit in ICH_EISR is 1.
This field resets to 0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_MISR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_MISR;
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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