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The ERRPIDR2 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Peripheral identification scheme'.in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
Implementation of this register is OPTIONAL.
This register is present only
when RAS is implemented.
Otherwise, direct accesses to ERRPIDR2 are RES0.
ERRPIDR2 is a 32-bit register.
The ERRPIDR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
IMPLEMENTATION DEFINED.
Component major revision. This field and ERRPIDR3.REVAND together form the revision number of the component, with REVISION being the most significant part and REVAND the least significant part.
Component major revision. ERRPIDR2.REVISION and ERRPIDR3.REVAND together form the revision number of the component, with ERRPIDR2.REVISION being the most significant part and ERRPIDR3.REVAND the least significant part. When a component is changed, ERRPIDR2.REVISION or ERRPIDR3.REVAND must be increased to ensure that software can differentiate the different revisions of the component. If ERRPIDR2.REVISION is increased then ERRPIDR3.REVAND should be set to 0b0000.
This field reads as an IMPLEMENTATION DEFINED value.
JEDEC-assigned JEP106 implementer code is used. This bit is RAO.
This bit reads as one.
IMPLEMENTATION DEFINED.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and this field together form the JEDEC-assigned JEP106 identification code for the designer of the component.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
This field reads as an IMPLEMENTATION DEFINED value.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_2 | JEDEC | DES_1 |
Reserved, RES0.
IMPLEMENTATION DEFINED.Part number, bits [15:12]
PartThe part number, bitsis [15:12].selected by the designer of the component. It is stored in this field,ERRPIDR1.PART_1 and ERRPIDR0.PART_0.
The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number:
This field reads as an IMPLEMENTATION DEFINED value.
JEDEC-assigned JEP106 implementer code is used. This bit is RAO.
This bit reads as one.
IMPLEMENTATION DEFINED.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and this field together form the JEDEC-assigned JEP106 identification code for the designer of the component.
Designer, JEP106 identification code, bits [6:4]. ERRPIDR1.DES_0 and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
This field reads as an IMPLEMENTATION DEFINED value.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
Component | Offset |
---|---|
RAS | 0xFE8 |
Accesses on this interface are RO.
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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