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The DBGBVR<n> characteristics are:
Holds a value for use in breakpoint matching, either the virtual address of an instruction or a context ID. Forms breakpoint n together with control register DBGBCR<n>. If EL2 is implemented and this breakpoint supports Context matching, DBGBVR<n> can be associated with a Breakpoint Extended Value Register DBGBXVR<n> for VMID matching.
AArch32 System register DBGBVR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGBVR<n>_EL1[31:0] .
AArch32 System register DBGBVR<n> bits [31:0] are architecturally mapped to External register DBGBVR<n>_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DBGBVR<n> are UNKNOWN.
If breakpoint n is not implemented then accesses to this register are UNDEFINED.
Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into an Exception level that is using AArch32.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.
How this register is interpreted depends on the value of DBGBCR<n>.BT.
For other values of DBGBCR<n>.BT, this register is RES0.
Some breakpoints might not support Context ID comparison. For more information, see the description of the DBGDIDR.CTX_CMPs field.
The DBGBVR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA[31:2] | RES0 |
Bits[31:2] of the address value for comparison.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ContextID |
Context ID value for comparison.
The value is compared against CONTEXTIDR_EL2 when all of the following are true:
Otherwise, the value is compared against CONTEXTIDR.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ContextID |
Context ID value for comparison against CONTEXTIDR.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ContextID |
Context ID value for comparison against CONTEXTIDR.
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)];
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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