DBGBVR<n>, Debug Breakpoint Value Registers, n = 0 - 15

The DBGBVR<n> characteristics are:

Purpose

Holds a value for use in breakpoint matching, either the virtual address of an instruction or a context ID. Forms breakpoint n together with control register DBGBCR<n>. If EL2 is implemented and this breakpoint supports Context matching, DBGBVR<n> can be associated with a Breakpoint Extended Value Register DBGBXVR<n> for VMID matching.

Configuration

AArch32 System register DBGBVR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGBVR<n>_EL1[31:0] .

AArch32 System register DBGBVR<n> bits [31:0] are architecturally mapped to External register DBGBVR<n>_EL1[31:0] .

If breakpoint n is not implemented then accesses to this register are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

How this register is interpreted depends on the value of DBGBCR<n>.BT.

For other values of DBGBCR<n>.BT, this register is RES0.

Some breakpoints might not support Context ID comparison. For more information, see the description of the DBGDIDR.CTX_CMPs field.

Field descriptions

The DBGBVR<n> bit assignments are:

When DBGBCR<n>.BT == 0b0x0x:

313029282726252423222120191817161514131211109876543210
VA[31:2]RES0

VA[31:2], bits [31:2]

Bits[31:2] of the address value for comparison.

The following resets apply:

Bits [1:0]

Reserved, RES0.

When DBGBCR<n>.BT == 0b001x:

313029282726252423222120191817161514131211109876543210
ContextID

ContextID, bits [31:0]

Context ID value for comparison.

The value is compared against CONTEXTIDR_EL2 when all of the following are true:

Otherwise, the value is compared against CONTEXTIDR.

The following resets apply:

When DBGBCR<n>.BT == 0b101x and HaveEL(EL2):

313029282726252423222120191817161514131211109876543210
ContextID

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR.

The following resets apply:

When DBGBCR<n>.BT == 0bx11x, HaveEL(EL2) and ARMv8.1-VHE is implemented:

313029282726252423222120191817161514131211109876543210
ContextID

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR.

The following resets apply:

Accessing the DBGBVR<n>

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11100b0000b0000n[3:0]0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGBVR[UInt(CRm<3:0>)];

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11100b0000b0000n[3:0]0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t]; elsif PSTATE.EL == EL3 then if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBVR[UInt(CRm<3:0>)] = R[t];




27/09/2019 18:48; 6134483bd14dc8c12a99c984cbfe3431cc1c9707

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