The EDCIDR1 characteristics are:
Provides information to identify an external debug component.
For more information see 'About the Component identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).
Implementation of this register is OPTIONAL.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
EDCIDR1 is a 32-bit register.
The EDCIDR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class. Debug component.
Reads as 0b1001.
Preamble.
Reads as 0b0000.
Component | Offset | Instance |
---|---|---|
Debug | 0xFF4 | EDCIDR1 |
This interface is accessible as follows:
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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