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The ITLBIASID characteristics are:
Invalidate all cached copies of translation table entries from instruction TLBs that meet the following requirements:
From the entries that match these requirements, the entries that are invalidated are required for the following translation regime:
The invalidation only applies to the PE that executes this System instruction.
Arm deprecates the use of this System instruction. It is only provided for backwards compatibility with earlier versions of the Arm architecture.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ITLBIASID are UNKNOWN.
ITLBIASID is a 32-bit System instruction.
The ITLBIASID input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ASID |
Reserved, RES0.
ASID value to match. Any TLB entries for non-global pages that match the ASID values will be affected by this System instruction.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1000 | 0b0101 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.TTLB == '1' then
AArch32.TakeHypTrapException(0x03);
else
ITLBIASID(R[t]);
elsif PSTATE.EL == EL2 then
ITLBIASID(R[t]);
elsif PSTATE.EL == EL3 then
ITLBIASID(R[t]);
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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