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The DBGDSAR characteristics are:
In earlier versions of the Arm Architecture, this register defines the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the PE. Armv8 deprecates any use of this register.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DBGDSAR are UNKNOWN.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDSAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, bits [31:0] are read.
The DBGDSAR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RAZ | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RAZ.
This field indicates whether the debug self address offset is valid. For ARMv8, this field is always 0b00, the offset is not valid.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0010 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x05);
elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDRA> != '00') then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDRA> != '00') then
AArch32.TakeHypTrapException(0x05);
else
return DBGDSAR<31:0>;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDRA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDRA> != '00' then
AArch32.TakeHypTrapException(0x05);
else
return DBGDSAR<31:0>;
elsif PSTATE.EL == EL2 then
return DBGDSAR<31:0>;
elsif PSTATE.EL == EL3 then
return DBGDSAR<31:0>;
coproc | CRm | opc1 |
---|---|---|
0b1110 | 0b0010 | 0b0000 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x0C);
elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDRA> != '00') then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDRA> != '00') then
AArch32.TakeHypTrapException(0x0C);
else
return DBGDSAR;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDRA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDRA> != '00' then
AArch32.TakeHypTrapException(0x0C);
else
return DBGDSAR;
elsif PSTATE.EL == EL2 then
return DBGDSAR;
elsif PSTATE.EL == EL3 then
return DBGDSAR;
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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