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The AMEVCNTR1<n> characteristics are:
Provides access to the auxiliary activity monitor event counters.
AArch32 System register AMEVCNTR1<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVCNTR1<n>_EL0[63:0] .
AArch32 System register AMEVCNTR1<n> bits [63:0] are architecturally mapped to External register AMEVCNTR1<n>[63:0] .
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR1<n> are UNDEFINED.
Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into an Exception level that is using AArch32.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.
AMEVCNTR1<n> is a 64-bit register.
The AMEVCNTR1<n> bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ACNT | |||||||||||||||||||||||||||||||
ACNT | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Auxiliary activity monitor event counter n.
Value of auxiliary activity monitor event counter n, where n is the number of this register and is a number from 0 to 15.
If ARMv8.6-AMU is implemented, HCR_EL2.AMVOFFEN is 1, SCR_EL3.AMVOFFEN is 1, HCR_EL2.{E2H, TGE} is not {1,1}, EL2 is using AArch64 and is implemented in the current Security state, and AMCR_EL0.CG1RZ is 0, reads to these registers at EL0 or EL1 return (PCount<63:0> - AMEVCNTVOFF1<n>_EL2<63:0>).
PCount is the physical count returned when AMEVCNTR1<n> is read from EL2 or EL3.
If the counter is enabled, writes to this register have UNPREDICTABLE results.
On a Cold reset, this field resets to 0.
If <n> is greater than or equal to the number of auxiliary activity monitor event counters, reads and writes of AMEVCNTR1<n> are UNDEFINEDCONSTRAINED UNPREDICTABLE., and the following behaviors are permitted:
AMCGCR.CG1NC identifies the number of auxiliary activity monitor event counters.
Accesses to this register use the following encodings:
coproc | CRm | opc1 |
---|---|---|
0b1111 | 0b010:n[3] |
if CRm == '0100'100 then
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x04);
elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T4 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T4 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HAFGRTR_EL2.AMEVCNTR1<n>_EL0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T4 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T4 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !IsHighestEL(PSTATE.EL) && !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif !IsHighestEL(PSTATE.EL) && HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !IsHighestEL(PSTATE.EL) && !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif !IsHighestEL(PSTATE.EL) && HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL3 then
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif CRm == '0101'101 then
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x04);
elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T5 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HAFGRTR_EL2.AMEVCNTR1<n>_EL0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !IsHighestEL(PSTATE.EL) && !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif !IsHighestEL(PSTATE.EL) && HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
elsif !IsHighestEL(PSTATE.EL) && !HighestELUsingAArch32() && AMCR_EL0.CG1RZ == '1' then
Zeros();
elsif !IsHighestEL(PSTATE.EL) && HighestELUsingAArch32() && AMCR.CG1RZ == '1' then
Zeros();
else
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
elsif PSTATE.EL == EL3 then
return AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)];
else
UNDEFINED;
coproc | CRm | opc1 |
---|---|---|
0b1111 | 0b010:n[3] |
if CRm == 100 then
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '01000' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x04);
elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T4 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T4 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elsif PSTATE.EL == EL1 then
if IsHighestELEL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T4 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T4 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elseelsif PSTATE.EL == EL3 then
UNDEFINED;AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elsif CRm == '0101'101 then
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x04);
elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T5 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then
AArch32.TakeHypTrapException(0x04);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x04);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then
AArch32.TakeHypTrapException(0x04);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elsif IsHighestELPSTATE.EL == EL2 then
if HaveEL(PSTATE.ELEL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x04);
else
AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
elseelsif PSTATE.EL == EL3 then
UNDEFINED;AMEVCNTR1[UInt(CRm<0>:opc1<2:0>)] = R[t2]:R[t];
else
UNDEFINED;
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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