System Register XML
for Armv8.6
(2019-12)
13th December 2019
1. Introduction
This is the 2019-12 release
of the System Register XML for Armv8.6, describing:
-
The AArch64 and AArch32 views of the System registers
(including Debug, PMU, Generic Timer, and GIC).
-
The AArch32 and AArch32 system control operations.
-
The memory-mapped Debug, CTI, PMU, GIC, and Generic Timer registers.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "System Register XML for Armv8.6".
- The version, "2019-12".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
2. Contents
3. Release notes
Change history
-
The behavior of GCR_EL1.RRND has been relaxed.
-
The accessibility pseudocode of the following registers have been updated:
- AArch64 registers: AMUSERENR_EL0, CNTV_CTL_EL0, CNTV_CVAL_EL0, CNTV_TVAL_EL0, PMUSERENR_EL0, RMR_EL2, RVBAR_EL2, VMPIDR_EL2, VPIDR_EL2
- AArch32 registers: AMEVCNTR1<n>, DBGDRAR, DBGDSAR, DBGDAUTHSTATUS, ICC_AP0RN, ICC_AP1RN, ICC_ASGI1R, ICC_BPR0, MVBAR, PMUSERENR, RVBAR
- AArch32 System instructions: DTLBIALL, DTLBIASID, DTLBIMVA, DCCIMVAC, DCCMVAC, DCIMVAC, DCCISW, DCCSW, DCISW, DCCMVAU, ICIALLU, ICIALLUIS, ICIMVAU
-
The RAS System Architecture v1.0 has been updated to permit the implementation of ERR<n>MISC2 and ERR<n>MISC3.
-
Some registers incorrectly had a statement about the register not having any effect if EL2 is not enabled. The text is hence deleted in the following registers:
- DBGBVCR32_EL2, FPEXC32_EL2, IFSR32_EL2.
-
The description of the DC CGVAP has been updated to have the correct reference to DC CGDVAP.
-
The description of the VMID fields in the following registers have been corrected to clarify the VMID size:
- AArch64 registers: DBGBVR_EL0
- AArch32 registers: DBGBXVR
-
The RNDR and RNDRRS register descriptions incorrectly state that if a random number is not returned in a
reasonable time, the value returned is UNKNOWN. This has been corrected to return 0.
-
The following registers were missing the check for the CNTHCTL_EL2.EL1TCT trap in their accessibility pseudocode:
AArch64: CNTHV_CTL_EL2,CNTHV_CVAL_EL2, CNTHV_TVAL_EL2, CNTHVS_CTL_EL2, CNTHVS_CVAL_EL2, CNTHVS_TVAL_EL2.
AArch32: CNTHV_CTL, CNTHV_CVAL, CNTHV_TVAL, CNTHVS_CTL, CNTHVS_CVAL, CNTHVS_TVAL.
-
The behavior of the MPAM1_EL1.FORCED_NS field has been tightened to be read-only.
-
Many simple clarifications and corrections are also present,
but are too small to be listed here. These can be seen in the
Change Markup PDF provided.
Known issues
-
MPAMVPM7_EL2, MPAM Virtual PARTID Mapping Register 7
The Configuration states that:
"This register is present only when MPAM is implemented, MPAMIDR_EL1.HAS_HCR == 1 and MPAMIDR_EL1.VPMR_MAX == 111."
All values given here are in binary. The previous release used decimal representation, MPAMIDR_EL1.VPMR_MAX == 7.
-
The memory-mapped Generic Timer register descriptions have
incorrect information, and so must not be relied upon.
This will be corrected in a future release. The definitive
source for these registers is the Arm Architecture Reference
Manual Armv8, for Armv8-A architecture profile.
-
There are differences in the GIC registers in this XML package
when compared to the GIC register descriptions in the Generic
Interrupt Controller Architecture Specification document. The
definitive source for these registers is the document, and
there will be corrections to these registers in the next
release.
-
The reset information in the 'Configuration' section of some
register descriptions have incorrect information, and must
not be relied upon. Please refer to the field descriptions
for the correct reset information.
-
Tightening of the UNPREDICTABLE behavior of the uninmplemented AMU counter, event type, and set/clear registers.
-
HCDR.TDA traps missing in the AArch32 debug registers
Potential upcoming changes
We are looking in improvements to the information that is
provided in the XML. In some cases these changes may impact
users. Here is a list of areas where we may make changes in a
future release:
-
The instruction encoding tables currently present values as
binary values, with the prefix "0b". We are considering
whether these values are better represented in a syntax
compatible with pseudocode.
-
How the read/write behaviors in register fields are identified
is being investigated.
-
The reset information in the 'Configuration' section of some
register descriptions have incorrect information, and must
not be relied upon. Please refer to the field descriptions
for the correct reset information. The information in the
'Configuration' section will be removed in a future release.
4. Documentation
General
A description within the XML contains the following sections:
- Purpose
-
A short description of the purpose of the register in the
Armv8 Architecture.
- Configuration
-
How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here.
- Attributes
-
The size of the register. For registers where the layouts of
the fields differ based on configuration, or other state
within the PE, this section also summarizes the different
layouts.
- Field descriptions
-
The register diagram, and a description of the behavior of
each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Accessing the ...
-
The address or offset of the register in the memory map, and
the accessibility.
System registers
A System register description also contains an "Accessing the
..." section, that includes:
-
The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
-
Pseudocode that describes the execution of all instructions
used to access the register, including information about
traps and enables that apply upon that access.
-
For some System registers, additional text is provided which
gives extra information regarding the access to the
register.
-
The accessibility pseudocode for a register assumes that
that register is implemented and that all features which
affects its accesses are implemented. In most cases, the
behavior upon access to a register is determined in part or
in whole by the Exception level at which it is accessed.