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PMCFGR, Performance Monitors Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU-specific configuration data.

Configuration

PMCFGR is in the Core power domain.

Attributes

PMCFGR is a 32-bit register.

Field descriptions

The PMCFGR bit assignments are:

313029282726252423222120191817161514131211109876543210
NCGRES0UENWTNAEXCCDCCSIZEN

NCG, bits [31:28]

This feature is not supported, so this field is RAZ.

Bits [27:20]

Reserved, RES0.

UEN, bit [19]

User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.

WT, bit [18]

This feature is not supported, so this bit is RAZ.

NA, bit [17]

This feature is not supported, so this bit is RAZ.

EX, bit [16]

Export supported. Value is IMPLEMENTATION DEFINED.

EXMeaning
0b0

PMCR_EL0.X is RES0.

0b1

PMCR_EL0.X is read/write.

CCD, bit [15]

Cycle counter has prescale.

Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL, and RAZ otherwise.

This is RES1 if AArch32 is supported at any Exception level, and RAZ otherwise.

CCDMeaning
0b0

PMCR_EL0.D is RES0.

0b1

PMCR_EL0.D is read/write.

CC, bit [14]

Dedicated cycle counter (counter 31) supported. This bit is RAO.

SIZE, bits [13:8]

Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.

From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.

This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.

N, bits [7:0]

Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31.

NMeaning
0x00

Only PMCCNTR_EL0 implemented.

0x01

PMCCNTR_EL0 plus one event counter implemented.

and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented.

Accessing the PMCFGR

Note

AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

PMCFGR can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xE00PMCFGR

This interface is accessible as follows:




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Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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