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RMR_EL2, Reset Management Register (EL2)

The RMR_EL2 characteristics are:

Purpose

WhenIf EL2 is the highest implemented Exception level and this register is implemented:

Configuration

AArch64 System register RMR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HRMR[31:0] when the highest implemented Exception level is EL2.IsHighestEL(EL2).

ThisOnly registerimplemented isif presentEL2 only whenis the highest implemented Exception levellevel. isIn EL2. Otherwise,this direct accesses to RMR_EL2 arecase: UNDEFINED.

When EL2 is the highest implemented Exception level:

This register has no effect if EL2 is not enabled in the current Security state.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

RMR_EL2 is a 64-bit register.

Field descriptions

The RMR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0RRAA64
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

RR, bit [1]

Reset Request. Setting this bit to 1 requests a Warm reset.

This field resets to 0.

AA64, bit [0]

When AArch32 is supported at any Exception level:

When EL2 can use AArch32, determines which Execution state the PE boots into after a Warm reset:

AA64Meaning
0b0

AArch32.

0b1

AArch64.

On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.

If EL2 cancannot only use AArch64 state,AArch32 this bit is RAO/WI.

When implemented as a RW field, this field resets to 1 on a Cold reset.


Otherwise:

Reserved, RAO/WI.

Accessing the RMR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, RMR_EL2

op0op1CRnCRmop2
0b110b1000b11000b00000b010

if PSTATE.EL == EL1 && EL2Enabled() && IsHighestEL(EL2) && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif PSTATE.EL == EL2 && IsHighestEL(EL2) then return RMR_EL2; else UNDEFINED;

MSR RMR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b11000b00000b010

if PSTATE.EL == EL1 && EL2Enabled() && IsHighestEL(EL2) && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif PSTATE.EL == EL2 && IsHighestEL(EL2) then RMR_EL2 = X[t]; else UNDEFINED;




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

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