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The CTIDEVCTL characteristics are:
Provides target-specific device controls
CTIDEVCTL is in the Debug power domain.
Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
This register is present only when ARMv8.3-DoPD is implemented. Otherwise, direct accesses to CTIDEVCTL are RES0.
CTIDEVCTL is a 32-bit register.
The CTIDEVCTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | RCE | OSUCE |
Reserved, RES0.
Reset Catch Enable.
RCE | Meaning |
---|---|
0b0 | Reset Catch debug event disabled. |
0b1 | Reset Catch debug event enabled. |
The following resets apply:
On a External debug reset, this field resets to 0.
On a Cold reset, the value of this field is unchanged.
On an External debug reset, this field resets to 0.
On a Warm reset, the value of this field is unchanged.
OS Unlock Catch Enable
OSUCE | Meaning |
---|---|
0b0 | OS Unlock Catch debug event disabled. |
0b1 | OS Unlock Catch debug event enabled. |
The following resets apply:
On a External debug reset, this field resets to 0.
On a Cold reset, the value of this field is unchanged.
On an External debug reset, this field resets to 0.
On a Warm reset, the value of this field is unchanged.
Component | Offset | Instance |
---|---|---|
CTI | 0x150 | CTIDEVCTL |
This interface is accessible as follows:
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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