The HFGRTR_EL2 characteristics are:
Provides controls for traps of MRS and MRC reads of System registers.
This register is present only when ARMv8.6-FGT is implemented. Otherwise, direct accesses to HFGRTR_EL2 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
HFGRTR_EL2 is a 64-bit register.
The HFGRTR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | ERXADDR_EL1 | ERXPFGCDN_EL1 | ERXPFGCTL_EL1 | ERXPFGF_EL1 | ERXMISCn_EL1 | ERXSTATUS_EL1 | ERXCTLR_EL1 | ERXFR_EL1 | ERRSELR_EL1 | ERRIDR_EL1 | ICC_IGRPENn_EL1 | VBAR_EL1 | TTBR1_EL1 | TTBR0_EL1 | TPIDR_EL0 | TPIDRRO_EL0 | TPIDR_EL1 | TCR_EL1 | |||||||||||||
SCXTNUM_EL0 | SCXTNUM_EL1 | SCTLR_EL1 | REVIDR_EL1 | PAR_EL1 | MPIDR_EL1 | MIDR_EL1 | MAIR_EL1 | LORSA_EL1 | LORN_EL1 | LORID_EL1 | LOREA_EL1 | LORC_EL1 | ISR_EL1 | FAR_EL1 | ESR_EL1 | DCZID_EL0 | CTR_EL0 | CSSELR_EL1 | CPACR_EL1 | CONTEXTIDR_EL1 | CLIDR_EL1 | CCSIDR_EL1 | APIBKey | APIAKey | APGAKey | APDBKey | APDAKey | AMAIR_EL1 | AIDR_EL1 | AFSR1_EL1 | AFSR0_EL1 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Trap MRS reads of ERXADDR_EL1 at EL1 using AArch64 to EL2.
ERXADDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXADDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXADDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 to EL2.
ERXPFGCDN_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGCDN_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 to EL2.
ERXPFGCTL_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGCTL_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXPFGF_EL1 at EL1 using AArch64 to EL2.
ERXPFGF_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGF_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXPFGF_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXMISC<n>_EL1 at EL1 using AArch64 to EL2.
ERXMISCn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXMISC<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXMISC<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 to EL2.
ERXSTATUS_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXSTATUS_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXCTLR_EL1 at EL1 using AArch64 to EL2.
ERXCTLR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXCTLR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXCTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERXFR_EL1 at EL1 using AArch64 to EL2.
ERXFR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXFR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERXFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERRSELR_EL1 at EL1 using AArch64 to EL2.
ERRSELR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERRSELR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERRSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ERRIDR_EL1 at EL1 using AArch64 to EL2.
ERRIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERRIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ERRIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 to EL2.
ICC_IGRPENn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ICC_IGRPEN<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of VBAR_EL1 at EL1 using AArch64 to EL2.
VBAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of VBAR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of VBAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TTBR1_EL1 at EL1 using AArch64 to EL2.
TTBR1_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TTBR1_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TTBR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TTBR0_EL1 at EL1 using AArch64 to EL2.
TTBR0_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TTBR0_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TTBR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 when EL1 is using AArch64 to EL2.
TPIDR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 when EL1 is using AArch64 to EL2.
TPIDRRO_EL0 | Meaning |
---|---|
0b0 |
MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TPIDR_EL1 at EL1 using AArch64 to EL2.
TPIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TPIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of TCR_EL1 at EL1 using AArch64 to EL2.
TCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 to EL2.
SCXTNUM_EL0 | Meaning |
---|---|
0b0 |
MRS reads of SCXTNUM_EL0 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of SCXTNUM_EL1 at EL1 using AArch64 to EL2.
SCXTNUM_EL1 | Meaning |
---|---|
0b0 |
MRS reads of SCXTNUM_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of SCXTNUM_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of SCTLR_EL1 at EL1 using AArch64 to EL2.
SCTLR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of SCTLR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of SCTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of REVIDR_EL1 at EL1 using AArch64 to EL2.
REVIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of REVIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of REVIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of PAR_EL1 at EL1 using AArch64 to EL2.
PAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PAR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of MPIDR_EL1 at EL1 using AArch64 to EL2.
MPIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MPIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of MPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of MIDR_EL1 at EL1 using AArch64 to EL2.
MIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of MIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of MAIR_EL1 at EL1 using AArch64 to EL2.
MAIR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MAIR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of MAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of LORSA_EL1 at EL1 using AArch64 to EL2.
LORSA_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORSA_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of LORSA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of LORN_EL1 at EL1 using AArch64 to EL2.
LORN_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORN_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of LORN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of LORID_EL1 at EL1 using AArch64 to EL2.
LORID_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORID_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of LORID_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of LOREA_EL1 at EL1 using AArch64 to EL2.
LOREA_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LOREA_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of LOREA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of LORC_EL1 at EL1 using AArch64 to EL2.
LORC_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORC_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of LORC_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of ISR_EL1 at EL1 using AArch64 to EL2.
ISR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ISR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ISR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of FAR_EL1 at EL1 using AArch64 to EL2.
FAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of FAR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of FAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of ESR_EL1 at EL1 using AArch64 to EL2.
ESR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ESR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of ESR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 to EL2.
DCZID_EL0 | Meaning |
---|---|
0b0 |
MRS reads of DCZID_EL0 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of CTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
CTR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of CTR at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CSSELR_EL1 at EL1 using AArch64 to EL2.
CSSELR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CSSELR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of CSSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CPACR_EL1 at EL1 using AArch64 to EL2.
CPACR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CPACR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of CPACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 to EL2.
CONTEXTIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CONTEXTIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CLIDR_EL1 at EL1 using AArch64 to EL2.
CLIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CLIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of CLIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of CCSIDR_EL1 at EL1 using AArch64 to EL2.
CCSIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CCSIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of CCSIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APIBKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APIAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APGAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APDBKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APDAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of AMAIR_EL1 at EL1 using AArch64 to EL2.
AMAIR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AMAIR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of AMAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AIDR_EL1 at EL1 using AArch64 to EL2.
AIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of AIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AFSR1_EL1 at EL1 using AArch64 to EL2.
AFSR1_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AFSR1_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of AFSR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of AFSR0_EL1 at EL1 using AArch64 to EL2.
AFSR0_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AFSR0_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of AFSR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1B8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return HFGRTR_EL2; elsif PSTATE.EL == EL3 then return HFGRTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1B8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else HFGRTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HFGRTR_EL2 = X[t];
27/09/2019 18:48; 6134483bd14dc8c12a99c984cbfe3431cc1c9707
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