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The DBGVCR characteristics are:
Controls Vector Catch debug events.
AArch32 System register DBGVCR bits [31:0] are architecturally mapped to AArch64 System register DBGVCR32_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DBGVCR are UNKNOWN.
This register is required in all implementations.
RW fields in this register reset to architecturally UNKNOWN values.
DBGVCR is a 32-bit register.
The DBGVCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NSF | NSI | RES0 | NSD | NSP | NSS | NSU | RES0 | MF | MI | RES0 | MD | MP | MS | RES0 | SF | SI | RES0 | SD | SP | SS | SU | RES0 |
FIQ vector catch enable in Non-secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable in Non-secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable in Non-secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable in Non-secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Supervisor Call (SVC) vector catch enable in Non-secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Undefined Instruction vector catch enable in Non-secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FIQ vector catch enable in Monitor mode.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable in Monitor mode.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable in Monitor mode.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable in Monitor mode.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Secure Monitor Call (SMC) vector catch enable in Monitor mode.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FIQ vector catch enable in Secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable in Secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable in Secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable in Secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Supervisor Call (SVC) vector catch enable in Secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Undefined Instruction vector catch enable in Secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NSF | NSI | RES0 | NSD | NSP | NSS | NSU | RES0 | SF | SI | RES0 | SD | SP | SS | SU | RES0 |
FIQ vector catch enable in Non-secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable in Non-secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable in Non-secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable in Non-secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Supervisor Call (SVC) vector catch enable in Non-secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Undefined Instruction vector catch enable in Non-secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FIQ vector catch enable in Secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable in Secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable in Secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable in Secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Supervisor Call (SVC) vector catch enable in Secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Undefined Instruction vector catch enable in Secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | F | I | RES0 | D | P | S | U | RES0 |
Reserved, RES0.
FIQ vector catch enable.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ vector catch enable.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Abort vector catch enable.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Prefetch Abort vector catch enable.
The exception vector offset 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Supervisor Call (SVC) vector catch enable.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Undefined Instruction vector catch enable.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGVCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGVCR; elsif PSTATE.EL == EL3 then return DBGVCR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL3 then DBGVCR = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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