The ERR<n>STATUS characteristics are:
Contains status information for the error record, including:
Within this register:
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>STATUS are RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>STATUS, writing zero must always be supported to return the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.
ERR<n>STATUS is a 64-bit register.
The ERR<n>STATUS bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
AV | V | UE | ER | OF | MV | CE | DE | PN | UET | CI | RES0 | IERR | SERR | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Address Valid.
AV | Meaning |
---|---|
0b0 |
ERR<n>ADDR not valid. |
0b1 |
ERR<n>ADDR contains an address associated with the highest priority error recorded by this record. |
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Reserved, RES0.
Status Register Valid.
V | Meaning |
---|---|
0b0 |
ERR<n>STATUS not valid. |
0b1 |
ERR<n>STATUS valid. At least one error has been recorded. |
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Uncorrected Error.
UE | Meaning |
---|---|
0b0 |
No errors have been detected, or all detected errors have been either corrected or deferred. |
0b1 |
At least one detected error was not corrected and not deferred. |
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Error Reported.
ER | Meaning |
---|---|
0b0 |
No in-band error (External Abort) reported. |
0b1 |
An External Abort was signaled by the node to the master making the access or other transaction. This can be because any of the following are true:
|
It is IMPLEMENTATION DEFINED whether this bit can be set to 0b1 by a Deferred error.
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if any of the following are true:
This bit is read/write-one-to-clear.
An External Abort signaled by the node might be masked and not generate any exception.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Overflow.
Indicates that multiple errors have been detected. This bit is set to 0b1 when one of the following occurs:
Otherwise, this bit is unchanged when an error is recorded.
If a Corrected error counter is implemented:
OF | Meaning |
---|---|
0b0 |
Since this bit was last cleared to zero, no error syndrome has been discarded and, if a Corrected error counter is implemented, it has not overflowed. |
0b1 |
Since this bit was last cleared to zero, at least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed. |
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Miscellaneous Registers Valid.
MV | Meaning |
---|---|
0b0 |
ERR<n>MISC<m> not valid. |
0b1 |
The IMPLEMENTATION DEFINED contents of the ERR<n>MISC<m> registers contains additional information for an error recorded by this record. |
This bit is read/write-one-to-clear.
If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Reserved, RES0.
Corrected Error.
CE | Meaning |
---|---|
0b00 |
No errors were corrected. |
0b01 |
At least one transient error was corrected. |
0b10 |
At least one error was corrected. |
0b11 |
At least one persistent error was corrected. |
The mechanism by which a node detects whether a correctable error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when an error is corrected.
When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then software must write ones to this field to clear this field to zero.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Deferred Error.
DE | Meaning |
---|---|
0b0 |
No errors were deferred. |
0b1 |
At least one error was not corrected and deferred. |
Support for deferring errors is IMPLEMENTATION DEFINED.
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Poison.
PN | Meaning |
---|---|
0b0 |
Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC). Note
If a producer node detects a corrupt value and defers the error by producing a poison value, then this bit is set to 0b0 at the producer node. |
0b1 |
Uncorrected error or Deferred error recorded because a poison value was detected. Note
This might only be an indication of poison, because, in some EDC schemes, a poison value is encoded as an unlikely form of corrupt data, meaning it is possible to mistake a corrupt value as a poison value. |
It is IMPLEMENTATION DEFINED whether a node can distinguish a poison value from a corrupt value.
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if any of the following are true:
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error.
UET | Meaning |
---|---|
0b00 |
Uncorrected error, Uncontainable error (UC). |
0b01 |
Uncorrected error, Unrecoverable error (UEU). |
0b10 |
Uncorrected error, Latent or Restartable error (UEO). |
0b11 |
Uncorrected error, Signaled or Recoverable error (UER). |
When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then software must write ones to this field to clear this field to zero.
This field is not valid and reads UNKNOWN if any of the following are true:
This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.
Software might use the information in the error record registers to determine what recovery is necessary.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Critical Error. Indicates whether a critical error condition has been recorded.
CI | Meaning |
---|---|
0b0 |
No critical error condition. |
0b1 |
Critical error condition. |
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
IMPLEMENTATION DEFINED error code. Used with any primary error code SERR value. Further IMPLEMENTATION DEFINED information can be placed in the MISC registers.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry.
SERR | Meaning |
---|---|
0x00 |
No error. |
0x01 |
IMPLEMENTATION DEFINED error. |
0x02 |
Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer. |
0x03 |
IMPLEMENTATION DEFINED pin. For example, nSEI pin. |
0x04 |
Assertion failure. For example, consistency failure. |
0x05 |
Error detected on internal data path. For example, parity on ALU result. |
0x06 |
Data value from associative memory. For example, ECC error on cache data. |
0x07 |
Address/control value from associative memory. For example, ECC error on cache tag. |
0x08 |
Data value from a TLB. For example, ECC error on TLB data. |
0x09 |
Address/control value from a TLB. For example, ECC error on TLB tag. |
0x0A |
Data value from producer. For example, parity error on write data bus. |
0x0B |
Address/control value from producer. For example, parity error on address bus. |
0x0C |
Data value from (non-associative) external memory. For example, ECC error in SDRAM. |
0x0D |
Illegal address (software fault). For example, access to unpopulated memory. |
0x0E |
Illegal access (software fault). For example, byte write to word register. |
0x0F |
Illegal state (software fault). For example, device not ready. |
0x10 |
Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, and SVE registers are data registers. |
0x11 |
Internal control register. For example, Parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, and SVE registers are control registers. |
0x12 |
Error response from slave. For example, error response from cache write-back. |
0x13 |
External timeout. For example, timeout on interaction with another node. |
0x14 |
Internal timeout. For example, timeout on interface within the node. |
0x15 |
Deferred error from slave not supported at master. For example, poisoned data received from a slave by a master that cannot defer the error further. |
0x16 |
Deferred error from master not supported at slave. For example, poisoned data received from a master by a slave that cannot defer the error further. |
0x17 |
Deferred error from slave passed through. For example, poisoned data received from a slave and returned to a master. |
0x18 |
Deferred error from master passed through. For example, poisoned data received from a master and deferred to a slave. |
0x19 |
Error recorded by PCIe error logs. Indicates that the node has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe. |
All other values are reserved.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
AV | V | UE | ER | OF | MV | CE | DE | PN | UET | RES0 | IERR | SERR | |||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Address Valid.
AV | Meaning |
---|---|
0b0 |
ERR<n>ADDR not valid. |
0b1 |
ERR<n>ADDR contains an address associated with the highest priority error recorded by this record. |
This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Reserved, RES0.
Status Register Valid.
V | Meaning |
---|---|
0b0 |
ERR<n>STATUS not valid. |
0b1 |
ERR<n>STATUS valid. At least one error has been recorded. |
This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and is not being cleared to 0b0 in the same write.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Uncorrected Error.
UE | Meaning |
---|---|
0b0 |
No errors have been detected, or all detected errors have been either corrected or deferred. |
0b1 |
At least one detected error was not corrected and not deferred. |
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This bit ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Error Reported.
ER | Meaning |
---|---|
0b0 |
No in-band error (External Abort) reported. |
0b1 |
An External Abort was signaled by the node to the master making the access or other transaction. This can be because any of the following are true:
|
It is IMPLEMENTATION DEFINED whether this bit can be set to 0b1 by a Deferred error.
If this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero, when any of:
This bit is not valid and reads UNKNOWN if any of the following are true:
This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
This bit is read/write-one-to-clear.
An External Abort signaled by the node might be masked and not generate any exception.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Overflow.
Indicates that multiple errors have been detected. This bit is set to 0b1 when one of the following occurs:
It is IMPLEMENTATION DEFINED whether this bit is set to 0b1 when one of the following occurs:
It is IMPLEMENTATION DEFINED whether this bit is cleared to 0b0 when one of the following occurs:
The IMPLEMENTATION DEFINED clearing of this bit might also depend on the value of the other error status bits.
If a Corrected error counter is implemented:
OF | Meaning |
---|---|
0b0 |
If ERR<n>STATUS.UE == 0b1, then no error syndrome for an Uncorrected error has been discarded. If ERR<n>STATUS.UE == 0b0 and ERR<n>STATUS.DE == 0b1, then no error syndrome for a Deferred error has been discarded. If ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, and a Corrected error counter is implemented, then the counter has not overflowed. If ERR<n>STATUS.UE == 0b0, ERR<n>STATUS.DE == 0b0, ERR<n>STATUS.CE != 0b00, and no Corrected error counter is implemented, then no error syndrome for a Corrected error has been discarded. Note
This bit might have been set to 0b1 when an error syndrome was discarded and later cleared to 0b0 when a higher priority syndrome was recorded. |
0b1 |
At least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed. |
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Miscellaneous Registers Valid.
MV | Meaning |
---|---|
0b0 |
ERR<n>MISC<m> not valid. |
0b1 |
The IMPLEMENTATION DEFINED contents of the ERR<n>MISC<m> registers contains additional information for an error recorded by this record. |
This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
This bit is read/write-one-to-clear.
If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to 0.
Reserved, RES0.
Corrected Error.
CE | Meaning |
---|---|
0b00 |
No errors were corrected. |
0b01 |
At least one transient error was corrected. |
0b10 |
At least one error was corrected. |
0b11 |
At least one persistent error was corrected. |
The mechanism by which a node detects whether a correctable error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when an error is corrected.
When clearing ERR<n>STATUS.V to 0b0, if this field is nonzero, then software must write ones to this field to clear this field to zero.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This field ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.
This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Deferred Error.
DE | Meaning |
---|---|
0b0 |
No errors were deferred. |
0b1 |
At least one error was not corrected and deferred. |
Support for deferring errors is IMPLEMENTATION DEFINED.
When clearing ERR<n>STATUS.V to 0b0, if this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero.
This bit is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This bit ignores writes if ERR<n>STATUS.OF == 0b1 and is not being cleared to 0b0 in the same write.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Poison.
PN | Meaning |
---|---|
0b0 |
Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC). Note
If a producer node detects a corrupt value and defers the error by producing a poison value, then this bit is set to 0b0 at the producer node. |
0b1 |
Uncorrected error or Deferred error recorded because a poison value was detected. Note
This might only be an indication of poison, because, in some EDC schemes, a poison value is encoded as an unlikely form of corrupt data, meaning it is possible to mistake a corrupt value as a poison value. |
It is IMPLEMENTATION DEFINED whether a node can distinguish a poison value from a corrupt value.
If this bit is nonzero, then software must write 0b1 to this bit to clear this bit to zero, when any of:
This bit is not valid and reads UNKNOWN if any of the following are true:
This bit ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
This bit is read/write-one-to-clear.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error.
UET | Meaning |
---|---|
0b00 |
Uncorrected error, Uncontainable error (UC). |
0b01 |
Uncorrected error, Unrecoverable error (UEU). |
0b10 |
Uncorrected error, Latent or Restartable error (UEO). |
0b11 |
Uncorrected error, Signaled or Recoverable error (UER). |
If this field is nonzero, then software must write ones to this field to clear this field to zero, when any of:
This field is not valid and reads UNKNOWN if any of the following are true:
This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
This field is read/write-ones-to-clear. Writing a value other than all-zeros or all-ones sets this field to an UNKNOWN value.
Software might use the information in the error record registers to determine what recovery is necessary.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
IMPLEMENTATION DEFINED error code. Used with any primary error code SERR value. Further IMPLEMENTATION DEFINED information can be placed in the MISC registers.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry.
SERR | Meaning |
---|---|
0x00 |
No error. |
0x01 |
IMPLEMENTATION DEFINED error. |
0x02 |
Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer. |
0x03 |
IMPLEMENTATION DEFINED pin. For example, nSEI pin. |
0x04 |
Assertion failure. For example, consistency failure. |
0x05 |
Error detected on internal data path. For example, parity on ALU result. |
0x06 |
Data value from associative memory. For example, ECC error on cache data. |
0x07 |
Address/control value from associative memory. For example, ECC error on cache tag. |
0x08 |
Data value from a TLB. For example, ECC error on TLB data. |
0x09 |
Address/control value from a TLB. For example, ECC error on TLB tag. |
0x0A |
Data value from producer. For example, parity error on write data bus. |
0x0B |
Address/control value from producer. For example, parity error on address bus. |
0x0C |
Data value from (non-associative) external memory. For example, ECC error in SDRAM. |
0x0D |
Illegal address (software fault). For example, access to unpopulated memory. |
0x0E |
Illegal access (software fault). For example, byte write to word register. |
0x0F |
Illegal state (software fault). For example, device not ready. |
0x10 |
Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, and SVE registers are data registers. |
0x11 |
Internal control register. For example, Parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, and SVE registers are control registers. |
0x12 |
Error response from slave. For example, error response from cache write-back. |
0x13 |
External timeout. For example, timeout on interaction with another node. |
0x14 |
Internal timeout. For example, timeout on interface within the node. |
0x15 |
Deferred error from slave not supported at master. For example, poisoned data received from a slave by a master that cannot defer the error further. |
0x16 |
Deferred error from master not supported at slave. For example, poisoned data received from a master by a slave that cannot defer the error further. |
0x17 |
Deferred error from slave passed through. For example, poisoned data received from a slave and returned to a master. |
0x18 |
Deferred error from master passed through. For example, poisoned data received from a master and deferred to a slave. |
0x19 |
Error recorded by PCIe error logs. Indicates that the node has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe. |
All other values are reserved.
This field is not valid and reads UNKNOWN if ERR<n>STATUS.V == 0b0. This field ignores writes if ERR<n>STATUS.{CE,DE,UE} != {0b00,0,0}, and the highest priority of these is not being cleared to zero in the same write.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
The {AV, V, UE, ER, OF, MV, CE, DE, PN, UET, CI} fields are write-one-to-clear, meaning writes of zero are ignored, and a write of one or all-ones to the field clears the field to zero. The {IERR, SERR} fields are read/write fields, although the set of permitted values that can be written to the fields is IMPLEMENTATION DEFINED.
After reading ERR<n>STATUS, software must clear the valid bits in the register to allow new errors to be recorded. However, between reading the register and clearing the valid bits, a new error might have overwritten the register. To prevent this error being lost by software, the register prevents updates to fields that might have been updated by a new error.
When RAS System Architecture v1.0 is implemented:
When RAS System Architecture v1.1 is implemented, a write to the register is ignored if all of:
To ensure correct and portable operation, when software is clearing the valid bits in the register to allow new errors to be recorded, software must:
Component | Offset | Instance |
---|---|---|
RAS | 0x010 + 64n | ERR<n>STATUS |
Accesses on this interface are RW.
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