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The DFAR characteristics are:
Holds the virtual address of the faulting address that caused a synchronous Data Abort exception.
AArch32 System register DFAR bits [31:0] are architecturally mapped to AArch64 System register FAR_EL1[31:0] .
AArch32 System register DFAR bits [31:0]
(S)
are architecturally mapped to
AArch32 System register HDFAR[31:0]
when HaveEL(EL2), is implemented, HaveEL(EL3) is implemented and the highest implemented Exception level is using AArch32 state.HighestELUsingAArch32().
ThisRW registerfields isin presentthis only
whenregister AArch32reset is supported at any Exception level.
Otherwise, direct accesses to DFAR arearchitecturally UNKNOWN.values.
DFAR is a 32-bit register.
The DFAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA of faulting address of synchronous Data Abort exception |
VA of faulting address of synchronous Data Abort exception.
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0110 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T6 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T6 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
return DFAR_S;
else
return DFAR_NS;
else
return DFAR;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
return DFAR_NS;
else
return DFAR;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
return DFAR_S;
else
return DFAR_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0110 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T6 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T6 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if SCR.NS == '0' then
DFAR_S = R[t];
else
DFAR_NS = R[t];
else
DFAR = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
DFAR_NS = R[t];
else
DFAR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
DFAR_S = R[t];
else
DFAR_NS = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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