The HDFGRTR_EL2 characteristics are:
Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling System registers.
This register is present only when ARMv8.6-FGT is implemented. Otherwise, direct accesses to HDFGRTR_EL2 are UNDEFINED.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
HDFGRTR_EL2 is a 64-bit register.
The HDFGRTR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | PMUSERENR_EL0 | RES0 | TRCVICTLR | TRCSTATR | TRCSSCSRn | TRCSEQSTR | TRCPRGCTLR | TRCOSLSR | RES0 | TRCIMSPECn | TRCID | RES0 | TRCCNTVRn | TRCCLAIM | TRCAUXCTLR | TRCAUTHSTATUS | TRC | PMSLATFR_EL1 | |||||||||||||
PMSIRR_EL1 | PMSIDR_EL1 | PMSICR_EL1 | PMSFCR_EL1 | PMSEVFR_EL1 | PMSCR_EL1 | PMBSR_EL1 | PMBPTR_EL1 | PMBLIMITR_EL1 | PMMIR_EL1 | RES0 | PMSELR_EL0 | PMOVS | PMINTEN | PMCNTEN | PMCCNTR_EL0 | PMCCFILTR_EL0 | PMEVTYPERn_EL0 | PMEVCNTRn_EL0 | OSDLR_EL1 | OSECCR_EL1 | OSLSR_EL1 | RES0 | DBGPRCR_EL1 | DBGAUTHSTATUS_EL1 | DBGCLAIM | MDSCR_EL1 | DBGWVRn_EL1 | DBGWCRn_EL1 | DBGBVRn_EL1 | DBGBCRn_EL1 | |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Trap MRS reads of PMUSERENR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMUSERENR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMUSERENR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of PMUSERENR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMUSERENR at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MRS reads of TRCVICTLR at EL1 using AArch64 to EL2.
TRCVICTLR | Meaning |
---|---|
0b0 |
MRS reads of TRCVICTLR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCVICTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCSTATR at EL1 using AArch64 to EL2.
TRCSTATR | Meaning |
---|---|
0b0 |
MRS reads of TRCSTATR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCSTATR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCSSCSR<n> at EL1 using AArch64 to EL2.
TRCSSCSRn | Meaning |
---|---|
0b0 |
MRS reads of TRCSSCSR<n> are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCSSCSR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If Single-shot Comparator n is not implementented, a read of TRCSSCSR<n> is UNDEFINED.
This bit is RES0 if TRCSSCSR<n> are not implemented.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCSEQSTR at EL1 using AArch64 to EL2.
TRCSEQSTR | Meaning |
---|---|
0b0 |
MRS reads of TRCSEQSTR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCSEQSTR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
This bit is RES0 if TRCSEQSTR is not implemented.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCPRGCTLR at EL1 using AArch64 to EL2.
TRCPRGCTLR | Meaning |
---|---|
0b0 |
MRS reads of TRCPRGCTLR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCPRGCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCOSLSR at EL1 using AArch64 to EL2.
TRCOSLSR | Meaning |
---|---|
0b0 |
MRS reads of TRCOSLSR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCOSLSR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MRS reads of TRCIMSPEC<n> at EL1 using AArch64 to EL2.
TRCIMSPECn | Meaning |
---|---|
0b0 |
MRS reads of TRCIMSPEC<n> are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCIMSPEC<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
TRCIMSPEC<1-7> are optional. If TRCIMSPEC<n> is not implemented, a read of TRCIMSPEC<n> is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRCID | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MRS reads of TRCCNTVR<n> at EL1 using AArch64 to EL2.
TRCCNTVRn | Meaning |
---|---|
0b0 |
MRS reads of TRCCNTVR<n> are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCCNTVR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If Counter n is not implemented, a read of TRCCNTVR<n> is UNDEFINED.
This bit is RES0 if TRCCNTVR<n> are not implemented.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRCCLAIM | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCAUXCTLR at EL1 using AArch64 to EL2.
TRCAUXCTLR | Meaning |
---|---|
0b0 |
MRS reads of TRCAUXCTLR are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCAUXCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of TRCAUTHSTATUS at EL1 using AArch64 to EL2.
TRCAUTHSTATUS | Meaning |
---|---|
0b0 |
MRS reads of TRCAUTHSTATUS are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of TRCAUTHSTATUS at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRC | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
A read of an unimplemented register is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSLATFR_EL1 at EL1 using AArch64 to EL2.
PMSLATFR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSLATFR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSLATFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSIRR_EL1 at EL1 using AArch64 to EL2.
PMSIRR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSIRR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSIRR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSIDR_EL1 at EL1 using AArch64 to EL2.
PMSIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSIDR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSICR_EL1 at EL1 using AArch64 to EL2.
PMSICR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSICR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSICR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSFCR_EL1 at EL1 using AArch64 to EL2.
PMSFCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSFCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSEVFR_EL1 at EL1 using AArch64 to EL2.
PMSEVFR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSEVFR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMSCR_EL1 at EL1 using AArch64 to EL2.
PMSCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMSCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMBSR_EL1 at EL1 using AArch64 to EL2.
PMBSR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMBSR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMBPTR_EL1 at EL1 using AArch64 to EL2.
PMBPTR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMBPTR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.
PMBLIMITR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMBLIMITR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMMIR_EL1 at EL1 using AArch64 to EL2.
PMMIR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PMMIR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of PMMIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MRS reads of PMSELR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMSELR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMSELR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of PMSELR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMSELR at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of PMOVSCLR_EL0 and PMOVSSET_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of PMOVSR and PMOVSSET.
PMOVS | Meaning |
---|---|
0b0 |
The operations listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
PMINTEN | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of PMCNTENCLR_EL0 and PMCNTENSET_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of PMCNTENCLR and PMCNTENSET.
PMCNTEN | Meaning |
---|---|
0b0 |
The operations listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MRC and MRRC reads of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCNTR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MRC and MRRC reads of PMCCNTR at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCFILTR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCCFILTR at EL0 using AArch32 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
PMCCFILTR_EL0 can also be accessed in AArch64 state using PMXEVTYPER_EL0 when PMSELR_EL0.SEL == 31, and PMCCFILTR can also be accessed in AArch32 state using PMXEVTYPER when PMSELR.SEL == 31.
Setting this bit to 1 has no effect on accesses to PMXEVTYPER_EL0 and PMXEVTYPER, regardless of the value of PMSELR_EL0 or PMSELR.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of PMEVTYPER<n>_EL0 and PMXEVTYPER_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of PMEVTYPER<n> and PMXEVTYPER.
PMEVTYPERn_EL0 | Meaning |
---|---|
0b0 |
The operations listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
If ARMv8.6-FGT is implemented, EL2 is implemented and enabled in the current Security state, then, regardless of the value of this bit, for each value n in the range UInt(MDCR_EL2.HPMN) to 30:
If event counter n is not implemented, the following are UNDEFINED:
In AArch64 state, a read of PMEVTYPER<n>_EL0, or a read of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n.
In AArch32 state, a read of PMEVTYPER<n>, or a read of PMXEVTYPER when PMSELR.SEL == n.
If event counter n is implemented, the following generate a Trap exception to EL2:
At EL0 or EL1 using AArch64, a read of PMEVTYPER<n>_EL0, or a read of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n, reported with EC syndrome value 0x18.
At EL0 using AArch32, a read of PMEVTYPER<n>, or a read of PMXEVTYPER when PMSELR.SEL == n, reported with EC syndrome value 0x03.
See also HDFGRTR_EL2.PMCCFILTR_EL0.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads and MRC reads of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MRS reads of PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MRC reads of PMEVCNTR<n> and PMXEVCNTR.
PMEVCNTRn_EL0 | Meaning |
---|---|
0b0 |
The operations listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
If ARMv8.6-FGT is implemented, EL2 is implemented and enabled in the current Security state, then, regardless of the value of this bit, for each value n in the range UInt(MDCR_EL2.HPMN) to 30:
If event counter n is not implemented, the following are UNDEFINED:
In AArch64 state, a read of PMEVCNTR<n>_EL0, or a read of PMXEVCNTR_EL0 when PMSELR_EL0.SEL == n.
In AArch32 state, a read of PMEVCNTR<n>, or a read of PMXEVCNTR when PMSELR.SEL == n.
If event counter n is implemented, the following generate a Trap exception to EL2:
At EL0 or EL1 using AArch64, a read of PMEVCNTR<n>_EL0, or a read of PMXEVCNTR_EL0 when PMSELR_EL0.SEL == n, reported with EC syndrome value 0x18.
At EL0 using AArch32, a read of PMEVCNTR<n>, or a read of PMXEVCNTR when PMSELR.SEL == n, reported with EC syndrome value 0x03.
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of OSDLR_EL1 at EL1 using AArch64 to EL2.
OSDLR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of OSDLR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of OSDLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of OSECCR_EL1 at EL1 using AArch64 to EL2.
OSECCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of OSECCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of OSECCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of OSLSR_EL1 at EL1 using AArch64 to EL2.
OSLSR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of OSLSR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of OSLSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MRS reads of DBGPRCR_EL1 at EL1 using AArch64 to EL2.
DBGPRCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGPRCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGPRCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DBGAUTHSTATUS_EL1 at EL1 using AArch64 to EL2.
DBGAUTHSTATUS_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGAUTHSTATUS_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGAUTHSTATUS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
DBGCLAIM | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of MDSCR_EL1 at EL1 using AArch64 to EL2.
MDSCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MDSCR_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of MDSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DBGWVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWVRn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGWVR<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGWVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If watchpoint n is not implemented, a read of DBGWVR<n>_EL1 is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DBGWCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWCRn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGWCR<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGWCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If watchpoint n is not implemented, a read of DBGWCR<n>_EL1 is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DBGBVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBVRn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGBVR<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGBVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If breakpoint n is not implemented, a read of DBGBVR<n>_EL1 is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Trap MRS reads of DBGBCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBCRn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of DBGBCR<n>_EL1 are not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, MRS reads of DBGBCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
If breakpoint n is not implemented, a read of DBGBCR<n>_EL1 is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1D0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else return HDFGRTR_EL2; elsif PSTATE.EL == EL3 then return HDFGRTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1D0] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else HDFGRTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HDFGRTR_EL2 = X[t];
27/09/2019 18:48; 6134483bd14dc8c12a99c984cbfe3431cc1c9707
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