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The ICC_IGRPEN1 characteristics are:
Controls whether Group 1 interrupts are enabled for the current Security state.
AArch32 System register ICC_IGRPEN1 bits [31:0] (S) are architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1[31:0] (S) .
AArch32 System register ICC_IGRPEN1 bits [31:0] (NS) are architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1[31:0] (NS) .
ThisSome or all RW fields of this register ishave presentdefined reset values.
These apply
only
when AArch32if isthe supportedPE atresets anyinto an Exception level.
level that is using AArch32.
If the PE resets into EL3 using AArch32 they apply only to the Secure instance of the register.
Otherwise,
RW directfields accessesin this register reset to ICC_IGRPEN1 arearchitecturally UNKNOWN.values.
ICC_IGRPEN1 is a 32-bit register.
The ICC_IGRPEN1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Enable |
Reserved, RES0.
Enables Group 1 interrupts for the current Security state.
Enable | Meaning |
---|---|
0b0 | Group 1 interrupts are disabled for the current Security state. |
0b1 | Group 1 interrupts are enabled for the current Security state. |
Virtual accesses to this register update ICH_VMCR.VENG1.
If EL3 is present:
This field resets to 0.
The lowest Exception level at which this register can be accessed is governed by the Exception level to which IRQ is routed. This routing depends on SCR.IRQ, SCR.NS and HCR.IMO.
If an interrupt is pending within the CPU interface when Enable becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
return ICV_IGRPEN1;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then
return ICV_IGRPEN1;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
if SCR.NS == '0' then
return ICC_IGRPEN1_S;
else
return ICC_IGRPEN1_NS;
else
return ICC_IGRPEN1;
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
return ICC_IGRPEN1_NS;
else
return ICC_IGRPEN1;
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
if SCR.NS == '0' then
return ICC_IGRPEN1_S;
else
return ICC_IGRPEN1_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1100 | 0b1100 | 0b111 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ICC_SRE.SRE == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
ICV_IGRPEN1 = R[t];
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR.IMO == '1' then
ICV_IGRPEN1 = R[t];
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
if SCR.NS == '0' then
ICC_IGRPEN1_S = R[t];
else
ICC_IGRPEN1_NS = R[t];
else
ICC_IGRPEN1 = R[t];
elsif PSTATE.EL == EL2 then
if ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then
AArch32.TakeMonitorTrapException();
elsif HaveEL(EL3) then
ICC_IGRPEN1_NS = R[t];
else
ICC_IGRPEN1 = R[t];
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
if SCR.NS == '0' then
ICC_IGRPEN1_S = R[t];
else
ICC_IGRPEN1_NS = R[t];
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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