The CP15ISB characteristics are:
Performs an Instruction Synchronization Barrier.
Arm deprecates any use of this System instruction, and strongly recommends that software use the ISB instruction instead.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to CP15ISB are UNKNOWN.
CP15ISB is a 32-bit System instruction.
CP15ISB ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b0101 | 0b100 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.CP15BEN == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.CP15BEN == '0' then UNDEFINED; elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else CP15ISB(); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then UNDEFINED; else CP15ISB(); elsif PSTATE.EL == EL2 then if HSCTLR.CP15BEN == '0' then UNDEFINED; else CP15ISB(); elsif PSTATE.EL == EL3 then CP15ISB();
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.