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ERRIRQSR, Error Interrupt Status Register

The ERRIRQSR characteristics are:

Purpose

Interrupt status register.

Configuration

External register ERRIRQSR is architecturally mapped to External register ERRIRQCR15.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

ThisRW registerfields isin presentthis only whenregister interruptreset configuration registers use the recommended format. Otherwise, direct accesses to ERRIRQSR arearchitecturally RES0UNKNOWN.values.

Attributes

ERRIRQSR is a 64-bit register.

Field descriptions

The ERRIRQSR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0CRIERRCRIERIERRERIFHIERRFHI
313029282726252423222120191817161514131211109876543210

Bits [63:6]

Reserved, RES0.

CRIERR, bit [5]

When Critical Error Interrupt is implemented:

Critical Errorerror Interruptinterrupt error.

CRIERRMeaning
0b0

Critical Error Interrupt write has not returned an error since this bit was last cleared to zero.0.

0b1

Critical Error Interrupt write has returned an error since this bit was last cleared to zero.0.

This bit is read/write-one-to-clear.

The following resets apply:

CRI, bit [4]

Otherwise:

Reserved,Critical error interrupt write in progress. RES0.

CRI, bit [4]

When Critical Error Interrupt is implemented:

Critical Error Interrupt write in progress.

CRIMeaning
0b0

Critical Error Interrupt write not in progress.

0b1

Critical Error Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

ERIERR, bit [3]

Error recovery interrupt error.

Access to this field is RO.


Otherwise:

Reserved, RES0.

ERIERR, bit [3]

When Error Recovery Interrupt is implemented:

Error Recovery Interrupt error.

ERIERRMeaning
0b0

Error Recovery Interrupt write has not returned an error since this bit was last cleared to zero.0.

0b1

Error Recovery Interrupt write has returned an error since this bit was last cleared to zero.0.

This bit is read/write-one-to-clear.

The following resets apply:

ERI, bit [2]

Otherwise:

Reserved,Error recovery interrupt write in progress. RES0.

ERI, bit [2]

When Error Recovery Interrupt is implemented:

Error Recovery Interrupt write in progress.

ERIMeaning
0b0

Error Recovery Interrupt write not in progress.

0b1

Error Recovery Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

FHIERR, bit [1]

Fault handling interrupt error.

Access to this field is RO.


Otherwise:

Reserved, RES0.

FHIERR, bit [1]

When Fault Handling Interrupt is implemented:

Fault Handling Interrupt error.

FHIERRMeaning
0b0

Fault Handling Interrupt write has not returned an error since this bit was last cleared to zero.0.

0b1

Fault Handling Interrupt write has returned an error since this bit was last cleared to zero.0.

This bit is read/write-one-to-clear.

The following resets apply:

FHI, bit [0]

Otherwise:

Reserved,Fault handling interrupt write in progress. RES0.

FHI, bit [0]

When Fault Handling Interrupt is implemented:

Fault Handling Interrupt write in progress.

FHIMeaning
0b0

Fault Handling Interrupt write not in progress.

0b1

Fault Handling Interrupt write in progress.

Software must not disable an interrupt whilst the write is in progress.

This bit is read-only.

Note

This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.

To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.

Access to this field is RO.


Otherwise:

Reserved, RES0.

Accessing the ERRIRQSR

ERRIRQSR can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xEF8
ComponentOffsetInstance
RAS0xEF8ERRIRQSR

Accesses on this interface are RW.




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

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