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The ERRPIDR4 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Peripheral identification scheme'.in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
Implementation of this register is OPTIONAL.
This register is present only
when RAS is implemented.
Otherwise, direct accesses to ERRPIDR4 are RES0.
ERRPIDR4 is a 32-bit register.
The ERRPIDR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
IMPLEMENTATION DEFINED.Size of the component. The distance from the start of the address space used by this component to the end of the component identification registers.
Size of the component.
If the value of this field is non-zero, then the component occupies 2ERRPIDR4.SIZE 4KB blocks.
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Using this bit field to indicate the size of the component is deprecated. This bit field might not correctly indicate the size of the component.
Arm recommends that software determine the size of the component from the Unique Component Identifier fields, and other IMPLEMENTATION DEFINED registers in the component.
This register reads as an IMPLEMENTATION DEFINED value.
The distance from the start of the address space used by this component to the end of the component identification registers.
A value of 0b0000 means one of the following is true:
Any other value means the component occupies 2ERRPIDR4.SIZE 4KB blocks.
Using this field to indicate the size of the component is deprecated. This field might not correctly indicate the size of the component. Arm recommends that software determine the size of the component from the Unique Component Identifier fields, and other IMPLEMENTATION DEFINED registers in the component.
This field reads as an IMPLEMENTATION DEFINED value.
IMPLEMENTATION DEFINED.Designer, JEP106 continuation code. This is the JEDEC-assigned JEP106 bank identifier for the designer of the component, minus 1.
Designer, JEP106 continuation code. This is the JEDEC-assigned JEP106 bank identifier for the designer of the component, minus 1. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
For a component designed by Arm Limited, the JEP106 bank is 5, meaning this field has the value 0x4.
Component | Offset |
---|---|
RAS | 0xFD0 |
Accesses on this interface are RO.
1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707
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