The DBGDEVID1 characteristics are:
Adds to the information given by the DBGDIDR by describing other features of the debug implementation.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DBGDEVID1 are UNKNOWN.
This register is required in all implementations.
DBGDEVID1 is a 32-bit register.
The DBGDEVID1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PCSROffset |
Reserved, RES0.
This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in Armv8 are:
PCSROffset | Meaning |
---|---|
0b0000 |
EDPCSR is not implemented. |
0b0010 |
EDPCSR implemented. Samples have no offset applied and do not sample the instruction set state in AArch32 state. |
When ARMv8.2-PCSample is implemented, the only permitted value is 0b0000.
ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMDEVID.PCSample.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0111 | 0b0001 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDEVID1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDEVID1; elsif PSTATE.EL == EL3 then return DBGDEVID1;
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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