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ERRPIDR0, Peripheral Identification Register 0

The ERRPIDR0 characteristics are:

Purpose

Provides discovery information about the component.

For more information, see 'About the Peripheral identification scheme'.in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

Configuration

Implementation of this register is OPTIONAL.

This register is present only when RAS is implemented. Otherwise, direct accesses to ERRPIDR0 are RES0.

Attributes

ERRPIDR0 is a 32-bit register.

Field descriptions

The ERRPIDR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0PART_0

Bits [31:8]

Reserved, RES0.

PART_0, bits [7:0]

IMPLEMENTATION DEFINED.

Part number, bits [7:0].

The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number, and:

This field reads as an IMPLEMENTATION DEFINED value.

Accessing the ERRPIDR0

ERRPIDR0 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xFE0
ComponentOffsetInstance
RAS0xFE0ERRPIDR0

Accesses on this interface are RO.




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

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