(old) htmldiff from-(new)

JOSCR, Jazelle OS Control Register

The JOSCR characteristics are:

Purpose

A Jazelle register, which provides operating system control of the Jazelle Extension.

Configuration

This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to JOSCR are UNKNOWN.

Attributes

JOSCR is a 32-bit register.

Field descriptions

The JOSCR bit assignments are:

313029282726252423222120191817161514131211109876543210
RAZ/WI

Bits [31:0]

Reserved, RAZ/WI.

Accessing the JOSCR

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11100b1110b00010b00000b000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JOSCR UNDEFINED at EL0" then UNDEFINED; else return JOSCR; elsif PSTATE.EL == EL1 then return JOSCR; elsif PSTATE.EL == EL2 then return JOSCR; elsif PSTATE.EL == EL3 then return JOSCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11100b1110b00010b00000b000

if PSTATE.EL == EL0 then if boolean IMPLEMENTATION_DEFINED "JOSCR UNDEFINED at EL0" then UNDEFINED; else //no operation elsif PSTATE.EL == EL1 then //no operation elsif PSTATE.EL == EL2 then //no operation elsif PSTATE.EL == EL3 then //no operation




1327/1209/2019 1518:1348; 391b5248b29fb2f001ef74792eaacbd6fc72f2116134483bd14dc8c12a99c984cbfe3431cc1c9707

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)