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The ERRCIDR0 characteristics are:
Provides discovery information aboutfor the component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
This register is present only
when RAS is implemented.
Otherwise, direct accesses to ERRCIDR0 are RES0.
ERRCIDR0 is a 32-bit register.
The ERRCIDR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_0 |
Reserved, RES0.
Component identification preamble, segment 0.
Component identification preamble, segment 0. This field reads as 0x0D.
This field reads as 0x0D.
Component | Offset |
---|---|
RAS | 0xFF0 |
Accesses on this interface are RO.
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