The PMCID2SR characteristics are:
Contains the sampled value of CONTEXTIDR_EL2, captured on reading PMPCSR[31:0].
PMCID2SR is in the Core power domain.
This register is present only when ARMv8.2-PCSample is implemented and EL2 is implemented. Otherwise, direct accesses to PMCID2SR are RES0.
If ARMv8.2-PCSample is not implemented, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMCID2SR is a 32-bit register.
The PMCID2SR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL2 |
Context ID. The value of CONTEXTIDR_EL2 that is associated with the most recent PMPCSR sample. When the most recent PMPCSR sample was generated:
Because the value written to PMCID2SR is an indirect read of CONTEXTIDR_EL2, it is CONSTRAINED UNPREDICTABLE whether PMCID2SR is set to the original or new value if PMPCSR samples:
The following resets apply:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile
Component | Offset | Instance |
---|---|---|
PMU | 0x22C | PMCID2SR |
This interface is accessible as follows:
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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