The PMLAR characteristics are:
Allows or disallows access to the Performance Monitors registers through a memory-mapped interface.
The optional Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage.
If ARMv8.3-DoPD is implemented, then ARMv8.0-SoftwareLock is not implemented by the architecturally-defined debug components of the PE in the Core power domain.
If ARMv8.3-DoPD is not implemented, then this register is in the Debug power domain.
Software uses PMLAR to set or clear the lock, and PMLSR to check the current status of the lock.
PMLAR is a 32-bit register.
The PMLAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY |
Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock, enabling write accesses to this component's registers through a memory-mapped interface.
Writing any other value to this register locks the lock, disabling write accesses to this component's registers through a memory mapped interface.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Otherwise
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
PMU | 0xFB0 | PMLAR |
This interface is accessible as follows:
13/12/2019 15:13; 391b5248b29fb2f001ef74792eaacbd6fc72f211
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