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The ERR<n>MISC3 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers mightcan contain:
A Corrected error counter or counters.
Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.
Other state information not present in the corresponding status and address registers.
If the node <q> that owns error record <n> supports the RAS Timestamp Extension, (then ERR<n>MISC3 contains the timestamp value for error record <n> when the error was detected. Otherwise the contents of ERR<n>MISC3 areERR<q>FR.TS != 0b00), then ERR<n>MISC3 contains the timestamp value for error record n when the error was detected. Otherwise the contents of ERR<n>MISC3 are IMPLEMENTATION DEFINED.
External register ERR<n>MISC3 bits [31:0]
are architecturally mapped to
AArch32 System register ERXMISC6[31:0]
when ERRSELR_EL1.SEL == n.
External register ERR<n>MISC3 bits [63:32]
are architecturally mapped to
AArch32 System register ERXMISC7[31:0]
when ERRSELR_EL1.SEL == n.
RW fields in this register reset to architecturally UNKNOWN values.
This register is present only
when ARMv8.4-RAS is implemented.
Otherwise, direct accesses to ERR<n>MISC3 are RES0.
The number of error records that are implemented is IMPLEMENTATION DEFINED.
If error record <n> is not implemented, ERR<n>MISC3 is RES0.
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>MISC3 are RES0.
External register ERR<n>MISC3
is architecturally mapped to
AArch64 System register ERXMISC3_EL1 when ERRSELR_EL1.SEL == n.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>MISC3this register, writing zero must always be supported to return the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL, where q is the index of the first error record owned by the same node as error record n. If the node owns a single record then q = n.
If RAS System Architecture v1.1 is not implemented, Arm recommendeds that ERR<n>MISC3 does not require zeroing to return the record to a quiescent state.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.
It is IMPLEMENTATION DEFINED whether ERR<n>MISC3 is present if RAS System Architecture v1.1 is not implemented. ERR<n>MISC3 is RES0 if not present.
ERR<n>MISC3 is a 64-bit register.
The ERR<n>MISC3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
TS | |||||||||||||||||||||||||||||||
TS | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Timestamp. Timestamp value recorded when the error was detected. Valid only if ERR<n>STATUS.V == 0b1.
TheTimestamp followingvalue resetsrecorded apply:when the error was detected. Valid only ifERR<n>STATUS.V == 1.
See ERR<n>FR.TS.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Access to this field is RO or RW.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED syndrome.
IMPLEMENTATION DEFINED syndrome. This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.
ReadsArm fromrecommends ERR<n>MISC3that returna anmiscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write. IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.
Arm recommends that miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.WhenERR<n>STATUS.MV is set to 1, the miscellaneous syndrome for the most recently recorded error should ignore writes.
When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error should ignore writes.
These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.
Component | Offset | Instance |
---|---|---|
RAS | 0x038 + 64n | ERR<n>MISC3 |
Accesses on this interface are RW.
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