(old) htmldiff from-(new)

VMSR

Move general-purpose register to SIMD&FP Special register moves the value of a general-purpose register to a floating-point System register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

When these settings permit the execution of floating-point and Advanced SIMD instructions:

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111111101110regRt1010(0)(0)(0)1(0)(0)(0)(0)
cond

A1

VMSR{<c>}{<q>} <spec_reg>, <Rt>

t = UInt(Rt); if reg != '000x' && reg != '1000' thenif reg != '000x' && reg != '1000' then UNPREDICTABLE; if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 Constraint c = ConstrainUnpredictable(Unpredictable_VMSR); assert c IN {Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNDEF UNDEFINED; when Constraint_NOPEndOfInstruction(); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

CONSTRAINED UNPREDICTABLE behavior

If reg != '000x' && reg != '1000', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111011101110regRt1010(0)(0)(0)1(0)(0)(0)(0)

T1

VMSR{<c>}{<q>} <spec_reg>, <Rt>

t = UInt(Rt); if reg != '000x' && reg != '1000' thenif reg != '000x' && reg != '1000' then UNPREDICTABLE; if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 Constraint c = ConstrainUnpredictable(Unpredictable_VMSR); assert c IN {Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNDEF UNDEFINED; when Constraint_NOPEndOfInstruction(); if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

CONSTRAINED UNPREDICTABLE behavior

If reg != '000x' && reg != '1000', then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<spec_reg> Is the destination Advanced SIMD and floating-point System register, encoded in reg:
reg<spec_reg>
0000FPSID
0001FPSCR
001xUNPREDICTABLE
01xxUNPREDICTABLE
1000FPEXC
1001UNPREDICTABLE
101xUNPREDICTABLE
11xxUNPREDICTABLE
<Rt>

Is the general-purpose source register, encoded in the "Rt" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if reg == '0001' then // FPSCR CheckVFPEnabled(TRUE); FPSCR = R[t]; elsif PSTATE.EL == EL0 then UNDEFINED; // Non-FPSCR registers accessible only at PL1 or above else CheckVFPEnabled(FALSE); // Non-FPSCR registers are not affected by FPEXC.EN case reg of when '0000' // VMSR access to FPSID is ignored when '1000' FPEXC = R[t]; otherwise Unreachable(); // Dealt with above or in encoding-specific pseudocode


Internal version only: isa v01_09v01_06, pseudocode v8r-00bet0_rc1-199-g1970297v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3 ; Build timestamp: 2020-04-15T122019-12-12T17:2134

Copyright © 2010-20202010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)