1. Introduction

This is the 2020-03 release of the AArch32 ISA XML for Armv8.6.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

If you have comments on the content of this package, please send them by e-mail to support-aarchv8@arm.com. Give:

• The title, "AArch32 ISA XML for Armv8.6".
• The version, "2020-03".
• A concise explanation of your comments.

2. Contents

3. Release Notes

Change history

The following general changes are made:

The following changes are made to the instruction definitions:

• A32 Assembler symbol definition update for PKHBT and PKHTB <imm>
• The "System register access, Advanced SIMD, floating-point and Supervisor call table" has been re-organised to remove apparant clashes in opcodes. This has resulted in the addition of the Unconditional Advanced SIMD and floating-point instructions table. No new instructions have been added as a result of this change.
• Alias conditions have been changed for:
  • LDR (immediate)
  • STR (immediate)
• Pseudocode for AArch32 MRC instruction with R15 as destination register is corrected to behave as UNPREDICTABLE.

The following changes are made to the Shared Pseudocode:

• Coproc encoding incorrect for AT instruction in A32 context.
  The Pseudocode function AArch32.ExecutingATS1xPInstr() is corrected for instruction encoding of ATS1CP(R/W)P instructions.
• ESB does not synchronize /all/ SEIs In Pseudocode functions AArch64.(ESBOperation) and AArch32.(ESBOperation) the check for masked Physical SError pending is changed to a check for a masked Physical SError pending that can be synchronized by an Error synchronization event.
• CPSRWriteByINstr() does not list SSBS and DIT
  The Pseudocode function CPSRWriteByInstr() now updates the SSBS and DIT bit fields.

Known issues

Potential upcoming changes