Advanced SIMD load single structure to all lanes<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
|
Advanced SIMD load single structure to all lanes<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD load/store multiple structures<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD load/store multiple structures<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | 64 |
|
Advanced SIMD load/store single structure to one lane<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32.
Where:
<size> |
Is the data size,
encoded in
size :
|
System register Load/Store+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
System register 32-bit move<coproc>
Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.
Where:
<coproc> |
Is the System register encoding space,
encoded in
coproc<0> :
coproc<0> | <coproc> |
---|
0 | p14 | 1 | p15 |
|
System register 64-bit move<coproc>
Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.
Where:
<coproc> |
Is the System register encoding space,
encoded in
coproc<0> :
coproc<0> | <coproc> |
---|
0 | p14 | 1 | p15 |
|
Change Process State<endian_specifier>
Original text: Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE
Where:
<endian_specifier> |
Is the endianness to be selected, and the value to be set in PSTATE.E,
encoded in
E :
E | <endian_specifier> |
---|
0 | LE | 1 | BE |
|
Change Processor State<endian_specifier>
Original text: Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in "E", where 0->LE, 1->BE
Where:
<endian_specifier> |
Is the endianness to be selected, and the value to be set in PSTATE.E,
encoded in
E :
E | <endian_specifier> |
---|
0 | LE | 1 | BE |
|
Data-processing (shifted register)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Data-processing (shifted register)<shift>
Original text: Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Extend and Add<amount>
Original text: Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24
Where:
<amount> |
Is the rotate amount,
encoded in
rotate :
rotate | <amount> |
---|
00 | (omitted) | 01 | 8 | 10 | 16 | 11 | 24 |
|
Register extends<amount>
Original text: Is the rotate amount, encoded in "rotate", where 00->(omitted), 01->8, 10->16, 11->24
Where:
<amount> |
Is the rotate amount,
encoded in
rotate :
rotate | <amount> |
---|
00 | (omitted) | 01 | 8 | 10 | 16 | 11 | 24 |
|
Advanced SIMD and floating-point multiply with accumulate<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Advanced SIMD and floating-point multiply with accumulate<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T :
|
Floating-point data-processing (two registers)<dt>
Original text: Is the data type for the operand, encoded in "op", where 0->U32, 1->S32
Where:
<dt> |
Is the data type for the operand,
encoded in
op :
|
Floating-point data-processing (two registers)<dt>
Original text: Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32
Where:
<dt> |
Is the data type for the fixed-point number,
encoded in
U:sx :
U | sx | <dt> |
---|
0 | 0 | S16 | 0 | 1 | S32 | 1 | 0 | U16 | 1 | 1 | U32 |
|
Floating-point move special register<spec_reg>
Original text: Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE
Where:
<spec_reg> |
Is the destination Advanced SIMD and floating-point System register,
encoded in
reg :
reg | <spec_reg> |
---|
0000 | FPSID | 0001 | FPSCR | 001x | UNPREDICTABLE | 01xx | UNPREDICTABLE | 1000 | FPEXC | 1001 | UNPREDICTABLE | 101x | UNPREDICTABLE | 11xx | UNPREDICTABLE |
|
Floating-point move special register<spec_reg>
Original text: Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE
Where:
<spec_reg> |
Is the source Advanced SIMD and floating-point System register,
encoded in
reg :
reg | <spec_reg> |
---|
0000 | FPSID | 0001 | FPSCR | 001x | UNPREDICTABLE | 0100 | UNPREDICTABLE | 0101 | MVFR2 | 0110 | MVFR1 | 0111 | MVFR0 | 1000 | FPEXC | 1001 | UNPREDICTABLE | 101x | UNPREDICTABLE | 11xx | UNPREDICTABLE |
|
Floating-point directed convert to integer<dt>
Original text: Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32
Where:
<dt> |
Is the data type for the elements of the destination,
encoded in
op :
|
Floating-point directed convert to integer<dt>
Original text: Is the data type for the elements of the destination, encoded in "op" where 0->U32, 1->S32
Where:
<dt> |
Is the data type for the elements of the destination,
encoded in
op :
|
Floating-point data-processing (two registers)<dt>
Original text: Is the data type for the fixed-point number, encoded in "U:sx", where 00->S16, 10->U16, 01->S32, 11->U32
Where:
<dt> |
Is the data type for the fixed-point number,
encoded in
U:sx :
U | sx | <dt> |
---|
0 | 0 | S16 | 0 | 1 | S32 | 1 | 0 | U16 | 1 | 1 | U32 |
|
Floating-point data-processing (two registers)<dt>
Original text: Is the data type for the operand, encoded in "op", where 0->U32, 1->S32
Where:
<dt> |
Is the data type for the operand,
encoded in
op :
|
Integer Test and Compare (two register, immediate shift)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Integer Test and Compare (two register, register shift)<type>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<type> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <type> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Integer Data Processing (three register, immediate shift)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Integer Data Processing (three register, register shift)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Load dual (literal)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load, signed (literal)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load, unsigned (literal)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store, signed (immediate, post-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store, signed (immediate, pre-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store, unsigned (immediate, post-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store, unsigned (immediate, pre-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
System register load/store+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store dual (immediate)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store dual (immediate, post-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/store dual (immediate, pre-indexed)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/Store Word, Unsigned Byte (immediate, literal)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/Store Word, Unsigned Byte (register)+/-
Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Advanced SIMD and floating-point load/store+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Advanced SIMD load/store multiple structures<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, 11->64.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | 64 |
|
Advanced SIMD load/store multiple structures<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD load/store single structure to one lane<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32.
Where:
<size> |
Is the data size,
encoded in
size :
|
Load/Store Dual, Half, Signed Byte (immediate, literal)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Load/Store Dual, Half, Signed Byte (register)+/-
Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Advanced SIMD load single structure to all lanes<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 1x->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
|
Advanced SIMD load single structure to all lanes<size>
Original text: Is the data size, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED.
Where:
<size> |
Is the data size,
encoded in
size :
size | <size> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Logical Arithmetic (three register, immediate shift)<shift>
Original text: Is the type of shift to be applied to the source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Logical Arithmetic (three register, immediate shift)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Logical Arithmetic (three register, register shift)<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
System register 32-bit move<coproc>
Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.
Where:
<coproc> |
Is the System register encoding space,
encoded in
coproc<0> :
coproc<0> | <coproc> |
---|
0 | p14 | 1 | p15 |
|
System register 64-bit move<coproc>
Original text: Is the System register encoding space, encoded in "coproc<0>", where 0->p14, 1->p15.
Where:
<coproc> |
Is the System register encoding space,
encoded in
coproc<0> :
coproc<0> | <coproc> |
---|
0 | p14 | 1 | p15 |
|
Floating-point move special register<spec_reg>
Original text: Is the destination Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 1000->FPEXC, otherwise UNPREDICTABLE
Where:
<spec_reg> |
Is the destination Advanced SIMD and floating-point System register,
encoded in
reg :
reg | <spec_reg> |
---|
0000 | FPSID | 0001 | FPSCR | 001x | UNPREDICTABLE | 01xx | UNPREDICTABLE | 1000 | FPEXC | 1001 | UNPREDICTABLE | 101x | UNPREDICTABLE | 11xx | UNPREDICTABLE |
|
Floating-point move special register<spec_reg>
Original text: Is the source Advanced SIMD and floating-point System register, encoded in "reg", where 0000->FPSID, 0001->FPSCR, 0101->MVFR2, 0110->MVFR1, 0111->MVFR0, 1000->FPEXC, otherwise UNPREDICTABLE
Where:
<spec_reg> |
Is the source Advanced SIMD and floating-point System register,
encoded in
reg :
reg | <spec_reg> |
---|
0000 | FPSID | 0001 | FPSCR | 001x | UNPREDICTABLE | 0100 | UNPREDICTABLE | 0101 | MVFR2 | 0110 | MVFR1 | 0111 | MVFR0 | 1000 | FPEXC | 1001 | UNPREDICTABLE | 101x | UNPREDICTABLE | 11xx | UNPREDICTABLE |
|
Move special register (register)<spec_reg>
Original text: Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.
Where:
<spec_reg> |
Is the special register to be accessed,
encoded in
R :
R | <spec_reg> |
---|
0 | CPSR|APSR | 1 | SPSR |
|
Move special register (register)<banked_reg>
Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE
Where:
<banked_reg> |
Is the name of the banked register to be transferred to or from,
encoded in
R:M:M1 :
R | M | M1 | <banked_reg> |
---|
0 | 0 | 0000 | R8_usr | 0 | 0 | 0001 | R9_usr | 0 | 0 | 0010 | R10_usr | 0 | 0 | 0011 | R11_usr | 0 | 0 | 0100 | R12_usr | 0 | 0 | 0101 | SP_usr | 0 | 0 | 0110 | LR_usr | 0 | 0 | 0111 | UNPREDICTABLE | 0 | 0 | 1000 | R8_fiq | 0 | 0 | 1001 | R9_fiq | 0 | 0 | 1010 | R10_fiq | 0 | 0 | 1011 | R11_fiq | 0 | 0 | 1100 | R12_fiq | 0 | 0 | 1101 | SP_fiq | 0 | 0 | 1110 | LR_fiq | 0 | 0 | 1111 | UNPREDICTABLE | 0 | 1 | 0000 | LR_irq | 0 | 1 | 0001 | SP_irq | 0 | 1 | 0010 | LR_svc | 0 | 1 | 0011 | SP_svc | 0 | 1 | 0100 | LR_abt | 0 | 1 | 0101 | SP_abt | 0 | 1 | 0110 | LR_und | 0 | 1 | 0111 | SP_und | 0 | 1 | 10xx | UNPREDICTABLE | 0 | 1 | 1100 | LR_mon | 0 | 1 | 1101 | SP_mon | 0 | 1 | 1110 | ELR_hyp | 0 | 1 | 1111 | SP_hyp | 1 | 0 | 0xxx | UNPREDICTABLE | 1 | 0 | 10xx | UNPREDICTABLE | 1 | 0 | 110x | UNPREDICTABLE | 1 | 0 | 1110 | SPSR_fiq | 1 | 0 | 1111 | UNPREDICTABLE | 1 | 1 | 0000 | SPSR_irq | 1 | 1 | 0001 | UNPREDICTABLE | 1 | 1 | 0010 | SPSR_svc | 1 | 1 | 0011 | UNPREDICTABLE | 1 | 1 | 0100 | SPSR_abt | 1 | 1 | 0101 | UNPREDICTABLE | 1 | 1 | 0110 | SPSR_und | 1 | 1 | 0111 | UNPREDICTABLE | 1 | 1 | 10xx | UNPREDICTABLE | 1 | 1 | 1100 | SPSR_mon | 1 | 1 | 1101 | UNPREDICTABLE | 1 | 1 | 1110 | SPSR_hyp | 1 | 1 | 1111 | UNPREDICTABLE |
|
MRS (banked)<banked_reg>
Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE
Where:
<banked_reg> |
Is the name of the banked register to be transferred to or from,
encoded in
R:M:M1 :
R | M | M1 | <banked_reg> |
---|
0 | 0 | 0000 | R8_usr | 0 | 0 | 0001 | R9_usr | 0 | 0 | 0010 | R10_usr | 0 | 0 | 0011 | R11_usr | 0 | 0 | 0100 | R12_usr | 0 | 0 | 0101 | SP_usr | 0 | 0 | 0110 | LR_usr | 0 | 0 | 0111 | UNPREDICTABLE | 0 | 0 | 1000 | R8_fiq | 0 | 0 | 1001 | R9_fiq | 0 | 0 | 1010 | R10_fiq | 0 | 0 | 1011 | R11_fiq | 0 | 0 | 1100 | R12_fiq | 0 | 0 | 1101 | SP_fiq | 0 | 0 | 1110 | LR_fiq | 0 | 0 | 1111 | UNPREDICTABLE | 0 | 1 | 0000 | LR_irq | 0 | 1 | 0001 | SP_irq | 0 | 1 | 0010 | LR_svc | 0 | 1 | 0011 | SP_svc | 0 | 1 | 0100 | LR_abt | 0 | 1 | 0101 | SP_abt | 0 | 1 | 0110 | LR_und | 0 | 1 | 0111 | SP_und | 0 | 1 | 10xx | UNPREDICTABLE | 0 | 1 | 1100 | LR_mon | 0 | 1 | 1101 | SP_mon | 0 | 1 | 1110 | ELR_hyp | 0 | 1 | 1111 | SP_hyp | 1 | 0 | 0xxx | UNPREDICTABLE | 1 | 0 | 10xx | UNPREDICTABLE | 1 | 0 | 110x | UNPREDICTABLE | 1 | 0 | 1110 | SPSR_fiq | 1 | 0 | 1111 | UNPREDICTABLE | 1 | 1 | 0000 | SPSR_irq | 1 | 1 | 0001 | UNPREDICTABLE | 1 | 1 | 0010 | SPSR_svc | 1 | 1 | 0011 | UNPREDICTABLE | 1 | 1 | 0100 | SPSR_abt | 1 | 1 | 0101 | UNPREDICTABLE | 1 | 1 | 0110 | SPSR_und | 1 | 1 | 0111 | UNPREDICTABLE | 1 | 1 | 10xx | UNPREDICTABLE | 1 | 1 | 1100 | SPSR_mon | 1 | 1 | 1101 | UNPREDICTABLE | 1 | 1 | 1110 | SPSR_hyp | 1 | 1 | 1111 | UNPREDICTABLE |
|
MRS (special)<spec_reg>
Original text: Is the special register to be accessed, encoded in "R", where 0->CPSR|APSR, 1->SPSR.
Where:
<spec_reg> |
Is the special register to be accessed,
encoded in
R :
R | <spec_reg> |
---|
0 | CPSR|APSR | 1 | SPSR |
|
MSR (banked)<banked_reg>
Original text: Is the name of the banked register to be transferred to or from, encoded in the "R:M:M1" field, where 000000->R8_usr, 000001->R9_usr, 000010->R10_usr, 000011->R11_usr, 000100->R12_usr, 000101->SP_usr, 000110->LR_usr, 001000->R8_fiq, 001001->R9_fiq, 001010->R10_fiq, 001011->R11_fiq, 001100->R12_fiq, 001101->SP_fiq, 001110->LR_fiq, 010000->LR_irq, 010001->SP_irq, 010010->LR_svc, 010011->SP_svc, 010100->LR_abt, 010101->SP_abt, 010110->LR_und, 010111->SP_und, 011100->LR_mon, 011101->SP_mon, 011110->ELR_hyp, 011111->SP_hyp, 101110->SPSR_fiq, 110000->SPSR_irq, 110010->SPSR_svc, 110100->SPSR_abt, 110110->SPSR_und, 111100->SPSR_mon, 111110->SPSR_hyp, otherwise UNPREDICTABLE
Where:
<banked_reg> |
Is the name of the banked register to be transferred to or from,
encoded in
R:M:M1 :
R | M | M1 | <banked_reg> |
---|
0 | 0 | 0000 | R8_usr | 0 | 0 | 0001 | R9_usr | 0 | 0 | 0010 | R10_usr | 0 | 0 | 0011 | R11_usr | 0 | 0 | 0100 | R12_usr | 0 | 0 | 0101 | SP_usr | 0 | 0 | 0110 | LR_usr | 0 | 0 | 0111 | UNPREDICTABLE | 0 | 0 | 1000 | R8_fiq | 0 | 0 | 1001 | R9_fiq | 0 | 0 | 1010 | R10_fiq | 0 | 0 | 1011 | R11_fiq | 0 | 0 | 1100 | R12_fiq | 0 | 0 | 1101 | SP_fiq | 0 | 0 | 1110 | LR_fiq | 0 | 0 | 1111 | UNPREDICTABLE | 0 | 1 | 0000 | LR_irq | 0 | 1 | 0001 | SP_irq | 0 | 1 | 0010 | LR_svc | 0 | 1 | 0011 | SP_svc | 0 | 1 | 0100 | LR_abt | 0 | 1 | 0101 | SP_abt | 0 | 1 | 0110 | LR_und | 0 | 1 | 0111 | SP_und | 0 | 1 | 10xx | UNPREDICTABLE | 0 | 1 | 1100 | LR_mon | 0 | 1 | 1101 | SP_mon | 0 | 1 | 1110 | ELR_hyp | 0 | 1 | 1111 | SP_hyp | 1 | 0 | 0xxx | UNPREDICTABLE | 1 | 0 | 10xx | UNPREDICTABLE | 1 | 0 | 110x | UNPREDICTABLE | 1 | 0 | 1110 | SPSR_fiq | 1 | 0 | 1111 | UNPREDICTABLE | 1 | 1 | 0000 | SPSR_irq | 1 | 1 | 0001 | UNPREDICTABLE | 1 | 1 | 0010 | SPSR_svc | 1 | 1 | 0011 | UNPREDICTABLE | 1 | 1 | 0100 | SPSR_abt | 1 | 1 | 0101 | UNPREDICTABLE | 1 | 1 | 0110 | SPSR_und | 1 | 1 | 0111 | UNPREDICTABLE | 1 | 1 | 10xx | UNPREDICTABLE | 1 | 1 | 1100 | SPSR_mon | 1 | 1 | 1101 | UNPREDICTABLE | 1 | 1 | 1110 | SPSR_hyp | 1 | 1 | 1111 | UNPREDICTABLE |
|
Preload (immediate)+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Preload (register)<shift>
Original text: Is the type of shift to be applied to the index register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the index register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Preload (register)+/-
Original text: Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Shift (immediate)<shift>
Original text: Is the type of shift to be applied to the source register, encoded in "op", where 00->LSL, 01->LSR, 10->ASR.
Where:
<shift> |
Is the type of shift to be applied to the source register,
encoded in
op :
|
Register shifts<shift>
Original text: Is the type of shift to be applied to the second source register, encoded in "stype", where 00->LSL, 01->LSR, 10->ASR, 11->ROR.
Where:
<shift> |
Is the type of shift to be applied to the second source register,
encoded in
stype :
stype | <shift> |
---|
00 | LSL | 01 | LSR | 10 | ASR | 11 | ROR |
|
Advanced SIMD one register and modified immediate<dt>
Original text: The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.
Where:
<dt> |
The data type,
encoded in
cmode :
cmode | <dt> |
---|
110x | I32 | 1110 | I8 | 1111 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
size | <dt> |
---|
00 | I8 | 01 | I16 | 10 | I32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
op<0>:size :
op<0> | size | <dt> |
---|
0 | 00 | S16 | 0 | 01 | S32 | 0 | 10 | S64 | 0 | 11 | RESERVED | 1 | 00 | U16 | 1 | 01 | U32 | 1 | 10 | U64 | 1 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
F:size :
F | size | <dt> |
---|
0 | 10 | U32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | I8 | 0 | 01 | I16 | 0 | 10 | I32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | I16 | 01 | I32 | 10 | I64 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | S16 | 01 | S32 | 10 | S64 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | S8 | 01 | S16 | 10 | S32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.
Where:
<dt> |
Is the data type,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | RESERVED | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the destination,
encoded in
op:size :
op | size | <dt> |
---|
0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
size :
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
size:op :
size | op | <dt2> |
---|
01 | 00 | S16 | 01 | 01 | U16 | 01 | 1x | F16 | 10 | 00 | S32 | 10 | 01 | U32 | 10 | 1x | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | RESERVED | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
op:size :
op | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 0 | 11 | RESERVED | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 | 1 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt1>
Original text: Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32
Where:
<dt1> |
Is the data type for the elements of the destination vector,
encoded in
size:op :
size | op | <dt1> |
---|
01 | 0x | F16 | 01 | 10 | S16 | 01 | 11 | U16 | 10 | 0x | F32 | 10 | 10 | S32 | 10 | 11 | U32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
size | <dt> |
---|
00 | S8 | 01 | S16 | 10 | S32 | 11 | RESERVED |
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the scalar and the elements of the operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the scalar and the elements of the operand vector,
encoded in
F:size :
F | size | <dt> |
---|
0 | 01 | I16 | 0 | 10 | I32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers and a scalar extension<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T
:
|
Advanced SIMD two registers and a scalar extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot
:
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Advanced SIMD two registers and shift amount<type>
Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.
Where:
<type> |
Is the data type for the elements of the vectors,
encoded in
U :
|
Advanced SIMD two registers and shift amount<size>
Original text: Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.
Where:
<size> |
Is the data size for the elements of the vectors,
encoded in
imm6<5:3> :
imm6<5:3> | <size> |
---|
001 | 16 | 01x | 32 | 1xx | 64 |
|
Advanced SIMD two registers and shift amount<dt1>
Original text: Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32
Where:
<dt1> |
Is the data type for the elements of the destination vector,
encoded in
op:U :
op | U | <dt1> |
---|
00 | x | F16 | 01 | 0 | S16 | 01 | 1 | U16 | 10 | x | F32 | 11 | 0 | S32 | 11 | 1 | U32 |
|
Advanced SIMD two registers and shift amount<size>
Original text: Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.
Where:
<size> |
Is the data size for the elements of the vectors,
encoded in
L:imm6<5:3> :
L | imm6<5:3> | <size> |
---|
0 | 001 | 8 | 0 | 01x | 16 | 0 | 1xx | 32 | 1 | xxx | 64 |
|
Advanced SIMD two registers and shift amount<type>
Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.
Where:
<type> |
Is the data type for the elements of the vectors,
encoded in
U :
|
Advanced SIMD two registers and shift amount<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
op:U :
op | U | <dt2> |
---|
00 | 0 | S16 | 00 | 1 | U16 | 01 | x | F16 | 10 | 0 | S32 | 10 | 1 | U32 | 11 | x | F32 |
|
Advanced SIMD two registers and shift amount<dt>
Original text: Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
U:imm3H :
U | imm3H | <dt> |
---|
0 | 001 | S8 | 0 | 010 | S16 | 0 | 100 | S32 | 1 | 001 | U8 | 1 | 010 | U16 | 1 | 100 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the second operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.
Where:
<dt> |
Is the data type for the elements of the second operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
op:U:size :
op | U | size | <dt> |
---|
0 | 0 | 00 | S8 | 0 | 0 | 01 | S16 | 0 | 0 | 10 | S32 | 0 | 1 | 00 | U8 | 0 | 1 | 01 | U16 | 0 | 1 | 10 | U32 | 1 | 0 | 00 | P8 | 1 | 0 | 10 | P64 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 0 | 11 | S64 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 | 1 | 11 | U64 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | I8 | 01 | I16 | 10 | I32 | 11 | I64 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
op:size :
op | size | <dt> |
---|
0 | 00 | I8 | 0 | 01 | I16 | 0 | 10 | I32 | 1 | 00 | P8 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
sz :
|
Advanced SIMD three registers of the same length extension<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T :
|
Advanced SIMD three registers of the same length extension<dt>
Original text: Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
S :
|
Advanced SIMD three registers of the same length extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Advanced SIMD three registers of the same length extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
|
Advanced SIMD one register and modified immediate<dt>
Original text: The data type, encoded in "cmode", where 110x->I32, 1110->I8, 1111->F32.
Where:
<dt> |
The data type,
encoded in
cmode :
cmode | <dt> |
---|
110x | I32 | 1110 | I8 | 1111 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I8, 01->I16, 10->I32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
size | <dt> |
---|
00 | I8 | 01 | I16 | 10 | I32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "size:op" where 0100->S16, 0101->U16, 011x->F16, 1000->S32, 1001->U32, 101x->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
size:op :
size | op | <dt2> |
---|
01 | 00 | S16 | 01 | 01 | U16 | 01 | 1x | F16 | 10 | 00 | S32 | 10 | 01 | U32 | 10 | 1x | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the destination, encoded in "op:size", where 001->S16, 010->S32, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the destination,
encoded in
op:size :
op | size | <dt> |
---|
0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, 10->32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | S8 | 01 | S16 | 10 | S32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size", where 00->S16, 01->S32, 10->S64, otherwise UNDEFINED.
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | S16 | 01 | S32 | 10 | S64 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 01->F16, 10->F32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "F:size", where 000->I8, 001->I16, 010->I32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | I8 | 0 | 01 | I16 | 0 | 10 | I32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type, encoded in "size", where 00->8, otherwise UNDEFINED.
Where:
<dt> |
Is the data type,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | RESERVED | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "op<0>:size", where 000->S16, 001->S32, 010->S64, 100->U16, 101->U32, 110->U64, otherwise UNDEFINED.
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
op<0>:size :
op<0> | size | <dt> |
---|
0 | 00 | S16 | 0 | 01 | S32 | 0 | 10 | S64 | 0 | 11 | RESERVED | 1 | 00 | U16 | 1 | 01 | U32 | 1 | 10 | U64 | 1 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->8, 01->16, 10->32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 10 | 32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, 01->16, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | 16 | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "op:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
op:size :
op | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 0 | 11 | RESERVED | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 | 1 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 010->U32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
F:size :
F | size | <dt> |
---|
0 | 10 | U32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "size" where 01->F16, 10->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
size :
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size" where 00->8, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | 8 | 01 | RESERVED | 1x | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->S8, 01->S16, 10->S32, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
size | <dt> |
---|
00 | S8 | 01 | S16 | 10 | S32 | 11 | RESERVED |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the vectors, encoded in "F:size", where 000->S8, 001->S16, 010->S32, 101->F16, 110->F32.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
F:size :
F | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers misc<dt1>
Original text: Is the data type for the elements of the destination vector, encoded in "size:op" where 010x->F16, 0110->S16, 0111->U16, 100x->F32, 1010->S32, 1011->U32
Where:
<dt1> |
Is the data type for the elements of the destination vector,
encoded in
size:op :
size | op | <dt1> |
---|
01 | 0x | F16 | 01 | 10 | S16 | 01 | 11 | U16 | 10 | 0x | F32 | 10 | 10 | S32 | 10 | 11 | U32 |
|
Advanced SIMD two registers misc<dt>
Original text: Is the data type for the elements of the operand, encoded in "size", where 00->I16, 01->I32, 10->I64, otherwise UNDEFINED
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
size :
size | <dt> |
---|
00 | I16 | 01 | I32 | 10 | I64 | 11 | RESERVED |
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "F:size", where 001->I16, 010->I32, 101->F16, 110->F32
Where:
<dt> |
Is the data type for the scalar and the elements of the operand vector,
encoded in
F:size :
F | size | <dt> |
---|
0 | 01 | I16 | 0 | 10 | I32 | 1 | 01 | F16 | 1 | 10 | F32 |
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD two registers and a scalar<dt>
Original text: Is the data type for the scalar and the elements of the operand vector, encoded in "U:size", where 001->S16, 010->S32, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the scalar and the elements of the operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 01 | S16 | 0 | 10 | S32 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD two registers and a scalar extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot
:
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Advanced SIMD two registers and a scalar extension<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T
:
|
Advanced SIMD two registers and shift amount<dt2>
Original text: Is the data type for the elements of the source vector, encoded in "op:U" where 000->S16, 001->U16, 01x->F16, 100->S32, 101->U32, 11x->F32
Where:
<dt2> |
Is the data type for the elements of the source vector,
encoded in
op:U :
op | U | <dt2> |
---|
00 | 0 | S16 | 00 | 1 | U16 | 01 | x | F16 | 10 | 0 | S32 | 10 | 1 | U32 | 11 | x | F32 |
|
Advanced SIMD two registers and shift amount<dt>
Original text: Is the data type for the elements of the operand, encoded in "U:imm3H" where 0001->S8, 0010->S16, 0100->S32, 1001->U8, 1010->U16, 1100->U32
Where:
<dt> |
Is the data type for the elements of the operand,
encoded in
U:imm3H :
U | imm3H | <dt> |
---|
0 | 001 | S8 | 0 | 010 | S16 | 0 | 100 | S32 | 1 | 001 | U8 | 1 | 010 | U16 | 1 | 100 | U32 |
|
Advanced SIMD two registers and shift amount<size>
Original text: Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field, where 0001->8, 001x->16, 01xx->32, 1xxx->64.
Where:
<size> |
Is the data size for the elements of the vectors,
encoded in
L:imm6<5:3> :
L | imm6<5:3> | <size> |
---|
0 | 001 | 8 | 0 | 01x | 16 | 0 | 1xx | 32 | 1 | xxx | 64 |
|
Advanced SIMD two registers and shift amount<type>
Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 0->S, 1->U.
Where:
<type> |
Is the data type for the elements of the vectors,
encoded in
U :
|
Advanced SIMD two registers and shift amount<type>
Original text: Is the data type for the elements of the vectors, encoded in the "U" field, where 1->S.
Where:
<type> |
Is the data type for the elements of the vectors,
encoded in
U :
|
Advanced SIMD two registers and shift amount<size>
Original text: Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field, where 001->16, 01x->32, 1xx->64.
Where:
<size> |
Is the data size for the elements of the vectors,
encoded in
imm6<5:3> :
imm6<5:3> | <size> |
---|
001 | 16 | 01x | 32 | 1xx | 64 |
|
Advanced SIMD two registers and shift amount<dt1>
Original text: Is the data type for the elements of the destination vector, encoded in "op:U" where 00x->F16, 010->S16, 011->U16, 10x->F32, 110->S32, 111->U32
Where:
<dt1> |
Is the data type for the elements of the destination vector,
encoded in
op:U :
op | U | <dt1> |
---|
00 | x | F16 | 01 | 0 | S16 | 01 | 1 | U16 | 10 | x | F32 | 11 | 0 | S32 | 11 | 1 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the second operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->I16, 01->I32, 10->I64
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the second operand vector, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32.
Where:
<dt> |
Is the data type for the elements of the second operand vector,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of different lengths<dt>
Original text: Is the data type for the elements of the operands, encoded in "op:U:size", where 0000->S8, 0001->S16, 0010->S32, 0100->U8, 0101->U16, 0110->U32, 1000->P8, 1010->P64
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
op:U:size :
op | U | size | <dt> |
---|
0 | 0 | 00 | S8 | 0 | 0 | 01 | S16 | 0 | 0 | 10 | S32 | 0 | 1 | 00 | U8 | 0 | 1 | 01 | U16 | 0 | 1 | 10 | U32 | 1 | 0 | 00 | P8 | 1 | 0 | 10 | P64 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "sz", where 0->F32, 1->F16.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
sz :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "op:size", where 000->I8, 001->I16, 010->I32, 100->P8
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
op:size :
op | size | <dt> |
---|
0 | 00 | I8 | 0 | 01 | I16 | 0 | 10 | I32 | 1 | 00 | P8 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 00->8, 01->16, 10->32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "size", where 01->S16, 10->S32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 011->S64, 100->U8, 101->U16, 110->U32, 111->U64.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 0 | 11 | S64 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 | 1 | 11 | U64 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the operands, encoded in "U:size", where 000->S8, 001->S16, 010->S32, 100->U8, 101->U16, 110->U32
Where:
<dt> |
Is the data type for the elements of the operands,
encoded in
U:size :
U | size | <dt> |
---|
0 | 00 | S8 | 0 | 01 | S16 | 0 | 10 | S32 | 1 | 00 | U8 | 1 | 01 | U16 | 1 | 10 | U32 |
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
|
Advanced SIMD three registers of the same length<dt>
Original text: Is the data type for the elements of the vectors, encoded in "size", where 00->I8, 01->I16, 10->I32, 11->I64.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
size :
size | <dt> |
---|
00 | I8 | 01 | I16 | 10 | I32 | 11 | I64 |
|
Advanced SIMD three registers of the same length extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Advanced SIMD three registers of the same length extension<dt>
Original text: Is the data type for the elements of the vectors, encoded in "S", where 0->F16, 1->F32.
Where:
<dt> |
Is the data type for the elements of the vectors,
encoded in
S :
|
Advanced SIMD three registers of the same length extension<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T :
|
Advanced SIMD three registers of the same length extension<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 0->90, 1->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
|
Advanced SIMD and floating-point load/store+/-
Original text: Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in the "U" field, where 0->-, 1->+.
Where:
+/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
U :
|
Advanced SIMD and floating-point multiply with accumulate<bt>
Original text: Is the bottom or top element specifier, encoded in "T" where 0->B, 1->T.
Where:
<bt> |
Is the bottom or top element specifier,
encoded in
T :
|
Advanced SIMD and floating-point multiply with accumulate<rotate>
Original text: Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in "rot", where 00->0, 01->90, 10->180, 11->270.
Where:
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot :
rot | <rotate> |
---|
00 | 0 | 01 | 90 | 10 | 180 | 11 | 270 |
|
Internal version only: isa v01_09v01_06, pseudocode v8r-00bet0_rc1-199-g1970297v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T122019-12-12T17:2134
Copyright © 2010-2015 Arm Limited or its affiliates. All rights reserved.
This document is Non-Confidential.