PKHBT, PKHTB
Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | Rn | Rd | imm5 | tb | 0 | 1 | Rm |
cond | | | | | | | |
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); tbform = (tb == '1');
(shift_t, shift_n) = DecodeImmShift(tb:'0', imm5);
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | Rn | (0) | imm3 | Rd | imm2 | tb | 0 | Rm |
| | S | | | | | | | T | |
if S == '1' || T == '1' then UNDEFINED;
d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); tbform = (tb == '1');
(shift_t, shift_n) = DecodeImmShift(tb:'0', imm3:imm2);
if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Assembler Symbols
<Rd> | Is the general-purpose destination register, encoded in the "Rd" field. |
<Rn> | Is the first general-purpose source register, encoded in the "Rn" field. |
<Rm> | Is the second general-purpose source register, encoded in the "Rm" field. |
<imm> | For encoding A1: the shift to apply to the value read from <Rm>, encoded in the "imm5" field. Is one of: For PKHBT, it is one of: - omitted
- No shift, encoded as 0b00000.
- 1-31
- Left shift by specified number of bits, encoded as a binary number.
For PKHTB, it is one of: - omitted
- Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written.
- 1-32
- Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers.
An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly. |
| For encoding T1A1: the shift to apply to the value read from <Rm>, encoded in the "imm3:imm2imm5" field. Is one of: For PKHBT, it is one of: - omitted
- No shift, encoded as 0b00000.
- 1-31
- Left shift by specified number of bits, encoded as a binary number.
For PKHTB, it is one of: - omitted
- Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written.
- 1-32
- Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers.
An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly. |
| For encoding T1: the shift to apply to the value read from <Rm>, encoded in the "imm3:imm2" field.
For PKHBT, it is one of:
omittedNo shift, encoded as 0b00000.1-31Left shift by specified number of bits, encoded as a binary number.
For PKHTB, it is one of:
omittedInstruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn> had been written.1-32Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as 0b00000. Other shift amounts are encoded as binary numbers.
An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.
|
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand2 = Shift(R[m], shift_t, shift_n, PSTATE.C); // PSTATE.C ignored
R[d]<15:0> = if tbform then operand2<15:0> else R[n]<15:0>;
R[d]<31:16> = if tbform then R[n]<31:16> else operand2<31:16>;
Operational information
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
- The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
Internal version only: isa v01_09v01_06, pseudocode v8r-00bet0_rc1-199-g1970297v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T122019-12-12T17:2134
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