The TLBIALLNSNHIS characteristics are:
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk that would be required for stage 1 or stage 2 of the Non-secure PL1&0 translation regime, regardless of the associated VMID.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TLBIALLNSNHIS are UNKNOWN.
TLBIALLNSNHIS is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1000 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBIALLNSNHIS(); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then UNDEFINED; else TLBIALLNSNHIS();
14/04/2020 20:09; dff0d3e465311dd9ce541b6a1e1d6c05a0668645
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