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The ERRCRICR1 characteristics are:
Critical Error Interrupt configuration register.
This register is present only
when (the Critical Error Interrupt is implemented orand theinterrupt implementationconfiguration doesregisters not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented.
format.
Otherwise, direct accesses to ERRCRICR1 are RES0IMPLEMENTATION DEFINED.
ERRCRICR1 is implemented only as part of a memory-mapped group of error records.
ERRCRICR1 is a 32-bit register.
The ERRCRICR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
Payload for thea message signaled interrupt.
OnThe anfollowing Error recovery reset, this field resets to an architecturallyapply: UNKNOWN value.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
Component | Offset |
---|---|
RAS | 0xEA8 |
Accesses on this interface are RW.
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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