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The EDECR characteristics are:
Controls Halting debug events.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. FEAT_DoPD is implemented, this register is in the Core power domain.
If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain. FEAT_DoPD is not implemented, this register is in the Debug power domain.
EDECR is a 32-bit register.
The EDECR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SS | RCE | OSUCE |
Reserved, RES0.
Halting step enable. Possible values of this field are:
SS | Meaning |
---|---|
0b0 | Halting step debug event disabled. |
0b1 | Halting step debug event enabled. |
If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state'.
OnThe afollowing Cold reset, when FEAT_DoPD is implemented, this field resets toapply: 0.
On a Cold reset, this field resets to:
On an External debug reset, this field resets to:
On a Warm reset, the value of this field is unchanged.
On a Cold reset, when FEAT_DoPD is not implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is not implemented, this field resets to 0.
On a Warm reset, the value of this field is unchanged.
Reset Catch Enable.
RCE | Meaning |
---|---|
0b0 | Reset Catch debug event disabled. |
0b1 | Reset Catch debug event enabled. |
OnThe afollowing Cold reset, when FEAT_DoPD is implemented, this field resets toapply: 0.
On a Cold reset, this field resets to:
On an External debug reset, this field resets to:
On a Warm reset, the value of this field is unchanged.
On a Cold reset, when FEAT_DoPD is not implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is not implemented, this field resets to 0.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
OS Unlock Catch Enable.
OSUCE | Meaning |
---|---|
0b0 | OS Unlock Catch debug event disabled. |
0b1 | OS Unlock Catch debug event enabled. |
OnThe afollowing Cold reset, when FEAT_DoPD is implemented, this field resets toapply: 0.
On a Cold reset, this field resets to:
On an External debug reset, this field resets to:
On a Warm reset, the value of this field is unchanged.
On a Cold reset, when FEAT_DoPD is not implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is implemented, the value of this field is unchanged.
On an External debug reset, when FEAT_DoPD is not implemented, this field resets to 0.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
Debug | 0x024 | EDECR |
This interface is accessible as follows:
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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