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The AMCIDR0 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Component identification scheme'.
The power domain of AMCIDR0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
This register is present only
when AMUv1 is implemented.
Otherwise, direct accesses to AMCIDR0 are RES0.
AMCIDR0 is a 32-bit register.
The AMCIDR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_0 |
Reserved, RES0.
Preamble.
Preamble. Must read as 0x0D.
Reads as 0x0D.
Component | Offset | Instance |
---|---|---|
AMU | 0xFF0 | AMCIDR0 |
Accesses on this interface are RO.
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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