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The DISR_EL1 characteristics are:
Records that an SError interrupt has been consumed by an ESB instruction.
AArch64 System register DISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DISR[31:0] .
This register is present only
when FEAT_RASRAS is implemented.
Otherwise, direct accesses to DISR_EL1 are UNDEFINED.
DISR_EL1 is a 64-bit register.
The DISR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
A | RES0 | IDS | RES0 | AET | EA | RES0 | DFSC | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Set to 1 when an ESB instruction defers an asynchronous SError interrupt. If the implementation does not include any sources of SError interrupt that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Indicates the deferred SError interrupt type.
IDS | Meaning |
---|---|
0b0 | Deferred error uses architecturally-defined format. |
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Asynchronous Error Type. See the description of ESR_ELx.AET for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
External abort Type. See the description of ESR_ELx.EA for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault Status Code. See the description of ESR_ELx.DFSC for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
A | RES0 | IDS | ISS | ||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Set to 1 when an ESB instruction defers an asynchronous SError interrupt. If the implementation does not include any sources of SError interrupt that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Indicates the deferred SError interrupt type.
IDS | Meaning |
---|---|
0b1 | Deferred error uses IMPLEMENTATION DEFINED format. |
This field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED syndrome. See the description of ESR_ELx[23:0] for an SError interrupt.
This field resets to an architecturally UNKNOWN value.
An indirect write to DISR_EL1 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction.
DISR_EL1 is RAZ/WI if EL3 is implemented, the PE is in Non-debug state, SCR_EL3.EA == 1, and any of the following apply:
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
return VDISR_EL2;
else
return DISR_EL1;
elsif PSTATE.EL == EL2 then
return DISR_EL1;
elsif PSTATE.EL == EL3 then
return DISR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.AMO == '1' then
VDISR_EL2 = X[t];
else
DISR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
DISR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
DISR_EL1 = X[t];
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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