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The ID_MMFR5_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register ID_MMFR5_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR5[31:0] .
This register is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to ID_MMFR5_EL1 are UNKNOWN.
ID_MMFR5_EL1 is a 64-bit register.
The ID_MMFR5_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | ETS | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Support for Enhanced Translation Synchronization. Defined values are:
ETS | Meaning |
---|---|
0b0000 | Enhanced Translation Synchronization is not supported. |
0b0001 | Enhanced Translation Synchronization is supported. |
All other values are reserved.
FEAT_ETSARMv8.0-ETS implements the functionality identified by the value 0b0001.
From Armv8.0, the permitted values are 0b0000 and 0b0001.
Accesses to this register use the following encodings:
if PSTATE.EL == EL0 then
if IsFeatureImplemented("ARMv8.4-IDST") then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_MMFR5_EL1) || boolean IMPLEMENTATION_DEFINED "ID_MMFR5_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_MMFR5_EL1;
elsif PSTATE.EL == EL2 then
return ID_MMFR5_EL1;
elsif PSTATE.EL == EL3 then
return ID_MMFR5_EL1;
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
UNKNOWN | |||||||||||||||||||||||||||||||
UNKNOWN | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, UNKNOWN.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0011 | 0b110 |
if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!IsZero(ID_MMFR5_EL1) || boolean IMPLEMENTATION_DEFINED "ID_MMFR5_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_MMFR5_EL1; elsif PSTATE.EL == EL2 then return ID_MMFR5_EL1; elsif PSTATE.EL == EL3 then return ID_MMFR5_EL1;
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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