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The MVFR2 characteristics are:
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0 and MVFR1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register MVFR2 bits [31:0] are architecturally mapped to AArch64 System register MVFR2_EL1[31:0] .
This register is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to MVFR2 are UNDEFINEDUNKNOWN.
Implemented only if the implementation includes Advanced SIMD and floating-point instructions.
MVFR2 is a 32-bit register.
The MVFR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FPMisc | SIMDMisc |
Reserved, RES0.
Indicates whether the floating-point implementation provides support for miscellaneous VFP features.
FPMisc | Meaning |
---|---|
0b0000 | Not implemented, or no support for miscellaneous features. |
0b0001 | Support for Floating-point selection. |
0b0010 | As 0b0001, and Floating-point Conversion to Integer with Directed Rounding modes. |
0b0011 | As 0b0010, and Floating-point Round to Integer Floating-point. |
0b0100 | As 0b0011, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0100.
Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features.
SIMDMisc | Meaning |
---|---|
0b0000 | Not implemented, or no support for miscellaneous features. |
0b0001 | Floating-point Conversion to Integer with Directed Rounding modes. |
0b0010 | As 0b0001, and Floating-point Round to Integer Floating-point. |
0b0011 | As 0b0010, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0011.
Accesses to this register use the following encodings:
reg |
---|
0b0101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if ELUsingAArch32(EL1) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || CPACR.cp10 == '00'') then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H != '1' && CPTR_EL2.TFP == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x07);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
AArch64.AArch32SystemAccessTrap(EL2, 0x07);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
AArch32.TakeHypTrapException(0x08);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x08);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then
AArch32.TakeHypTrapException(0x08);
else
return MVFR2;
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x07);
elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then
AArch64.AArch32SystemAccessTrap(EL2, 0x07);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ((ELUsingAArch32(EL3) && SCR.NS == '1' && NSACR.cp10 == '0') || HCPTR.TCP10 == '1') then
AArch32.TakeHypTrapException(0x00);
else
return MVFR2;
elsif PSTATE.EL == EL3 then
if CPACR.cp10 == '00' then
UNDEFINED;
else
return MVFR2;
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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