The ERRCRICR0 characteristics are:
Critical Error Interrupt configuration register.
This register is present only when the Critical Error Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRCRICR0 are IMPLEMENTATION DEFINED.
ERRCRICR0 is implemented only as part of a memory-mapped group of error records.
ERRCRICR0 is a 64-bit register.
The ERRCRICR0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | ADDR | ||||||||||||||||||||||||||||||
ADDR | RES0 | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Message Signaled Interrupt address. Specifies the address that the component writes to when signaling an interrupt.
The size of a physical address is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.
The following resets apply:
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Component | Offset |
---|---|
RAS | 0xEA0 |
Accesses on this interface are RW.
14/04/2020 20:09; dff0d3e465311dd9ce541b6a1e1d6c05a0668645
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