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The EDCIDSR characteristics are:
Contains the sampled value of the Context ID, captured on reading EDPCSR[31:0].
EDCIDSR is in the Core power domain.
This register is present only
when FEAT_PCSRv8ARMv8.0-PCSample is implemented and FEAT_PCSRv8p2ARMv8.2-PCSample is not implemented.
Otherwise, direct accesses to EDCIDSR are RES0.
Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space.
FEAT_PCSRv8p2ARMv8.2-PCSample implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.
EDCIDSR is a 32-bit register.
The EDCIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR |
Context ID. The value of CONTEXTIDR that is associated with the most recent EDPCSR sample. When the most recent EDPCSR sample was generated:
Because the value written to EDCIDSR is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether EDCIDSR is set to the original or new value if EDPCSR samples:
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance |
---|---|---|
Debug | 0x0A4 | EDCIDSR |
This interface is accessible as follows:
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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