The ERRCRICR1 characteristics are:
Critical Error Interrupt configuration register.
This register is present only when the Critical Error Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRCRICR1 are IMPLEMENTATION DEFINED.
ERRCRICR1 is implemented only as part of a memory-mapped group of error records.
ERRCRICR1 is a 32-bit register.
The ERRCRICR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
Payload for a message signaled interrupt.
The following resets apply:
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Component | Offset |
---|---|
RAS | 0xEA8 |
Accesses on this interface are RW.
14/04/2020 20:09; dff0d3e465311dd9ce541b6a1e1d6c05a0668645
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