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The CP15DSB characteristics are:
Performs a Data Synchronization Barrier.
Arm deprecates any use of this System instruction, and strongly recommends that software use the DSB instruction instead.
This instruction is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to CP15DSB are UNDEFINEDUNKNOWN.
CP15DSB is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b1010 | 0b100 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.CP15BEN == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.CP15BEN == '0' then
UNDEFINED;
elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
else
CP15DSB();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15DSB();
elsif PSTATE.EL == EL2 then
if HSCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15DSB();
elsif PSTATE.EL == EL3 then
if SCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15DSB();
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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