(old) | htmldiff from- | (new) |
The DBGBCR<n> characteristics are:
Holds control information for a breakpoint. Forms breakpoint n together with value register DBGBVR<n>. If EL2 is implemented and this breakpoint supports Context matching, DBGBVR<n> can be associated with a Breakpoint Extended Value Register DBGBXVR<n> for VMID matching.
AArch32 System register DBGBCR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGBCR<n>_EL1[31:0] .
AArch32 System register DBGBCR<n> bits [31:0] are architecturally mapped to External register DBGBCR<n>_EL1[31:0] .
This register is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to DBGBCR<n> are UNDEFINEDUNKNOWN.
If breakpoint n is not implemented then accesses to this register are UNDEFINED.
DBGBCR<n> is a 32-bit register.
The DBGBCR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | BT | LBN | SSC | HMC | RES0 | BAS | RES0 | PMC | E |
When the E field is zero, all the other fields in the register are ignored.
Reserved, RES0.
Breakpoint Type. Possible values are:
BT | Meaning |
---|---|
0b0000 | Unlinked instruction address match. DBGBVR<n> is the address of an instruction. |
0b0001 | As 0b0000 with linking enabled. |
0b0010 | Unlinked Context ID match. When |
0b0011 | As 0b0010 with linking enabled. |
0b0100 | Unlinked instruction address mismatch. DBGBVR<n> is the address of an instruction to be stepped. |
0b0101 | As 0b0100 with linking enabled. |
0b0110 | Unlinked CONTEXTIDR_EL1 match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR. |
0b0111 | As 0b0110 with linking enabled. |
0b1000 | Unlinked VMID match. DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID. |
0b1001 | As 0b1000 with linking enabled. |
0b1010 | Unlinked VMID and Context ID match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR, and DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID. |
0b1011 | As 0b1010 with linking enabled. |
0b1100 | Unlinked CONTEXTIDR_EL2 match. DBGBXVR<n>.ContextID2 is a Context ID compared against CONTEXTIDR_EL2. |
0b1101 | As 0b1100 with linking enabled. |
0b1110 | Unlinked Full Context ID match. DBGBVR<n>.ContextID is compared against CONTEXTIDR, and DBGBXVR<n>.ContextID2 is compared against CONTEXTIDR_EL2. |
0b1111 | As 0b1110 with linking enabled. |
For more information on Breakpoints and their constraints, see 'Breakpoint exceptions' and 'Reserved DBGBCR<n>.BT values'.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
For all other breakpoint types this field is ignored and reads of the register return an UNKNOWN value.
This field is ignored when the value of DBGBCR<n>.E is 0.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields.
For more information, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>.{SSC, HMC, PMC} values'.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the SSC, bits [15:14] description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and Execution state.
The permitted values depend on the breakpoint type.
For Address match breakpoints, the permitted values are:
BAS | Match instruction at | Constraint for debuggers |
---|---|---|
0b0011 | DBGBVR<n> | Use for T32 instructions |
0b1100 | DBGBVR<n>+2 | Use for T32 instructions |
0b1111 | DBGBVR<n> | Use for A32 instructions |
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in Address Match breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Address mismatch breakpoints in an AArch32 stage 1 translation regime, the permitted values are:
BAS | Step instruction at | Constraint for debuggers |
---|---|---|
0b0000 | - | Use for a match anywhere breakpoint |
0b0011 | DBGBVR<n> | Use for T32 instructions |
0b1100 | DBGBVR<n>+2 | Use for T32 instructions |
0b1111 | DBGBVR<n> | Use for A32 instructions |
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in address mismatch breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Context matching breakpoints, this field is RES1 and ignored.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Enable breakpoint DBGBVR<n>. Possible values are:
E | Meaning |
---|---|
0b0 | Breakpoint disabled. |
0b1 | Breakpoint enabled. |
OnThe afollowing Cold reset, this field resets to an architecturallyapply: UNKNOWN value.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then
AArch32.TakeHypTrapException(0x05);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x05);
elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
return DBGBCR[UInt(CRm<3:0>)];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x05);
elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
return DBGBCR[UInt(CRm<3:0>)];
elsif PSTATE.EL == EL3 then
if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
return DBGBCR[UInt(CRm<3:0>)];
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | n[3:0] | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then
AArch32.TakeHypTrapException(0x05);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x05);
elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR[UInt(CRm<3:0>)] = R[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x05);
elsif ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR[UInt(CRm<3:0>)] = R[t];
elsif PSTATE.EL == EL3 then
if ELUsingAArch32(EL1) && DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
DBGBCR[UInt(CRm<3:0>)] = R[t];
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |