ERRCRICR1, Critical Error Interrupt Configuration Register 1

The ERRCRICR1 characteristics are:

Purpose

Critical Error Interrupt configuration register.

Configuration

This register is present only when the Critical Error Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRCRICR1 are IMPLEMENTATION DEFINED.

ERRCRICR1 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRCRICR1 is a 32-bit register.

Field descriptions

The ERRCRICR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
DATA

DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

Accessing the ERRCRICR1

ERRCRICR1 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xEA8

Accesses on this interface are RW.




14/04/2020 20:09; dff0d3e465311dd9ce541b6a1e1d6c05a0668645

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