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The ID_ISAR4 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_ISAR4 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR4_EL1[31:0] .
This register is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to ID_ISAR4 are UNDEFINEDUNKNOWN.
ID_ISAR4 is a 32-bit register.
The ID_ISAR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWP_frac | PSR_M | SynchPrim_frac | Barrier | SMC | Writeback | WithShifts | Unpriv |
Indicates support for the memory system locking the bus for SWP or SWPB instructions. Defined values are:
SWP_frac | Meaning |
---|---|
0b0000 | SWP or SWPB instructions not implemented. |
0b0001 | SWP or SWPB implemented but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other Requesters |
All other values are reserved. This field is valid only if ID_ISAR0.Swap is 0b0000.
In Armv8-A, the only permitted value is 0b0000.
Indicates the implemented M profile instructions to modify the PSRs. Defined values are:
PSR_M | Meaning |
---|---|
0b0000 | None implemented. |
0b0001 | Adds the M profile forms of the CPS, MRS, and MSR instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions. Possible values are:
SynchPrim_frac | Meaning |
---|---|
0b0000 | If SynchPrim == 0b0000, no Synchronization Primitives implemented. If SynchPrim == 0b0001, adds the LDREX and STREX instructions. If SynchPrim == 0b0010, also adds the CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and STREXD instructions. |
0b0011 | If SynchPrim == 0b0001, adds the LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions. |
All other combinations of SynchPrim and SynchPrim_frac are reserved.
In Armv8-A, the only permitted value is 0b0000.
Indicates the implemented Barrier instructions in the A32 and T32 instruction sets. Defined values are:
Barrier | Meaning |
---|---|
0b0000 | None implemented. Barrier operations are provided only as System instructions in the (coproc==0b1111) encoding space. |
0b0001 | Adds the DMB, DSB, and ISB barrier instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Indicates the implemented SMC instructions. Defined values are:
SMC | Meaning |
---|---|
0b0000 | None implemented. |
0b0001 | Adds the SMC instruction. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Indicates the support for Writeback addressing modes. Defined values are:
Writeback | Meaning |
---|---|
0b0000 | Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support writeback addressing modes. These instructions support all of their writeback addressing modes. |
0b0001 | Adds support for all of the writeback addressing modes. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Indicates the support for instructions with shifts. Defined values are:
WithShifts | Meaning |
---|---|
0b0000 | Nonzero shifts supported only in MOV and shift instructions. |
0b0001 | Adds support for shifts of loads and stores over the range LSL 0-3. |
0b0011 | As for 0b0001, and adds support for other constant shift options, both on load/store and other instructions. |
0b0100 | As for 0b0011, and adds support for register-controlled shift options. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0100.
Indicates the implemented unprivileged instructions. Defined values are:
Unpriv | Meaning |
---|---|
0b0000 | None implemented. No T variant instructions are implemented. |
0b0001 | Adds the LDRBT, LDRT, STRBT, and STRT instructions. |
0b0010 | As for 0b0001, and adds the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR4; elsif PSTATE.EL == EL2 then return ID_ISAR4; elsif PSTATE.EL == EL3 then return ID_ISAR4;
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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