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The MAIR0 characteristics are:
Along with MAIR1, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
AttrIndx[2] indicates the MAIR register to be used:
AArch32 System register MAIR0 bits [31:0]
are architecturally mapped to
AArch64 System register MAIR_EL1[31:0]
when EL3TTBCR.EAE is== not implemented or EL3 is using AArch64.1.
AArch32 System register MAIR0 bits [31:0] are architecturally mapped to AArch32 System register PRRR[31:0] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register MAIR0 bits [31:0] (MAIR0_NS) are architecturally mapped to AArch32 System register PRRR[31:0] (PRRR_NS) when EL3 is using AArch32.
AArch32 System register MAIR0 bits [31:0] (MAIR0_S) are architecturally mapped to AArch32 System register PRRR[31:0] (PRRR_S) when EL3 is using AArch32.
This register is present only
when AArch32 is supported at any Exception level.
Otherwise, direct accesses to MAIR0 are UNDEFINEDUNKNOWN.
MAIR0 and PRRR are the same register, with a different view depending on the value of TTBCR.EAE:
When EL3 is using AArch32, write access to MAIR0(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
MAIR0 is a 32-bit register.
The MAIR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Attr3 | Attr2 | Attr1 | Attr0 |
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
Bits [7:4] are encoded as follows:
Attr<n>[7:4] | Meaning |
---|---|
0b0000 | Device memory. See encoding of Attr<n>[3:0] for the type of Device memory. |
0b00RW, RW not0b00 | Normal memory, Outer Write-Through Transient. |
0b0100 | Normal memory, Outer Non-cacheable. |
0b01RW, RW not0b00 | Normal memory, Outer Write-Back Transient. |
0b10RW | Normal memory, Outer Write-Through Non-transient. |
0b11RW | Normal memory, Outer Write-Back Non-transient. |
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
The meaning of bits [3:0] depends on the value of bits [7:4]:
Attr<n>[3:0] | Meaning when Attr<n>[7:4] is0b0000 | Meaning when Attr<n>[7:4] is not0b0000 |
---|---|---|
0b0000 | Device-nGnRnE memory | UNPREDICTABLE |
0b00RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Through Transient |
0b0100 | Device-nGnRE memory | Normal memory, Inner Non-cacheable |
0b01RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Back Transient |
0b1000 | Device-nGRE memory | Normal memory, Inner Write-Through Non-transient (RW=0b00) |
0b10RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Through Non-transient |
0b1100 | Device-GRE memory | Normal memory, Inner Write-Back Non-transient (RW=0b00) |
0b11RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Back Non-transient |
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in some Attr<n> fields have the following meanings:
R or W | Meaning |
---|---|
0b0 | No Allocate |
0b1 | Allocate |
This field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
return MAIR0_NS;
else
return PRRR_NS;
else
if TTBCR.EAE == '1' then
return MAIR0;
else
return PRRR;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
return MAIR0_NS;
else
return PRRR_NS;
else
if TTBCR.EAE == '1' then
return MAIR0;
else
return PRRR;
elsif PSTATE.EL == EL3 then
if TTBCR.EAE == '1' then
if SCR.NS == '0' then
return MAIR0_S;
else
return MAIR0_NS;
else
if SCR.NS == '0' then
return PRRR_S;
else
return PRRR_NSMAIR0_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
MAIR0_NS = R[t];
else
PRRR_NS = R[t];
else
if TTBCR.EAE == '1' then
MAIR0 = R[t];
else
PRRR = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
MAIR0_NS = R[t];
else
PRRR_NS = R[t];
else
if TTBCR.EAE == '1' then
MAIR0 = R[t];
else
PRRR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
if TTBCR.EAE == '1' then
if SCR.NS == '0' then
MAIR0_S = R[t];
else
MAIR0_NS = R[t];
else
if SCR.NS == '0' then
PRRR_S = R[t];
else
PRRR_NSMAIR0_NS = R[t];
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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