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The PMAUTHSTATUS characteristics are:
Provides information about the state of the IMPLEMENTATION DEFINED authentication interface for Performance Monitors.
If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain. FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is OPTIONAL, and is required for CoreSight compliance. Arm recommends that this register is implemented.
PMAUTHSTATUS is a 32-bit register.
The PMAUTHSTATUS bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SNID | SID | NSNID | NSID |
Reserved, RES0.
Holds the same value as DBGAUTHSTATUS_EL1.SNID.
Secure invasive debug. Possible values of this field are:
SID | Meaning |
---|---|
0b00 | Not implemented. |
All other values are reserved.
Holds the same value as DBGAUTHSTATUS_EL1.NSNID.
Non-secure invasive debug. Possible values of this field are:
NSID | Meaning |
---|---|
0b00 | Not implemented. |
All other values are reserved.
Component | Offset | Instance |
---|---|---|
PMU | 0xFB8 | PMAUTHSTATUS |
This interface is accessible as follows:
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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