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The AMDEVARCH characteristics are:
Identifies the programmers' model architecture of the AMU component.
The power domain of AMDEVARCH is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
This register is present only
when AMUv1 is implemented.
Otherwise, direct accesses to AMDEVARCH are RES0.
AMDEVARCH is a 32-bit register.
The AMDEVARCH bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For AMU, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
When set to 1, indicates that the DEVARCH is present.
This field is 1 in Armv8.
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
REVISION | Meaning |
---|---|
0b0000 | Architecture revision is AMUv1. |
All other values are reserved.
Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.
For AMU:
This corresponds to AMU architecture version AMUv1.
Component | Offset | Instance |
---|---|---|
AMU | 0xFBC | AMDEVARCH |
Accesses on this interface are RO.
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
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