The ID_PFR0 characteristics are:
Gives top-level information about the instruction sets and other features supported by the PE in AArch32 state.
Must be interpreted with ID_PFR1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'
AArch32 System register ID_PFR0 bits [31:0] are architecturally mapped to AArch64 System register ID_PFR0_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_PFR0 are UNKNOWN.
ID_PFR0 is a 32-bit register.
The ID_PFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAS | DIT | AMU | CSV2 | State3 | State2 | State1 | State0 |
RAS Extension version. Defined values are:
RAS | Meaning |
---|---|
0b0000 |
No RAS Extension. |
0b0001 |
RAS Extension present. |
0b0010 |
ARMv8.4-RAS present. As 0b0001, and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. |
All other values are reserved.
In Armv8.1 and Armv8.0, the permitted values are 0b0000 and 0b0001.
In Armv8.2, the only permitted value is 0b0001.
From Armv8.4, when ARMv8.4-DFE is not implemented, and ERRIDR.NUM is 0, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010. Otherwise, from Armv8.4, the only permitted value is 0b0010.
ARMv8.4-RAS implements the functionality identified by the value 0b0010.
Data Independent Timing. Defined values are:
DIT | Meaning |
---|---|
0b0000 |
AArch32 does not guarantee constant execution time of any instructions. |
0b0001 |
AArch32 provides the CPSR.DIT mechanism to guarantee constant execution time of certain instructions. |
All other values are reserved.
ARMv8.4-DIT implements the functionality identified by the value 0b0001.
From Armv8.4, the only permitted value is 0b0001.
Activity Monitors Extension. Defined values are:
AMU | Meaning |
---|---|
0b0000 |
Activity Monitors Extension is not implemented. |
0b0001 |
AMUv1 for Armv8.4 is implemented. |
0b0010 |
AMUv1 for Armv8.6 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. |
All other values are reserved.
AMUv1 implements the functionality identified by the value 0b0001.
ARMv8.6-AMU implements the functionality identified by the value 0b0010.
Speculative use of out of context branch targets. Defined values are:
CSV2 | Meaning |
---|---|
0b0000 |
This Device does not disclose whether branch targets trained in one hardware described context can affect speculative execution in a different hardware described context. |
0b0001 |
Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. |
All other values are reserved.
ARMv8.0-CSV2 implements the functionality identified by 0b0001.
From Armv8.5, the only permitted value is 0b0001.
T32EE instruction set support. Defined values are:
State3 | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
T32EE instruction set implemented. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0000.
Jazelle extension support. Defined values are:
State2 | Meaning |
---|---|
0b0000 |
Not implemented. |
0b0001 |
Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. |
0b0010 |
Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
T32 instruction set support. Defined values are:
State1 | Meaning |
---|---|
0b0000 |
T32 instruction set not implemented. |
0b0001 |
T32 encodings before the introduction of Thumb-2 technology implemented:
|
0b0011 |
T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0011.
A32 instruction set support. Defined values are:
State0 | Meaning |
---|---|
0b0000 |
A32 instruction set not implemented. |
0b0001 |
A32 instruction set implemented. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_PFR0; elsif PSTATE.EL == EL2 then return ID_PFR0; elsif PSTATE.EL == EL3 then return ID_PFR0;
14/04/2020 20:09; dff0d3e465311dd9ce541b6a1e1d6c05a0668645
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