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The ID_AA64PFR1_EL1 characteristics are:
Reserved for future expansion of information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
There are no configuration notes.
ID_AA64PFR1_EL1 is a 64-bit register.
The ID_AA64PFR1_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT | ||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
MPAM Extension fractional field. Defined values are:
MPAM_frac | Meaning |
---|---|
0b0000 | If ID_AA64PFR0_EL1.MPAM == 0b0000, MPAM Extension not implemented. If ID_AA64PFR0_EL1.MPAM == 0b0001, MPAM Extension v1.0 |
0b0001 | If ID_AA64PFR0_EL1.MPAM == 0b0000, implements MPAM v0.1, If ID_AA64PFR0_EL1.MPAM == 0b0001, implements MPAM v1.1 |
All other values are reserved.
RAS Extension fractional field. Defined values are:
RAS_frac | Meaning |
---|---|
0b0000 | If ID_AA64PFR0_EL1.RAS == 0b0001, RAS Extension implemented. |
0b0001 | If ID_AA64PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for:
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions. |
All other values are reserved.
FEAT_RASv1p1 implements the functionality identified by the value 0b0001.
This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.
Support for the Memory Tagging Extension. Defined values are:
MTE | Meaning |
---|---|
0b0000 | Memory Tagging Extension is not implemented. |
0b0001 | Memory Tagging Extension instructions accessible at EL0 are implemented. Instructions and System Registers defined by the extension not configurably accessible at EL0 are Unallocated and other System Register fields defined by the extension are RES0. |
0b0010 | Memory Tagging Extension is implemented. |
All other values are reserved.
FEAT_MTEARMv8.5-MemTag implements the functionality identified by the value 0b0001.
When ID_AA64PFR1_EL1.MTE <!= 0b0010:
All register fields added to existing System registers and Special-purpose registers as part of the extension are RES0, and treated as 0.
The following System registers are UNDEFINED:
The following System instructions are UNDEFINED:
The following instructions are UNDEFINED:
The Tagged memory type encoding in MAIR_ELx is UNPREDICTABLE.
Speculative Store Bypassing controls in AArch64 state. Defined values are:
SSBS | Meaning |
---|---|
0b0000 | AArch64 provides no mechanism to control the use of Speculative Store Bypassing. |
0b0001 | AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. |
0b0010 | AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypassing Safe, and the MSR and MRS instructions to directly read and write the PSTATE.SSBS field. |
All other values are reserved.
FEAT_SSBS implements the functionality identified by the value 0b0001.
FEAT_SSBS2 implements the functionality identified by the value 0b0010.
Branch Target Identification mechanism support in AArch64 state. Defined values are:
BT | Meaning |
---|---|
0b0000 | The Branch Target Identification mechanism is not implemented. |
0b0001 | The Branch Target Identification mechanism is implemented. |
All other values are reserved.
FEAT_BTIARMv8.5-BTI implements the functionality identified by the value 0b0001.
From Armv8.5, the only permitted value is 0b0001.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0100 | 0b001 |
if PSTATE.EL == EL0 then
if IsFeatureImplemented("FEAT_IDSTARMv8.4-IDST") then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL2 then
return ID_AA64PFR1_EL1;
elsif PSTATE.EL == EL3 then
return ID_AA64PFR1_EL1;
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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