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The TRFCR characteristics are:
Provides EL1 controls for Trace.
AArch32 System register TRFCR bits [31:0] are architecturally mapped to AArch64 System register TRFCR_EL1[31:0] .
This register is present only
when AArch32 is supported at any Exception level and FEAT_TRFARMv8.4-Trace is implemented.
Otherwise, direct accesses to TRFCR are UNDEFINED.
TRFCR is a 32-bit register.
The TRFCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | TS | RES0 | E1TRE | E0TRE |
Reserved, RES0.
Timestamp Control. Controls which timebase is used for trace timestamps.
TS | Meaning | Applies when |
---|---|---|
0b01 | Virtual timestamp. The traced timestamp is the physical counter value, minus the value of CNTVOFF. | |
0b10 | Guest Physical timestamp. The traced timestamp is the physical counter value, minus the value of CNTPOFF_EL2. | When FEAT_ECV |
0b11 | Physical timestamp. The traced timestamp is the physical counter value. |
All other values are reserved.
This field is ignored if any of the following are true:
If FEAT_ECVARMv8.6-ECV is implemented, the physical counter uses a fixed physical offset of zero if any of the following are true:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
EL1 Trace Enable.
E1TRE | Meaning |
---|---|
0b0 | Tracing is prohibited in PL1 modes. |
0b1 | Tracing is allowed in PL1 modes. |
This field is ignored if SelfHostedTraceEnabled() == FALSE.
On a Warm reset, this field resets to 0.
EL0 Trace Enable.
E0TRE | Meaning |
---|---|
0b0 | Tracing is prohibited at EL0. |
0b1 | Tracing is allowed at EL0. |
This field is ignored if any of the following are true:
On a Warm reset, this field resets to 0.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif SCR.NS == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TTRF == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
return TRFCR;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
return TRFCR;
elsif PSTATE.EL == EL3 then
if PSTATE.MSCR.NS != M32_Monitor && SDCR.TTRF == '10' then
AArch32.TakeMonitorTrapException();UNDEFINED;
else
return TRFCR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif SCR.NS == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TTRF == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
TRFCR = R[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
TRFCR = R[t];
elsif PSTATE.EL == EL3 then
if PSTATE.MSCR.NS != M32_Monitor && SDCR.TTRF == '10' then
AArch32.TakeMonitorTrapException();UNDEFINED;
else
TRFCR = R[t];
0114/0704/2020 1520:5709; 80324f0b9997bede489cc15ad1565345720bcd2adff0d3e465311dd9ce541b6a1e1d6c05a0668645
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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