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This instruction determines the floating-point maximum number.
It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMAX.
This instruction is not conditional.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 0 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | Q | M | 1 | Vm | |||||||||
op |
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !HaveFP16Ext() then UNDEFINED; maximum = (op == '0'); advsimd = TRUE; case sz of when '0' esize = 32; elements = 2; when '1' esize = 16; elements = 4; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 0 | 0 | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm | ||||||||||
size | op |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; advsimd = FALSE; maximum = (op == '0'); case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 0 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | Q | M | 1 | Vm | |||||||||
op |
if InITBlock() then UNPREDICTABLE; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !HaveFP16Ext() then UNDEFINED; maximum = (op == '0'); advsimd = TRUE; case sz of when '0' esize = 32; elements = 2; when '1' esize = 16; elements = 4; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
If InITBlock(), then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 0 | 0 | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm | ||||||||||
size | op |
VMAXNM{<q>}.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; advsimd = FALSE; maximum = (op == '0'); case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
If InITBlock(), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<q> |
<dt> |
Is the data type for the elements of the vectors,
encoded in
sz:
|
<Qd> | Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> | Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Qm> | Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> | Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sn> | Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
<Sm> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. |
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[n+r], e, esize]; op2 = Elem[D[m+r], e, esize];
if maximum then
Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, StandardFPSCRValue());
else
Elem[D[d+r], e, esize] = FPMinNum(op1, op2, StandardFPSCRValue());
else // VFP instruction
case esize of
when 16
if maximum then
S[d] = Zeros(16) : FPMaxNum(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
[m]<15:0>, FPSCR);
else
S[d] = Zeros(16) : FPMinNum(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
[m]<15:0>, FPSCR);
when 32
if maximum then
S[d] = FPMaxNum(S[n], S[m], FPSCR[]);
[m], FPSCR);
else
S[d] = FPMinNum(S[n], S[m], FPSCR[]);
[m], FPSCR);
when 64
if maximum then
D[d] = FPMaxNum(D[n], D[m], FPSCR[]);
[m], FPSCR);
else
D[d] = FPMinNum(D[n], D[m], FPSCR[]);[m], FPSCR);
Internal version only: isa v01_19v01_15, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06-29-gc9614a3
; Build timestamp: 2020-09-30T212020-07-03T11:3536
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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