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Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C, V} Condition flags by a subsequent VMRS instruction.
ThisIt instruction raises an Invalid Operation floating-point exception only if either or both of the operandsoperand is a signaling NaN.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 0 | Vd | 1 | 0 | size | 0 | 1 | M | 0 | Vm | ||||||||||
cond | E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = FALSE; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
If size == '01' && cond != '1110', then one of the following behaviors must occur:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 1 | Vd | 1 | 0 | size | 0 | 1 | (0) | 0 | (0) | (0) | (0) | (0) | |||||||
cond | E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = TRUE; case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
If size == '01' && cond != '1110', then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 0 | Vd | 1 | 0 | size | 0 | 1 | M | 0 | Vm | |||||||
E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = FALSE; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);
If size == '01' && InITBlock(), then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 1 | 0 | 1 | Vd | 1 | 0 | size | 0 | 1 | (0) | 0 | (0) | (0) | (0) | (0) | ||||
E |
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; quiet_nan_exc = (E == '1'); with_zero = TRUE; case size of when '01' esize = 16; d = UInt(Vd:D); when '10' esize = 32; d = UInt(Vd:D); when '11' esize = 64; d = UInt(D:Vd);
If size == '01' && InITBlock(), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
<Sm> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dm> | Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
bits(4) nzcv;
case esize of
when 16
bits(16) op16 = if with_zero then FPZero('0') else S[m]<15:0>;
nzcv = FPCompare(S[d]<15:0>, op16, quiet_nan_exc, FPSCR);
when 32
bits(32) op32 = if with_zero then FPZero('0') else S[m];
nzcv = FPCompare(S[d], op32, quiet_nan_exc, FPSCR);
when 64
bits(64) op64 = if with_zero then FPZero('0') else D[m];
nzcv = FPCompare(D[d], op64, quiet_nan_exc, FPSCR);
FPSCR<31:28> = nzcv; // FPSCR.<N,Z,C,V> set to nzcv FPSCR.<N,Z,C,V> = nzcv;
The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If eitherCPSR.DIT or both of the operands is a1 NaN, they are unordered, and allthis threeinstruction ofpasses (Operand1its <condition Operand2),execution (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets thecheck: FPSCR condition flags to N=0, Z=0, C=1, and V=1. If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_15v01_09, pseudocode 2020-06_relv8r-00bet0_rc1-199-g1970297, sve v2020-06-29-gc9614a3v2020-03_rc1
; Build timestamp: 2020-07-03T112020-04-15T12:3621
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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