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Store single 4-element structure from one lane of four registers stores one 4-element structure to memory from corresponding elements of four registers. For details of the addressing mode see Advanced SIMD addressing mode.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | D | 0 | 0 | Rn | Vd | 1 | 0 | 1 | 1 | index_align | 1 | 1 | 1 | 1 | |||||||||
size | Rm |
if size == '11' then UNDEFINED; if size != '10' then SEE "Related encodings"; if index_align<1:0> == '11' then UNDEFINED; ebytes = 4; index = UInt(index_align<3>); inc = if index_align<2> == '0' then 1 else 2; alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>); d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; d4 = d3 + inc; n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d4 > 31 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST4 (single 4-element structure from one lane).
<c> | See Standard assembler syntax fields. This encoding must be unconditional. |
<q> |
<size> |
Is the data size,
encoded in
size:
|
<Rn> | Is the general-purpose base register, encoded in the "Rn" field. |
<align> | Is the optional alignment. Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and the encoding depends on <size>:
Whenever <align> is present, the permitted values and encoding depend on <size>:
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode. |
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; iswrite = TRUE; - = AArch32.CheckAlignment(address, alignment, AccType_VEC, iswrite); MemU[address, ebytes] = Elem[D[d], index]; MemU[address+ebytes, ebytes] = Elem[D[d2],index]; MemU[address+2*ebytes,ebytes] = Elem[D[d3],index]; MemU[address+3*ebytes,ebytes] = Elem[D[d4],index]; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 4*ebytes;
Internal version only: isa v01_09, pseudocode v8r-00bet0_rc1-199-g1970297, sve v2020-03_rc1 ; Build timestamp: 2020-04-15T12:21
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