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Move to Register from Banked or Special register moves the value from the Banked general-purpose register or Saved Program Status Registers (SPSRs) of the specified mode, or the value of ELR_hyp, to a general-purpose register.
MRS (Banked register) is unpredictable if executed in User mode.
When EL3 is using AArch64, if an MRS (Banked register) instruction that is executed in a Secure EL1 mode would access SPSR_mon, SP_mon, or LR_mon, it is trapped to EL3.
The effect of using an MRS (Banked register) instruction with a register argument that is not valid for the current mode is unpredictable. For more information see Usage restrictions on the Banked register transfer instructions.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 0 | R | 0 | 0 | M1 | Rd | (0) | (0) | 1 | M | 0 | 0 | 0 | 0 | (0) | (0) | (0) | (0) | |||||||||
cond |
MRS{<c>}{<q>} <Rd>, <banked_reg>
d = UInt(Rd); read_spsr = (R == '1'); if d == 15 then UNPREDICTABLE; SYSm = M:M1;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | R | M1 | 1 | 0 | (0) | 0 | Rd | (0) | (0) | 1 | M | (0) | (0) | (0) | (0) |
MRS{<c>}{<q>} <Rd>, <banked_reg>
d = UInt(Rd); read_spsr = (R == '1'); if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 SYSm = M:M1;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
<Rd> | Is the general-purpose destination register, encoded in the "Rd" field. |
if ConditionPassed() then
EncodingSpecificOperations();
if PSTATE.EL == EL0 then
UNPREDICTABLE;
else
mode = PSTATE.M;
if read_spsr then
SPSRaccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
case SYSm of
when '01110' R[d] = SPSR_fiq<31:0>;
[d] = SPSR_fiq;
when '10000' R[d] = SPSR_irq<31:0>;
[d] = SPSR_irq;
when '10010' R[d] = SPSR_svc<31:0>;
[d] = SPSR_svc;
when '10100' R[d] = SPSR_abt<31:0>;
[d] = SPSR_abt;
when '10110' R[d] = SPSR_und<31:0>;
[d] = SPSR_und;
when '11100'
if !ELUsingAArch32(EL3) then AArch64.MonitorModeTrap();
R[d] = SPSR_mon;
when '11110' R[d] = SPSR_hyp<31:0>;
[d] = SPSR_hyp;
else
BankedRegisterAccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
case SYSm of
when '00xxx' // Access the User mode registers
m = UInt(SYSm<2:0>) + 8;
R[d] = Rmode[m,M32_User];
when '01xxx' // Access the FIQ mode registers
m = UInt(SYSm<2:0>) + 8;
R[d] = Rmode[m,M32_FIQ];
when '1000x' // Access the IRQ mode registers
m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
R[d] = Rmode[m,M32_IRQ];
when '1001x' // Access the Supervisor mode registers
m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
R[d] = Rmode[m,M32_Svc];
when '1010x' // Access the Abort mode registers
m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
R[d] = Rmode[m,M32_Abort];
when '1011x' // Access the Undefined mode registers
m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
R[d] = Rmode[m,M32_Undef];
when '1110x' // Access Monitor registers
if !ELUsingAArch32(EL3) then AArch64.MonitorModeTrap();
m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
R[d] = Rmode[m,M32_Monitor];
when '11110' // Access ELR_hyp register
R[d] = ELR_hyp;
when '11111' // Access SP_hyp register
R[d] = Rmode[13,M32_Hyp];
If PSTATE.EL == EL0, then one of the following behaviors must occur:
Internal version only: isa v01_19v01_15, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06-29-gc9614a3
; Build timestamp: 2020-09-30T212020-07-03T11:3536
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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