(old) | htmldiff from- | (new) |
The GICR_ICENABLER<n>E characteristics are:
Disables forwarding of the corresponding PPI to the CPU interfaces.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ICENABLER<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ICENABLER<n>E is a 32-bit register.
The GICR_ICENABLER<n>E bit assignments are:
For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
Clear_enable_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, disables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 0. |
On a Warm reset, thisThis field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0180 + (4 * n) | GICR_ICENABLER<n>E |
This interface is accessible as follows:
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |