The PMPIDR4 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR4 is a 32-bit register.
The PMPIDR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | DES_2 |
Reserved, RES0.
Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.
Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.
Component | Offset | Instance |
---|---|---|
PMU | 0xFD0 | PMPIDR4 |
This interface is accessible as follows:
30/09/2020 15:06; ccead0cb9f089f9ceec50268e82aec9e71047211
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.