TFSR_EL1, Tag Fault Status Register (EL1)

The TFSR_EL1 characteristics are:

Purpose

Holds accumulated Tag Check Faults occurring in EL1 that are not taken precisely.

Configuration

This register is present only when FEAT_MTE2 is implemented. Otherwise, direct accesses to TFSR_EL1 are UNDEFINED.

Attributes

TFSR_EL1 is a 64-bit register.

Field descriptions

The TFSR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0TF1TF0
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

TF1, bit [1]

Tag Check Fault. Asynchronously set to 1 when a Tag Check Fault using a virtual address with bit[55] == 0b1 occurs.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

TF0, bit [0]

Tag Check Fault. Asynchronously set to 1 when a Tag Check Fault using a virtual address with bit[55] == 0b0 occurs.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing the TFSR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, TFSR_EL1

op0op1CRnCRmop2
0b110b0000b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x190]; else return TFSR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return TFSR_EL2; else return TFSR_EL1; elsif PSTATE.EL == EL3 then return TFSR_EL1;

MSR TFSR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x190] = X[t]; else TFSR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then TFSR_EL2 = X[t]; else TFSR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TFSR_EL1 = X[t];

MRS <Xt>, TFSR_EL12

op0op1CRnCRmop2
0b110b1010b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x190]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TFSR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then return TFSR_EL1; else UNDEFINED;

MSR TFSR_EL12, <Xt>

op0op1CRnCRmop2
0b110b1010b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x190] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TFSR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then TFSR_EL1 = X[t]; else UNDEFINED;

MRS <Xt>, TFSR_EL2

op0op1CRnCRmop2
0b110b1000b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TFSR_EL1; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TFSR_EL2; elsif PSTATE.EL == EL3 then return TFSR_EL2;

MSR TFSR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b01010b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.ATA == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TFSR_EL1 = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.ATA == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.ATA == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TFSR_EL2 = X[t]; elsif PSTATE.EL == EL3 then TFSR_EL2 = X[t];




30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.