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The TLBI RVAE2OS, TLBI RVAE2OSNXS characteristics are:
When EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 translation table entry.
The entry would be used to translate the specified VA in the specified range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2^(5*SCALE +1) * Translation_Granule_Size)], using the EL2 or EL2&0 translation regime.(5*SCALE +1) * Translation_Granule_Size)], using the EL2 or EL2&0 translation regime.
If HCR_EL2.E2H == 0, the entry is from any level of the translation table walk.
If HCR_EL2.E2H == 1, one of the following applies:
The entry is from a level of the translation table walk above the final level and matches the specified ASID.
The entry is a global entry from the final level of the translation table walk.
The entry is a non-global entry from the final level of the translation table walk and matches the specified ASID.
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
The range of addresses invalidated is UNPREDICTABLE when:
For the 4K translation granule:
If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.
If TTL==10 and BaseADDR[20:12] is not equal to 000000000.
For the 16K translation granule:
For the 64K translation granule:
If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.
If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
This instruction is present only when FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented. Otherwise, direct accesses to TLBI RVAE2OS, TLBI RVAE2OSNXS are UNDEFINED.
TLBI RVAE2OS, TLBI RVAE2OSNXS is a 64-bit System instruction.
The TLBI RVAE2OS, TLBI RVAE2OSNXS input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ASID | TG | SCALE | NUM | TTL | BaseADDR | ||||||||||||||||||||||||||
BaseADDR | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.
Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.
If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.
Reserved, RES0.
Translation granule size.
TG | Meaning |
---|---|
0b00 | Reserved. |
0b01 | 4K translation granule. |
0b10 | 16K translation granule. |
0b11 | 64K translation granule. |
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
The exponent element of the calculation that is used to produce the upper range.
The base element of the calculation that is used to produce the upper range.
TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.
TTL | Meaning |
---|---|
0b00 | The entries in the range can be using any level for the translation table entries. |
0b01 | All If |
0b10 | All entries to invalidate are Level 2 translation table entries. |
0b11 | All entries to invalidate are Level 3 translation table entries. |
The starting address for the range of the maintenance instructions. This field is BaseADDR[52:16] for all translation granules.
When using a 4KB translation granule, BaseADDR[15:12] is treated as 0b0000.
When using a 16KB translation granule, BaseADDR[15:14] is treated as 0b00.
The starting address for the range of the maintenance instruction.
When using a 4KB translation granule, this field is BaseADDR[48:12].
When using a 16KB translation granule, this field is BaseADDR[50:14].
When using a 64KB translation granule, this field is BaseADDR[52:16].
Accesses to this instruction use the following encodings:
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
TLBI_RVAE2OS(X[t]);
elsif PSTATE.EL == EL3 then
if !EL2Enabled() then
UNDEFINED;
else
TLBI_RVAE2OS(X[t]);
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Any, TLBI_AllAttr, X[t]); else TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_Outer, TLBILevel_Any, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; elsif HCR_EL2.E2H == '1' then TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Any, TLBI_AllAttr, X[t]); else TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_Outer, TLBILevel_Any, TLBI_AllAttr, X[t]);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1001 | 0b0101 | 0b001 |
if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Any, TLBI_ExcludeXS, X[t]); else TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_Outer, TLBILevel_Any, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then UNDEFINED; elsif HCR_EL2.E2H == '1' then TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Any, TLBI_ExcludeXS, X[t]); else TLBI_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID[], Shareability_Outer, TLBILevel_Any, TLBI_ExcludeXS, X[t]);
3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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