The RMR_EL3 characteristics are:
If EL3 is the implemented and this register is implemented:
AArch64 System register RMR_EL3 bits [31:0] are architecturally mapped to AArch32 System register RMR[31:0] when EL3 is implemented.
This register is present only when EL3 is implemented. Otherwise, direct accesses to RMR_EL3 are UNDEFINED.
When EL3 is implemented:
Otherwise, direct accesses to RMR_EL3 are UNDEFINED.
RMR_EL3 is a 64-bit register.
The RMR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RR | AA64 | |||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reset Request. Setting this bit to 1 requests a Warm reset.
On a Warm reset, this field resets to 0.
When EL3 can use AArch32, determines which Execution state the PE boots into after a Warm reset:
AA64 | Meaning |
---|---|
0b0 |
AArch32. |
0b1 |
AArch64. |
On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.
If EL3 can only use AArch64 state, this bit is RAO/WI.
When implemented as a RW field, this field resets to 1 on a Cold reset.
Reserved, RAO/WI.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b1100 | 0b0000 | 0b010 |
if PSTATE.EL == EL3 && IsHighestEL(EL3) then return RMR_EL3; else UNDEFINED;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b1100 | 0b0000 | 0b010 |
if PSTATE.EL == EL3 && IsHighestEL(EL3) then RMR_EL3 = X[t]; else UNDEFINED;
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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