TLBI VMALLE1, TLBI VMALLE1NXS, TLB Invalidate by VMID, All at stage 1, EL1

The TLBI VMALLE1, TLBI VMALLE1NXS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to the PE that executes this System instruction.

Note

For the EL1&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID.

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

There are no configuration notes.

Attributes

TLBI VMALLE1, TLBI VMALLE1NXS is a 64-bit System instruction.

Field descriptions

This instruction has no applicable fields.

The value in the register specified by <Xt> is ignored.

Executing the TLBI VMALLE1, TLBI VMALLE1NXS instruction

When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:

Accesses to this instruction use the following encodings:

TLBI VMALLE1{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b01110b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIVMALLE1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FB == '1' then if IsFeatureImplemented(FEAT_XS) && HCRX_EL2.FnXS == '1' then TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_AllAttr); else if IsFeatureImplemented(FEAT_XS) && HCRX_EL2.FnXS == '1' then TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_None, TLBI_AllAttr); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_None, TLBI_AllAttr); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr);

TLBI VMALLE1NXS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10010b01110b000

if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HCRX_EL2.FGTnXS == '0' && HFGITR_EL2.TLBIVMALLE1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FB == '1' then TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_None, TLBI_ExcludeXS); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VMALL(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_None, TLBI_ExcludeXS); else TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS);




30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211

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