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CTIGATE, CTI Channel Gate Enable register

The CTIGATE characteristics are:

Purpose

Determines whether events on channels propagate through the CTM to other ECT components, or from the CTM into the CTI.

Configuration

CTIGATE is in the Debug power domain.

Attributes

CTIGATE is a 32-bit register.

Field descriptions

The CTIGATE bit assignments are:

313029282726252423222120191817161514131211109876543210
GATE31GATE<x>, bit [x] GATE30GATE29GATE28GATE27GATE26GATE25GATE24GATE23GATE22GATE21GATE20GATE19GATE18GATE17GATE16GATE15GATE14GATE13GATE12GATE11GATE10GATE9GATE8GATE7GATE6GATE5GATE4GATE3GATE2GATE1GATE0

GATE<x>, bit [x], for x = 0 to 31

GATE<x>, bit [x], for x = 31 to 0

Channel <x> gate enable.

Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.

GATE<x>Meaning
0b0

Disable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.

0b1

Enable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation.

If GATE[x] is set to 0, no new events will be propagated to the ECT, and if the ECT supports multicycle channel events any existing output channel events will be terminated.

On a Cold reset, the value of this field is unchanged.

On an External debug reset, this field resets to an architecturally UNKNOWN value.

On a Warm reset, the value of this field is unchanged.

Accessing the CTIGATE

CTIGATE can be accessed through the external debug interface:

ComponentOffsetInstance
CTI0x140CTIGATE

This interface is accessible as follows:




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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