The TLBI VMALLS12E1, TLBI VMALLS12E1NXS characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 0, then:
The entry would be required to translate an address using the Secure EL1&0 translation regime.
If FEAT_SEL2 is implemented and enabled, the entry would be used with the current VMID.
If SCR_EL3.NS is 1, then:
The entry would be required to translate an address using the Non-secure EL1&0 translation regime.
If Non-secure EL2 is implemented, the entry would be used with the current VMID.
The invalidation applies to the PE that executes this System instruction.
For the EL1&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
There are no configuration notes.
TLBI VMALLS12E1, TLBI VMALLS12E1NXS is a 64-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
The instruction is UNDEFINED.
The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0111 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr); else TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_AllAttr);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1001 | 0b0111 | 0b110 |
if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS); elsif PSTATE.EL == EL3 then if !EL2Enabled() then TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS); else TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_None, TLBI_ExcludeXS);
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.