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TLBI ASIDE1IS, TLBI ASIDE1ISNXS, TLB Invalidate by ASID, EL1, Inner Shareable

The TLBI ASIDE1IS, TLBI ASIDE1ISNXS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

There are no configuration notes.

Attributes

TLBI ASIDE1IS, TLBI ASIDE1ISNXS is a 64-bit System instruction.

Field descriptions

The TLBI ASIDE1IS, TLBI ASIDE1ISNXS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDRES0
RES0
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.

If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.

Bits [47:0]

Reserved, RES0.

Executing the TLBI ASIDE1IS instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1IS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00110b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIASIDE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1IS(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1IS(X[t]);

Executing the TLBI ASIDE1IS, TLBI ASIDE1ISNXS instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1IS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00110b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIASIDE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_XS) && HCRX_EL2.FnXS == '1' then TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS, X[t]); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBI_AllAttr, X[t]); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBI_AllAttr, X[t]); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_AllAttr, X[t]);

TLBI ASIDE1ISNXS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10010b00110b010

if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HCRX_EL2.FGTnXS == '0' && HFGITR_EL2.TLBIASIDE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBI_ExcludeXS, X[t]); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_ASID(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBI_ExcludeXS, X[t]); else TLBI_ASID(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBI_ExcludeXS, X[t]);




3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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