The ERRIRQSR characteristics are:
Interrupt status register.
This register is present only when interrupt configuration registers are implemented. Otherwise, direct accesses to ERRIRQSR are RES0.
ERRIRQSR is implemented only as part of a memory-mapped group of error records.
ERRIRQSR is a 64-bit register.
The ERRIRQSR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | CRIERR | CRI | ERIERR | ERI | FHIERR | FHI | |||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Critical Error Interrupt error.
CRIERR | Meaning |
---|---|
0b0 |
Critical Error Interrupt write has not returned an error since this bit was last cleared to zero. |
0b1 |
Critical Error Interrupt write has returned an error since this bit was last cleared to zero. |
This bit is read/write-one-to-clear.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Critical Error Interrupt write in progress.
CRI | Meaning |
---|---|
0b0 |
Critical Error Interrupt write not in progress. |
0b1 |
Critical Error Interrupt write in progress. |
Software must not disable an interrupt whilst the write is in progress.
This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.
To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.
Access to this field is RO.
Reserved, RES0.
Error Recovery Interrupt error.
ERIERR | Meaning |
---|---|
0b0 |
Error Recovery Interrupt write has not returned an error since this bit was last cleared to zero. |
0b1 |
Error Recovery Interrupt write has returned an error since this bit was last cleared to zero. |
This bit is read/write-one-to-clear.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Error Recovery Interrupt write in progress.
ERI | Meaning |
---|---|
0b0 |
Error Recovery Interrupt write not in progress. |
0b1 |
Error Recovery Interrupt write in progress. |
Software must not disable an interrupt whilst the write is in progress.
This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.
To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.
Access to this field is RO.
Reserved, RES0.
Fault Handling Interrupt error.
FHIERR | Meaning |
---|---|
0b0 |
Fault Handling Interrupt write has not returned an error since this bit was last cleared to zero. |
0b1 |
Fault Handling Interrupt write has returned an error since this bit was last cleared to zero. |
This bit is read/write-one-to-clear.
On an Error recovery reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault Handling Interrupt write in progress.
FHI | Meaning |
---|---|
0b0 |
Fault Handling Interrupt write not in progress. |
0b1 |
Fault Handling Interrupt write in progress. |
Software must not disable an interrupt whilst the write is in progress.
This bit does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.
To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers.
Access to this field is RO.
Reserved, RES0.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
Component | Offset |
---|---|
RAS | 0xEF8 |
Accesses on this interface are RW.
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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