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TLBI RVAALE1IS, TLBI RVAALE1ISNXS, TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable

The TLBI RVAALE1IS, TLBI RVAALE1ISNXS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.

Note

When a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:

For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both:

Note

For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID.

The range of addresses invalidated is UNPREDICTABLE when:

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

This instruction is present only when FEAT_TLBIRANGE is implemented. Otherwise, direct accesses to TLBI RVAALE1IS, TLBI RVAALE1ISNXS are UNDEFINED.

Attributes

TLBI RVAALE1IS, TLBI RVAALE1ISNXS is a 64-bit System instruction.

Field descriptions

The TLBI RVAALE1IS, TLBI RVAALE1ISNXS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0TGSCALENUMTTLBaseADDR
BaseADDR
313029282726252423222120191817161514131211109876543210

Bits [63:48]

Reserved, RES0.

TG, bits [47:46]

Translation granule size.

TGMeaning
0b00

Reserved.

0b01

4K translation granule.

0b10

16K translation granule.

0b11

64K translation granule.

The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.

SCALE, bits [45:44]

The exponent element of the calculation that is used to produce the upper range.

NUM, bits [43:39]

The base element of the calculation that is used to produce the upper range.

TTL, bits [38:37]

TTL Level hint. The TTL hint is only guaranteed to invalidate entries in the range that match the level described by the TTL hint.

TTLMeaning
0b00

The entries in the range can be using any level for the translation table entries.

0b01

AllWhen using a 4KB or 64KB translation granule, all entries to invalidate are Level 1 translation table entries.

IfWhen using a 16KB translation granule, this value is reserved and hardware should treat this field as FEAT_LPA2 is not implemented, when using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00.

0b10

All entries to invalidate are Level 2 translation table entries.

0b11

All entries to invalidate are Level 3 translation table entries.

BaseADDR, bits [36:0]

When FEAT_LPA2 is implemented and TCR_EL1.DS == 1:

The starting address for the range of the maintenance instructions. This field is BaseADDR[52:16] for all translation granules.

When using a 4KB translation granule, BaseADDR[15:12] is treated as 0b0000.

When using a 16KB translation granule, BaseADDR[15:14] is treated as 0b00.


Otherwise:

The starting address for the range of the maintenance instruction.

When using a 4KB translation granule, this field is BaseADDR[48:12].

When using a 16KB translation granule, this field is BaseADDR[50:14].

When using a 64KB translation granule, this field is BaseADDR[52:16].

Executing the TLBI RVAALE1IS instruction

Accesses to this instruction use the following encodings:

TLBI RVAALE1IS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00100b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIRVAALE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_RVAALE1IS(X[t]); elsif PSTATE.EL == EL2 then TLBI_RVAALE1IS(X[t]); elsif PSTATE.EL == EL3 then TLBI_RVAALE1IS(X[t]);

Executing the TLBI RVAALE1IS, TLBI RVAALE1ISNXS instruction

Accesses to this instruction use the following encodings:

TLBI RVAALE1IS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00100b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIRVAALE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_XS) && HCRX_EL2.FnXS == '1' then TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_RVAA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBILevel_Last, TLBI_AllAttr, X[t]); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_RVAA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBILevel_Last, TLBI_AllAttr, X[t]); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_AllAttr, X[t]);

TLBI RVAALE1ISNXS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10010b00100b111

if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HCRX_EL2.FGTnXS == '0' && HFGITR_EL2.TLBIRVAALE1IS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_RVAA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_RVAA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Inner, TLBILevel_Last, TLBI_ExcludeXS, X[t]);




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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