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The CPTR_EL3 characteristics are:
Controls trapping to EL3 of accessesaccess to CPACR, CPACR_EL1, HCPTR, CPTR_EL2, trace, Activityfunctionality Monitorand registers associated with SVE, Advanced SIMD and floating-point execution. Also controls EL3 access to trace functionality and registers associated with SVE, Advanced SIMD and floating-point functionality.execution.
This register is present only when EL3 is implemented. Otherwise, direct accesses to CPTR_EL3 are UNDEFINED.
CPTR_EL3 is a 64-bit register.
The CPTR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
TCPAC | TAM | RES0 | TTA | RES0 | TFP | RES0 | EZ | RES0 | |||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Traps all of the following to EL3, from both Security states and both Execution states.
When CPTR_EL3.TCPAC is:
TCPAC | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Trap Activity Monitor access. Traps EL2, EL1 and EL0 accesses to all Activity Monitor registers to EL3.
Accesses to the Activity Monitors registers are trapped as follows:
In AArch64 state, the following registers are trapped to EL3 and reported with ESR_ELx.ECEC syndrome value 0x18:
In AArch32 state, accesses with MRC or MCR to the following registers reported with ESR_ELx.ECEC syndrome value 0x03:
In AArch32 state, accesses with MRRC or MCRR to the following registers, reported with ESR_ELx.ECEC syndrome value 0x04:
TAM | Meaning |
---|---|
0b0 | Accesses from EL2, EL1, and EL0 to Activity Monitor registers are not trapped. |
0b1 | Accesses from EL2, EL1, and EL0 to Activity Monitor registers are trapped to EL3. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Traps System register accesses. Accesses to the trace registers, from all Exception levels, both Security states, and both Execution states are trapped to EL3 as follows:
In AArch64 state, Trace registers with op0=2, op1=1, are trapped to EL3 and CRn<reported using EC syndrome value0b1000 are trapped to EL3 and reported using EC syndrome value 0x18.
In AArch32 state, accesses using MCR or MRC to the Trace registers with cpnum=14, and opc1=1, andare CRn<reported using EC syndrome value0b1000 are reported using EC syndrome value 0x05.
In AArch32 state, accesses using MCRR or MRRC to the Trace registers with cpnum=14 and opc1=1 are reported using EC syndrome value 0x0C.
TTA | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | Any System register access to the trace registers is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPACR.TRCDIS, CPACR_EL1.TTA or CPTR_EL2.TTA. |
If System register access to trace functionality is not supported, this bit is RES0.
The ETMv4 architecture does not permit EL0 to access the trace registers. If the PE trace unit implements FEAT_ETMv4, EL0 accesses to the trace registers are UNDEFINED, and any resulting exception is higher priority than this trap exception.
EL3 does not provide traps on trace register accesses through the Memory-mapped interface.
System register accesses to the trace registers can have side-effects. When a System register access is trapped, no side-effects occur before the exception is taken, see 'Traps on instructions'.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps all accesses to SVE, Advanced SIMD and floating-point functionality, from all Exception levels, both Security states, and both Execution states, to EL3. Defined values are:
This includes the following registers, all reported using ESR_ELx.ECEC syndrome value 0x07:
Permitted VMSR accesses to FPSID are ignored, but for the purposes of this trap the architecture define a VMSR access to the FPSID from EL1 or higher as an access to a SIMD and floating-point register.
Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL3.EZ has precedence over the value of CPTR_EL3.TFP.
Defined values are:
TFP | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | Any attempt at any Exception level to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point is trapped to EL3, subject to the exception prioritization rules. |
FPEXC32_EL2 is not accessible from EL0 using AArch64.
FPSID, MVFR0, MVFR1, and FPEXC are not accessible from EL0 using AArch32.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Traps executionall ofaccesses to SVE instructionsfunctionality and instructionsregisters thatfrom directlyall accessException thelevels, and both Security states, to EL3. ZCR_EL3, ZCR_EL2, and ZCR_EL1 System registers, from all Exception levels and both Security states, to EL3.
The exception is reported using ESR_ELx.EC value 0x19.
Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL3.EZ has precedence over the value of CPTR_EL3.TFP.
EZ | Meaning |
---|---|
0b0 | This control causes these instructions executed at any Exception level to be trapped, subject to the exception prioritization rules. |
0b1 | This control does not cause any instruction to be trapped. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return CPTR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then CPTR_EL3 = X[t];
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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