The ID_ISAR6 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_ISAR6 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR6_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_ISAR6 are UNDEFINED.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_ISAR6 is a 32-bit register.
The ID_ISAR6 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | I8MM | BF16 | SPECRES | SB | FHM | DP | JSCVT |
Reserved, RES0.
Indicates support for Advanced SIMD and floating-point Int8 matrix multiplication instructions in AArch32 state. Defined values are:
I8MM | Meaning |
---|---|
0b0000 |
Int8 matrix multiplication instructions are not implemented. |
0b0001 |
VSMMLA, VSUDOT, VUMMLA, VUSMMLA, and VUSDOT instructions are implemented. |
All other values are reserved.
FEAT_AA32I8MM implements the functionality identified by 0b0001.
From Armv8.2, the permitted values are 0b0000 and 0b0001.
Indicates support for Advanced SIMD and floating-point BFloat16 instructions in AArch32 state. Defined values are:
BF16 | Meaning |
---|---|
0b0000 |
BFloat16 instructions are not implemented. |
0b0001 |
VCVT, VCVTB, VCVTT, VDOT, VFMAB, VFMAT, and VMMLA instructions with BF16 operand or result types are implemented. |
All other values are reserved.
FEAT_AA32BF16 implements the functionality identified by 0b0001.
From Armv8.2, the permitted values are 0b0000 and 0b0001.
Indicates support for Speculation invalidation instructions in AArch32 state. Defined values are:
SPECRES | Meaning |
---|---|
0b0000 |
CFPRCTX, DVPRCTX, and CPPRCTX instructions are not implemented. |
0b0001 |
CFPRCTX, DVPRCTX, and CPPRCTX instructions are implemented. |
All other values are reserved.
From Armv8.5, the only permitted value is 0b0001.
Indicates support for SB instruction in AArch32 state. Defined values are:
SB | Meaning |
---|---|
0b0000 |
SB instruction is not implemented. |
0b0001 |
SB instruction is implemented. |
All other values are reserved.
From Armv8.5, the only permitted value is 0b0001.
Indicates support for Advanced SIMD and floating-point VFMAL and VFMSL instructions in AArch32 state. Defined values are:
FHM | Meaning |
---|---|
0b0000 |
VFMAL and VMFSL instructions not implemented. |
0b0001 |
VFMAL and VMFSL instructions implemented. |
FEAT_FHM implements the functionality identified by the value 0b0001.
Indicates support for dot product instructions in AArch32 state. Defined values are:
DP | Meaning |
---|---|
0b0000 |
No dot product instructions implemented. |
0b0001 |
VUDOT and VSDOT instructions implemented. |
All other values are reserved.
FEAT_DotProd implements the functionality identified by the value 0b0001.
Indicates support for the Javascript conversion instruction in AArch32 state. Defined values are:
JSCVT | Meaning |
---|---|
0b0000 |
The VJCVT instruction is not implemented. |
0b0001 |
The VJCVT instruction is implemented. |
All other values are reserved.
In Armv8.0, the only permitted value is 0b0000.
FEAT_JSCVT implements the functionality identified by 0b0001.
From Armv8.3, if Advanced SIMD or Floating-point is implemented, the only permitted value is 0b0001.
From Armv8.3, if Advanced SIMD or Floating-point is not implemented, the only permitted value is 0b0000.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && (!IsZero(ID_ISAR6) || boolean IMPLEMENTATION_DEFINED "ID_ISAR6 trapped by HCR.TID3") && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR6; elsif PSTATE.EL == EL2 then return ID_ISAR6; elsif PSTATE.EL == EL3 then return ID_ISAR6;
30/09/2020 15:06; ccead0cb9f089f9ceec50268e82aec9e71047211
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