The GICD_IPRIORITYR<n> characteristics are:
Holds the priority of the corresponding interrupt.
These registers are available in all configurations of the GIC. When GICD_CTLR.DS==0, these registers are Common.
The number of implemented GICD_IPRIORITYR<n> registers is 8*(GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_IPRIORITYR0 to GICD_IPRIORITYR7 are Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_IPRIORITYR0 to GICD_IPRIORITYR7 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
GICD_IPRIORITYR<n> is a 32-bit register.
The GICD_IPRIORITYR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Priority_offset_3B | Priority_offset_2B | Priority_offset_1B | Priority_offset_0B |
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 3. Lower priority values correspond to greater priority of the interrupt.
This field resets to 0.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 2. Lower priority values correspond to greater priority of the interrupt.
This field resets to 0.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 1. Lower priority values correspond to greater priority of the interrupt.
This field resets to 0.
Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 0. Lower priority values correspond to greater priority of the interrupt.
This field resets to 0.
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
These registers are always used when affinity routing is not enabled. When affinity routing is enabled for the Security state of an interrupt:
These registers are byte-accessible.
A register field corresponding to an unimplemented interrupt is RAZ/WI.
A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
When GICD_CTLR.DS==0:
It is IMPLEMENTATION DEFINED whether changing the value of a priority field changes the priority of an active interrupt.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x0400 + (4 * n) | GICD_IPRIORITYR<n> |
This interface is accessible as follows:
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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