AMCG1IDR_EL0, Activity Monitors Counter Group 1 Identification Register

The AMCG1IDR_EL0 characteristics are:

Purpose

Defines which auxiliary counters are implemented, and which of them have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMCG1IDR_EL0 are UNDEFINED.

Attributes

AMCG1IDR_EL0 is a 64-bit register.

Field descriptions

The AMCG1IDR_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
AMEVCNTOFF1<n>_EL2, bit [n+16], for n = 0 to 15AMEVCNTR1<n>_EL0, bit [n], for n = 0 to 15
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

AMEVCNTOFF1<n>_EL2, bit [n+16], for n = 0 to 15

Indicates which implemented auxiliary counters have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

AMEVCNTOFF1<n>_EL2Meaning
0b0

When read, mean that AMEVCNTR1<n>_EL0 does not have an offset, or is not implemented.

0b1

When read, means the offset AMEVCNTVOFF1<n>_EL2 is implemented for AMEVCNTR1<n>_EL0.

AMEVCNTR1<n>_EL0, bit [n], for n = 0 to 15

Indicates which auxiliary counters AMEVCNTR1<n>_EL0 are implemented.

AMEVCNTR1<n>_EL0Meaning
0b0

When read, means that AMEVCNTR1<n>_EL0 is not implemented.

0b1

When read, means that AMEVCNTR1<n>_EL0 is implemented.

Accessing the AMCG1IDR_EL0

Accesses to this register use the following encodings:

MRS <Xt>, AMCG1IDR_EL0

op0op1CRnCRmop2
0b110b0110b11010b00100b110

if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then UNDEFINED; elsif AMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return AMCG1IDR_EL0; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return AMCG1IDR_EL0; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return AMCG1IDR_EL0; elsif PSTATE.EL == EL3 then return AMCG1IDR_EL0;




01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a

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