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The HDFGWTR_EL2 characteristics are:
Provides controls for traps of MSR and MCR writes of debug, trace, PMU, and Statistical Profiling System registers.
This register is present only when FEAT_FGT is implemented. Otherwise, direct accesses to HDFGWTR_EL2 are UNDEFINED.
HDFGWTR_EL2 is a 64-bit register.
The HDFGWTR_EL2 bit assignments are:
Reserved, RES0.
Trap MSR writes of PMSNEVFR_EL1PMUSERENR_EL0 at EL1 using AArch64 to EL2.
nPMSNEVFR_EL1 | Meaning |
---|---|
0b0 | If EL2 is implemented and enabled in the current Security state then MSR writes of PMSNEVFR_EL1 |
0b1 | MSR writes of PMSNEVFR_EL1 are not affected by this bit.
|
This bit is ignored by the PE and treated as zero when EL3 is implemented and SCR_EL3.FGTEn == 0b0.
In a system where the PE resets into EL2, this field resets to 0.
On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMUSERENR_EL0 at EL1 using AArch64 to EL2.
PMUSERENR_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMUSERENR_EL0 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 0b1, then MSR writes of PMUSERENR_EL0 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRFCR_EL1 at EL1 using AArch64 to EL2.
TRFCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of TRFCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of TRCVICTLR at EL1 using AArch64 to EL2.
TRCVICTLR | Meaning |
---|---|
0b0 | MSR writes of TRCVICTLR are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCSSCSR<n> at EL1 using AArch64 to EL2.
TRCSSCSRn | Meaning |
---|---|
0b0 | MSR writes of TRCSSCSR<n> are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If Single-shot Comparator n is not implementented, a write of TRCSSCSR<n> is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
OnThis abit Warm reset, in a system where the PE resets into EL2, this field resets tois if TRCSSCSR<n>0RES0.are not implemented.
Reserved, RES0.
Trap MSR writes of TRCSEQSTR at EL1 using AArch64 to EL2.
TRCSEQSTR | Meaning |
---|---|
0b0 | MSR writes of TRCSEQSTR are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
In a system where the PE resets into EL2, this field resets to 0.
OnThis abit Warm reset, in a system where the PE resets into EL2, this field resets tois if TRCSEQSTR0RES0.is not implemented.
Reserved, RES0.
Trap MSR writes of TRCPRGCTLR at EL1 using AArch64 to EL2.
TRCPRGCTLR | Meaning |
---|---|
0b0 | MSR writes of TRCPRGCTLR are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCOSLAR at EL1 using AArch64 to EL2.
TRCOSLAR | Meaning |
---|---|
0b0 | MSR writes of TRCOSLAR are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of TRCIMSPEC<n> at EL1 using AArch64 to EL2.
TRCIMSPECn | Meaning |
---|---|
0b0 | MSR writes of TRCIMSPEC<n> are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
TRCIMSPEC<1-7> are optional. If TRCIMSPEC<n> is not implemented, a write of TRCIMSPEC<n> is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCCNTVR<n> at EL1 using AArch64 to EL2.
TRCCNTVRn | Meaning |
---|---|
0b0 | MSR writes of TRCCNTVR<n> are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If Counter n is not implemented, a write of TRCCNTVR<n> is UNDEFINED.
In a system where the PE resets into EL2, this field resets to 0.
OnThis abit Warm reset, in a system where the PE resets into EL2, this field resets tois if TRCCNTVR<n>0RES0.are not implemented.
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRCCLAIM | Meaning |
---|---|
0b0 | MSR writes of the System registers listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of TRCAUXCTLR at EL1 using AArch64 to EL2.
TRCAUXCTLR | Meaning |
---|---|
0b0 | MSR writes of TRCAUXCTLR are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRC | Meaning |
---|---|
0b0 | MSR writes of the System registers listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
A write of an unimplemented register is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSLATFR_EL1 at EL1 using AArch64 to EL2.
PMSLATFR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSLATFR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSIRR_EL1 at EL1 using AArch64 to EL2.
PMSIRR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSIRR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMSICR_EL1 at EL1 using AArch64 to EL2.
PMSICR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSICR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSFCR_EL1 at EL1 using AArch64 to EL2.
PMSFCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSFCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSEVFR_EL1 at EL1 using AArch64 to EL2.
PMSEVFR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSEVFR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSCR_EL1 at EL1 using AArch64 to EL2.
PMSCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMSCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMBSR_EL1 at EL1 using AArch64 to EL2.
PMBSR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMBSR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMBPTR_EL1 at EL1 using AArch64 to EL2.
PMBPTR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMBPTR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.
PMBLIMITR_EL1 | Meaning |
---|---|
0b0 | MSR writes of PMBLIMITR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCR_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMSWINC_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMSELR_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MSR writes of PMOVSCLR_EL0 and PMOVSSET_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MCR writes of PMOVSR and PMOVSSET.
PMOVS | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
PMINTEN | Meaning |
---|---|
0b0 | MSR writes of the System registers listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MSR writes of PMCNTENCLR_EL0 and PMCNTENSET_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MCR writes of PMCNTENCLR and PMCNTENSET.
PMCNTEN | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCNTR_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCFILTR_EL0 | Meaning |
---|---|
0b0 | MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
PMCCFILTR_EL0 can also be accessed in AArch64 state using PMXEVTYPER_EL0 when PMSELR_EL0.SEL == 31, and PMCCFILTR can also be accessed in AArch32 state using PMXEVTYPER when PMSELR.SEL == 31.
Setting this bit to 1 has no effect on accesses to PMXEVTYPER_EL0 and PMXEVTYPER, regardless of the value of PMSELR_EL0.SEL or PMSELR.SEL.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MSR writes of PMEVTYPER<n>_EL0 and PMXEVTYPER_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MCR writes of PMEVTYPER<n> and PMXEVTYPER.
PMEVTYPERn_EL0 | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
When FEAT_FGT is implemented, then, regardless of the value of this bit, for each value n:
If event counter n is not implemented, the following accesses are UNDEFINED:
In AArch64 state, a write of PMEVTYPER<n>_EL0, or, if n is not 31, a write of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n.
In AArch32 state, a write of PMEVTYPER<n>, or, if n is not 31, a write of PMXEVTYPER when PMSELR.SEL == n.
If event counter n is implemented and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1:
In AArch64 state, a write of PMEVTYPER<n>_EL0, or a write of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n, reported with EC syndrome value 0x18.
In AArch32 state, a write of PMEVTYPER<n>, or a write of PMXEVTYPER when PMSELR.SEL == n, reported with EC syndrome value 0x03.
See also HDFGWTR_EL2.PMCCFILTR_EL0.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
At EL1 and EL0 using AArch64: MSR writes of PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0.
At EL0 using Arch32 when EL1 is using AArch64: MCR writes of PMEVCNTR<n> and PMXEVCNTR.
PMEVCNTRn_EL0 | Meaning |
---|---|
0b0 | The operations listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn ==
|
When FEAT_FGT is implemented, then, regardless of the value of this bit, for each value n:
If event counter n is not implemented, the following accesses are UNDEFINED:
In AArch64 state, a write of PMEVCNTR<n>_EL0, or a write of PMXEVCNTR_EL0 when PMSELR_EL0.SEL == n.
In AArch32 state, a write of PMEVCNTR<n> , or a write of PMXEVCNTR when PMSELR.SEL == n.
If event counter n is implemented, and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1:
In AArch64 state, a write of PMEVCNTR<n>_EL0, or a write of PMXEVCNTR_EL0 when PMSELR_EL0.SEL == n, reported with EC syndrome value 0x18.
In AArch32 state, a write of PMEVCNTR<n>, or a write of PMXEVCNTR when PMSELR.SEL == n, reported with EC syndrome value 0x03.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of OSDLR_EL1 at EL1 using AArch64 to EL2.
OSDLR_EL1 | Meaning |
---|---|
0b0 | MSR writes of OSDLR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of OSECCR_EL1 at EL1 using AArch64 to EL2.
OSECCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of OSECCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of OSLAR_EL1 at EL1 using AArch64 to EL2.
OSLAR_EL1 | Meaning |
---|---|
0b0 | MSR writes of OSLAR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of DBGPRCR_EL1 at EL1 using AArch64 to EL2.
DBGPRCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of DBGPRCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
DBGCLAIM | Meaning |
---|---|
0b0 | MSR writes of the System registers listed above are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of MDSCR_EL1 at EL1 using AArch64 to EL2.
MDSCR_EL1 | Meaning |
---|---|
0b0 | MSR writes of MDSCR_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of DBGWVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWVRn_EL1 | Meaning |
---|---|
0b0 | MSR writes of DBGWVR<n>_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If watchpoint n is not implemented, a write of DBGWVR<n>_EL1 is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of DBGWCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWCRn_EL1 | Meaning |
---|---|
0b0 | MSR writes of DBGWCR<n>_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If watchpoint n is not implemented, a write of DBGWCR<n>_EL1 is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of DBGBVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBVRn_EL1 | Meaning |
---|---|
0b0 | MSR writes of DBGBVR<n>_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If breakpoint n is not implemented, a write of DBGBVR<n>_EL1 is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Trap MSR writes of DBGBCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBCRn_EL1 | Meaning |
---|---|
0b0 | MSR writes of DBGBCR<n>_EL1 are not affected by this bit. |
0b1 | If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == |
If breakpoint n is not implemented, a write of DBGBCR<n>_EL1 is UNDEFINED.
On a Warm reset, inIn a system where the PE resets into EL2, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1D8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return HDFGWTR_EL2; elsif PSTATE.EL == EL3 then return HDFGWTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1D8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HDFGWTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HDFGWTR_EL2 = X[t];
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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