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The PMPCSR characteristics are:
Holds a sampled instruction address value.
PMPCSR is in the Core power domain.
This register is present only when FEAT_PCSRv8p2 is implemented. Otherwise, direct accesses to PMPCSR are RES0.
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
Support for 64-bit atomic reads is IMPLEMENTATION DEFINED. If 64-bit atomic reads are implemented, a 64-bit read of PMPCSR has the same side-effect as a 32-bit read of PMCSR[31:0] followed by a 32-bit read of PMPCSR[63:32], returning the combined value. For example, if the PE is in Debug state then a 64-bit atomic read returns bits[31:0] == 0xFFFFFFFF and bits[63:32] UNKNOWN.
PMPCSR is a 64-bit register.
The PMPCSR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
NS | EL | RES0 | PCSample[55:32] | ||||||||||||||||||||||||||||
PCSample[31:0] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Non-secure state sample. Indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
If EL3 is not implemented, this bit indicates the Effective value of SCR.NS.
NS | Meaning |
---|---|
0b0 | Sample is from Secure state. |
0b1 | Sample is from Non-secure state. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Exception level status sample. Indicates the Exception level that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
EL | Meaning |
---|---|
0b00 | Sample is from EL0. |
0b01 | Sample is from EL1. |
0b10 | Sample is from EL2. |
0b11 | Sample is from EL3. |
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Reserved, RES0.
Bits[55:32] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
Bits[31:0] of the sampled instruction address value.
PMPCSR[31:0] reads as 0xFFFFFFFF when any of the following are true:
If an instruction has retired since the PE left Reset state, then the first read of PMPCSR[31:0] is permitted but not required to return 0xFFFFFFFF.
PMPCSR[31:0] reads as an UNKNOWN value when any of the following are true:
For the cases where a read of PMPCSR[31:0] returns 0xFFFFFFFF or an UNKNOWN value, the read has the side-effect of setting PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR to UNKNOWN values.
Otherwise, a read of PMPCSR[31:0] returns bits [31:0] of the sampled instruction address value and has the side-effect of indirectly writing to PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
For a read of PMPCSR[31:0] from the memory-mapped interface, if PMLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the side-effect of the access does not occur and PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR are unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance | Range |
---|---|---|---|
PMU | 0x200 | PMPCSR | 31:0 |
This interface is accessible as follows:
Component | Offset | Instance | Range |
---|---|---|---|
PMU | 0x204 | PMPCSR | 63:32 |
This interface is accessible as follows:
Component | Offset | Instance | Range |
---|---|---|---|
PMU | 0x220 | PMPCSR | 31:0 |
This interface is accessible as follows:
Component | Offset | Instance | Range |
---|---|---|---|
PMU | 0x224 | PMPCSR | 63:32 |
This interface is accessible as follows:
3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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