The ID_AFR0 characteristics are:
Provides information about the IMPLEMENTATION DEFINED features of the PE in AArch32 state.
Must be interpreted with the Main ID Register, MIDR.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_AFR0 bits [31:0] are architecturally mapped to AArch64 System register ID_AFR0_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_AFR0 are UNDEFINED.
ID_AFR0 is a 32-bit register.
The ID_AFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
Reserved, RES0.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED.
IMPLEMENTATION DEFINED.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0001 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_AFR0; elsif PSTATE.EL == EL2 then return ID_AFR0; elsif PSTATE.EL == EL3 then return ID_AFR0;
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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