(old) htmldiff from-(new)

External register index by offset

Below are indexes for external registers in the following blocks:

In the AMU block:

OffsetNameDescription
0x000 + (8 * n)AMEVCNTR0<n>[31:0]Activity Monitors Event Counter Registers 0
0x004 + (8 * n)AMEVCNTR0<n>[63:32]Activity Monitors Event Counter Registers 0
0x100 + (8 * n)AMEVCNTR1<n>[31:0]Activity Monitors Event Counter Registers 1
0x104 + (8 * n)AMEVCNTR1<n>[63:32]Activity Monitors Event Counter Registers 1
0x400 + (4 * n)AMEVTYPER0<n>Activity Monitors Event Type Registers 0
0x480 + (4 * n)AMEVTYPER1<n>Activity Monitors Event Type Registers 1
0xC00AMCNTENSET0Activity Monitors Count Enable Set Register 0
0xC04AMCNTENSET1Activity Monitors Count Enable Set Register 1
0xC20AMCNTENCLR0Activity Monitors Count Enable Clear Register 0
0xC24AMCNTENCLR1Activity Monitors Count Enable Clear Register 1
0xCE0AMCGCRActivity Monitors Counter Group Configuration Register
0xE00AMCFGRActivity Monitors Configuration Register
0xE04AMCRActivity Monitors Control Register
0xE08AMIIDRActivity Monitors Implementation Identification Register
0xFA8AMDEVAFF0Activity Monitors Device Affinity Register 0
0xFACAMDEVAFF1Activity Monitors Device Affinity Register 1
0xFBCAMDEVARCHActivity Monitors Device Architecture Register
0xFCCAMDEVTYPEActivity Monitors Device Type Register
0xFD0AMPIDR4Activity Monitors Peripheral Identification Register 4
0xFE0AMPIDR0Activity Monitors Peripheral Identification Register 0
0xFE4AMPIDR1Activity Monitors Peripheral Identification Register 1
0xFE8AMPIDR2Activity Monitors Peripheral Identification Register 2
0xFECAMPIDR3Activity Monitors Peripheral Identification Register 3
0xFF0AMCIDR0Activity Monitors Component Identification Register 0
0xFF4AMCIDR1Activity Monitors Component Identification Register 1
0xFF8AMCIDR2Activity Monitors Component Identification Register 2
0xFFCAMCIDR3Activity Monitors Component Identification Register 3

In the CTI block:

OffsetNameDescription
0x000CTICONTROLCTI Control register
0x010CTIINTACKCTI Output Trigger Acknowledge register
0x014CTIAPPSETCTI Application Trigger Set register
0x018CTIAPPCLEARCTI Application Trigger Clear register
0x01CCTIAPPPULSECTI Application Pulse register
0x020 + (4 * n)CTIINEN<n>CTI Input Trigger to Output Channel Enable registers
0x0A0 + (4 * n)CTIOUTEN<n>CTI Input Channel to Output Trigger Enable registers
0x130CTITRIGINSTATUSCTI Trigger In Status register
0x134CTITRIGOUTSTATUSCTI Trigger Out Status register
0x138CTICHINSTATUSCTI Channel In Status register
0x13CCTICHOUTSTATUSCTI Channel Out Status register
0x140CTIGATECTI Channel Gate Enable register
0x144ASICCTLCTI External Multiplexer Control register
0x150CTIDEVCTLCTI Device Control register
0xF00CTIITCTRLCTI Integration mode Control register
0xFA0CTICLAIMSETCTI CLAIM Tag Set register
0xFA4CTICLAIMCLRCTI CLAIM Tag Clear register
0xFA8CTIDEVAFF0CTI Device Affinity register 0
0xFACCTIDEVAFF1CTI Device Affinity register 1
0xFB0CTILARCTI Lock Access Register
0xFB4CTILSRCTI Lock Status Register
0xFB8CTIAUTHSTATUSCTI Authentication Status register
0xFBCCTIDEVARCHCTI Device Architecture register
0xFC0CTIDEVID2CTI Device ID register 2
0xFC4CTIDEVID1CTI Device ID register 1
0xFC8CTIDEVIDCTI Device ID register 0
0xFCCCTIDEVTYPECTI Device Type register
0xFD0CTIPIDR4CTI Peripheral Identification Register 4
0xFE0CTIPIDR0CTI Peripheral Identification Register 0
0xFE4CTIPIDR1CTI Peripheral Identification Register 1
0xFE8CTIPIDR2CTI Peripheral Identification Register 2
0xFECCTIPIDR3CTI Peripheral Identification Register 3
0xFF0CTICIDR0CTI Component Identification Register 0
0xFF4CTICIDR1CTI Component Identification Register 1
0xFF8CTICIDR2CTI Component Identification Register 2
0xFFCCTICIDR3CTI Component Identification Register 3

In the Debug block:

OffsetNameDescription
0x020EDESRExternal Debug Event Status Register
0x024EDECRExternal Debug Execution Control Register
0x030EDWAR[31:0]External Debug Watchpoint Address Register
0x034EDWAR[63:32]External Debug Watchpoint Address Register
0x080DBGDTRRX_EL0Debug Data Transfer Register, Receive
0x084EDITRExternal Debug Instruction Transfer Register
0x088EDSCRExternal Debug Status and Control Register
0x08CDBGDTRTX_EL0Debug Data Transfer Register, Transmit
0x090EDRCRExternal Debug Reserve Control Register
0x094EDACRExternal Debug Auxiliary Control Register
0x098EDECCRExternal Debug Exception Catch Control Register
0x0A0EDPCSR[31:0]External Debug Program Counter Sample Register
0x0A4EDCIDSRExternal Debug Context ID Sample Register
0x0A8EDVIDSRExternal Debug Virtual Context Sample Register
0x0ACEDPCSR[63:32]External Debug Program Counter Sample Register
0x300OSLAR_EL1OS Lock Access Register
0x310EDPRCRExternal Debug Power/Reset Control Register
0x314EDPRSRExternal Debug Processor Status Register
0x400 + (16 * n)DBGBVR<n>_EL1[63:0]Debug Breakpoint Value Registers
0x408 + (16 * n)DBGBCR<n>_EL1Debug Breakpoint Control Registers
0x800 + (16 * n)DBGWVR<n>_EL1[63:0]Debug Watchpoint Value Registers
0x808 + (16 * n)DBGWCR<n>_EL1Debug Watchpoint Control Registers
0xD00MIDR_EL1Main ID Register
0xD20EDPFR[31:0]External Debug Processor Feature Register
0xD24EDPFR[63:32]External Debug Processor Feature Register
0xD28EDDFR[31:0]External Debug Feature Register
0xD2CEDDFR[63:32]External Debug Feature Register
0xD60EDAA32PFRExternal Debug Auxiliary Processor Feature Register
0xF00EDITCTRLExternal Debug Integration mode Control register
0xFA0DBGCLAIMSET_EL1Debug CLAIM Tag Set register
0xFA4DBGCLAIMCLR_EL1Debug CLAIM Tag Clear register
0xFA8EDDEVAFF0External Debug Device Affinity register 0
0xFACEDDEVAFF1External Debug Device Affinity register 1
0xFB0EDLARExternal Debug Lock Access Register
0xFB4EDLSRExternal Debug Lock Status Register
0xFB8DBGAUTHSTATUS_EL1Debug Authentication Status register
0xFBCEDDEVARCHExternal Debug Device Architecture register
0xFC0EDDEVID2External Debug Device ID register 2
0xFC4EDDEVID1External Debug Device ID register 1
0xFC8EDDEVIDExternal Debug Device ID register 0
0xFCCEDDEVTYPEExternal Debug Device Type register
0xFD0EDPIDR4External Debug Peripheral Identification Register 4
0xFE0EDPIDR0External Debug Peripheral Identification Register 0
0xFE4EDPIDR1External Debug Peripheral Identification Register 1
0xFE8EDPIDR2External Debug Peripheral Identification Register 2
0xFECEDPIDR3External Debug Peripheral Identification Register 3
0xFF0EDCIDR0External Debug Component Identification Register 0
0xFF4EDCIDR1External Debug Component Identification Register 1
0xFF8EDCIDR2External Debug Component Identification Register 2
0xFFCEDCIDR3External Debug Component Identification Register 3

In the PMUGIC CPU interface block:

OffsetNameDescription
0x000 + (8 * n)0x0000PMEVCNTR<n>_EL0GICC_CTLRPerformanceCPU MonitorsInterface EventControl Count RegistersRegister
0x0F80x0004PMCCNTR_EL0[31:0]GICC_PMRPerformanceCPU MonitorsInterface CyclePriority CounterMask Register
0x0FC0x0008PMCCNTR_EL0[63:32]GICC_BPRPerformanceCPU MonitorsInterface CycleBinary CounterPoint Register
0x2000x000CPMPCSR[31:0]GICC_IARProgramCPU CounterInterface SampleInterrupt Acknowledge Register
0x2040x0010PMPCSR[63:32]GICC_EOIRProgramCPU CounterInterface SampleEnd Of Interrupt Register
0x2080x0014PMCID1SRGICC_RPRCONTEXTIDR_EL1CPU SampleInterface Running Priority Register
0x20C0x0018PMVIDSRGICC_HPPIRVMIDCPU SampleInterface Highest Priority Pending Interrupt Register
0x2200x001CPMPCSR[31:0]GICC_ABPRProgramCPU CounterInterface SampleAliased Binary Point Register
0x2240x0020PMPCSR[63:32]GICC_AIARProgramCPU CounterInterface SampleAliased Interrupt Acknowledge Register
0x2280x0024PMCID1SRGICC_AEOIRCONTEXTIDR_EL1CPU SampleInterface Aliased End Of Interrupt Register
0x22C0x0028PMCID2SRGICC_AHPPIRCONTEXTIDR_EL2CPU SampleInterface Aliased Highest Priority Pending Interrupt Register
0x400 + (4 * n)0x002CPMEVTYPER<n>_EL0GICC_STATUSRPerformanceCPU MonitorsInterface EventStatus Type RegistersRegister
0x47C0x002CPMCCFILTR_EL0GICC_STATUSRPerformanceCPU MonitorsInterface Cycle Counter FilterStatus Register
0xC000x00D0 + (4 * n)PMCNTENSET_EL0GICC_APR<n>PerformanceCPU MonitorsInterface CountActive EnablePriorities Set registerRegisters
0xC200x00E0 + (4 * n)PMCNTENCLR_EL0GICC_NSAPR<n>PerformanceCPU MonitorsInterface CountNon-secure EnableActive ClearPriorities registerRegisters
0xC400x00FCPMINTENSET_EL1GICC_IIDRPerformanceCPU MonitorsInterface InterruptIdentification Enable Set registerRegister
0xC600x1000PMINTENCLR_EL1GICC_DIRPerformanceCPU MonitorsInterface Deactivate Interrupt Enable Clear registerRegister
0xC80PMOVSCLR_EL0Performance Monitors Overflow Flag Status Clear register
0xCA0PMSWINC_EL0Performance Monitors Software Increment register
0xCC0PMOVSSET_EL0Performance Monitors Overflow Flag Status Set register
0xE00PMCFGRPerformance Monitors Configuration Register
0xE04PMCR_EL0Performance Monitors Control Register
0xE20PMCEID0Performance Monitors Common Event Identification register 0
0xE24PMCEID1Performance Monitors Common Event Identification register 1
0xE28PMCEID2Performance Monitors Common Event Identification register 2
0xE2CPMCEID3Performance Monitors Common Event Identification register 3
0xE40PMMIRPerformance Monitors Machine Identification Register
0xF00PMITCTRLPerformance Monitors Integration mode Control register
0xFA8PMDEVAFF0Performance Monitors Device Affinity register 0
0xFACPMDEVAFF1Performance Monitors Device Affinity register 1
0xFB0PMLARPerformance Monitors Lock Access Register
0xFB4PMLSRPerformance Monitors Lock Status Register
0xFB8PMAUTHSTATUSPerformance Monitors Authentication Status register
0xFBCPMDEVARCHPerformance Monitors Device Architecture register
0xFC8PMDEVIDPerformance Monitors Device ID register
0xFCCPMDEVTYPEPerformance Monitors Device Type register
0xFD0PMPIDR4Performance Monitors Peripheral Identification Register 4
0xFE0PMPIDR0Performance Monitors Peripheral Identification Register 0
0xFE4PMPIDR1Performance Monitors Peripheral Identification Register 1
0xFE8PMPIDR2Performance Monitors Peripheral Identification Register 2
0xFECPMPIDR3Performance Monitors Peripheral Identification Register 3
0xFF0PMCIDR0Performance Monitors Component Identification Register 0
0xFF4PMCIDR1Performance Monitors Component Identification Register 1
0xFF8PMCIDR2Performance Monitors Component Identification Register 2
0xFFCPMCIDR3Performance Monitors Component Identification Register 3

In the Timer block:

FrameOffsetNameDescription
CNTBaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTBaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTBaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTBaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTBaseN0x010CNTFRQCounter-timer Frequency
CNTBaseN0x014CNTEL0ACRCounter-timer EL0 Access Control Register
CNTBaseN0x018CNTVOFF[31:0]Counter-timer Virtual Offset
CNTBaseN0x01CCNTVOFF[63:32]Counter-timer Virtual Offset
CNTBaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTBaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTBaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTBaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTBaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTBaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTBaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTBaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTBaseN0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTCTLBase0x000CNTFRQCounter-timer Frequency
CNTCTLBase0x004CNTNSARCounter-timer Non-secure Access Register
CNTCTLBase0x008CNTTIDRCounter-timer Timer ID Register
CNTCTLBase0x040 + (4 * n)CNTACR<n>Counter-timer Access Control Registers
CNTCTLBase0x080 + (8 * n)CNTVOFF<n>[31:0]Counter-timer Virtual Offsets
CNTCTLBase0x084 + (8 * n)CNTVOFF<n>[63:32]Counter-timer Virtual Offsets
CNTCTLBase0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTControlBase0x000CNTCRCounter Control Register
CNTControlBase0x004CNTSRCounter Status Register
CNTControlBase0x008CNTCV[63:0]Counter Count Value register
CNTControlBase0x020CNTFID0Counter Frequency ID
CNTControlBase0x020 + (4 * n)CNTFID<n>Counter Frequency IDs, n > 0
CNTControlBase0x10CNTSCRCounter Scale Register
CNTControlBase0x1CCNTIDCounter Identification Register
CNTControlBase0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTEL0BaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTEL0BaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTEL0BaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTEL0BaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTEL0BaseN0x010CNTFRQCounter-timer Frequency
CNTEL0BaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTEL0BaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTEL0BaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTEL0BaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTEL0BaseN0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTReadBase0x000CNTCV[63:0]Counter Count Value register
CNTReadBase0xFD0 + (4 * n)CounterID<n>Counter ID registers

In the GIC Distributor block:

OffsetNameDescription
0x0000GICD_CTLRDistributor Control Register
0x0004GICD_TYPERInterrupt Controller Type Register
0x0008GICD_IIDRDistributor Implementer Identification Register
0x000CGICD_TYPER2Interrupt Controller Type Register 2
0x0010GICD_STATUSRError Reporting Status Register
0x0010GICD_STATUSRError Reporting Status Register
0x0040GICD_SETSPI_NSRSet Non-secure SPI Pending Register
0x0048GICD_CLRSPI_NSRClear Non-secure SPI Pending Register
0x0050GICD_SETSPI_SRSet Secure SPI Pending Register
0x0058GICD_CLRSPI_SRClear Secure SPI Pending Register
0x0080 + (4 * n)GICD_IGROUPR<n>Interrupt Group Registers
0x0100 + (4 * n)GICD_ISENABLER<n>Interrupt Set-Enable Registers
0x0180 + (4 * n)GICD_ICENABLER<n>Interrupt Clear-Enable Registers
0x0200 + (4 * n)GICD_ISPENDR<n>Interrupt Set-Pending Registers
0x0280 + (4 * n)GICD_ICPENDR<n>Interrupt Clear-Pending Registers
0x0300 + (4 * n)GICD_ISACTIVER<n>Interrupt Set-Active Registers
0x0380 + (4 * n)GICD_ICACTIVER<n>Interrupt Clear-Active Registers
0x0400 + (4 * n)GICD_IPRIORITYR<n>Interrupt Priority Registers
0x0800 + (4 * n)GICD_ITARGETSR<n>Interrupt Processor Targets Registers
0x0C00 + (4 * n)GICD_ICFGR<n>Interrupt Configuration Registers
0x0D00 + (4 * n)GICD_IGRPMODR<n>Interrupt Group Modifier Registers
0x0E00 + (4 * n)GICD_NSACR<n>Non-secure Access Control Registers
0x0F00GICD_SGIRSoftware Generated Interrupt Register
0x0F10 + (4 * n)GICD_CPENDSGIR<n>SGI Clear-Pending Registers
0x0F20 + (4 * n)GICD_SPENDSGIR<n>SGI Set-Pending Registers
0x1000 + (4 * n)GICD_IGROUPR<n>EInterrupt Group Registers (extended SPI range)
0x1200 + (4 * n)GICD_ISENABLER<n>EInterrupt Set-Enable Registers
0x1400 + (4 * n)GICD_ICENABLER<n>EInterrupt Clear-Enable Registers
0x1600 + (4 * n)GICD_ISPENDR<n>EInterrupt Set-Pending Registers (extended SPI range)
0x1800 + (4 * n)GICD_ICPENDR<n>EInterrupt Clear-Pending Registers (extended SPI range)
0x1A00 + (4 * n)GICD_ISACTIVER<n>EInterrupt Set-Active Registers (extended SPI range)
0x1C00 + (4 * n)GICD_ICACTIVER<n>EInterrupt Clear-Active Registers (extended SPI range)
0x2000 + (4 * n)GICD_IPRIORITYR<n>EHolds the priority of the corresponding interrupt for each extended SPI supported by the GIC.
0x3000 + (4 * n)GICD_ICFGR<n>EInterrupt Configuration Registers (Extended SPI Range)
0x3400 + (4 * n)GICD_IGRPMODR<n>EInterrupt Group Modifier Registers (extended SPI range)
0x3600 + (4 * n)GICD_NSACR<n>ENon-secure Access Control Registers
0x6000 + (8 * n)GICD_IROUTER<n>Interrupt Routing Registers
0x8000 + (8 * n)GICD_IROUTER<n>EInterrupt Routing Registers (Extended SPI Range)

In the GIC ITS control block:

OffsetNameDescription
0x0000GITS_CTLRITS Control Register
0x0004GITS_IIDRITS Identification Register
0x0008GITS_TYPERITS Type Register
0x0010GITS_MPAMIDRReport maximum PARTID and PMG Register
0x0014GITS_PARTIDRSet PARTID and PMG Register
0x0018GITS_MPIDRReport ITS's affinity.
0x0080GITS_CBASERITS Command Queue Descriptor
0x0088GITS_CWRITERITS Write Register
0x0090GITS_CREADRITS Read Register
0x0100 + (8 * n)GITS_BASER<n>ITS Translation Table Descriptors
0x20020GITS_SGIRITS SGI Register

In the GIC ITS translation block:

OffsetNameDescription
0x0040GITS_TRANSLATERITS Translation Register

In the GIC Redistributor block:

FrameOffsetNameDescription
RD_base0x0000GICR_CTLRRedistributor Control Register
RD_base0x0004GICR_IIDRRedistributor Implementer Identification Register
RD_base0x0008GICR_TYPERRedistributor Type Register
RD_base0x0010GICR_STATUSRError Reporting Status Register
RD_base0x0010GICR_STATUSRError Reporting Status Register
RD_base0x0014GICR_WAKERRedistributor Wake Register
RD_base0x0018GICR_MPAMIDRReport maximum PARTID and PMG Register
RD_base0x001CGICR_PARTIDRSet PARTID and PMG Register
RD_base0x0040GICR_SETLPIRSet LPI Pending Register
RD_base0x0048GICR_CLRLPIRClear LPI Pending Register
RD_base0x0070GICR_PROPBASERRedistributor Properties Base Address Register
RD_base0x0078GICR_PENDBASERRedistributor LPI Pending Table Base Address Register
RD_base0x00A0GICR_INVLPIRRedistributor Invalidate LPI Register
RD_base0x00B0GICR_INVALLRRedistributor Invalidate All Register
RD_base0x00C0GICR_SYNCRRedistributor Synchronize Register
SGI_base0x0080GICR_IGROUPR0Interrupt Group Register 0
SGI_base0x0080 + (4 * n)GICR_IGROUPR<n>EInterrupt Group Registers
SGI_base0x0100GICR_ISENABLER0Interrupt Set-Enable Register 0
SGI_base0x0100 + (4 * n)GICR_ISENABLER<n>EInterrupt Set-Enable Registers
SGI_base0x0180GICR_ICENABLER0Interrupt Clear-Enable Register 0
SGI_base0x0180 + (4 * n)GICR_ICENABLER<n>EInterrupt Clear-Enable Registers
SGI_base0x0200GICR_ISPENDR0Interrupt Set-Pending Register 0
SGI_base0x0200 + (4 * n)GICR_ISPENDR<n>EInterrupt Set-Pending Registers
SGI_base0x0280GICR_ICPENDR0Interrupt Clear-Pending Register 0
SGI_base0x0280 + (4 * n)GICR_ICPENDR<n>EInterrupt Clear-Pending Registers
SGI_base0x0300GICR_ISACTIVER0Interrupt Set-Active Register 0
SGI_base0x0300 + (4 * n)GICR_ISACTIVER<n>EInterrupt Set-Active Registers
SGI_base0x0380GICR_ICACTIVER0Interrupt Clear-Active Register 0
SGI_base0x0380 + (4 * n)GICR_ICACTIVER<n>EInterrupt Clear-Active Registers
SGI_base0x0400 + (4 * n)GICR_IPRIORITYR<n>Interrupt Priority Registers
SGI_base0x0400 + (4 * n)GICR_IPRIORITYR<n>EInterrupt Priority Registers (extended PPI range)
SGI_base0x0400 + (4 * n)GICR_IPRIORITYR<n>Interrupt Priority Registers
SGI_base0x0C00GICR_ICFGR0Interrupt Configuration Register 0
SGI_base0x0C00 + (4 * n)GICR_ICFGR<n>EInterrupt configuration registers
SGI_base0x0C04GICR_ICFGR1Interrupt Configuration Register 1
SGI_base0x0D00GICR_IGRPMODR0Interrupt Group Modifier Register 0
SGI_base0x0D00 + (4 * n)GICR_IGRPMODR<n>EInterrupt Group Modifier Registers
SGI_base0x0E00GICR_NSACRNon-secure Access Control Register
VLPI_base0x0070GICR_VPROPBASERVirtual Redistributor Properties Base Address Register
VLPI_base0x0078GICR_VPENDBASERVirtual Redistributor LPI Pending Table Base Address Register
VLPI_base0x0080GICR_VSGIRRedistributor virtual SGI pending state request register
VLPI_base0x0088GICR_VSGIPENDRRedistributor virtual SGI pending state register

In the GIC Virtual CPU interface block:

OffsetNameDescription
0x0000GICV_CTLRVirtual Machine Control Register
0x0004GICV_PMRVirtual Machine Priority Mask Register
0x0008GICV_BPRVirtual Machine Binary Point Register
0x000CGICV_IARVirtual Machine Interrupt Acknowledge Register
0x0010GICV_EOIRVirtual Machine End Of Interrupt Register
0x0014GICV_RPRVirtual Machine Running Priority Register
0x0018GICV_HPPIRVirtual Machine Highest Priority Pending Interrupt Register
0x001CGICV_ABPRVirtual Machine Aliased Binary Point Register
0x0020GICV_AIARVirtual Machine Aliased Interrupt Acknowledge Register
0x0024GICV_AEOIRVirtual Machine Aliased End Of Interrupt Register
0x0028GICV_AHPPIRVirtual Machine Aliased Highest Priority Pending Interrupt Register
0x002CGICV_STATUSRVirtual Machine Error Reporting Status Register
0x00D0 + (4 * n)GICV_APR<n>Virtual Machine Active Priorities Registers
0x00FCGICV_IIDRVirtual Machine CPU Interface Identification Register
0x1000GICV_DIRVirtual Machine Deactivate Interrupt Register

In the CTIGIC Virtual interface control block:

OffsetNameDescription
0x0000x0000CTICONTROLGICH_HCRCTIHypervisor Control registerRegister
0x0100x0004CTIINTACKGICH_VTRCTIVirtual OutputType Trigger Acknowledge registerRegister
0x0140x0008CTIAPPSETGICH_VMCRCTIVirtual ApplicationMachine TriggerControl Set registerRegister
0x0180x0010CTIAPPCLEARGICH_MISRCTIMaintenance ApplicationInterrupt TriggerStatus Clear registerRegister
0x01C0x0020CTIAPPPULSEGICH_EISRCTIEnd ApplicationInterrupt PulseStatus registerRegister
0x020 + (4 * n)0x0030CTIINEN<n>GICH_ELRSRCTIEmpty InputList TriggerRegister toStatus Output Channel Enable registersRegister
0x0A00x00F0 + (4 * n)CTIOUTEN<n>GICH_APR<n>CTIActive InputPriorities Channel to Output Trigger Enable registersRegisters
0x1300x0100 + (4 * n)CTITRIGINSTATUSGICH_LR<n>CTIList Trigger In Status registerRegisters
0x134CTITRIGOUTSTATUSCTI Trigger Out Status register
0x138CTICHINSTATUSCTI Channel In Status register
0x13CCTICHOUTSTATUSCTI Channel Out Status register
0x140CTIGATECTI Channel Gate Enable register
0x144ASICCTLCTI External Multiplexer Control register
0x150CTIDEVCTLCTI Device Control register
0xF00CTIITCTRLCTI Integration mode Control register
0xFA0CTICLAIMSETCTI CLAIM Tag Set register
0xFA4CTICLAIMCLRCTI CLAIM Tag Clear register
0xFA8CTIDEVAFF0CTI Device Affinity register 0
0xFACCTIDEVAFF1CTI Device Affinity register 1
0xFB0CTILARCTI Lock Access Register
0xFB4CTILSRCTI Lock Status Register
0xFB8CTIAUTHSTATUSCTI Authentication Status register
0xFBCCTIDEVARCHCTI Device Architecture register
0xFC0CTIDEVID2CTI Device ID register 2
0xFC4CTIDEVID1CTI Device ID register 1
0xFC8CTIDEVIDCTI Device ID register 0
0xFCCCTIDEVTYPECTI Device Type register
0xFD0CTIPIDR4CTI Peripheral Identification Register 4
0xFE0CTIPIDR0CTI Peripheral Identification Register 0
0xFE4CTIPIDR1CTI Peripheral Identification Register 1
0xFE8CTIPIDR2CTI Peripheral Identification Register 2
0xFECCTIPIDR3CTI Peripheral Identification Register 3
0xFF0CTICIDR0CTI Component Identification Register 0
0xFF4CTICIDR1CTI Component Identification Register 1
0xFF8CTICIDR2CTI Component Identification Register 2
0xFFCCTICIDR3CTI Component Identification Register 3

In the GIC CPU interfaceMPAM block:

OffsetNameDescription
0x0000GICC_CTLRCPU Interface Control Register
0x0004GICC_PMRCPU Interface Priority Mask Register
0x0008GICC_BPRCPU Interface Binary Point Register
0x000CGICC_IARCPU Interface Interrupt Acknowledge Register
0x0010GICC_EOIRCPU Interface End Of Interrupt Register
0x0014GICC_RPRCPU Interface Running Priority Register
0x0018GICC_HPPIRCPU Interface Highest Priority Pending Interrupt Register
0x001CGICC_ABPRCPU Interface Aliased Binary Point Register
0x0020GICC_AIARCPU Interface Aliased Interrupt Acknowledge Register
0x0024GICC_AEOIRCPU Interface Aliased End Of Interrupt Register
0x0028GICC_AHPPIRCPU Interface Aliased Highest Priority Pending Interrupt Register
0x002CGICC_STATUSRCPU Interface Status Register
0x002CGICC_STATUSRCPU Interface Status Register
0x00D0 + (4 * n)GICC_APR<n>CPU Interface Active Priorities Registers
0x00E0 + (4 * n)GICC_NSAPR<n>CPU Interface Non-secure Active Priorities Registers
0x00FCGICC_IIDRCPU Interface Identification Register
0x1000GICC_DIRCPU Interface Deactivate Interrupt Register
FrameOffsetNameDescription
MPAMF_BASE_ns0x0000MPAMF_IDRMPAM Features Identification Register
MPAMF_BASE_ns0x0018MPAMF_IIDRMPAM Implementation Identification Register
MPAMF_BASE_ns0x0020MPAMF_AIDRMPAM Architecture Identification Register
MPAMF_BASE_ns0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification Register
MPAMF_BASE_ns0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID register
MPAMF_BASE_ns0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID register
MPAMF_BASE_ns0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification Register
MPAMF_BASE_ns0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification Register
MPAMF_BASE_ns0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID register
MPAMF_BASE_ns0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification Register
MPAMF_BASE_ns0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID register
MPAMF_BASE_ns0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID register
MPAMF_BASE_ns0x00F0MPAMF_ECRMPAM Error Control Register
MPAMF_BASE_ns0x00F8MPAMF_ESRMPAM Error Status Register
MPAMF_BASE_ns0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection Register
MPAMF_BASE_ns0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration Register
MPAMF_BASE_ns0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration Register
MPAMF_BASE_ns0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration Register
MPAMF_BASE_ns0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration Register
MPAMF_BASE_ns0x0400MPAMCFG_PRIMPAM Priority Partition Configuration Register
MPAMF_BASE_ns0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration Register
MPAMF_BASE_ns0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration Register
MPAMF_BASE_ns0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection Register
MPAMF_BASE_ns0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation Register
MPAMF_BASE_ns0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register
MPAMF_BASE_ns0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register
MPAMF_BASE_ns0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register
MPAMF_BASE_ns0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
MPAMF_BASE_ns0x0840MSMON_CSUMPAM Cache Storage Usage Monitor Register
MPAMF_BASE_ns0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture Register
MPAMF_BASE_ns0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor Register
MPAMF_BASE_ns0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_ns0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor Register
MPAMF_BASE_ns0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_ns0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration Register
MPAMF_BASE_ns0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration Register
MPAMF_BASE_s0x0000MPAMF_IDRMPAM Features Identification Register
MPAMF_BASE_s0x0008MPAMF_SIDRMPAM Features Secure Identification Register
MPAMF_BASE_s0x0018MPAMF_IIDRMPAM Implementation Identification Register
MPAMF_BASE_s0x0020MPAMF_AIDRMPAM Architecture Identification Register
MPAMF_BASE_s0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification Register
MPAMF_BASE_s0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID register
MPAMF_BASE_s0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID register
MPAMF_BASE_s0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification Register
MPAMF_BASE_s0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification Register
MPAMF_BASE_s0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID register
MPAMF_BASE_s0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification Register
MPAMF_BASE_s0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID register
MPAMF_BASE_s0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID register
MPAMF_BASE_s0x00F0MPAMF_ECRMPAM Error Control Register
MPAMF_BASE_s0x00F8MPAMF_ESRMPAM Error Status Register
MPAMF_BASE_s0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection Register
MPAMF_BASE_s0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration Register
MPAMF_BASE_s0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration Register
MPAMF_BASE_s0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration Register
MPAMF_BASE_s0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration Register
MPAMF_BASE_s0x0400MPAMCFG_PRIMPAM Priority Partition Configuration Register
MPAMF_BASE_s0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration Register
MPAMF_BASE_s0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration Register
MPAMF_BASE_s0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection Register
MPAMF_BASE_s0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation Register
MPAMF_BASE_s0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register
MPAMF_BASE_s0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register
MPAMF_BASE_s0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register
MPAMF_BASE_s0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
MPAMF_BASE_s0x0840MSMON_CSUMPAM Cache Storage Usage Monitor Register
MPAMF_BASE_s0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture Register
MPAMF_BASE_s0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor Register
MPAMF_BASE_s0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_s0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor Register
MPAMF_BASE_s0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_s0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration Register
MPAMF_BASE_s0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration Register

In the GIC ITS controlPMU block:

OffsetNameDescription
0xC00PMCNTENSET_EL0Performance Monitors Count Enable Set register
0xC20PMCNTENCLR_EL0Performance Monitors Count Enable Clear register
0xC40PMINTENSET_EL1Performance Monitors Interrupt Enable Set register
0xC60PMINTENCLR_EL1Performance Monitors Interrupt Enable Clear register
0xC80PMOVSCLR_EL0Performance Monitors Overflow Flag Status Clear register
0xCA0PMSWINC_EL0Performance Monitors Software Increment register
0xCC0PMOVSSET_EL0Performance Monitors Overflow Flag Status Set register
0xE00PMCFGRPerformance Monitors Configuration Register
0xE04PMCR_EL0Performance Monitors Control Register
0xE20PMCEID0Performance Monitors Common Event Identification register 0
0xE24PMCEID1Performance Monitors Common Event Identification register 1
0xE28PMCEID2Performance Monitors Common Event Identification register 2
0xE2CPMCEID3Performance Monitors Common Event Identification register 3
0xE40PMMIRPerformance Monitors Machine Identification Register
0xF00PMITCTRLPerformance Monitors Integration mode Control register
0xFA8PMDEVAFF0Performance Monitors Device Affinity register 0
0xFACPMDEVAFF1Performance Monitors Device Affinity register 1
0xFB0PMLARPerformance Monitors Lock Access Register
0xFB4PMLSRPerformance Monitors Lock Status Register
0xFB8PMAUTHSTATUSPerformance Monitors Authentication Status register
0xFBCPMDEVARCHPerformance Monitors Device Architecture register
0xFC8PMDEVIDPerformance Monitors Device ID register
0xFCCPMDEVTYPEPerformance Monitors Device Type register
0xFD0PMPIDR4Performance Monitors Peripheral Identification Register 4
0xFE0PMPIDR0Performance Monitors Peripheral Identification Register 0
0xFE4PMPIDR1Performance Monitors Peripheral Identification Register 1
0xFE8PMPIDR2Performance Monitors Peripheral Identification Register 2
0xFECPMPIDR3Performance Monitors Peripheral Identification Register 3
0xFF0PMCIDR0Performance Monitors Component Identification Register 0
0xFF4PMCIDR1Performance Monitors Component Identification Register 1
0xFF8PMCIDR2Performance Monitors Component Identification Register 2
0xFFCPMCIDR3Performance Monitors Component Identification Register 3
0x00000x000 + (8 * n)GITS_CTLRPMEVCNTR<n>_EL0ITSPerformance ControlMonitors RegisterEvent Count Registers
0x00040x0F8GITS_IIDRPMCCNTR_EL0[31:0]ITSPerformance IdentificationMonitors RegisterCycle Counter
0x00080x0FCGITS_TYPERPMCCNTR_EL0[63:32]ITSPerformance TypeMonitors RegisterCycle Counter
0x00100x200GITS_MPAMIDRPMPCSR[31:0]ReportProgram maximumCounter PARTID and PMGSample Register
0x00140x204GITS_PARTIDRPMPCSR[63:32]SetProgram PARTIDCounter and PMGSample Register
0x00180x208GITS_MPIDRPMCID1SRReportCONTEXTIDR_EL1 ITS'sSample affinity.Register
0x00200x20CGITS_STATUSRPMVIDSRITSVMID Error Reporting StatusSample Register
0x00280x220GITS_UMSIRPMPCSR[31:0]ITSProgram UnmappedCounter MSISample registerRegister
0x00800x224GITS_CBASERPMPCSR[63:32]ITSProgram CommandCounter QueueSample DescriptorRegister
0x00880x228GITS_CWRITERPMCID1SRITSCONTEXTIDR_EL1 WriteSample Register
0x00900x22CGITS_CREADRPMCID2SRITSCONTEXTIDR_EL2 ReadSample Register
0x01000x400 + (84 * n)GITS_BASER<n>PMEVTYPER<n>_EL0ITSPerformance TranslationMonitors TableEvent DescriptorsType Registers
0x200200x47CGITS_SGIRPMCCFILTR_EL0ITSPerformance SGIMonitors Cycle Counter Filter Register

In the GIC Virtual interface control block:

OffsetNameDescription
0x0000GICH_HCRHypervisor Control Register
0x0004GICH_VTRVirtual Type Register
0x0008GICH_VMCRVirtual Machine Control Register
0x0010GICH_MISRMaintenance Interrupt Status Register
0x0020GICH_EISREnd Interrupt Status Register
0x0030GICH_ELRSREmpty List Register Status Register
0x00F0 + (4 * n)GICH_APR<n>Active Priorities Registers
0x0100 + (4 * n)GICH_LR<n>List Registers

In the GIC ITS translation block:

OffsetNameDescription
0x0040GITS_TRANSLATERITS Translation Register

In the RAS block:

OffsetNameDescription
0x000 + (64 * n)ERR<n>FRError Record Feature Register
0x008 + (64 * n)ERR<n>CTLRError Record Control Register
0x010 + (64 * n)ERR<n>STATUSError Record Primary Status Register
0x018 + (64 * n)ERR<n>ADDRError Record Address Register
0x020 + (64 * n)ERR<n>MISC0Error Record Miscellaneous Register 0
0x028 + (64 * n)ERR<n>MISC1Error Record Miscellaneous Register 1
0x030 + (64 * n)ERR<n>MISC2Error Record Miscellaneous Register 2
0x038 + (64 * n)ERR<n>MISC3Error Record Miscellaneous Register 3
0x800 + (8 * n)ERRIMPDEF<n>IMPLEMENTATION DEFINED Register <n>
0x800 + (64 * n)ERR<n>PFGFPseudo-fault Generation Feature Register
0x800 + (8 * n)ERRIMPDEF<n>IMPLEMENTATION DEFINED Register &lt;n&gt;
0x808 + (64 * n)ERR<n>PFGCTLPseudo-fault Generation Control Register
0x810 + (64 * n)ERR<n>PFGCDNPseudo-fault Generation Countdown Register
0xE00ERRGSRError Group Status Register
0xE10ERRIIDRImplementation Identification Register
0xE80ERRFHICR0Fault Handling Interrupt Configuration Register 0
0xE80 + (8 * n)ERRIRQCR<n>Generic Error Interrupt Configuration Register
0xE88ERRFHICR1Fault Handling Interrupt Configuration Register 1
0xE8CERRFHICR2Fault Handling Interrupt Configuration Register 2
0xE90ERRERICR0Error Recovery Interrupt Configuration Register 0
0xE98ERRERICR1Error Recovery Interrupt Configuration Register 1
0xE9CERRERICR2Error Recovery Interrupt Configuration Register 2
0xEA0ERRCRICR0Critical Error Interrupt Configuration Register 0
0xEA8ERRCRICR1Critical Error Interrupt Configuration Register 1
0xEACERRCRICR2Critical Error Interrupt Configuration Register 2
0xEF8ERRIRQSRError Interrupt Status Register
0xFA8ERRDEVAFFDevice Affinity Register
0xFBCERRDEVARCHDevice Architecture Register
0xFC8ERRDEVIDDevice Configuration Register
0xFD0ERRPIDR4Peripheral Identification Register 4
0xFE0ERRPIDR0Peripheral Identification Register 0
0xFE4ERRPIDR1Peripheral Identification Register 1
0xFE8ERRPIDR2Peripheral Identification Register 2
0xFECERRPIDR3Peripheral Identification Register 3
0xFF0ERRCIDR0Component Identification Register 0
0xFF4ERRCIDR1Component Identification Register 1
0xFF8ERRCIDR2Component Identification Register 2
0xFFCERRCIDR3Component Identification Register 3

In the AMUTimer block:

OffsetNameDescription
0x000 + (8 * n)AMEVCNTR0<n>[31:0]Activity Monitors Event Counter Registers 0
0x004 + (8 * n)AMEVCNTR0<n>[63:32]Activity Monitors Event Counter Registers 0
0x100 + (8 * n)AMEVCNTR1<n>[31:0]Activity Monitors Event Counter Registers 1
0x104 + (8 * n)AMEVCNTR1<n>[63:32]Activity Monitors Event Counter Registers 1
0x400 + (4 * n)AMEVTYPER0<n>Activity Monitors Event Type Registers 0
0x480 + (4 * n)AMEVTYPER1<n>Activity Monitors Event Type Registers 1
0xC00AMCNTENSET0Activity Monitors Count Enable Set Register 0
0xC04AMCNTENSET1Activity Monitors Count Enable Set Register 1
0xC20AMCNTENCLR0Activity Monitors Count Enable Clear Register 0
0xC24AMCNTENCLR1Activity Monitors Count Enable Clear Register 1
0xCE0AMCGCRActivity Monitors Counter Group Configuration Register
0xE00AMCFGRActivity Monitors Configuration Register
0xE04AMCRActivity Monitors Control Register
0xE08AMIIDRActivity Monitors Implementation Identification Register
0xFA8AMDEVAFF0Activity Monitors Device Affinity Register 0
0xFACAMDEVAFF1Activity Monitors Device Affinity Register 1
0xFBCAMDEVARCHActivity Monitors Device Architecture Register
0xFCCAMDEVTYPEActivity Monitors Device Type Register
0xFD0AMPIDR4Activity Monitors Peripheral Identification Register 4
0xFE0AMPIDR0Activity Monitors Peripheral Identification Register 0
0xFE4AMPIDR1Activity Monitors Peripheral Identification Register 1
0xFE8AMPIDR2Activity Monitors Peripheral Identification Register 2
0xFECAMPIDR3Activity Monitors Peripheral Identification Register 3
0xFF0AMCIDR0Activity Monitors Component Identification Register 0
0xFF4AMCIDR1Activity Monitors Component Identification Register 1
0xFF8AMCIDR2Activity Monitors Component Identification Register 2
0xFFCAMCIDR3Activity Monitors Component Identification Register 3
FrameOffsetNameDescription
CNTBaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTBaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTBaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTBaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTBaseN0x010CNTFRQCounter-timer Frequency
CNTBaseN0x014CNTEL0ACRCounter-timer EL0 Access Control Register
CNTBaseN0x018CNTVOFF[31:0]Counter-timer Virtual Offset
CNTBaseN0x01CCNTVOFF[63:32]Counter-timer Virtual Offset
CNTBaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTBaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTBaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTBaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTBaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTBaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTBaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTBaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTBaseN0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTCTLBase0x000CNTFRQCounter-timer Frequency
CNTCTLBase0x004CNTNSARCounter-timer Non-secure Access Register
CNTCTLBase0x008CNTTIDRCounter-timer Timer ID Register
CNTCTLBase0x040 + (4 * n)CNTACR<n>Counter-timer Access Control Registers
CNTCTLBase0x080 + (8 * n)CNTVOFF<n>[31:0]Counter-timer Virtual Offsets
CNTCTLBase0x084 + (8 * n)CNTVOFF<n>[63:32]Counter-timer Virtual Offsets
CNTCTLBase0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTControlBase0x000CNTCRCounter Control Register
CNTControlBase0x004CNTSRCounter Status Register
CNTControlBase0x008CNTCV[63:0]Counter Count Value register
CNTControlBase0x020CNTFID0Counter Frequency ID
CNTControlBase0x020 + (4 * n)CNTFID<n>Counter Frequency IDs, n > 0
CNTControlBase0x10CNTSCRCounter Scale Register
CNTControlBase0x1CCNTIDCounter Identification Register
CNTControlBase0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTEL0BaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTEL0BaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTEL0BaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTEL0BaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTEL0BaseN0x010CNTFRQCounter-timer Frequency
CNTEL0BaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTEL0BaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTEL0BaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTEL0BaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTEL0BaseN0xFD0 + (4 * n)CounterID<n>Counter ID registers
CNTReadBase0x000CNTCV[63:0]Counter Count Value register
CNTReadBase0xFD0 + (4 * n)CounterID<n>Counter ID registers

In the MPAM block:

FrameOffsetNameDescription
MPAMF_BASE_ns0x0000MPAMF_IDRMPAM Features Identification Register
MPAMF_BASE_ns0x0018MPAMF_IIDRMPAM Implementation Identification Register
MPAMF_BASE_ns0x0020MPAMF_AIDRMPAM Architecture Identification Register
MPAMF_BASE_ns0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification Register
MPAMF_BASE_ns0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID register
MPAMF_BASE_ns0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID register
MPAMF_BASE_ns0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification Register
MPAMF_BASE_ns0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification Register
MPAMF_BASE_ns0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID register
MPAMF_BASE_ns0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification Register
MPAMF_BASE_ns0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID register
MPAMF_BASE_ns0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID register
MPAMF_BASE_ns0x00F0MPAMF_ECRMPAM Error Control Register
MPAMF_BASE_ns0x00F8MPAMF_ESRMPAM Error Status Register
MPAMF_BASE_ns0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection Register
MPAMF_BASE_ns0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration Register
MPAMF_BASE_ns0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration Register
MPAMF_BASE_ns0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration Register
MPAMF_BASE_ns0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration Register
MPAMF_BASE_ns0x0400MPAMCFG_PRIMPAM Priority Partition Configuration Register
MPAMF_BASE_ns0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration Register
MPAMF_BASE_ns0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration Register
MPAMF_BASE_ns0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection Register
MPAMF_BASE_ns0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation Register
MPAMF_BASE_ns0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register
MPAMF_BASE_ns0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register
MPAMF_BASE_ns0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register
MPAMF_BASE_ns0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
MPAMF_BASE_ns0x0840MSMON_CSUMPAM Cache Storage Usage Monitor Register
MPAMF_BASE_ns0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture Register
MPAMF_BASE_ns0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor Register
MPAMF_BASE_ns0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_ns0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor Register
MPAMF_BASE_ns0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_ns0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration Register
MPAMF_BASE_ns0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration Register
MPAMF_BASE_s0x0000MPAMF_IDRMPAM Features Identification Register
MPAMF_BASE_s0x0008MPAMF_SIDRMPAM Features Secure Identification Register
MPAMF_BASE_s0x0018MPAMF_IIDRMPAM Implementation Identification Register
MPAMF_BASE_s0x0020MPAMF_AIDRMPAM Architecture Identification Register
MPAMF_BASE_s0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification Register
MPAMF_BASE_s0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID register
MPAMF_BASE_s0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID register
MPAMF_BASE_s0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification Register
MPAMF_BASE_s0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification Register
MPAMF_BASE_s0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID register
MPAMF_BASE_s0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification Register
MPAMF_BASE_s0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID register
MPAMF_BASE_s0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID register
MPAMF_BASE_s0x00F0MPAMF_ECRMPAM Error Control Register
MPAMF_BASE_s0x00F8MPAMF_ESRMPAM Error Status Register
MPAMF_BASE_s0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection Register
MPAMF_BASE_s0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration Register
MPAMF_BASE_s0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration Register
MPAMF_BASE_s0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration Register
MPAMF_BASE_s0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration Register
MPAMF_BASE_s0x0400MPAMCFG_PRIMPAM Priority Partition Configuration Register
MPAMF_BASE_s0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration Register
MPAMF_BASE_s0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration Register
MPAMF_BASE_s0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection Register
MPAMF_BASE_s0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation Register
MPAMF_BASE_s0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter Register
MPAMF_BASE_s0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control Register
MPAMF_BASE_s0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter Register
MPAMF_BASE_s0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control Register
MPAMF_BASE_s0x0840MSMON_CSUMPAM Cache Storage Usage Monitor Register
MPAMF_BASE_s0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture Register
MPAMF_BASE_s0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor Register
MPAMF_BASE_s0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_s0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor Register
MPAMF_BASE_s0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture Register
MPAMF_BASE_s0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration Register
MPAMF_BASE_s0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration Register

3001/0907/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e7104721157

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)