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CNTHV_CTL_EL2, Counter-timer Virtual Timer Control register (EL2)

The CNTHV_CTL_EL2 characteristics are:

Purpose

Control register for the EL2 virtual timer.

Configuration

AArch64 System register CNTHV_CTL_EL2 bits [31:0] are architecturally mapped to AArch32 System register CNTHV_CTL[31:0] .

This register is present only when FEAT_VHE is implemented. Otherwise, direct accesses to CNTHV_CTL_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

CNTHV_CTL_EL2 is a 64-bit register.

Field descriptions

The CNTHV_CTL_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0ISTATUSIMASKENABLE
313029282726252423222120191817161514131211109876543210

Bits [63:3]

Reserved, RES0.

ISTATUS, bit [2]

The status of the timer. This bit indicates whether the timer condition is met:

ISTATUSMeaning
0b0

Timer condition is not met.

0b1

Timer condition is met.

When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.

When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.

This bit is read-only.

IMASK, bit [1]

Timer interrupt mask bit. Permitted values are:

IMASKMeaning
0b0

Timer interrupt is not masked by the IMASK bit.

0b1

Timer interrupt is masked by the IMASK bit.

For more information, see the description of the ISTATUS bit.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

ENABLE, bit [0]

Enables the timer. Permitted values are:

ENABLEMeaning
0b0

Timer disabled.

0b1

Timer enabled.

Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTHV_TVAL_EL2 continues to count down.

Note

Disabling the output signal might be a power-saving option.

Accessing the CNTHV_CTL_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHV_CTL_EL2 or CNTV_CTL_EL0 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, CNTHV_CTL_EL2

op0op1CRnCRmop2
0b110b1000b11100b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return CNTHV_CTL_EL2; elsif PSTATE.EL == EL3 then return CNTHV_CTL_EL2;

MSR CNTHV_CTL_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b11100b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then CNTHV_CTL_EL2 = X[t]; elsif PSTATE.EL == EL3 then CNTHV_CTL_EL2 = X[t];

MRS <Xt>, CNTV_CTL_EL0

op0op1CRnCRmop2
0b110b0110b11100b00110b001

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then return CNTHVS_CTL_EL2; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then return CNTHV_CTL_EL2; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x170]; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then return CNTHVS_CTL_EL2; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then return CNTHV_CTL_EL2; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL3 then return CNTV_CTL_EL0;

MSR CNTV_CTL_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b11100b00110b001

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then CNTHVS_CTL_EL2 = X[t]; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x170] = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then CNTHVS_CTL_EL2 = X[t]; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL3 then CNTV_CTL_EL0 = X[t];

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

Accessing the CNTHV_CTL_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHV_CTL_EL2 or CNTV_CTL_EL0 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, CNTHV_CTL_EL2

op0op1CRnCRmop2
0b110b1000b11100b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return CNTHV_CTL_EL2; elsif PSTATE.EL == EL3 then return CNTHV_CTL_EL2;

MSR CNTHV_CTL_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b11100b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then CNTHV_CTL_EL2 = X[t]; elsif PSTATE.EL == EL3 then CNTHV_CTL_EL2 = X[t];

MRS <Xt>, CNTV_CTL_EL0

op0op1CRnCRmop2
0b110b0110b11100b00110b001

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then return CNTHVS_CTL_EL2; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then return CNTHV_CTL_EL2; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x170]; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then return CNTHVS_CTL_EL2; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then return CNTHV_CTL_EL2; else return CNTV_CTL_EL0; elsif PSTATE.EL == EL3 then return CNTV_CTL_EL0;

MSR CNTV_CTL_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b11100b00110b001

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then CNTHVS_CTL_EL2 = X[t]; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x170] = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then CNTHVS_CTL_EL2 = X[t]; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t]; else CNTV_CTL_EL0 = X[t]; elsif PSTATE.EL == EL3 then CNTV_CTL_EL0 = X[t];




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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