ESR_EL2, Exception Syndrome Register (EL2)

The ESR_EL2 characteristics are:

Purpose

Holds syndrome information for an exception taken to EL2.

Configuration

AArch64 System register ESR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HSR[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

ESR_EL2 is a 64-bit register.

Field descriptions

The ESR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0ISS2
ECILISS
313029282726252423222120191817161514131211109876543210

ESR_EL2 is made UNKNOWN as a result of an exception return from EL2.

When an UNPREDICTABLE instruction is treated as UNDEFINED, and the exception is taken to EL2, the value of ESR_EL2 is UNKNOWN. The value written to ESR_EL2 must be consistent with a value that could be created as a result of an exception from the same Exception level that generated the exception as a result of a situation that is not UNPREDICTABLE at that Exception level, in order to avoid the possibility of a privilege violation.

Bits [63:37]

Reserved, RES0.

ISS2, bits [36:32]

When FEAT_LS64 is implemented:

If a memory access generated by an ST64BV or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field holds register specifier, Xs.

For any other Data Abort, this field is RES0.


Otherwise:

Reserved, RES0.

EC, bits [31:26]

Exception Class. Indicates the reason for the exception that this register holds information about.

For each EC value, the table references a subsection that gives information about:

Possible values of the EC field are:

ECMeaningISSApplies when
0b000000

Unknown reason.

ISS encoding for exceptions with an unknown reason
0b000001

Trapped WF* instruction execution.

Conditional WF* instructions that fail their condition code check do not cause an exception.

ISS encoding for an exception from a WF* instruction
0b000011

Trapped MCR or MRC access with (coproc==0b1111) that is not reported using EC 0b000000.

ISS encoding for an exception from an MCR or MRC accessWhen AArch32 is supported at any Exception level
0b000100

Trapped MCRR or MRRC access with (coproc==0b1111) that is not reported using EC 0b000000.

ISS encoding for an exception from an MCRR or MRRC accessWhen AArch32 is supported at any Exception level
0b000101

Trapped MCR or MRC access with (coproc==0b1110).

ISS encoding for an exception from an MCR or MRC accessWhen AArch32 is supported at any Exception level
0b000110

Trapped LDC or STC access.

The only architected uses of these instruction are:

ISS encoding for an exception from an LDC or STC instructionWhen AArch32 is supported at any Exception level
0b000111

Access to SVE, Advanced SIMD or floating-point functionality trapped by CPACR_EL1.FPEN, CPTR_EL2.FPEN, CPTR_EL2.TFP, or CPTR_EL3.TFP control.

Excludes exceptions resulting from CPACR_EL1 when the value of HCR_EL2.TGE is 1, or because SVE or Advanced SIMD and floating-point are not implemented. These are reported with EC value 0b000000 as described in 'The EC used to report an exception routed to EL2 because HCR_EL2.TGE is 1'.

ISS encoding for an exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from the FPEN and TFP traps
0b001000

Trapped VMRS access, from ID group trap, that is not reported using EC 0b000111.

ISS encoding for an exception from an MCR or MRC accessWhen AArch32 is supported at any Exception level
0b001001

Trapped use of a Pointer authentication instruction because HCR_EL2.API == 0 || SCR_EL3.API == 0.

ISS encoding for an exception from a Pointer Authentication instruction when HCR_EL2.API == 0 || SCR_EL3.API == 0When FEAT_PAuth is implemented
0b001010

Trapped execution of an LD64B, ST64B, ST64BV, or ST64BV0 instruction.

ISS encoding for an exception from an LD64B or ST64B* instructionWhen FEAT_LS64 is implemented
0b001100

Trapped MRRC access with (coproc==0b1110).

ISS encoding for an exception from an MCRR or MRRC accessWhen AArch32 is supported at any Exception level
0b001101

Branch Target Exception.

ISS encoding for an exception from Branch Target Identification instructionWhen FEAT_BTI is implemented
0b001110

Illegal Execution state.

ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault
0b010001

SVC instruction execution in AArch32 state.

This is reported in ESR_EL2 only when the exception is generated because the value of HCR_EL2.TGE is 1.

ISS encoding for an exception from HVC or SVC instruction executionWhen AArch32 is supported at any Exception level
0b010010

HVC instruction execution in AArch32 state, when HVC is not disabled.

ISS encoding for an exception from HVC or SVC instruction executionWhen AArch32 is supported at any Exception level
0b010011

SMC instruction execution in AArch32 state, when SMC is not disabled.

This is reported in ESR_EL2 only when the exception is generated because the value of HCR_EL2.TSC is 1.

ISS encoding for an exception from SMC instruction execution in AArch32 stateWhen AArch32 is supported at any Exception level
0b010101

SVC instruction execution in AArch64 state.

ISS encoding for an exception from HVC or SVC instruction executionWhen AArch64 is supported at any Exception level
0b010110

HVC instruction execution in AArch64 state, when HVC is not disabled.

ISS encoding for an exception from HVC or SVC instruction executionWhen AArch64 is supported at any Exception level
0b010111

SMC instruction execution in AArch64 state, when SMC is not disabled.

This is reported in ESR_EL2 only when the exception is generated because the value of HCR_EL2.TSC is 1.

ISS encoding for an exception from SMC instruction execution in AArch64 stateWhen AArch64 is supported at any Exception level
0b011000

Trapped MSR, MRS or System instruction execution in AArch64 state, that is not reported using EC 0b000000, 0b000001 or 0b000111.

This includes all instructions that cause exceptions that are part of the encoding space defined in 'System instruction class encoding overview', except for those exceptions reported using EC values 0b000000, 0b000001, or 0b000111.

ISS encoding for an exception from MSR, MRS, or System instruction execution in AArch64 stateWhen AArch64 is supported at any Exception level
0b011001

Access to SVE functionality trapped as a result of CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ, that is not reported using EC 0b000000.

ISS encoding for an exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZWhen FEAT_SVE is implemented
0b011010

Trapped ERET, ERETAA, or ERETAB instruction execution.

ISS encoding for an exception from an ERET, ERETAA, or ERETAB instructionWhen FEAT_PAuth is implemented and FEAT_NV is implemented
0b011100

Exception from a Pointer Authentication instruction authentication failure

ISS encoding for an exception from a Pointer Authentication instruction authentication failureWhen FEAT_FPAC is implemented
0b100000

Instruction Abort from a lower Exception level.

Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions.

ISS encoding for an exception from an Instruction Abort
0b100001

Instruction Abort taken without a change in Exception level.

Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions.

ISS encoding for an exception from an Instruction Abort
0b100010

PC alignment fault exception.

ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault
0b100100

Data Abort from a lower Exception level, excluding Data Aborts taken to EL2 as a result of accesses generated associated with VNCR_EL2 as part of nested virtualization support.

These Data Aborts might be generated from Exception levels in any Execution state.

Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions.

ISS encoding for an exception from a Data Abort
0b100101

Data Abort without a change in Exception level, or Data Aborts taken to EL2 as a result of accesses generated associated with VNCR_EL2 as part of nested virtualization support.

Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related exceptions.

ISS encoding for an exception from a Data Abort
0b100110

SP alignment fault exception.

ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault
0b101000

Trapped floating-point exception taken from AArch32 state.

This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is IMPLEMENTATION DEFINED.

ISS encoding for an exception from a trapped floating-point exceptionWhen AArch32 is supported at any Exception level
0b101100

Trapped floating-point exception taken from AArch64 state.

This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is IMPLEMENTATION DEFINED.

ISS encoding for an exception from a trapped floating-point exceptionWhen AArch64 is supported at any Exception level
0b101111

SError interrupt.

ISS encoding for an SError interrupt
0b110000

Breakpoint exception from a lower Exception level.

ISS encoding for an exception from a Breakpoint or Vector Catch debug exception
0b110001

Breakpoint exception taken without a change in Exception level.

ISS encoding for an exception from a Breakpoint or Vector Catch debug exception
0b110010

Software Step exception from a lower Exception level.

ISS encoding for an exception from a Software Step exception
0b110011

Software Step exception taken without a change in Exception level.

ISS encoding for an exception from a Software Step exception
0b110100

Watchpoint from a lower Exception level, excluding Watchpoint Exceptions taken to EL2 as a result of accesses generated associated with VNCR_EL2 as part of nested virtualization support.

These Watchpoint Exceptions might be generated from Exception levels using any Execution state.

ISS encoding for an exception from a Watchpoint exception
0b110101

Watchpoint exceptions without a change in Exception level, or Watchpoint exceptions taken to EL2 as a result of accesses generated associated with VNCR_EL2 as part of nested virtualization support.

ISS encoding for an exception from a Watchpoint exception
0b111000

BKPT instruction execution in AArch32 state.

ISS encoding for an exception from execution of a Breakpoint instructionWhen AArch32 is supported at any Exception level
0b111010

Vector Catch exception from AArch32 state.

The only case where a Vector Catch exception is taken to an Exception level that is using AArch64 is when the exception is routed to EL2 and EL2 is using AArch64.

ISS encoding for an exception from a Breakpoint or Vector Catch debug exceptionWhen AArch32 is supported at any Exception level
0b111100

BRK instruction execution in AArch64 state.

This is reported in ESR_EL3 only if a BRK instruction is executed.

ISS encoding for an exception from execution of a Breakpoint instructionWhen AArch64 is supported at any Exception level

All other EC values are reserved by Arm, and:

The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IL, bit [25]

Instruction Length for synchronous exceptions. Possible values of this bit are:

ILMeaning
0b0

16-bit instruction trapped.

0b1

32-bit instruction trapped. This value is also used when the exception is one of the following:

  • An SError interrupt.

  • An Instruction Abort exception.

  • A PC alignment fault exception.

  • An SP alignment fault exception.

  • A Data Abort exception for which the value of the ISV bit is 0.

  • An Illegal Execution state exception.

  • Any debug exception except for Breakpoint instruction exceptions. For Breakpoint instruction exceptions, this bit has its standard meaning:

    • 0b0: 16-bit T32 BKPT instruction.

    • 0b1: 32-bit A32 BKPT instruction or A64 BRK instruction.

  • An exception reported using EC value 0b000000.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ISS, bits [24:0]

Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class.

Typically, an ISS encoding has a number of subfields. When an ISS subfield holds a register number, the value returned in that field is the AArch64 view of the register number.

For an exception taken from AArch32 state, see 'Mapping of the general-purpose registers between the Execution states'.

If the AArch32 register descriptor is 0b1111, then:

When the EC field is 0b000000, indicating an exception with an unknown reason, the ISS field is not valid, RES0.

ISS encoding for exceptions with an unknown reason

2423222120191817161514131211109876543210
RES0

Bits [24:0]

Reserved, RES0.

When an exception is reported using this EC code the IL field is set to 1.

This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations:

ISS encoding for an exception from a WF* instruction

2423222120191817161514131211109876543210
CVCONDRES0TI

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [19:2]

Reserved, RES0.

TI, bits [1:0]

Trapped instruction. Possible values of this bit are:

TIMeaningApplies when
0b00

WFI trapped.

0b01

WFE trapped.

0b10

WFIT trapped.

When FEAT_WFxT is implemented
0b11

WFET trapped.

When FEAT_WFxT is implemented

When FEAT_WFxT is implemented, this is a two bit field as shown. Otherwise, bit[1] is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The following fields describe configuration settings for generating this exception:

ISS encoding for an exception from an MCR or MRC access

2423222120191817161514131211109876543210
CVCONDOpc2Opc1CRnRtCRmDirection

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Opc2, bits [19:17]

The Opc2 value from the issued instruction.

For a trapped VMRS access, holds the value 0b000.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Opc1, bits [16:14]

The Opc1 value from the issued instruction.

For a trapped VMRS access, holds the value 0b111.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CRn, bits [13:10]

The CRn value from the issued instruction.

For a trapped VMRS access, holds the reg field from the VMRS instruction encoding.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Rt, bits [9:5]

The Rt value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CRm, bits [4:1]

The CRm value from the issued instruction.

For a trapped VMRS access, holds the value 0b0000.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Direction, bit [0]

Indicates the direction of the trapped instruction.

DirectionMeaning
0b0

Write to System register space. MCR instruction.

0b1

Read from System register space. MRC or VMRS instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000011:

The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000101:

The following fields describe configuration settings for generating exceptions that are reported using EC value 0b001000:

ISS encoding for an exception from an LD64B or ST64B* instruction

2423222120191817161514131211109876543210
ISS

ISS, bits [24:0]

ISSMeaning
0b0000000000000000000000000

ST64BV instruction trapped.

0b0000000000000000000000001

ST64BV0 instruction trapped.

0b0000000000000000000000010

LD64B or ST64B instruction trapped.

All other values are reserved.

ISS encoding for an exception from an MCRR or MRRC access

2423222120191817161514131211109876543210
CVCONDOpc1RES0Rt2RtCRmDirection

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Opc1, bits [19:16]

The Opc1 value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [15]

Reserved, RES0.

Rt2, bits [14:10]

The Rt2 value from the issued instruction, the second general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Rt, bits [9:5]

The Rt value from the issued instruction, the first general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CRm, bits [4:1]

The CRm value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Direction, bit [0]

Indicates the direction of the trapped instruction.

DirectionMeaning
0b0

Write to System register space. MCRR instruction.

0b1

Read from System register space. MRRC instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000100:

The following sections describe configuration settings for generating exceptions that are reported using EC value 0b001100:

Note

If the Armv8-A architecture is implemented with an ETMv4 implementation, MCRR and MRRC accesses to trace registers are UNDEFINED and the resulting exception is higher priority than an exception due to these traps.

ISS encoding for an exception from an LDC or STC instruction

2423222120191817161514131211109876543210
CVCONDimm8RES0RnOffsetAMDirection

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

imm8, bits [19:12]

The immediate value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [11:10]

Reserved, RES0.

Rn, bits [9:5]

The Rn value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.

This field is valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction. When AM[2] is 1, indicating a literal form of the LDC or STC instruction, this field is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Offset, bit [4]

Indicates whether the offset is added or subtracted:

OffsetMeaning
0b0

Subtract offset.

0b1

Add offset.

This bit corresponds to the U bit in the instruction encoding.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

AM, bits [3:1]

Addressing mode. The permitted values of this field are:

AMMeaning
0b000

Immediate unindexed.

0b001

Immediate post-indexed.

0b010

Immediate offset.

0b011

Immediate pre-indexed.

0b100

For a trapped STC instruction or a trapped T32 LDC instruction this encoding is reserved.

0b110

For a trapped STC instruction, this encoding is reserved.

The values 0b101 and 0b111 are reserved. The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in System and memory-mapped registers and translation table entries'.

Bit [2] in this subfield indicates the instruction form, immediate or literal.

Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Direction, bit [0]

Indicates the direction of the trapped instruction.

DirectionMeaning
0b0

Write to memory. STC instruction.

0b1

Read from memory. LDC instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The following fields describe the configuration settings for the traps that are reported using EC value 0b000110:

ISS encoding for an exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from the FPEN and TFP traps

2423222120191817161514131211109876543210
CVCONDRES0

The accesses covered by this trap include:

For an implementation that does not include either SVE or support for floating-point and Advanced SIMD, the exception is reported using the EC value 0b000000.

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [19:0]

Reserved, RES0.

The following sections describe the configuration settings for the traps that are reported using EC value 0b000111:

ISS encoding for an exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ

2423222120191817161514131211109876543210
RES0

The accesses covered by this trap include:

For an implementation that does not include SVE, the exception is reported using the EC value 0b000000.

Bits [24:0]

Reserved, RES0.

The following sections describe the configuration settings for the traps that are reported using EC value 0b011001:

ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault

2423222120191817161514131211109876543210
RES0

Bits [24:0]

Reserved, RES0.

There are no configuration settings for generating Illegal Execution state exceptions and PC alignment fault exceptions. For more information about these exceptions, see 'The Illegal Execution state exception' and 'PC alignment checking'.

'SP alignment checking' describes the configuration settings for generating SP alignment fault exceptions.

ISS encoding for an exception from HVC or SVC instruction execution

2423222120191817161514131211109876543210
RES0imm16

Bits [24:16]

Reserved, RES0.

imm16, bits [15:0]

The value of the immediate field from the HVC or SVC instruction.

For an HVC instruction, and for an A64 SVC instruction, this is the value of the imm16 field of the issued instruction.

For an A32 or T32 SVC instruction:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

In AArch32 state, the HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.

For T32 and A32 instructions, see 'SVC' and 'HVC'.

For A64 instructions, see 'SVC' and 'HVC'.

If FEAT_FGT is implemented, HFGITR_EL2.{SVC_EL1, SVC_EL0} control fine-grained traps on SVC execution.

ISS encoding for an exception from SMC instruction execution in AArch32 state

2423222120191817161514131211109876543210
CVCONDCCKNOWNPASSRES0

For an SMC instruction that completes normally and generates an exception that is taken to EL3, the ISS encoding is RES0.

For an SMC instruction that is trapped to EL2 from EL1 because HCR_EL2.TSC is 1, the ISS encoding is as shown in the diagram.

CV, bit [24]

Condition code valid.

CVMeaning
0b0

The COND field is not valid.

0b1

The COND field is valid.

For exceptions taken from AArch64, CV is set to 1.

For exceptions taken from AArch32:

This field is valid only if CCKNOWNPASS is 1, otherwise it is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

COND, bits [23:20]

For exceptions taken from AArch64, this field is set to 0b1110.

The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.

For exceptions taken from AArch32:

This field is valid only if CCKNOWNPASS is 1, otherwise it is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CCKNOWNPASS, bit [19]

Indicates whether the instruction might have failed its condition code check.

CCKNOWNPASSMeaning
0b0

The instruction was unconditional, or was conditional and passed its condition code check.

0b1

The instruction was conditional, and might have failed its condition code check.

Note

In an implementation in which an SMC instruction that fails it code check is not trapped, this field can always return the value 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [18:0]

Reserved, RES0.

HCR_EL2.TSC describes the configuration settings for trapping SMC instructions to EL2.

'System calls' describes the case where these exceptions are trapped to EL3.

ISS encoding for an exception from SMC instruction execution in AArch64 state

2423222120191817161514131211109876543210
RES0imm16

Bits [24:16]

Reserved, RES0.

imm16, bits [15:0]

The value of the immediate field from the issued SMC instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The value of ISS[24:0] described here is used both:

HCR_EL2.TSC describes the configuration settings for trapping SMC from EL1 modes.

'System calls' describes the case where these exceptions are trapped to EL3.

ISS encoding for an exception from MSR, MRS, or System instruction execution in AArch64 state

2423222120191817161514131211109876543210
RES0Op0Op2Op1CRnRtCRmDirection

Bits [24:22]

Reserved, RES0.

Op0, bits [21:20]

The Op0 value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Op2, bits [19:17]

The Op2 value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Op1, bits [16:14]

The Op1 value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CRn, bits [13:10]

The CRn value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Rt, bits [9:5]

The Rt value from the issued instruction, the general-purpose register used for the transfer.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CRm, bits [4:1]

The CRm value from the issued instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Direction, bit [0]

Indicates the direction of the trapped instruction.

DirectionMeaning
0b0

Write access, including MSR instructions.

0b1

Read access, including MRS instructions.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For exceptions caused by System instructions, see 'System instructions' subsection of 'Branches, exception generating and System instructions' for the encoding values returned by an instruction.

The following fields describe configuration settings for generating the exception that is reported using EC value 0b011000:

ISS encoding for an IMPLEMENTATION DEFINED exception to EL3

2423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [24:0]

IMPLEMENTATION DEFINED.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ISS encoding for an exception from an Instruction Abort

2423222120191817161514131211109876543210
RES0SETFnVEARES0S1PTWRES0IFSC

Bits [24:13]

Reserved, RES0.

SET, bits [12:11]

When FEAT_RAS is implemented:

Synchronous Error Type. When IFSC is 0b010000, describes the PE error state after taking the Instruction Abort exception.

SETMeaning
0b00

Recoverable state (UER).

0b10

Uncontainable (UC).

0b11

Restartable state (UEO).

All other values are reserved.

Note

Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in a PE state that is not recoverable.

This field is valid only if the IFSC code is 0b010000. It is RES0 for all other aborts.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

FnV, bit [10]

FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.

FnVMeaning
0b0

FAR is valid.

0b1

FAR is not valid, and holds an UNKNOWN value.

This field is valid only if the IFSC code is 0b010000. It is RES0 for all other aborts.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

EA, bit [9]

External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.

For any abort other than an External abort this bit returns a value of 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [8]

Reserved, RES0.

S1PTW, bit [7]

For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:

S1PTWMeaning
0b0

Fault not on a stage 2 translation for a stage 1 translation table walk.

0b1

Fault on the stage 2 translation of an access for a stage 1 translation table walk.

For any abort other than a stage 2 fault this bit is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [6]

Reserved, RES0.

IFSC, bits [5:0]

Instruction Fault Status Code.

IFSCMeaningApplies when
0b000000

Address size fault, level 0 of translation or translation table base register.

0b000001

Address size fault, level 1.

0b000010

Address size fault, level 2.

0b000011

Address size fault, level 3.

0b000100

Translation fault, level 0.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001001

Access flag fault, level 1.

0b001010

Access flag fault, level 2.

0b001011

Access flag fault, level 3.

0b001000

Access flag fault, level 0.

When FEAT_LPA2 is implemented
0b001100

Permission fault, level 0.

When FEAT_LPA2 is implemented
0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External abort, not on translation table walk or hardware update of translation table.

0b010011

Synchronous External abort on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented
0b010100

Synchronous External abort on translation table walk or hardware update of translation table, level 0.

0b010101

Synchronous External abort on translation table walk or hardware update of translation table, level 1.

0b010110

Synchronous External abort on translation table walk or hardware update of translation table, level 2.

0b010111

Synchronous External abort on translation table walk or hardware update of translation table, level 3.

0b011000

Synchronous parity or ECC error on memory access, not on translation table walk.

When FEAT_RAS is not implemented
0b011011

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b011100

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0.

When FEAT_RAS is not implemented
0b011101

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1.

When FEAT_RAS is not implemented
0b011110

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2.

When FEAT_RAS is not implemented
0b011111

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3.

When FEAT_RAS is not implemented
0b101001

Address size fault, level -1.

When FEAT_LPA2 is implemented
0b101011

Translation fault, level -1.

When FEAT_LPA2 is implemented
0b110000

TLB conflict abort.

0b110001

Unsupported atomic hardware update fault.

When FEAT_HAFDBS is implemented

All other values are reserved.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults'.

Note

Because Access flag faults and Permission faults can result only from a Block or Page translation table descriptor, they cannot occur at level 0.

If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ISS encoding for an exception from a Data Abort

2423222120191817161514131211109876543210
ISVSASSSESRTSFARVNCRBits[12:11]FnVEACMS1PTWWnRDFSC

When FEAT_LS64 is implemented, if a memory access generated by an ST64BV or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this ISS encoding includes ISS2, bits[36:32].

ISV, bit [24]

Instruction Syndrome Valid. Indicates whether the syndrome information in ISS[23:14] is valid.

ISVMeaning
0b0

No valid instruction syndrome. ISS[23:14] are RES0.

0b1

ISS[23:14] hold a valid instruction syndrome.

In ESR_EL2, ISV is 1 when FEAT_LS64 is implemented and a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault.

For other faults reported in ESR_EL2, ISV is 0 except for the following stage 2 aborts:

For these stage 2 aborts, ISV is UNKNOWN if the exception was generated in Debug state in memory access mode, and otherwise indicates whether ISS[23:14] hold a valid syndrome.

For faults reported in ESR_EL1 or ESR_EL3, ISV is 1 when FEAT_LS64 is implemented and a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault. ISV is 0 for all other faults reported in ESR_EL1 or ESR_EL3.

When FEAT_RAS is implemented, ISV is 0 for any synchronous External abort.

For ISS reporting, a stage 2 abort on a stage 1 translation table walk does not return a valid instruction syndrome, and therefore ISV is 0 for these aborts.

When FEAT_RAS is not implemented, it is IMPLEMENTATION DEFINED whether ISV is set to 1 or 0 on a synchronous External abort on a stage 2 translation table walk.

When FEAT_MTE is implemented, for a synchronous Tag Check Fault abort taken to ELx, ESR_ELx.FNV is 0 and FAR_ELx is valid.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

SAS, bits [23:22]

When ISV == '1':

Syndrome Access Size. Indicates the size of the access attempted by the faulting operation.

SASMeaning
0b00

Byte

0b01

Halfword

0b10

Word

0b11

Doubleword

When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 0b11.

This field is UNKNOWN when the value of ISV is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

SSE, bit [21]

When ISV == '1':

Syndrome Sign Extend. For a byte, halfword, or word load operation, indicates whether the data item must be sign extended.

SSEMeaning
0b0

Sign-extension not required.

0b1

Data item must be sign-extended.

When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 0.

For all other operations, this field is 0.

This field is UNKNOWN when the value of ISV is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

SRT, bits [20:16]

When ISV == '1':

Syndrome Register Transfer. When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field holds register specifier, Xt.

If the exception was taken from an Exception level that is using AArch32, then this is the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.

This field is UNKNOWN when the value of ISV is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

SF, bit [15]

When ISV == '1':

Width of the register accessed by the instruction is Sixty-Four.

SFMeaning
0b0

Instruction loads/stores a 32-bit wide register.

0b1

Instruction loads/stores a 64-bit wide register.

Note

This field specifies the register width identified by the instruction, not the Execution state.

When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 1.

This field is UNKNOWN when the value of ISV is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

AR, bit [14]

When ISV == '1':

Acquire/Release.

ARMeaning
0b0

Instruction did not have acquire/release semantics.

0b1

Instruction did have acquire/release semantics.

When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 0.

This field is UNKNOWN when the value of ISV is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

VNCR, bit [13]

When FEAT_NV2 is implemented:

Indicates that the fault came from use of VNCR_EL2 register by EL1 code.

VNCRMeaning
0b0

The fault was not generated by the use of VNCR_EL2, by an MRS or MSR instruction executed at EL1.

0b1

The fault was generated by the use of VNCR_EL2, by an MRS or MSR instruction executed at EL1.

This field is 0 in ESR_EL1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

SET, bits [12:11]

When FEAT_RAS is implemented and FEAT_LS64 is not implemented:

Synchronous Error Type. When DFSC is 0b010000, describes the PE error state after taking the Data Abort exception.

SETMeaning
0b00

Recoverable state (UER).

0b10

Uncontainable (UC).

0b11

Restartable state (UEO).

All other values are reserved.

Note

Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in a PE state that is not recoverable.

This field is valid only if the DFSC code is 0b010000. It is RES0 for all other aborts.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


When FEAT_LS64 is implemented:

Load/Store Type. Used when an LD64B, ST64B, ST64BV, or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault.

LSTMeaning
0b01

An ST64BV instruction generated the Data Abort.

0b10

An LD64B or ST64B instruction generated the Data Abort.

0b11

An ST64BV0 instruction generated the Data Abort.

All other values are reserved.

This field is valid only if the DFSC code is 0b110101. It is RES0 for all other aborts.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

FnV, bit [10]

FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.

FnVMeaning
0b0

FAR is valid.

0b1

FAR is not valid, and holds an UNKNOWN value.

This field is valid only if the DFSC code is 0b010000. It is RES0 for all other aborts.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

EA, bit [9]

External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.

For any abort other than an External abort this bit returns a value of 0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CM, bit [8]

Cache maintenance. Indicates whether the Data Abort came from a cache maintenance or address translation instruction:

CMMeaning
0b0

The Data Abort was not generated by the execution of one of the System instructions identified in the description of value 1.

0b1

The Data Abort was generated by either the execution of a cache maintenance instruction or by a synchronous fault on the execution of an address translation instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not classified as cache maintenance instructions, and therefore their execution cannot cause this field to be set to 1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

S1PTW, bit [7]

For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:

S1PTWMeaning
0b0

Fault not on a stage 2 translation for a stage 1 translation table walk.

0b1

Fault on the stage 2 translation of an access for a stage 1 translation table walk.

For any abort other than a stage 2 fault this bit is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

WnR, bit [6]

Write not Read. Indicates whether a synchronous abort was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.

WnRMeaning
0b0

Abort caused by an instruction reading from a memory location.

0b1

Abort caused by an instruction writing to a memory location.

For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.

For faults from an atomic instruction that both reads and writes from a memory location, this bit is set to 0 if a read of the address specified by the instruction would have generated the fault which is being reported, otherwise it is set to 1. The architecture permits, but does not require, a relaxation of this requirement such that for all stage 2 aborts on stage 1 translation table walks for atomic instructions, the WnR bit is always 0.

This field is UNKNOWN for:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DFSC, bits [5:0]

Data Fault Status Code.

DFSCMeaningApplies when
0b000000

Address size fault, level 0 of translation or translation table base register.

0b000001

Address size fault, level 1.

0b000010

Address size fault, level 2.

0b000011

Address size fault, level 3.

0b000100

Translation fault, level 0.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001001

Access flag fault, level 1.

0b001010

Access flag fault, level 2.

0b001011

Access flag fault, level 3.

0b001000

Access flag fault, level 0.

When FEAT_LPA2 is implemented
0b001100

Permission fault, level 0.

When FEAT_LPA2 is implemented
0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External abort, not on translation table walk or hardware update of translation table.

0b010001

Synchronous Tag Check Fault.

When FEAT_MTE is implemented
0b010011

Synchronous External abort on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented
0b010100

Synchronous External abort on translation table walk or hardware update of translation table, level 0.

0b010101

Synchronous External abort on translation table walk or hardware update of translation table, level 1.

0b010110

Synchronous External abort on translation table walk or hardware update of translation table, level 2.

0b010111

Synchronous External abort on translation table walk or hardware update of translation table, level 3.

0b011000

Synchronous parity or ECC error on memory access, not on translation table walk.

When FEAT_RAS is not implemented
0b011011

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b011100

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0.

When FEAT_RAS is not implemented
0b011101

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1.

When FEAT_RAS is not implemented
0b011110

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2.

When FEAT_RAS is not implemented
0b011111

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3.

When FEAT_RAS is not implemented
0b100001

Alignment fault.

0b101001

Address size fault, level -1.

When FEAT_LPA2 is implemented
0b101011

Translation fault, level -1.

When FEAT_LPA2 is implemented
0b110000

TLB conflict abort.

0b110001

Unsupported atomic hardware update fault.

When FEAT_HAFDBS is implemented
0b110100

IMPLEMENTATION DEFINED fault (Lockdown).

0b110101

IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access).

All other values are reserved.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults'.

Note

Because Access flag faults and Permission faults can result only from a Block or Page translation table descriptor, they cannot occur at level 0.

If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ISS encoding for an exception from a trapped floating-point exception

2423222120191817161514131211109876543210
RES0TFVRES0VECITRIDFRES0IXFUFFOFFDZFIOF

Bit [24]

Reserved, RES0.

TFV, bit [23]

Trapped Fault Valid bit. Indicates whether the IDF, IXF, UFF, OFF, DZF, and IOF bits hold valid information about trapped floating-point exceptions.

TFVMeaning
0b0

The IDF, IXF, UFF, OFF, DZF, and IOF bits do not hold valid information about trapped floating-point exceptions and are UNKNOWN.

0b1

One or more floating-point exceptions occurred during an operation performed while executing the reported instruction. The IDF, IXF, UFF, OFF, DZF, and IOF bits indicate trapped floating-point exceptions that occurred. For more information, see 'Floating-point exceptions and exception traps'.

It is IMPLEMENTATION DEFINED whether this field is set to 0 on an exception generated by a trapped floating point exception from a vector instruction.

Note

This is not a requirement. Implementations can set this field to 1 on a trapped floating-point exception from a vector instruction and return valid information in the {IDF, IXF, UFF, OFF, DZF, IOF} fields.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [22:11]

Reserved, RES0.

VECITR, bits [10:8]

For a trapped floating-point exception from an instruction executed in AArch32 state this field is RES1.

For a trapped floating-point exception from an instruction executed in AArch64 state this field is UNKNOWN.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IDF, bit [7]

Input Denormal floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

IDFMeaning
0b0

Input denormal floating-point exception has not occurred.

0b1

Input denormal floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [6:5]

Reserved, RES0.

IXF, bit [4]

Inexact floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

IXFMeaning
0b0

Inexact floating-point exception has not occurred.

0b1

Inexact floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

UFF, bit [3]

Underflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

UFFMeaning
0b0

Underflow floating-point exception has not occurred.

0b1

Underflow floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

OFF, bit [2]

Overflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

OFFMeaning
0b0

Overflow floating-point exception has not occurred.

0b1

Overflow floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DZF, bit [1]

Divide by Zero floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

DZFMeaning
0b0

Divide by Zero floating-point exception has not occurred.

0b1

Divide by Zero floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IOF, bit [0]

Invalid Operation floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:

IOFMeaning
0b0

Invalid Operation floating-point exception has not occurred.

0b1

Invalid Operation floating-point exception occurred during execution of the reported instruction.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

In an implementation that supports the trapping of floating-point exceptions:

ISS encoding for an SError interrupt

2423222120191817161514131211109876543210
IDSRES0IESBAETEARES0DFSC

IDS, bit [24]

IMPLEMENTATION DEFINED syndrome.

IDSMeaning
0b0

Bits [23:0] of the ISS field holds the fields described in this encoding.

Note

If FEAT_RAS is not implemented, bits [23:0] of the ISS field are RES0.

0b1

Bits [23:0] of the ISS field holds IMPLEMENTATION DEFINED syndrome information that can be used to provide additional information about the SError interrupt.

Note

This field was previously called ISV.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [23:14]

Reserved, RES0.

IESB, bit [13]

When FEAT_IESB is implemented:

Implicit error synchronization event.

IESBMeaning
0b0

The SError interrupt was either not synchronized by the implicit error synchronization event or not taken immediately.

0b1

The SError interrupt was synchronized by the implicit error synchronization event and taken immediately.

This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

AET, bits [12:10]

When FEAT_RAS is implemented:

Asynchronous Error Type.

When DFSC is 0b010001, describes the PE error state after taking the SError interrupt exception.

AETMeaning
0b000

Uncontainable (UC).

0b001

Unrecoverable state (UEU).

0b010

Restartable state (UEO).

0b011

Recoverable state (UER).

0b110

Corrected (CE).

All other values are reserved.

If multiple errors are taken as a single SError interrupt exception, the overall PE error state is reported.

Note

Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.

This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

EA, bit [9]

When FEAT_RAS is implemented:

External abort type. When DFSC is 0b010001, provides an IMPLEMENTATION DEFINED classification of External aborts.

This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [8:6]

Reserved, RES0.

DFSC, bits [5:0]

When FEAT_RAS is implemented:

Data Fault Status Code.

DFSCMeaning
0b000000

Uncategorized error.

0b010001

Asynchronous SError interrupt.

All other values are reserved.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

ISS encoding for an exception from a Breakpoint or Vector Catch debug exception

2423222120191817161514131211109876543210
RES0IFSC

Bits [24:6]

Reserved, RES0.

IFSC, bits [5:0]

Instruction Fault Status Code.

IFSCMeaning
0b100010

Debug exception.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For more information about generating these exceptions:

ISS encoding for an exception from a Software Step exception

2423222120191817161514131211109876543210
ISVRES0EXIFSC

ISV, bit [24]

Instruction syndrome valid. Indicates whether the EX bit, ISS[6], is valid, as follows:

ISVMeaning
0b0

EX bit is RES0.

0b1

EX bit is valid.

See the EX bit description for more information.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [23:7]

Reserved, RES0.

EX, bit [6]

Exclusive operation. If the ISV bit is set to 1, this bit indicates whether a Load-Exclusive instruction was stepped.

EXMeaning
0b0

An instruction other than a Load-Exclusive instruction was stepped.

0b1

A Load-Exclusive instruction was stepped.

If the ISV bit is set to 0, this bit is RES0, indicating no syndrome data is available.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

IFSC, bits [5:0]

Instruction Fault Status Code.

IFSCMeaning
0b100010

Debug exception.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For more information about generating these exceptions, see 'Software Step exceptions'.

ISS encoding for an exception from a Watchpoint exception

2423222120191817161514131211109876543210
RES0RES0VNCRRES0CMRES0WnRDFSC

Bits [24:15]

Reserved, RES0.

Bit [14]

Reserved, RES0.

VNCR, bit [13]

When FEAT_NV2 is implemented:

Indicates that the watchpoint came from use of VNCR_EL2 register by EL1 code.

VNCRMeaning
0b0

The watchpoint was not generated by the use of VNCR_EL2 by EL1 code.

0b1

The watchpoint was generated by the use of VNCR_EL2 by EL1 code.

This field is 0 in ESR_EL1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [12:9]

Reserved, RES0.

CM, bit [8]

Cache maintenance. Indicates whether the Watchpoint exception came from a cache maintenance or address translation instruction:

CMMeaning
0b0

The Watchpoint exception was not generated by the execution of one of the System instructions identified in the description of value 1.

0b1

The Watchpoint exception was generated by either the execution of a cache maintenance instruction or by a synchronous Watchpoint exception on the execution of an address translation instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not classified as a cache maintenance instructions, and therefore their execution cannot cause this field to be set to 1.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [7]

Reserved, RES0.

WnR, bit [6]

Write not Read. Indicates whether the Watchpoint exception was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.

WnRMeaning
0b0

Watchpoint exception caused by an instruction reading from a memory location.

0b1

Watchpoint exception caused by an instruction writing to a memory location.

For Watchpoint exceptions on cache maintenance and address translation instructions, this bit always returns a value of 1.

For Watchpoint exceptions from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint exception, otherwise it is set to 1.

If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint exception.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

DFSC, bits [5:0]

Data Fault Status Code.

DFSCMeaning
0b100010

Debug exception.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For more information about generating these exceptions, see 'Watchpoint exceptions'.

ISS encoding for an exception from execution of a Breakpoint instruction

2423222120191817161514131211109876543210
RES0Comment

Bits [24:16]

Reserved, RES0.

Comment, bits [15:0]

Set to the instruction comment field value, zero extended as necessary.

For the AArch32 BKPT instructions, the comment field is described as the immediate field.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For more information about generating these exceptions, see 'Breakpoint instruction exceptions'.

ISS encoding for an exception from an ERET, ERETAA, or ERETAB instruction

2423222120191817161514131211109876543210
RES0ERETERETA

This EC value applies when FEAT_FGT is implemented, or when HCR_EL2.NV is 1.

Bits [24:2]

Reserved, RES0.

ERET, bit [1]

Indicates whether an ERET or ERETA* instruction was trapped to EL2.

ERETMeaning
0b0

ERET instruction trapped to EL2.

0b1

ERETAA or ERETAB instruction trapped to EL2.

If this bit is 0, the ERETA field is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

ERETA, bit [0]

Indicates whether an ERETAA or ERETAB instruction was trapped to EL2.

ERETAMeaning
0b0

ERETAA instruction trapped to EL2.

0b1

ERETAB instruction trapped to EL2.

When the ERET field is 0, this bit is RES0.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

For more information about generating these exceptions, see HCR_EL2.NV.

If FEAT_FGT is implemented, HFGITR_EL2.ERET controls fine-grained trap exceptions from ERET, ERETAA and ERETAB execution.

ISS encoding for an exception from Branch Target Identification instruction

2423222120191817161514131211109876543210
RES0BTYPE

Bits [24:2]

Reserved, RES0.

BTYPE, bits [1:0]

This field is set to the PSTATE.BTYPE value that generated the Branch Target Exception.

For more information about generating these exceptions, see 'The AArch64 application level programmers model'.

ISS encoding for an exception from a Pointer Authentication instruction when HCR_EL2.API == 0 || SCR_EL3.API == 0

2423222120191817161514131211109876543210
RES0

Bits [24:0]

Reserved, RES0.

For more information about generating these exceptions, see:

ISS encoding for an exception from a Pointer Authentication instruction authentication failure

2423222120191817161514131211109876543210
RES0Exception as a result of an Instruction key or a Data keyException as a result of an A key or a B key

Bits [24:2]

Reserved, RES0.

Bit [1]

This field indicates whether the exception is as a result of an Instruction key or a Data key.

Meaning
0b0

Instruction Key.

0b1

Data Key.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [0]

This field indicates whether the exception is as a result of an A key or a B key.

Meaning
0b0

A key.

0b1

B key.

On a Warm reset, this field resets to an architecturally UNKNOWN value.

The following instructions generate an exception when the Pointer Authentication Code (PAC) is incorrect:

It is IMPLEMENTATION DEFINED whether the following instructions generate an exception directly from the authorization failure, rather than changing the address in a way that will generate a translation fault when the address is accessed:

Accessing the ESR_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ESR_EL2 or ESR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings:

MRS <Xt>, ESR_EL2

op0op1CRnCRmop2
0b110b1000b01010b00100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return ESR_EL1; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return ESR_EL2; elsif PSTATE.EL == EL3 then return ESR_EL2;

MSR ESR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b01010b00100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then ESR_EL1 = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then ESR_EL2 = X[t]; elsif PSTATE.EL == EL3 then ESR_EL2 = X[t];

MRS <Xt>, ESR_EL1

op0op1CRnCRmop2
0b110b0000b01010b00100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.ESR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x138]; else return ESR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return ESR_EL2; else return ESR_EL1; elsif PSTATE.EL == EL3 then return ESR_EL1;

MSR ESR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b01010b00100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.ESR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x138] = X[t]; else ESR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then ESR_EL2 = X[t]; else ESR_EL1 = X[t]; elsif PSTATE.EL == EL3 then ESR_EL1 = X[t];




30/09/2020 15:06; ccead0cb9f089f9ceec50268e82aec9e71047211

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