The TLBIMVAAL characteristics are:
Invalidate all cached copies of translation table entries from TLBs that meet the following requirements:
From the entries that match these requirements, the entries that are invalidated are required for the following translation regime:
The invalidation only applies to the PE that executes this System instruction.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TLBIMVAAL are UNDEFINED.
This System instruction is not implemented in architecture versions before Armv8.
TLBIMVAAL is a 32-bit System instruction.
The TLBIMVAAL input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA | RES0 |
Virtual address to match. Any unlocked TLB entries that match the VA will be affected by this System instruction, regardless of the ASID.
Reserved, RES0.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1000 | 0b0111 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TTLB == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FB == '1' then TLBIMVAALIS(R[t]); else TLBIMVAAL(R[t]); elsif PSTATE.EL == EL2 then TLBIMVAAL(R[t]); elsif PSTATE.EL == EL3 then TLBIMVAAL(R[t]);
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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