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MPAMCFG_MBW_PBM<n>, MPAM Bandwidth Portion Bitmap Partition Configuration Register, n = 0 - 127

The MPAMCFG_MBW_PBM<n> characteristics are:

Purpose

The MPAMCFG_MBW_PBM<n> register array gives access to the memory bandwidth portion bitmap. Each register in the array is a read-write register that configures the bandwidthcache portions <3232n * n> to <(3232n * n) + 31> that a PARTID is allowed to allocate.

After setting MPAMCFG_PART_SEL with a PARTID, software writes to one or more of the MPAMCFG_MBW_PBM<n> registers to configure which bandwidthcache portions the PARTID is allowed to allocate.

The MPAMCFG_MBW_PBM<n> register that contains the bitmap bit corresponding to memory bandwidth portion p has n equal to p[11:5]. The field, P<<x + (32 * n)>> of that MPAMCFG_MBW_PBM<n> register that contain the bitmap bit corresponding to memory bandwidth portion p has x equal to p[4:0].

The MPAMCFG_MBW_PBM<n> register that contains the bitmap bit corresponding to memory bandwidth portion p has n equal to p >> 5. The field, P<x> of that MPAMCFG_MBW_PBM<n> register that contain the bitmap bit corresponding to memory bandwidth portion p has x equal to p & 0x1F.

The MPAMCFG_MBW_PBM<n>_s registers control the bandwidth portion bitmap for the Secure PARTID selected by the Secure instance of MPAMCFG_PART_SEL. The MPAMCFG_MBW_PBM<n>_ns registers control the bandwidth portion bitmap for the Non-secure PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL.

If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

Configuration

The power domain of MPAMCFG_MBW_PBM<n> is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM is implemented, MPAMF_IDR.HAS_MBW_PART == 1 and MPAMF_MBW_IDR.HAS_PBM == 1. Otherwise, direct accesses to MPAMCFG_MBW_PBM<n> are RES0.

Attributes

MPAMCFG_MBW_PBM<n> is a 32-bit register.

Field descriptions

The MPAMCFG_MBW_PBM<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
P<32 * n + 31>P31P<32 * n + 30>P30P<32 * n + 29>P29P<32 * n + 28>P28P<32 * n + 27>P27P<32 * n + 26>P26P<32 * n + 25>P25P<32 * n + 24>P24P<32 * n + 23>P23P<32 * n + 22>P22P<32 * n + 21>P21P<32 * n + 20>P20P<32 * n + 19>P19P<32 * n + 18>P18P<32 * n + 17>P17P<32 * n + 16>P16P<32 * n + 15>P15P<32 * n + 14>P14P<32 * n + 13>P13P<32 * n + 12>P12P<32 * n + 11>P11P<32 * n + 10>P10P<32 * n + 9>P9P<32 * n + 8>P8P<32 * n + 7>P7P<32 * n + 6>P6P<32 * n + 5>P5P<32 * n + 4>P4P<32 * n + 3>P3P<32 * n + 2>P2P<32 * n + 1>P1P<32 * n>P0

P<x>, bit [x], for x = 0 to 31

Portion allocation control bit. Each bandwidth portion allocation control bit MPAMCFG_MBW_PBM<n>.P<x> grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate bandwidth within bandwidth portion 32n + x.

P<x + (32 * n)>, bit [x], for x = 31 to 0

Portion allocation control bit. Each bandwidth portion allocation control bit MPAMCFG_MBW_PBM<n>.P<<x + (32 * n)>> grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate bandwidth within bandwidth portion <x + (32 * n)>.

P<x + (32 * n)>>Meaning
0b0

The PARTID is not permitted to allocate into bandwidth portion <x32n + (32 * n)>.x.

0b1

The PARTID is permitted to allocate within bandwidth portion <x32n + (32 * n)>.x.

The number of bits in the bandwidth portion partitioning bit map of this component is given in MPAMF_MBW_IDR.BWPBM_WD. BWPBM_WD contains a value from 1 to 212, inclusive. Values of BWPBM_WD greater than 32 require a group of 32-bit registers to access the bandwidth portion bitmap, up to 128 32-bit registers.

Bits MPAMCFG_MBW_PBM<n>.P<<<x>, + (32 * n)>>, where <x32n + (32x * n)>is greater than orBWPBM_WD, equalare not required to BWPBM_WDbe areimplemented. RES0:

Accessing the MPAMCFG_MBW_PBM<n>

This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.

MPAMCFG_MBW_PBM<n>_s must be accessible from the Secure MPAM feature page. MPAMCFG_MBW_PBM<n>_ns must be accessible from the Non-secure MPAM feature page.

MPAMCFG_MBW_PBM<n>_s and MPAMCFG_MBW_PBM<n>_ns must be separate registers. The Secure instance (MPAMCFG_MBW_PBM<n>_s) accesses the memory bandwidth portion bitmap used for Secure PARTIDs, and the Non-secure instance (MPAMCFG_MBW_PBM<n>_ns) accesses the memory bandwidth portion bitmap used for Non-secure PARTIDs.

When RIS is implemented, loads and stores to MPAMCFG_MBW_PBM<n> access the memory bandwidth portion bitmap configuration settings for the bandwidth resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When RIS is not implemented, loads and stores to MPAMCFG_MBW_PBM<n> access the memory bandwidth portion bitmap configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When PARTID narrowing is implemented, loads and stores to MPAMCFG_MBW_PBM<n> access the memory bandwidth portion bitmap configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.

When PARTID narrowing is not implemented, loads and stores to MPAMCFG_MBW_PBM<n> access the memory bandwidth portion bitmap configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.

MPAMCFG_MBW_PBM<n> can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>_s

Accesses on this interface are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>_ns

Accesses on this interface are RW.




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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