The GICR_IGROUPR<n>E characteristics are:
Controls whether the corresponding PPI is in Group 0 or Group 1.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_IGROUPR<n>E are RES0.
When GICD_CTLR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGROUPR<n>E is a 32-bit register.
The GICR_IGROUPR<n>E bit assignments are:
Group status bit.
Group_status_bit<x> | Meaning |
---|---|
0b0 | When GICD_CTLR.DS==1, the corresponding interrupt is Group 0. When GICD_CTLR.DS==0, the corresponding interrupt is Secure. |
0b1 | When GICD_CTLR.DS==1, the corresponding interrupt is Group 1. When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
If affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGRPMODR<n>E to form a 2-bit field that defines an interrupt group. The encoding of this field is described in GICR_IGRPMODR<n>E.
If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGROUPR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0080 + (4 * n) | GICR_IGROUPR<n>E |
This interface is accessible as follows:
30/09/2020 15:06; ccead0cb9f089f9ceec50268e82aec9e71047211
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