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The GICD_ICFGR<n> characteristics are:
Determines whether the corresponding interrupt is edge-triggered or level-sensitive.
These registers are available in all GIC configurations. If the GIC implementation supports two Security states, these registers are Common.
GICD_ICFGR1 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICFGR1 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
For SGIs and PPIs:
For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
For SGIs, Int_config fields are RO, meaning that GICD_ICFGR0 is RO.
Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE.
Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state.
Fields corresponding to unimplemented interrupts are RAZ/WI.
GICD_ICFGR<n> is a 32-bit register.
The GICD_ICFGR<n> bit assignments are:
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit [2x]) is RES0.
Possible values of Int_config[1] (bit [2x+1]) are:
Int_config<x> | Meaning |
---|---|
0b00 | Corresponding interrupt is level-sensitive. |
0b01 | Corresponding interrupt is edge-triggered. |
For SGIs, Int_config[1] is RAO/WI.
For SPIs and PPIs, Int_config[1] is programmable unless the implementation supports two Security states and the bit corresponds to a Group 0 or Secure Group 1 interrupt, in which case the bit is RAZ/WI to Non-secure accesses.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x0C00 + (4 * n) | GICD_ICFGR<n> |
This interface is accessible as follows:
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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