The AMIIDR characteristics are:
Defines the implementer and revisions of the AMU.
The power domain of AMIIDR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMIIDR are RES0.
AMIIDR is a 32-bit register.
The AMIIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Variant | Revision | Implementer |
This field is an AMU part identifier.
The value of this field is IMPLEMENTATION DEFINED.
If AMPIDR0 is implemented, AMPIDR0.PART_0 matches bits [27:20] of this field.
If AMPIDR1 is implemented, AMPIDR1.PART_1 matches bits [31:28] of this field.
This field distinguishes product variants or major revisions of the product.
The value of this field is IMPLEMENTATION DEFINED.
If AMPIDR2 is implemented, AMPIDR2.REVISION matches AMIIDR.Variant.
This field distinguishes minor revisions of the product.
The value of this field is IMPLEMENTATION DEFINED.
If AMPIDR3 is implemented, AMPIDR3.REVAND matches AMIIDR.Revision.
Contains the JEP106 code of the company that implemented the AMU.
For an Arm implementation, this field reads as 0x43B.
Bits [11:8] contain the JEP106 continuation code of the implementer.
Bit 7 is RES0
Bits [6:0] contain the JEP106 identity code of the implementer.
If AMPIDR4 is implemented, AMPIDR4.DES_2 matches bits [11:8] of this field.
If AMPIDR2 is implemented, AMPIDR2.DES_1 matches bits [6:4] of this field.
If AMPIDR1 is implemented, AMPIDR1.DES_0 matches bits [3:0] of this field.
Component | Offset | Instance |
---|---|---|
AMU | 0xE08 | AMIIDR |
Accesses on this interface are RO.
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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