(old) htmldiff from-(new)

MPAMCFG_CPBM<n>, MPAM Cache Portion Bitmap Partition Configuration Register, n = 0 - 1023

The MPAMCFG_CPBM<n> characteristics are:

Purpose

The MPAMCFG_CPBM<n> register array gives access to the cache portion bitmap. Each register in the array is a read-write register that configures the cache portions numbered from <n32n * 32> to <3132n + (n * 32)>31 that a PARTID is allowed to allocate.

After setting MPAMCFG_PART_SEL with a PARTID, software writes to the MPAMCFG_CPBM<n> register to configure which cache portions the PARTID is allowed to allocate.

The MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has n equal to p[15:5]. The field, P<x>, of that MPAMCFG_CPBM<n> register that contain the bitmap bit corresponding to cache portion p has x equal to p[4:0].

The MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has n equal to p >> 5. The field, P<x>, of that MPAMCFG_CPBM<n> register that contain the bitmap bit corresponding to cache portion p has x equal to p & 0x1F.

MPAMCFG_CPBM<n>_s controls cache portions for the Secure PARTID selected by the Secure instance of MPAMCFG_PART_SEL. MPAMCFG_CPBM<n>_ns controls the cache portions for the Non-secure PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL.

If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

Configuration

The power domain of MPAMCFG_CPBM<n> is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM is implemented and MPAMF_IDR.HAS_CPOR_PART == 1. Otherwise, direct accesses to MPAMCFG_CPBM<n> are RES0.

Attributes

MPAMCFG_CPBM<n> is a 32-bit register.

Field descriptions

The MPAMCFG_CPBM<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
P<32 * n + 31>P31P<32 * n + 30>P30P<32 * n + 29>P29P<32 * n + 28>P28P<32 * n + 27>P27P<32 * n + 26>P26P<32 * n + 25>P25P<32 * n + 24>P24P<32 * n + 23>P23P<32 * n + 22>P22P<32 * n + 21>P21P<32 * n + 20>P20P<32 * n + 19>P19P<32 * n + 18>P18P<32 * n + 17>P17P<32 * n + 16>P16P<32 * n + 15>P15P<32 * n + 14>P14P<32 * n + 13>P13P<32 * n + 12>P12P<32 * n + 11>P11P<32 * n + 10>P10P<32 * n + 9>P9P<32 * n + 8>P8P<32 * n + 7>P7P<32 * n + 6>P6P<32 * n + 5>P5P<32 * n + 4>P4P<32 * n + 3>P3P<32 * n + 2>P2P<32 * n + 1>P1P<32 * n>P0

P<x>, bit [x], for x = 0 to 31

Portion allocation control bit. Each cache portion allocation control bit, MPAMCFG_CPBM<n>.P<x>, grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate cache lines within cache portion 32n + x.

P<x + (n * 32)>, bit [x], for x = 31 to 0

Portion allocation control bit. Each cache portion allocation control bit, MPAMCFG_CPBM<n>.P<x>, grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate cache lines within cache portion <x + (n * 32)>.

P<x + (n * 32)>>Meaning
0b0

The PARTID is not permitted to allocate into cache portion <x32n + (n * 32)>.x.

0b1

The PARTID is permitted to allocate within cache portion <x32n + (n * 32)>.x.

The number of bits in the cache portion partitioning bit map of this component is given in MPAMF_CPOR_IDR.CPBM_WD. CPBM_WD contains a value from 1 to 215, inclusive. Values of CPBM_WD greater than 32 require an array of 32-bit MPAMCFG_CPBM<n> registers to access the cache portion bitmap, up to 1024 registers.

Bits MPAMCFG_CPBM<n>.P<<<x>, + (n * 32)>>, where <x32n + (nx * 32)> is greater than orCPBM_WD, equalare not required to CPBM_WD,be areimplemented. RES0:

Accessing the MPAMCFG_CPBM<n>

This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.

MPAMCFG_CPBM<n>_s must be accessible from the Secure MPAM feature page. MPAMCFG_CPBM<n>_ns must be accessible from the Non-secure MPAM feature page.

MPAMCFG_CPBM<n>_s and MPAMCFG_CPBM<n>_ns must be separate registers. The Secure instance (MPAMCFG_CPBM<n>_s) accesses the cache portion bitmap used for Secure PARTIDs, and the Non-secure instance (MPAMCFG_CPBM<n>_ns) accesses the cache portion bitmap used for Non-secure PARTIDs.

When RIS is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When RIS is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When PARTID narrowing is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.

When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.

MPAMCFG_CPBM<n> can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_s0x1000 + (4 * n)MPAMCFG_CPBM<n>_s

Accesses on this interface are RW.

ComponentFrameOffsetInstance
MPAMMPAMF_BASE_ns0x1000 + (4 * n)MPAMCFG_CPBM<n>_ns

Accesses on this interface are RW.




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)