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The GICD_ICFGR<n>E characteristics are:
Determines whether the corresponding SPI in the extended SPI range is edge-triggered or level-sensitive.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ICFGR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ICFGR<n>E registers is ((GICD_TYPER.ESPI_range+1)*2). Registers are numbered from 0.
GICD_ICFGR<n>E is a 32-bit register.
The GICD_ICFGR<n>E bit assignments are:
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit[2x]) is RES0.
Possible values of Int_config[1] (bit[2x+1]) are:
Int_config<x> | Meaning |
---|---|
0b00 | Corresponding interrupt is level-sensitive. |
0b01 | Corresponding interrupt is edge-triggered. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
When affinity routing is not enabled for the Security state of an interrupt in GICD_ICFGR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x3000 + (4 * n) | GICD_ICFGR<n>E |
This interface is accessible as follows:
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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