ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1

The ID_AA64AFR1_EL1 characteristics are:

Purpose

Reserved for future expansion of information about the IMPLEMENTATION DEFINED features of the PE in AArch64 state.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

There are no configuration notes.

Attributes

ID_AA64AFR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64AFR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Reserved, RES0.

Accessing the ID_AA64AFR1_EL1

Accesses to this register use the following encodings:

MRS <Xt>, ID_AA64AFR1_EL1

op0op1CRnCRmop2
0b110b0000b00000b01010b101

if PSTATE.EL == EL0 then if IsFeatureImplemented("FEAT_IDST") then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64AFR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64AFR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64AFR1_EL1;




01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a

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