The EDPIDR2 characteristics are:
Provides information to identify an external debug component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
EDPIDR2 is a 32-bit register.
The EDPIDR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
Part major revision. Parts can also use this field to extend Part number to 16-bits.
RAO. Indicates a JEP106 identity code is used.
Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.
Component | Offset | Instance |
---|---|---|
Debug | 0xFE8 | EDPIDR2 |
This interface is accessible as follows:
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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