The DFSR characteristics are:
Holds status information about the last data fault.
AArch32 System register DFSR bits [31:0] are architecturally mapped to AArch64 System register ESR_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DFSR are UNDEFINED.
The current translation table format determines which format of the register is used.
DFSR is a 32-bit register.
The DFSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FnV | AET | CM | ExT | WnR | FS[4] | LPAE | RES0 | Domain | FS[3:0] |
Reserved, RES0.
FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.
FnV | Meaning |
---|---|
0b0 |
DFAR is valid. |
0b1 |
DFAR is not valid, and holds an UNKNOWN value. |
This field is only valid for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Data Abort exceptions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Asynchronous Error Type. When DFSC is 0b010001, describes the PE error state after taking the SError interrupt exception. Possible values are:
AET | Meaning |
---|---|
0b00 |
Uncontainable (UC). |
0b01 |
Unrecoverable state (UEU). |
0b10 |
Restartable state (UEO). |
0b11 |
Recoverable state (UER). |
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other aborts.
In the event of multiple errors taken as a single SError interrupt exception, the overall PE error state is reported.
Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance instruction generated the fault. The possible values of this bit are:
CM | Meaning |
---|---|
0b0 |
Abort not caused by execution of a cache maintenance instruction. |
0b1 |
Abort caused by execution of a cache maintenance instruction, or on an address translation. |
On a synchronous Data Abort on a translation table walk, this bit is UNKNOWN.
On an asynchronous fault, this bit is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts.
In an implementation that does not provide any classification of External aborts, this bit is RES0.
For aborts other than External aborts this bit always returns 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Write not Read bit. Indicates whether the abort was caused by a write or a read instruction. The possible values of this bit are:
WnR | Meaning |
---|---|
0b0 |
Abort caused by a read instruction. |
0b1 |
Abort caused by a write instruction. |
For faults on the cache maintenance and address translation System instructions in the (coproc==0b1111) encoding space this bit always returns a value of 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Fault status bits. Possible values of FS[4:0] are:
FS | Meaning | Applies when |
---|---|---|
0b00001 |
Alignment fault. | |
0b00010 |
Debug exception. | |
0b00011 |
Access flag fault, level 1. | |
0b00100 |
Fault on instruction cache maintenance. | |
0b00101 |
Translation fault, level 1. | |
0b00110 |
Access flag fault, level 2. | |
0b00111 |
Translation fault, level 2. | |
0b01000 |
Synchronous External abort, not on translation table walk. | |
0b01001 |
Domain fault, level 1. | |
0b01011 |
Domain fault, level 2. | |
0b01100 |
Synchronous External abort, on translation table walk, level 1. | |
0b01101 |
Permission fault, level 1. | |
0b01110 |
Synchronous External abort, on translation table walk, level 2. | |
0b01111 |
Permission fault, level 2. | |
0b10000 |
TLB conflict abort. | |
0b10100 |
IMPLEMENTATION DEFINED fault (Lockdown fault). | |
0b10101 |
IMPLEMENTATION DEFINED fault (Unsupported Exclusive access fault). | |
0b10110 |
SError interrupt. | |
0b11000 |
SError interrupt, from a parity or ECC error on memory access. | When FEAT_RAS is not implemented |
0b11001 |
Synchronous parity or ECC error on memory access, not on translation table walk. | When FEAT_RAS is not implemented |
0b11100 |
Synchronous parity or ECC error on translation table walk, level 1. | When FEAT_RAS is not implemented |
0b11110 |
Synchronous parity or ECC error on translation table walk, level 2. | When FEAT_RAS is not implemented |
All other values are reserved.
For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Short-descriptor translation table lookup'.
The FS field is split as follows:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
On taking a Data Abort exception, this bit is set as follows:
LPAE | Meaning |
---|---|
0b0 |
Using the Short-descriptor translation table formats. |
0b1 |
Using the Long-descriptor translation table formats. |
Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The domain of the fault address.
Arm deprecates any use of this field, see 'The Domain field in the DFSR'.
This field is UNKNOWN for certain faults where the DFSR is updated and reported using the Short-descriptor FSR encodings, see 'Validity of Domain field on faults that update the DFSR when using the Short-descriptor encodings'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FnV | AET | CM | ExT | WnR | RES0 | LPAE | RES0 | STATUS |
Reserved, RES0.
FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.
FnV | Meaning |
---|---|
0b0 |
DFAR is valid. |
0b1 |
DFAR is not valid, and holds an UNKNOWN value. |
This field is only valid for a synchronous External abort other than a synchronous External abort on a translation table walk. It is RES0 for all other Data Abort exceptions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Asynchronous Error Type. When DFSC is 0b010001, describes the PE error state after taking the SError interrupt exception. Possible values are:
AET | Meaning |
---|---|
0b00 |
Uncontainable (UC). |
0b01 |
Unrecoverable state (UEU). |
0b10 |
Restartable state (UEO). |
0b11 |
Recoverable state (UER). |
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other aborts.
In the event of multiple errors taken as a single SError interrupt exception, the overall PE error state is reported.
Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance instruction generated the fault. The possible values of this bit are:
CM | Meaning |
---|---|
0b0 |
Abort not caused by execution of a cache maintenance instruction. |
0b1 |
Abort caused by execution of a cache maintenance instruction. |
On a synchronous Data Abort on a translation table walk, this bit is UNKNOWN.
On an asynchronous fault, this bit is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of External aborts.
In an implementation that does not provide any classification of External aborts, this bit is RES0.
For aborts other than External aborts this bit always returns 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Write not Read bit. Indicates whether the abort was caused by a write or a read instruction. The possible values of this bit are:
WnR | Meaning |
---|---|
0b0 |
Abort caused by a read instruction. |
0b1 |
Abort caused by a write instruction. |
For faults on the cache maintenance and address translation System instructions in the (coproc==0b1111) encoding space this bit always returns a value of 1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
On taking a Data Abort exception, this bit is set as follows:
LPAE | Meaning |
---|---|
0b0 |
Using the Short-descriptor translation table formats. |
0b1 |
Using the Long-descriptor translation table formats. |
Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Fault status bits. Possible values of this field are:
STATUS | Meaning | Applies when |
---|---|---|
0b000000 |
Address size fault in translation table base register. | |
0b000001 |
Address size fault, level 1. | |
0b000010 |
Address size fault, level 2. | |
0b000011 |
Address size fault, level 3. | |
0b000101 |
Translation fault, level 1. | |
0b000110 |
Translation fault, level 2. | |
0b000111 |
Translation fault, level 3. | |
0b001001 |
Access flag fault, level 1. | |
0b001010 |
Access flag fault, level 2. | |
0b001011 |
Access flag fault, level 3. | |
0b001101 |
Permission fault, level 1. | |
0b001110 |
Permission fault, level 2. | |
0b001111 |
Permission fault, level 3. | |
0b010000 |
Synchronous External abort, not on translation table walk. | |
0b010001 |
Asynchronous SError interrupt. | |
0b010101 |
Synchronous External abort on translation table walk, level 1. | |
0b010110 |
Synchronous External abort on translation table walk, level 2. | |
0b010111 |
Synchronous External abort on translation table walk, level 3. | |
0b011000 |
Synchronous parity or ECC error on memory access, not on translation table walk. | When FEAT_RAS is not implemented |
0b011001 |
Asynchronous SError interrupt, from a parity or ECC error on memory access. | When FEAT_RAS is not implemented |
0b011101 |
Synchronous parity or ECC error on memory access on translation table walk, level 1. | When FEAT_RAS is not implemented |
0b011110 |
Synchronous parity or ECC error on memory access on translation table walk, level 2. | When FEAT_RAS is not implemented |
0b011111 |
Synchronous parity or ECC error on memory access on translation table walk, level 3. | When FEAT_RAS is not implemented |
0b100001 |
Alignment fault. | |
0b100010 |
Debug exception. | |
0b110000 |
TLB conflict abort. | |
0b110100 |
IMPLEMENTATION DEFINED fault (Lockdown). | |
0b110101 |
IMPLEMENTATION DEFINED fault (Unsupported Exclusive access). |
All other values are reserved.
For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Long-descriptor translation table lookup'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0101 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then return DFSR_NS; else return DFSR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then return DFSR_NS; else return DFSR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then return DFSR_S; else return DFSR_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0101 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then DFSR_NS = R[t]; else DFSR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then DFSR_NS = R[t]; else DFSR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then DFSR_S = R[t]; else DFSR_NS = R[t];
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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