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The MPAMF_ESR characteristics are:
Indicates MPAM error status for this MSC. MPAMF_ESR_s reports Secure MPAM errors. MPAMF_ESR_ns reports Non-secure MPAM errors.
Software should write this register after reading the status of an error to reset ERRCODE to 0x0000 and OVRWR to 0 so that future errors are not reported with OVRWR set.
The power domain of MPAMF_ESR is IMPLEMENTATION DEFINED.
ThisIf registera isMSC presentcannot onlyencounter whenany FEAT_MPAMof isthe implemented.error Otherwise,conditions directlisted accesses to MPAMF_ESR arein , both the MPAMF_ESR and MPAMF_ECRRES0'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598).must be RAZ/WI.
MAMPF_ESR is 64-bit register when MPAM v0.1 or v1.1 is implemented and MPAMF_IDR.HAS_EXTD_ESR == 1.
Otherwise, MAMPF_ESR is a 32-bit register.
If a MSC cannot encounter any of the error conditions listed in 'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.
MPAMF_ESR is a:
The MPAMF_ESR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | RIS | ||||||||||||||||||||||||||||||
OVRWR | RES0 | ERRCODE | PMG | PARTID_MON | |||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Resource Instance Selector. Where applicable to the ERRCODE, captures the RIS value for the error.
Reserved, RES0.
Overwritten.
If 0 and ERRCODE == 0b0000, no errors have occurred.
If 0 and ERRCODE is non-zero, a single error has occurred and is recorded in this register.
If 1 and ERRCODE is non-zero, multiple errors have occurred and this register records the most recent error.
The state where this bit is 1 and ERRCODE is zero must not be produced by hardware and is only reached when software writes this combination into this register.
Reserved, RES0.
Error code.
ERRCODE | Meaning |
---|---|
0b0000 | No error. |
0b0001 | PARTID_SEL_Range. |
0b0010 | Req_PARTID_Range. |
0b0011 | MSMONCFG_ID_RANGE. |
0b0100 | Req_PMG_Range. |
0b0101 | Monitor_Range. |
0b0110 | intPARTID_Range. |
0b0111 | Unexpected_INTERNAL. |
0b1000 | Undefined_RIS_PART_SEL. |
0b1001 | RIS_No_Control. |
0b1010 | Undefined_RIS_MON_SEL. |
0b1011 | RIS_No_Monitor. |
0b1100 | Reserved. |
0b1101 | Reserved. |
0b1110 | Reserved. |
0b1111 | Reserved. |
Program monitoring group.
Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG.
PARTID or monitor.
Set to the PARTID on an error that captures PARTID.
Set to the monitor index on an error that captures MON.
On an error that captures neither PARTID nor MON, this field is set to 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVRWR | RES0 | ERRCODE | PMG | PARTID_MON |
Overwritten.
If 0 and ERRCODE == 0b0000, no errors have occurred.
If 0 and ERRCODE is non-zero, a single error has occurred and is recorded in this register.
If 1 and ERRCODE is non-zero, multiple errors have occurred and this register records the most recent error.
The state where this bit is 1 and ERRCODE is 0 must not be produced by hardware and is only reached when software writes this combination into this register.
Reserved, RES0.
Error code.
ERRCODE | Meaning |
---|---|
0b0000 | No error. |
0b0001 | PARTID_SEL_Range. |
0b0010 | Req_PARTID_Range. |
0b0011 | MSMONCFG_ID_RANGE. |
0b0100 | Req_PMG_Range. |
0b0101 | Monitor_Range. |
0b0110 | intPARTID_Range. |
0b0111 | Unexpected_INTERNAL. |
0b1000 | Reserved. |
0b1001 | Reserved. |
0b1010 | Reserved. |
0b1011 | Reserved. |
0b1100 | Reserved. |
0b1101 | Reserved. |
0b1110 | Reserved. |
0b1111 | Reserved. |
Program monitoring group.
Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG.
PARTID or monitor.
Set to the PARTID on an error that captures PARTID.
Set to the monitor index on an error that captures MON.
On an error that captures neither PARTID nor MON, this field is set to 0x0000.
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_ESR_s must be accessible from the Secure MPAM feature page. MPAMF_ESR_ns must be accessible from the Non-secure MPAM feature page.
MPAMF_ESR_s and MPAMF_ESR_ns must be separate registers. The Secure instance (MPAMF_ESR_s) accesses the error status used for Secure PARTIDs, and the Non-secure instance (MPAMF_ESR_ns) accesses the error status used for Non-secure PARTIDs.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x00F8 | MPAMF_ESR_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x00F8 | MPAMF_ESR_ns |
Accesses on this interface are RW.
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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