The TLBIALLIS characteristics are:
Invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk. The entries that are invalidated are as follows:
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TLBIALLIS are UNDEFINED.
TLBIALLIS is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
Accesses to this instruction use the following encodings:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1000 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TTLBIS == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TTLB == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR2.TTLBIS == '1' then AArch32.TakeHypTrapException(0x03); else TLBIALLIS(); elsif PSTATE.EL == EL2 then TLBIALLIS(); elsif PSTATE.EL == EL3 then TLBIALLIS();
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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