(old) | htmldiff from- | (new) |
The CNTSR characteristics are:
Provides counter frequency status information.
The power domain of CNTSR is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTSR is a 32-bit register.
The CNTSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FCACK | RES0 | DBGH | RES0 |
Frequency change acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table'.
On a Warm reset, thisThis field resets to 0.
Reserved, RES0.
Indicates whether the counter is halted because the Halt-on-debug signal is asserted:
DBGH | Meaning |
---|---|
0b0 | Counter is not halted. |
0b1 | Counter is halted. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTControlBase | 0x004 | CNTSR |
Accesses on this interface are RO.
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |