The MPAMF_AIDR characteristics are:
Identifies the version of the MPAM architecture that this MSC implements.
Note: The following values are defined for bits [7:0]:
0x01 == MPAM architecture v0.1
0x10 == MPAM architecture v1.0
0x11 == MPAM architecture v1.1
The power domain of MPAMF_AIDR is IMPLEMENTATION DEFINED.
MPAMF_AIDR is a 32-bit register.
The MPAMF_AIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ArchMajorRev | ArchMinorRev |
Reserved, RES0.
Major revision of the MPAM architecture implemented by the MSC.
This table shows the only valid combinations of MPAM version numbers in an MSC. FORCE_NS functionality is only available in MPAM v0.1.
ArchMajorRev | ArchMinorRev | MPAMv | Available |
---|---|---|---|
0 | 0 | None. | |
0 | 1 | v0.1 | MPAMv1.0 + MPAMv1.1 + FORCE_NS |
1 | 0 | v1.0 | MPAMv1.0 |
1 | 1 | v1.1 | MPAMv1.0 + MPAMv1.1 - FORCE_NS |
Minor revision of the MPAM architecture implemented by the MSC.
See the table in the description of the ArchMajorRev field in this register.
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_AIDR is read-only.
MPAMF_AIDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_AIDR must have the same contents in the Secure and Non-secure MPAM feature pages.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0020 | MPAMF_AIDR |
Accesses on this interface are RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0020 | MPAMF_AIDR |
Accesses on this interface are RO.
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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