(old) | htmldiff from- | (new) |
The ESR_EL1 characteristics are:
Holds syndrome information for an exception taken to EL1.
AArch64 System register ESR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DFSR[31:0] .
ESR_EL1 is a 64-bit register.
The ESR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | ISS2 | ||||||||||||||||||||||||||||||
EC | IL | ISS | |||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ESR_EL1 is made UNKNOWN as a result of an exception return from EL1.
When an UNPREDICTABLE instruction is treated as UNDEFINED, and the exception is taken to EL1, the value of ESR_EL1 is UNKNOWN. The value written to ESR_EL1 must be consistent with a value that could be created as a result of an exception from the same Exception level that generated the exception as a result of a situation that is not UNPREDICTABLE at that Exception level, in order to avoid the possibility of a privilege violation.
Reserved, RES0.
If a memory access generated by an ST64BV or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field holds register specifier, Xs.
For any other Data Abort, this field is RES0.
Reserved, RES0.
Exception Class. Indicates the reason for the exception that this register holds information about.
For each EC value, the table references a subsection that gives information about:
Possible values of the EC field are:
EC | Meaning | ISS | Applies when |
---|---|---|---|
0b000000 | Unknown reason. | ISS encoding for exceptions with an unknown reason | |
0b000001 | Trapped WF* Conditional WF* | ISS encoding for an exception from a WF* instruction | |
0b000011 | Trapped MCR or MRC access with (coproc==0b1111) that is not reported using EC 0b000000. | ISS encoding for an exception from an MCR or MRC access | When AArch32 is supported at any Exception level |
0b000100 | Trapped MCRR or MRRC access with (coproc==0b1111) that is not reported using EC 0b000000. | ISS encoding for an exception from an MCRR or MRRC access | When AArch32 is supported at any Exception level |
0b000101 | Trapped MCR or MRC access with (coproc==0b1110). | ISS encoding for an exception from an MCR or MRC access | When AArch32 is supported at any Exception level |
0b000110 | Trapped LDC or STC access. The only architected uses of these instruction are:
| ISS encoding for an exception from an LDC or STC instruction | When AArch32 is supported at any Exception level |
0b000111 | Access to SVE, Advanced SIMD Excludes exceptions resulting from CPACR_EL1 when the value of HCR_EL2.TGE is 1, or because SVE or Advanced SIMD and floating-point are not implemented. These are reported with EC value 0b000000 as described in 'The EC used to report an exception routed to EL2 because HCR_EL2.TGE is 1'. | ISS encoding for an exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from the FPEN and TFP traps | |
0b001010 | Trapped execution of an LD64B, ST64B, ST64BV, or ST64BV0 instruction. | ISS encoding for an exception from an LD64B or ST64B* instruction | When FEAT_LS64 is implemented |
0b001100 | Trapped MRRC access with (coproc==0b1110). | ISS encoding for an exception from an MCRR or MRRC access | When AArch32 is supported at any Exception level |
0b001101 | Branch Target Exception. | ISS encoding for an exception from Branch Target Identification instruction | When FEAT_BTI is implemented |
0b001110 | Illegal Execution state. | ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault | |
0b010001 | SVC instruction execution in AArch32 state. This is reported in ESR_EL2 only when the exception is generated because the value of HCR_EL2.TGE is 1. | ISS encoding for an exception from HVC or SVC instruction execution | When AArch32 is supported at any Exception level |
0b010101 | SVC instruction execution in AArch64 state. | ISS encoding for an exception from HVC or SVC instruction execution | When AArch64 is supported at any Exception level |
0b011000 | Trapped MSR, MRS or System instruction execution in AArch64 state, that is not reported using EC 0b000000, 0b000001, or 0b000111. This includes all instructions that cause exceptions that are part of the encoding space defined in 'System instruction class encoding overview', except for those exceptions reported using EC values 0b000000, 0b000001, or 0b000111. | ISS encoding for an exception from MSR, MRS, or System instruction execution in AArch64 state | When AArch64 is supported at any Exception level |
0b011001 | Access to SVE functionality trapped as a result of CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ, that is not reported using EC 0b000000. | ISS encoding for an exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ | When FEAT_SVE is implemented |
0b011100 | Exception from a Pointer Authentication instruction authentication failure | ISS encoding for an exception from a Pointer Authentication instruction authentication failure | When FEAT_FPAC is implemented |
0b100000 | Instruction Abort from a lower Exception level. Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related | ISS encoding for an exception from an Instruction Abort | |
0b100001 | Instruction Abort taken without a change in Exception level. Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related | ISS encoding for an exception from an Instruction Abort | |
0b100010 | PC alignment fault exception. | ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault | |
0b100100 | Data Abort from a lower Exception level. Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related | ISS encoding for an exception from a Data Abort | |
0b100101 | Data Abort taken without a change in Exception level. Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug-related | ISS encoding for an exception from a Data Abort | |
0b100110 | SP alignment fault exception. | ISS encoding for an exception from an Illegal Execution state, or a PC or SP alignment fault | |
0b101000 | Trapped floating-point exception taken from AArch32 state. This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is IMPLEMENTATION DEFINED. | ISS encoding for an exception from a trapped floating-point exception | When AArch32 is supported at any Exception level |
0b101100 | Trapped floating-point exception taken from AArch64 state. This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is IMPLEMENTATION DEFINED. | ISS encoding for an exception from a trapped floating-point exception | When AArch64 is supported at any Exception level |
0b101111 | SError interrupt. | ISS encoding for an SError interrupt | |
0b110000 | Breakpoint exception from a lower Exception level. | ISS encoding for an exception from a Breakpoint or Vector Catch debug exception | |
0b110001 | Breakpoint exception taken without a change in Exception level. | ISS encoding for an exception from a Breakpoint or Vector Catch debug exception | |
0b110010 | Software Step exception from a lower Exception level. | ISS encoding for an exception from a Software Step exception | |
0b110011 | Software Step exception taken without a change in Exception level. | ISS encoding for an exception from a Software Step exception | |
0b110100 | Watchpoint exception from a lower Exception level. | ISS encoding for an exception from a Watchpoint exception | |
0b110101 | Watchpoint exception taken without a change in Exception level. | ISS encoding for an exception from a Watchpoint exception | |
0b111000 | BKPT instruction execution in AArch32 state. | ISS encoding for an exception from execution of a Breakpoint instruction | When AArch32 is supported at any Exception level |
0b111100 | BRK instruction execution in AArch64 state. This is reported in ESR_EL3 only if a BRK instruction is executed. | ISS encoding for an exception from execution of a Breakpoint instruction | When AArch64 is supported at any Exception level |
All other EC values are reserved by Arm, and:
The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Instruction Length for synchronous exceptions. Possible values of this bit are:
IL | Meaning |
---|---|
0b0 | 16-bit instruction trapped. |
0b1 | 32-bit instruction trapped. This value is also used when the exception is one of the following:
|
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class.
Typically, an ISS encoding has a number of subfields. When an ISS subfield holds a register number, the value returned in that field is the AArch64 view of the register number.
For an exception taken from AArch32 state, see 'Mapping of the general-purpose registers between the Execution states'.
If the AArch32 register descriptor is 0b1111, then:
When the EC field is 0b000000, indicating an exception with an unknown reason, the ISS field is not valid, RES0.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
When an exception is reported using this EC code the IL field is set to 1.
This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | RES0 | TI |
Condition code valid. Possible values of this bit are:
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Trapped instruction. Possible values of this bit are:
TI | Meaning | Applies when |
---|---|---|
0b00 | WFI trapped. | |
0b01 | WFE trapped. | |
0b10 | WFIT trapped. | When FEAT_WFxT is implemented |
0b11 | WFET trapped. | When FEAT_WFxT is implemented |
WhenThis field resets to an architecturally FEAT_WFxTUNKNOWN is implemented, this is a two bit field as shown. Otherwise, bit[1] is RES0.value.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | Opc2 | Opc1 | CRn | Rt | CRm | Direction |
Condition code valid. Possible values of this bit are:
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The Opc2 value from the issued instruction.
For a trapped VMRS access, holds the value 0b000.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The Opc1 value from the issued instruction.
For a trapped VMRS access, holds the value 0b111.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The CRn value from the issued instruction.
For a trapped VMRS access, holds the reg field from the VMRS instruction encoding.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The Rt value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The CRm value from the issued instruction.
For a trapped VMRS access, holds the value 0b0000.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction. The possible values of this bit are:
Direction | Meaning |
---|---|
0b0 | Write to System register space. MCR instruction. |
0b1 | Read from System register space. MRC or VMRS instruction. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000011:
The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000101:
The following fields describe configuration settings for generating exceptions that are reported using EC value 0b001000:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISS |
Condition code valid. Possible values of this bit are:
ISS | Meaning |
---|---|
0b0000000000000000000000000 | ST64BV |
0b0000000000000000000000001 | ST64BV0 |
0b0000000000000000000000010 | LD64B or ST64B instruction trapped. |
For exceptions taken from AArch32:
This field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
This field resets to an architecturally UNKNOWN value.
The Opc1 value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The Rt2 value from the issued instruction, the second general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
This field resets to an architecturally UNKNOWN value.
The Rt value from the issued instruction, the first general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
This field resets to an architecturally UNKNOWN value.
The CRm value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction. The possible values of this bit are:
| |
|
This field resets to an architecturally UNKNOWN value.
The following fields describe configuration settings for generating exceptions that are reported using EC value 0b000100:
The following sections describe configuration settings for generating exceptions that are reported using EC value 0b001100:
If the Armv8-A architecture is implemented with an ETMv4 implementation, MCRR and MRRC accesses to trace registers are UNDEFINED and the resulting exception is higher priority than an exception due to these traps.
AllFor otherexceptions valuestaken arefrom reserved.AArch64, CV is set to 1.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | Opc1 | RES0 | Rt2 | Rt | CRm | Direction |
Condition code valid. Possible values of this bit are:
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The Opc1immediate value from the issued instruction.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The Rt2Rn value from the issued instruction, the second general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
OnThis field is valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction. When AM[2] is 1, indicating a Warmliteral resetform of the LDC or STC instruction, this field resets to an architecturallyis UNKNOWN value..
This field resets to an architecturally UNKNOWN value.
Indicates whether the offset is added or subtracted:
| |
|
This bit corresponds to the U bit in the instruction encoding.
This field resets to an architecturally UNKNOWN value.
Addressing mode. The permitted values of this field are:
| |
| |
| |
| |
| |
|
The values 0b101 and 0b111 are reserved. The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in System and memory-mapped registers and translation table entries'.
Bit [2] in this subfield indicates the instruction form, immediate or literal.
Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.
This field resets to an architecturally UNKNOWN value.
The Rt value from the issued instruction, the first general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The CRm value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction. The possible values of this bit are:
Direction | Meaning |
---|---|
0b0 | Write to System |
0b1 | Read from System |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The following fields describe the configuration settings for generatingthe exceptionstraps that are reported using EC value 0b0001000b000110:
The following sections describe configuration settings for generating exceptions that are reported using EC value 0b001100:
If the Armv8-A architecture is implemented with an ETMv4 implementation, MCRR and MRRC accesses to trace registers are UNDEFINED and the resulting exception is higher priority than an exception due to these traps.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | imm8 | RES0 | Rn | Offset | AM | Direction |
The accesses covered by this trap include:
For an implementation that does not include either SVE or support for floating-point and Advanced SIMD, the exception is reported using the EC value 0b000000.
Condition code valid. Possible values of this bit are:
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The immediate value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The following sections describe the configuration settings for the traps that are reported using EC value 0b000111:
The Rn value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
This field is valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction. When AM[2] is 1, indicating a literal form of the LDC or STC instruction, this field is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates whether the offset is added or subtracted:
Offset | Meaning |
---|---|
0b0 | Subtract offset. |
0b1 | Add offset. |
This bit corresponds to the U bit in the instruction encoding.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Addressing mode. The permitted values of this field are:
AM | Meaning |
---|---|
0b000 | Immediate unindexed. |
0b001 | Immediate post-indexed. |
0b010 | Immediate offset. |
0b011 | Immediate pre-indexed. |
0b100 | For a trapped STC instruction or a trapped T32 LDC instruction this encoding is reserved. |
0b110 | For a trapped STC instruction, this encoding is reserved. |
The values 0b101 and 0b111 are reserved. The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in System and memory-mapped registers and translation table entries'.
Bit [2] in this subfield indicates the instruction form, immediate or literal.
Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction.
Direction | Meaning |
---|---|
0b0 | Write to memory. STC instruction. |
0b1 | Read from memory. LDC instruction. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The following fields describe the configuration settings for the traps that are reported using EC value 0b000110:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | RES0 |
The accesses covered by this trap include:
For an implementation that does not include either SVE or support for floating-point and Advanced SIMD, the exception is reported using the EC value 0b000000.
Condition code valid.
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The following sections describe the configuration settingssetting for the traps that are reported using EC value: 0b000111:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
The accesses covered by this trap include:
For an implementation that does not include SVE, the exception is reported using the EC value 0b000000.
Reserved, RES0.
The following sections describe the configuration settings for the traps that are reported using EC value 0b011001:
There are no configuration settings for generating Illegal Execution state exceptions and PC alignment fault exceptions. For more information about these exceptions see 'The Illegal Execution state exception' and 'PC alignment checking'.
'SP alignment checking' describes the configuration settings for generating SP alignment fault exceptions.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
The value of the immediate field from the HVC or SVC instruction.
For an HVC instruction, and for an A64 SVC instruction, this is the value of the imm16 field of the issued instruction.
For an A32 or T32 SVC instruction:
This field resets to an architecturally UNKNOWN value.
In AArch32 state, the HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.
For T32 and A32 instructions, see 'SVC' and 'HVC'.
For A64 instructions, see 'SVC' and 'HVC'.
If FEAT_FGT is implemented, HFGITR_EL2.{SVC_EL1, SVC_EL0} control fine-grained traps on SVC execution.
There are no configuration settings for generating Illegal Execution state exceptions and PC alignment fault exceptions. For more information about these exceptions, see 'The Illegal Execution state exception' and 'PC alignment checking'.
'SP alignment checking' describes the configuration settings for generating SP alignment fault exceptions.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | imm16 |
For an SMC instruction that completes normally and generates an exception that is taken to EL3, the ISS encoding is RES0.
For an SMC instruction that is trapped to EL2 from EL1 because HCR_EL2.TSC is 1, the ISS encoding is as shown in the diagram.
Condition code valid. Possible values of this bit are:
| |
|
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
This field is only valid if CCKNOWNPASS is 1, otherwise it is RES0.
This field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
This field is only valid if CCKNOWNPASS is 1, otherwise it is RES0.
This field resets to an architecturally UNKNOWN value.
Indicates whether the instruction might have failed its condition code check.
| |
|
In an implementation in which an SMC instruction that fails it code check is not trapped, this field can always return the value 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
HCR_EL2.TSC describes the configuration settings for trapping SMC instructions to EL2.
'System calls' describes the case where these exceptions are trapped to EL3.
The value of the immediate field from the HVC or SVC instruction.
For an HVC instruction, and for an A64 SVC instruction, this is the value of the imm16 field of the issued instruction.
For an A32 or T32 SVC instruction:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
In AArch32 state, the HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.
For T32 and A32 instructions, see 'SVC' and 'HVC'.
For A64 instructions, see 'SVC' and 'HVC'.
If FEAT_FGT is implemented, HFGITR_EL2.{SVC_EL1, SVC_EL0} control fine-grained traps on SVC execution.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CV | COND | CCKNOWNPASS | RES0 |
For an SMC instruction that completes normally and generates an exception that is taken to EL3, the ISS encoding is RES0.
For an SMC instruction that is trapped to EL2 from EL1 because HCR_EL2.TSC is 1, the ISS encoding is as shown in the diagram.
Condition code valid.
CV | Meaning |
---|---|
0b0 | The COND field is not valid. |
0b1 | The COND field is valid. |
For exceptions taken from AArch64, CV is set to 1.
For exceptions taken from AArch32:
This field is valid only if CCKNOWNPASS is 1, otherwise it is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For exceptions taken from AArch64, this field is set to 0b1110.
The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.
For exceptions taken from AArch32:
This field is valid only if CCKNOWNPASS is 1, otherwise it is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates whether the instruction might have failed its condition code check.
CCKNOWNPASS | Meaning |
---|---|
0b0 | The instruction was unconditional, or was conditional and passed its condition code check. |
0b1 | The instruction was conditional, and might have failed its condition code check. |
In an implementation in which an SMC instruction that fails it code check is not trapped, this field can always return the value 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The value of the immediate field from the issued SMC instruction.
This field resets to an architecturally UNKNOWN value.
The value of ISS[24:0] described here is used both:
HCR_EL2.TSC describes the configuration settings for trapping SMC from EL1 modes.
'System calls' describes the case where these exceptions are trapped to EL3.
HCR_EL2.TSC describes the configuration settings for trapping SMC instructions to EL2.
'System calls' describes the case where these exceptions are trapped to EL3.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | imm16 |
Reserved, RES0.
The Op0 value of the immediate field from the issued SMC instruction.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
The Op2 value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
The Op1 value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
The CRn value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
The Rt value from the issued instruction, the general-purpose register used for the transfer.
This field resets to an architecturally UNKNOWN value.
The CRm value from the issued instruction.
This field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction. The possible values of this bit are:
| |
|
This field resets to an architecturally UNKNOWN value.
For exceptions caused by System instructions, see 'System instructions' subsection of 'Branches, exception generating and System instructions' for the encoding values returned by an instruction.
The following fields describe configuration settings for generating the exception that is reported using EC value 0b011000:
The value of ISS[24:0] described here is used both:
HCR_EL2.TSC describes the configuration settings for trapping SMC from EL1 modes.
'System calls' describes the case where these exceptions are trapped to EL3.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Op0 | Op2 | Op1 | CRn | Rt | CRm | Direction |
IMPLEMENTATION DEFINED.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
The Op0 value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The Op2 value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The Op1 value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The CRn value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The Rt value from the issued instruction, the general-purpose register used for the transfer.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The CRm value from the issued instruction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates the direction of the trapped instruction.
Direction | Meaning |
---|---|
0b0 | Write access, including MSR instructions. |
0b1 | Read access, including MRS instructions. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For exceptions caused by System instructions, see 'System instructions' subsection of 'Branches, exception generating and System instructions' for the encoding values returned by an instruction.
The following fields describe configuration settings for generating the exception that is reported using EC value 0b011000:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
Reserved, RES0.
Synchronous Error Type. When IFSC is 0b010000, describes the PE error state after taking the Instruction Abort exception. The possible values of this field are:
| |
| |
|
All other values are reserved.
Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in a PE state that is not recoverable.
This field is valid only if the IFSC code is 0b010000. It is RES0 for all other aborts.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.
| |
|
This field is only valid if the IFSC code is 0b010000. It is RES0 for all other aborts.
This field resets to an architecturally UNKNOWN value.
External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.
For any abort other than an External abort this bit returns a value of 0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:
| |
|
For any abort other than a stage 2 fault this bit is RES0.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Instruction Fault Status Code.
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
|
All other values are reserved.
For more information about the lookup level associated with a fault, see 'The level associated with MMU faults'.
Because Access flag faults and Permission faults can only result from a Block or Page translation table descriptor, they cannot occur at level 0.
If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.
This field resets to an architecturally UNKNOWN value.
IMPLEMENTATION DEFINED.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SET | FnV | EA | RES0 | S1PTW | RES0 | IFSC |
Instruction Syndrome Valid. Indicates whether the syndrome information in ISS[23:14] is valid.
| |
|
This bit is 0 for all faults reported in ESR_EL2 except the following stage 2 aborts:
For these cases, ISV is UNKNOWN if the exception was generated in Debug state in memory access mode, and otherwise indicates whether ISS[23:14] hold a valid syndrome.
ISV is 0 for all faults reported in ESR_EL1 or ESR_EL3.
When the RAS Extension is implemented, ISV is 0 for any synchronous External abort.
For ISS reporting, a stage 2 abort on a stage 1 translation table walk does not return a valid instruction syndrome, and therefore ISV is 0 for these aborts.
When the RAS Extension is not implemented, the value of ISV on a synchronous External abort on a stage 2 translation table walk is IMPLEMENTATION DEFINED.
When FEAT_MTE is implemented, for a synchronous Tag Check Fault abort taken to ELx, ESR_ELx.FNV is 0 and FAR_ELx is valid.
This field resets to an architecturally UNKNOWN value.
Syndrome Access Size. When ISV is 1, indicates the size of the access attempted by the faulting operation.
| |
| |
| |
|
This field is UNKNOWN when the value of ISV is UNKNOWN.
This field is RES0 when the value of ISV is 0.
This field resets to an architecturally UNKNOWN value.
Syndrome Sign Extend. When ISV is 1, for a byte, halfword, or word load operation, indicates whether the data item must be sign extended. For these cases, the possible values of this bit are:
| |
|
For all other operations this bit is 0.
This field is UNKNOWN when the value of ISV is UNKNOWN.
This field is RES0 when the value of ISV is 0.
This field resets to an architecturally UNKNOWN value.
Syndrome Register Transfer. When ISV is 1, the register number of the Rt operand of the faulting instruction.
If the exception was taken from an Exception level that is using AArch32 then this is the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'.
This field is UNKNOWN when the value of ISV is UNKNOWN.
This field is RES0 when the value of ISV is 0.
This field resets to an architecturally UNKNOWN value.
Width of the register accessed by the instruction is Sixty-Four. When ISV is 1, the possible values of this bit are:
| |
|
This field specifies the register width identified by the instruction, not the Execution state.
This field is UNKNOWN when the value of ISV is UNKNOWN.
This field is RES0 when the value of ISV is 0.
This field resets to an architecturally UNKNOWN value.
Acquire/Release. The possible values of this bit are:
| |
|
This field is UNKNOWN when the value of ISV is UNKNOWN.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Synchronous Error Type. When IFSC is 0b010000, describes the PE error state after taking the Instruction Abort exception.
Indicates that the fault came from use of VNCR_EL2 register by EL1 code.
SET | Meaning |
---|---|
0b00 | Recoverable |
0b10 | Uncontainable |
0b11 | Restartable state (UEO). |
This field is 0 in ESR_EL1.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Synchronous Error Type. When DFSC is 0b010000, describes the PE error state after taking the Data Abort exception. The possible values of this field are:
| |
| |
|
All other values are reserved.
Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in a PE state that is not recoverable.
This field is valid only if the IFSCDFSC code is 0b010000. It is RES0 for all other aborts.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.
FnV | Meaning |
---|---|
0b0 | FAR is valid. |
0b1 | FAR is not valid, and holds an UNKNOWN value. |
This field is valid only if the IFSCDFSC code is 0b010000. It is RES0 for all other aborts.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.
For any abort other than an External abort this bit returns a value of 0.
| |
|
This field resets to an architecturally UNKNOWN value.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved,Cache maintenance. Indicates whether the Data Abort came from a cache maintenance or address translation instruction: RES0.
For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:
S1PTW | Meaning |
---|---|
0b0 | Fault not on a stage 2 translation for a stage 1 translation table walk. |
0b1 | Fault on the stage 2 translation of an access for a stage 1 translation table walk. |
For any abort other than a stage 2 fault this bit is RES0.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
ReservedWrite not Read. Indicates whether a synchronous abort was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are: RES0.
Instruction Fault Status Code.
IFSC | Meaning | Applies when |
---|---|---|
0b000000 | Address | |
0b000001 | Address | |
0b000010 | Address size fault, level 2. | |
0b000011 | Address size fault, level 3. | |
0b000100 | Translation fault, level 0. | |
0b000101 | Translation fault, level 1. | |
0b000110 | Translation fault, level 2. | |
0b000111 | Translation fault, level 3. | |
0b001001 | Access flag fault, level 1. | |
0b001010 | Access flag fault, level 2. | |
0b001011 | Access flag fault, level 3. | |
0b001000 | Access flag fault, level 0. | When FEAT_LPA2 is implemented |
0b001100 | Permission fault, level 0. | When FEAT_LPA2 is implemented |
0b001101 | Permission fault, level 1. | |
0b001110 | Permission fault, level 2. | |
0b001111 | Permission fault, level 3. | |
0b010000 | Synchronous External abort, not on translation table walk or hardware update of translation table. | |
0b010011 | Synchronous External abort on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented |
0b010100 | Synchronous External abort on translation table walk or hardware update of translation table, level 0. | |
0b010101 | Synchronous External abort on translation table walk or hardware update of translation table, level 1. | |
0b010110 | Synchronous External abort on translation table walk or hardware update of translation table, level 2. | |
0b010111 | Synchronous External abort on translation table walk or hardware update of translation table, level 3. | |
0b011000 | Synchronous parity or ECC error on memory access, not on translation table walk. | When FEAT_RAS is not implemented |
0b011011 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented and FEAT_RAS is not implemented |
0b011100 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0. | When FEAT_RAS is not implemented |
0b011101 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1. | When FEAT_RAS is not implemented |
0b011110 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2. | When FEAT_RAS is not implemented |
0b011111 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3. | When FEAT_RAS is not implemented |
0b101001 | Address size fault, level -1. | When FEAT_LPA2 is implemented |
0b101011 | Translation fault, level -1. | When FEAT_LPA2 is implemented |
0b110000 | TLB conflict abort. | |
0b110001 | Unsupported atomic hardware update fault. | When FEAT_HAFDBS is implemented |
For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.
For faults from an atomic instruction that both reads and writes from a memory location, this bit is set to 0 if a read of the address specified by the instruction would have generated the fault which is being reported, otherwise it is set to 1. The architecture permits, but does not require, a relaxation of this requirement such that for all stage 2 aborts on stage 1 translation table walks for atomic instructions, the WnR bit is always 0.
This field is UNKNOWN for:
This field resets to an architecturally UNKNOWN value.
Data Fault Status Code.
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
| ||
|
All other values are reserved.
For more information about the lookup level associated with a fault, see 'The level associated with MMU faults'.
Because Access flag faults and Permission faults can only result only from a Block or Page translation table descriptor, they cannot occur at level 0.
If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISV | SAS | SSE | SRT | SF | AR | VNCR | Bits[12:11] | FnV | EA | CM | S1PTW | WnR | DFSC |
When FEAT_LS64 is implemented, if a memory access generated by an ST64BV or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this ISS encoding includes ISS2, bits[36:32].
Instruction Syndrome Valid. Indicates whether the syndrome information in ISS[23:14] is valid.
ISV | Meaning |
---|---|
0b0 | No valid instruction syndrome. ISS[23:14] are RES0. |
0b1 | ISS[23:14] hold a valid instruction syndrome. |
In ESR_EL2, ISV is 1 when FEAT_LS64 is implemented and a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault.
For other faults reported in ESR_EL2, ISV is 0 except for the following stage 2 aborts:
For these stage 2 aborts, ISV is UNKNOWN if the exception was generated in Debug state in memory access mode, and otherwise indicates whether ISS[23:14] hold a valid syndrome.
For faults reported in ESR_EL1 or ESR_EL3, ISV is 1 when FEAT_LS64 is implemented and a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault. ISV is 0 for all other faults reported in ESR_EL1 or ESR_EL3.
When FEAT_RAS is implemented, ISV is 0 for any synchronous External abort.
For ISS reporting, a stage 2 abort on a stage 1 translation table walk does not return a valid instruction syndrome, and therefore ISV is 0 for these aborts.
When FEAT_RAS is not implemented, it is IMPLEMENTATION DEFINED whether ISV is set to 1 or 0 on a synchronous External abort on a stage 2 translation table walk.
When FEAT_MTE is implemented, for a synchronous Tag Check Fault abort taken to ELx, ESR_ELx.FNV is 0 and FAR_ELx is valid.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Syndrome Access Size. Indicates the size of the access attempted by the faulting operation.
SAS | Meaning |
---|---|
0b00 | Byte |
0b01 | Halfword |
0b10 | Word |
0b11 | Doubleword |
When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 0b11.
This field is UNKNOWN when the value of ISV is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
SyndromeTrapped SignFault Extend.Valid Forbit. aIndicates bytewhether the IDF, halfwordIXF, orUFF, wordOFF, load operationDZF, indicatesand whetherIOF thebits datahold itemvalid mustinformation beabout signtrapped extended.floating-point exceptions. The possible values of this bit are:
SSE | Meaning |
---|---|
0b0 | Sign-extension not required.
|
0b1 | Data item must be sign-extended.
|
WhenIt is FEAT_LS64IMPLEMENTATION DEFINED iswhether implemented,this iffield ais memoryset accessto generated0 byon an ST64BV,exception ST64BV0,generated ST64B,by ora LD64Btrapped instructionfloating generatespoint aexception Datafrom Abort for a Translationvector fault, Access flag fault, or Permission fault, then this field is 0.instruction.
This is not a requirement. Implementations can set this field to 1 on a trapped floating-point exception from a vector instruction and return valid information in the {IDF, IXF, UFF, OFF, DZF, IOF} fields.
This field resets to an architecturally UNKNOWN value.
For all other operations, this field is 0.
This field is UNKNOWN when the value of ISV is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
SyndromeFor Registera Transfer.trapped Whenfloating-point exception from an instruction executed in AArch32 state this field is FEAT_LS64RES1 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field holds register specifier, Xt..
IfFor thea exceptiontrapped wasfloating-point takenexception from an Exceptioninstruction levelexecuted thatin isAArch64 usingstate AArch32,this thenfield this is the AArch64 view of the register. See 'Mapping of the general-purpose registers between the Execution states'UNKNOWN.
This field isresets to an architecturally UNKNOWN when the value of ISV isvalue. UNKNOWN.
Input Denormal floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Width of the register accessed by the instruction is Sixty-Four.
SF | Meaning |
---|---|
0b0 | Instruction |
0b1 | Instruction |
This field resets to an architecturally UNKNOWN value.
This field specifies the register width identified by the instruction, not the Execution state.
When FEAT_LS64 is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 1.
This field is UNKNOWN when the value of ISV is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Acquire/Release.
Inexact floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
AR | Meaning |
---|---|
0b0 | Instruction |
0b1 | Instruction |
WhenThis field resets to an architecturally FEAT_LS64UNKNOWN is implemented, if a memory access generated by an ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault, then this field is 0.value.
Underflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
This field is UNKNOWN when the value of ISV is UNKNOWN.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Indicates that the fault came from use of VNCR_EL2 register by EL1 code.
VNCR | Meaning |
---|---|
0b0 | The |
0b1 | The |
This field is 0 in ESR_EL1.
This field resets to an architecturally UNKNOWN value.
Overflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Synchronous Error Type. When DFSC is 0b010000, describes the PE error state after taking the Data Abort exception.
SET | Meaning |
---|---|
0b00 | Recoverable |
0b10 | Uncontainable |
0b11 | Restartable state (UEO). |
All other values are reserved.
This field resets to an architecturally UNKNOWN value.
Divide by Zero floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in a PE state that is not recoverable.
This field is valid only if the DFSC code is 0b010000. It is RES0 for all other aborts.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Load/Store Type. Used when an LD64B, ST64B, ST64BV, or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault.
LST | Meaning |
---|---|
0b01 | An |
0b10 | An |
0b11 | An ST64BV0 instruction generated the Data Abort. |
All other values are reserved.
This field resets to an architecturally UNKNOWN value.
Invalid Operation floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
This field is valid only if the DFSC code is 0b110101. It is RES0 for all other aborts.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.
FnV | Meaning |
---|---|
0b0 | FAR |
0b1 | FAR |
This field isresets validto onlyan if the DFSC code isarchitecturally 0b010000UNKNOWN. It is RES0 for all other aborts.value.
In an implementation that supports the trapping of floating-point exceptions:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.
For any abort other than an External abort this bit returns a value of 0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Cache maintenance. Indicates whether the Data Abort came from a cache maintenance or address translation instruction:
CM | Meaning |
---|---|
0b0 | The Data Abort was not generated by the execution of one of the System instructions identified in the description of value 1. |
0b1 | The Data Abort was generated by either the execution of a cache maintenance instruction or by a synchronous fault on the execution of an address translation instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not classified as cache maintenance instructions, and therefore their execution cannot cause this field to be set to 1. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:
S1PTW | Meaning |
---|---|
0b0 | Fault not on a stage 2 translation for a stage 1 translation table walk. |
0b1 | Fault on the stage 2 translation of an access for a stage 1 translation table walk. |
For any abort other than a stage 2 fault this bit is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Write not Read. Indicates whether a synchronous abort was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.
WnR | Meaning |
---|---|
0b0 | Abort caused by an instruction reading from a memory location. |
0b1 | Abort caused by an instruction writing to a memory location. |
For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.
For faults from an atomic instruction that both reads and writes from a memory location, this bit is set to 0 if a read of the address specified by the instruction would have generated the fault which is being reported, otherwise it is set to 1. The architecture permits, but does not require, a relaxation of this requirement such that for all stage 2 aborts on stage 1 translation table walks for atomic instructions, the WnR bit is always 0.
This field is UNKNOWN for:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Data Fault Status Code.
DFSC | Meaning | Applies when |
---|---|---|
0b000000 | Address size fault, level 0 of translation or translation table base register. | |
0b000001 | Address size fault, level 1. | |
0b000010 | Address size fault, level 2. | |
0b000011 | Address size fault, level 3. | |
0b000100 | Translation fault, level 0. | |
0b000101 | Translation fault, level 1. | |
0b000110 | Translation fault, level 2. | |
0b000111 | Translation fault, level 3. | |
0b001001 | Access flag fault, level 1. | |
0b001010 | Access flag fault, level 2. | |
0b001011 | Access flag fault, level 3. | |
0b001000 | Access flag fault, level 0. | When FEAT_LPA2 is implemented |
0b001100 | Permission fault, level 0. | When FEAT_LPA2 is implemented |
0b001101 | Permission fault, level 1. | |
0b001110 | Permission fault, level 2. | |
0b001111 | Permission fault, level 3. | |
0b010000 | Synchronous External abort, not on translation table walk or hardware update of translation table. | |
0b010001 | Synchronous Tag Check Fault. | When FEAT_MTE is implemented |
0b010011 | Synchronous External abort on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented |
0b010100 | Synchronous External abort on translation table walk or hardware update of translation table, level 0. | |
0b010101 | Synchronous External abort on translation table walk or hardware update of translation table, level 1. | |
0b010110 | Synchronous External abort on translation table walk or hardware update of translation table, level 2. | |
0b010111 | Synchronous External abort on translation table walk or hardware update of translation table, level 3. | |
0b011000 | Synchronous parity or ECC error on memory access, not on translation table walk. | When FEAT_RAS is not implemented |
0b011011 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented and FEAT_RAS is not implemented |
0b011100 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0. | When FEAT_RAS is not implemented |
0b011101 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1. | When FEAT_RAS is not implemented |
0b011110 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2. | When FEAT_RAS is not implemented |
0b011111 | Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3. | When FEAT_RAS is not implemented |
0b100001 | Alignment fault. | |
0b101001 | Address size fault, level -1. | When FEAT_LPA2 is implemented |
0b101011 | Translation fault, level -1. | When FEAT_LPA2 is implemented |
0b110000 | TLB conflict abort. | |
0b110001 | Unsupported atomic hardware update fault. | When FEAT_HAFDBS is implemented |
0b110100 | IMPLEMENTATION DEFINED fault (Lockdown). | |
0b110101 | IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access). |
All other values are reserved.
For more information about the lookup level associated with a fault, see 'The level associated with MMU faults'.
Because Access flag faults and Permission faults can result only from a Block or Page translation table descriptor, they cannot occur at level 0.
If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | TFV | RES0 | VECITR | IDF | RES0 | IXF | UFF | OFF | DZF | IOF |
IMPLEMENTATION DEFINED syndrome. Possible values of this bit are:
| |
|
This field was previously called ISV.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
TrappedImplicit Faulterror Validsynchronization bit. Indicates whether the IDF, IXF, UFF, OFF, DZF, and IOF bits hold valid information about trapped floating-point exceptions.event.
TFV | Meaning |
---|---|
0b0 | The IDF, |
0b1 | One |
It is IMPLEMENTATION DEFINED whether this field is set to 0 on an exception generated by a trapped floating point exception from a vector instruction.
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.
This field resets to an architecturally UNKNOWN value.
This is not a requirement. Implementations can set this field to 1 on a trapped floating-point exception from a vector instruction and return valid information in the {IDF, IXF, UFF, OFF, DZF, IOF} fields.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
ForAsynchronous aError trapped floating-point exception from an instruction executed in AArch32 state this field isType. RES1.
ForWhen a trapped floating-point exception from an instruction executed in AArch64 state this fieldDFSC is UNKNOWN0b010001., describes the PE error state after taking the SError interrupt exception. The possible values of this field are:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Input Denormal floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
| |
| |
| |
IDF | Meaning |
---|---|
0b0 | Input |
0b1 | Input |
OnAll aother Warmvalues reset,are this field resets to an architecturallyreserved. UNKNOWN value.
If multiple errors are taken as a single SError interrupt exception, the overall PE error state is reported.
Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Data Fault Status Code.
Inexact floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
External abort type. When DFSC is 0b010001, provides an IMPLEMENTATION DEFINED classification of External aborts.
IXF | Meaning |
---|---|
0b0 | Inexact |
0b1 | Inexact |
OnAll aother Warmvalues reset,are this field resets to an architecturallyreserved. UNKNOWN value.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Underflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
UFF | Meaning |
---|---|
0b0 | Underflow floating-point exception has not occurred. |
0b1 | Underflow floating-point exception occurred during execution of the reported instruction. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Overflow floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
OFF | Meaning |
---|---|
0b0 | Overflow floating-point exception has not occurred. |
0b1 | Overflow floating-point exception occurred during execution of the reported instruction. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Divide by Zero floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
DZF | Meaning |
---|---|
0b0 | Divide by Zero floating-point exception has not occurred. |
0b1 | Divide by Zero floating-point exception occurred during execution of the reported instruction. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Invalid Operation floating-point exception trapped bit. If the TFV field is 0, this bit is UNKNOWN. Otherwise, the possible values of this bit are:
IOF | Meaning |
---|---|
0b0 | Invalid Operation floating-point exception has not occurred. |
0b1 | Invalid Operation floating-point exception occurred during execution of the reported instruction. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
In an implementation that supports the trapping of floating-point exceptions:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDS | RES0 | IESB | AET | EA | RES0 | DFSC |
IMPLEMENTATION DEFINED syndrome.
IDS | Meaning |
---|---|
0b0 | Bits [23:0] of the ISS field holds the fields described in this encoding. Note If FEAT_RAS is not implemented, bits [23:0] of the ISS field are RES0. |
0b1 | Bits [23:0] of the ISS field holds IMPLEMENTATION DEFINED syndrome information that can be used to provide additional information about the SError interrupt. |
This field was previously called ISV.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
ImplicitInstruction errorFault synchronizationStatus event.Code.
IESB | Meaning |
---|---|
0b0 | The |
0b1 | The SError interrupt was synchronized by the implicit error synchronization event and taken immediately. |
This field isresets validto onlyan if the DFSC code isarchitecturally 0b010001UNKNOWN. It is RES0 for all other errors.value.
For more information about generating these exceptions:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Asynchronous Error Type.
When DFSC is 0b010001, describes the PE error state after taking the SError interrupt exception.
AET | Meaning |
---|---|
0b000 | Uncontainable (UC). |
0b001 | Unrecoverable state (UEU). |
0b010 | Restartable state (UEO). |
0b011 | Recoverable state (UER). |
0b110 | Corrected (CE). |
All other values are reserved.
If multiple errors are taken as a single SError interrupt exception, the overall PE error state is reported.
Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
External abort type. When DFSC is 0b010001, provides an IMPLEMENTATION DEFINED classification of External aborts.
This field is valid only if the DFSC code is 0b010001. It is RES0 for all other errors.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Data Fault Status Code.
DFSC | Meaning |
---|---|
0b000000 | Uncategorized error. |
0b010001 | Asynchronous SError interrupt. |
All other values are reserved.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | IFSC |
Instruction syndrome valid. Indicates whether the EX bit, ISS[6], is valid, as follows:
| |
|
See the EX bit description for more information.
This field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Exclusive operation. If the ISV bit is set to 1, this bit indicates whether a Load-Exclusive instruction was stepped.
| |
|
If the ISV bit is set to 0, this bit is RES0, indicating no syndrome data is available.
This field resets to an architecturally UNKNOWN value.
Instruction Fault Status Code.
IFSC | Meaning |
---|---|
0b100010 | Debug exception. |
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions:
For more information about generating these exceptions, see 'Software Step exceptions'.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ISV | RES0 | EX | IFSC |
Reserved, RES0.
Reserved, RES0.
Indicates that the watchpoint came from use of VNCR_EL2 register by EL1 code.
Instruction syndrome valid. Indicates whether the EX bit, ISS[6], is valid, as follows:
ISV | Meaning |
---|---|
0b0 | EX bit is RES0.
|
0b1 | EX |
SeeThis thefield EXis bit0 descriptionin for more information.ESR_EL1.
On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Cache maintenance. Indicates whether the Watchpoint exception came from a cache maintenance or address translation instruction:
Exclusive operation. If the ISV bit is set to 1, this bit indicates whether a Load-Exclusive instruction was stepped.
Reserved, RES0.
EX | Meaning |
---|---|
0b0 | An |
0b1 | A |
IfThis thefield ISVresets bit is set to 0,an this bit isarchitecturally RES0UNKNOWN, indicating no syndrome data is available.value.
Reserved, RES0.
Write not Read. Indicates whether the Watchpoint exception was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are:
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Instruction Fault Status Code.
| |
IFSC | Meaning |
---|---|
0b100010 | Debug |
OnFor aWatchpoint Warmexceptions reseton cache maintenance and address translation instructions, this fieldbit resetsalways toreturns ana architecturallyvalue of 1. UNKNOWN value.
For Watchpoint exceptions from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint exception, otherwise it is set to 1.
If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint exception.
This field resets to an architecturally UNKNOWN value.
Data Fault Status Code.
|
This field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see 'Watchpoint exceptions'.
For more information about generating these exceptions, see 'Software Step exceptions'.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | RES0 | VNCR | RES0 | CM | RES0 | WnR | DFSC |
Reserved, RES0.
ReservedSet to the instruction comment field value, zero extended as necessary. RES0.
For the AArch32 BKPT instructions, the comment field is described as the immediate field.
This field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see 'Breakpoint instruction exceptions'.
Indicates that the watchpoint came from use of VNCR_EL2 register by EL1 code.
VNCR | Meaning |
---|---|
0b0 | The watchpoint was not generated by the use of VNCR_EL2 by EL1 code. |
0b1 | The watchpoint was generated by the use of VNCR_EL2 by EL1 code. |
This field is 0 in ESR_EL1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Reserved, RES0.
Cache maintenance. Indicates whether the Watchpoint exception came from a cache maintenance or address translation instruction:
CM | Meaning |
---|---|
0b0 | The Watchpoint exception was not generated by the execution of one of the System instructions identified in the description of value 1. |
0b1 | The Watchpoint exception was generated by either the execution of a cache maintenance instruction or by a synchronous Watchpoint exception on the execution of an address translation instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not classified as a cache maintenance instructions, and therefore their execution cannot cause this field to be set to 1. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Write not Read. Indicates whether the Watchpoint exception was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.
WnR | Meaning |
---|---|
0b0 | Watchpoint exception caused by an instruction reading from a memory location. |
0b1 | Watchpoint exception caused by an instruction writing to a memory location. |
For Watchpoint exceptions on cache maintenance and address translation instructions, this bit always returns a value of 1.
For Watchpoint exceptions from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint exception, otherwise it is set to 1.
If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint exception.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Data Fault Status Code.
DFSC | Meaning |
---|---|
0b100010 | Debug exception. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see 'Watchpoint exceptions'.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Comment |
This EC value applies when FEAT_FGT is implemented, or when HCR_EL2.NV is 1.
Reserved, RES0.
SetIndicates towhether thean ERET or ERETA* instruction commentwas fieldtrapped value,to zeroEL2. extendedPossible asvalues necessary.are:
| |
|
If this bit is 0, the ERETA field is RES0.
This field resets to an architecturally UNKNOWN value.
Indicates whether an ERETAA or ERETAB instruction was trapped to EL2. Possible values are:
| |
|
When the ERET field is 0, this bit is RES0.
This field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see HCR_EL2.NV.
If FEAT_FGT is implemented, HFGITR_EL2.ERET controls fine-grained trap exceptions from ERET, ERETAA and ERETAB execution.
For the AArch32 BKPT instructions, the comment field is described as the immediate field.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see 'Breakpoint instruction exceptions'.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | ERET | ERETA |
This EC value applies when FEAT_FGT is implemented, or when HCR_EL2.NV is 1.
Reserved, RES0.
IndicatesThis whetherfield anis ERETset orto ERETA*the instructionPSTATE.BTYPE wasvalue trappedthat togenerated EL2.the Branch Target Exception.
For more information about generating these exceptions, see 'The AArch64 application level programmers model'.
ERET | Meaning |
---|---|
0b0 | ERET instruction trapped to EL2. |
0b1 | ERETAA or ERETAB instruction trapped to EL2. |
If this bit is 0, the ERETA field is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Indicates whether an ERETAA or ERETAB instruction was trapped to EL2.
ERETA | Meaning |
---|---|
0b0 | ERETAA instruction trapped to EL2. |
0b1 | ERETAB instruction trapped to EL2. |
When the ERET field is 0, this bit is RES0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
For more information about generating these exceptions, see HCR_EL2.NV.
If FEAT_FGT is implemented, HFGITR_EL2.ERET controls fine-grained trap exceptions from ERET, ERETAA and ERETAB execution.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | BTYPE |
Reserved, RES0.
For more information about generating these exceptions, see:
This field is set to the PSTATE.BTYPE value that generated the Branch Target Exception.
For more information about generating these exceptions, see 'The AArch64 application level programmers model'.
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
This field indicates whether the exception is as a result of an Instruction key or a Data key.
| |
|
This field resets to an architecturally UNKNOWN value.
This field indicates whether the exception is as a result of an A key or a B key.
| |
|
This field resets to an architecturally UNKNOWN value.
The following instructions generate an exception when the Pointer Authentication Code (PAC) is incorrect:
It is IMPLEMENTATION DEFINED whether the following instructions generate an exception directly from the authorization failure, rather than changing the address in a way that will generate a translation fault when the address is accessed:
24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Exception as a result of an Instruction key or a Data key | Exception as a result of an A key or a B key |
Reserved, RES0.
This field indicates whether the exception is as a result of an Instruction key or a Data key.
Meaning | |
---|---|
0b0 | Instruction Key. |
0b1 | Data Key. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
This field indicates whether the exception is as a result of an A key or a B key.
Meaning | |
---|---|
0b0 | A key. |
0b1 | B key. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
The following instructions generate an exception when the Pointer Authentication Code (PAC) is incorrect:
It is IMPLEMENTATION DEFINED whether the following instructions generate an exception directly from the authorization failure, rather than changing the address in a way that will generate a translation fault when the address is accessed:
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ESR_EL1 or ESR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.ESR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x138]; else return ESR_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return ESR_EL2; else return ESR_EL1; elsif PSTATE.EL == EL3 then return ESR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.ESR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x138] = X[t]; else ESR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then ESR_EL2 = X[t]; else ESR_EL1 = X[t]; elsif PSTATE.EL == EL3 then ESR_EL1 = X[t];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then return NVMem[0x138]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return ESR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then return ESR_EL1; else UNDEFINED;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x138] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then ESR_EL1 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then ESR_EL1 = X[t]; else UNDEFINED;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return ESR_EL1; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return ESR_EL2; elsif PSTATE.EL == EL3 then return ESR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0101 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then ESR_EL1 = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then ESR_EL2 = X[t]; elsif PSTATE.EL == EL3 then ESR_EL2 = X[t];
3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |