The CTICLAIMSET characteristics are:
Used by software to set CLAIM bits to 1.
CTICLAIMSET is in the Debug power domain.
Implementation of this register is OPTIONAL.
CTICLAIMSET is a 32-bit register.
The CTICLAIMSET bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAIM<x>, bit [x] |
CLAIM tag set bit.
For values of x greater than or equal to the IMPLEMENTATION DEFINED number of CLAIM tags, this bit is RAZ/SBZ. Software can rely on these bits reading as zero, and must use a Should-Be-Zero policy on writes. Implementations must ignore writes.
For other values of x, the bit is RAO and the behavior on writes is:
CLAIM<x> | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Indirectly set CLAIM[x] tag to 1. |
A single write to CTICLAIMSET can set multiple tags to 1.
An External Debug reset clears the CLAIM tag bits to 0.
Component | Offset | Instance |
---|---|---|
CTI | 0xFA0 | CTICLAIMSET |
This interface is accessible as follows:
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.