The PMSNEVFR_EL1 characteristics are:
Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 0b1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 (TLB walk) clear are recorded.
This register is present only when FEAT_SPEv1p2 is implemented. Otherwise, direct accesses to PMSNEVFR_EL1 are UNDEFINED.
PMSNEVFR_EL1 is a 64-bit register.
The PMSNEVFR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
E[63] | E[62] | E[61] | E[60] | E[59] | E[58] | E[57] | E[56] | E[55] | E[54] | E[53] | E[52] | E[51] | E[50] | E[49] | E[48] | RAZ/WI | |||||||||||||||
E[31] | E[30] | E[29] | E[28] | E[27] | E[26] | E[25] | E[24] | RAZ/WI | E[18] | E[17] | RAZ/WI | E[15] | E[14] | E[13] | E[12] | E[11] | RAZ/WI | E[7] | E[6] | E[5] | RAZ/WI | E[3] | RAZ/WI | E[1] | RAZ/WI | ||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E[<x>] is the event filter for IMPLEMENTATION DEFINED event <x>.
E[<x>] | Meaning |
---|---|
0b0 |
Event <x> is ignored. |
0b1 |
Do not record samples that have event <x> == 1. |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSNEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
When event <x> is not implemented, or filtering on event <x> is not supported, access to this field is RAZ/WI.
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Not empty predicate.
E[18] | Meaning |
---|---|
0b0 |
Empty predicate event is ignored. |
0b1 |
Do not record samples that have the Empty predicate event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Not partial predicate.
E[17] | Meaning |
---|---|
0b0 |
Partial predicate event is ignored. |
0b1 |
Do not record samples that have the Partial predicate event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Aligned.
E[11] | Meaning |
---|---|
0b0 |
Misalignment event is ignored. |
0b1 |
Do not record samples that have the Misalignment event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Correctly predicted.
E[7] | Meaning |
---|---|
0b0 |
Mispredicted event is ignored. |
0b1 |
Do not record samples that have the Mispredicted event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Taken.
E[6] | Meaning |
---|---|
0b0 |
Not taken event is ignored. |
0b1 |
Do not record samples that have the Not taken event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
TLB hit.
E[5] | Meaning |
---|---|
0b0 |
TLB walk event is ignored. |
0b1 |
Do not record samples that have the TLB walk event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Level 1 data or unified cache hit.
E[3] | Meaning |
---|---|
0b0 |
Level 1 data or unified cache refill event is ignored. |
0b1 |
Do not record samples that have the Level 1 data or unified cache refill event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Speculative.
E[1] | Meaning |
---|---|
0b0 |
Architecturally retired event is ignored. |
0b1 |
Do not record samples that have the Architecturally retired event == 1. |
This bit is ignored by the PE when PMSFCR_EL1.FnE == 0b0. This bit is RES0 if the PE does not support sampling of speculative instructions.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RAZ/WI.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGRTR_EL2.nPMSNEVFR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then return NVMem[0x850]; else return PMSNEVFR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMSNEVFR_EL1; elsif PSTATE.EL == EL3 then return PMSNEVFR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && ((HaveEL(EL3) && SCR_EL3.FGTEn == '0') || HDFGWTR_EL2.nPMSNEVFR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then NVMem[0x850] = X[t]; else PMSNEVFR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSNEVFR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSNEVFR_EL1 = X[t];
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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