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ICV_PMR, Interrupt Controller Virtual Interrupt Priority Mask Register

The ICV_PMR characteristics are:

Purpose

Provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE.

Configuration

AArch32 System register ICV_PMR bits [31:0] are architecturally mapped to AArch64 System register ICV_PMR_EL1[31:0] .

This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICV_PMR are UNDEFINED.

To allow software to ensure appropriate observability of actions initiated by GIC register accesses, the PE and CPU interface logic must ensure that writes to this register are self-synchronising. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. For more information, see 'Observability of the effects of accesses to the GIC registers' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

Attributes

ICV_PMR is a 32-bit register.

Field descriptions

The ICV_PMR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0Priority

Bits [31:8]

Reserved, RES0.

Priority, bits [7:0]

The priority mask level for the virtual CPU interface. If the priority of a virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE.

The possible priority field values are as follows:

Implemented priority bitsPossible priority field valuesNumber of priority levels
[7:0]0x00-0xFF (0-255), all values256
[7:1]0x00-0xFE (0-254), even values only128
[7:2]0x00-0xFC (0-252), in steps of 464
[7:3]0x00-0xF8 (0-248), in steps of 832
[7:4]0x00-0xF0 (0-240), in steps of 1616

Unimplemented priority bits are RAZ/WI.

On a Warm reset, thisThis field resets to 0.

Accessing the ICV_PMR

Accesses to this register use the following encodings:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01000b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TC == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then return ICV_PMR; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then return ICV_PMR; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FMO == '1' then return ICV_PMR; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.IMO == '1' then return ICV_PMR; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else return ICC_PMR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else return ICC_PMR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICC_PMR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01000b01100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TC == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then ICV_PMR = R[t]; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_PMR = R[t]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FMO == '1' then ICV_PMR = R[t]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.IMO == '1' then ICV_PMR = R[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else ICC_PMR = R[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else ICC_PMR = R[t]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else ICC_PMR = R[t];




3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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