The CTIGATE characteristics are:
Determines whether events on channels propagate through the CTM to other ECT components, or from the CTM into the CTI.
CTIGATE is in the Debug power domain.
CTIGATE is a 32-bit register.
The CTIGATE bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GATE<x>, bit [x] |
Channel <x> gate enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
GATE<x> | Meaning |
---|---|
0b0 |
Disable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation. |
0b1 |
Enable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation. |
If GATE[x] is set to 0, no new events will be propagated to the ECT, and if the ECT supports multicycle channel events any existing output channel events will be terminated.
On a Cold reset, the value of this field is unchanged.
On an External debug reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Component | Offset | Instance |
---|---|---|
CTI | 0x140 | CTIGATE |
This interface is accessible as follows:
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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