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The GICR_SYNCR characteristics are:
Indicates completion of register based invalidate operations.
A copy of this register is provided for each Redistributor.
GICR_SYNCR is a 32-bit register.
The GICR_SYNCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Busy |
Reserved, RES0.
Indicates completion of invalidation operations
Busy | Meaning |
---|---|
0b0 | No operations are in progress. |
0b1 | A write is in progress to one or more of the following registers:
|
This field tracks operations initiated on the same Redistributor.
When this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.
This register is mandatory when any of the following are true:
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
Otherwise, the functionality is IMPLEMENTATION DEFINED.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | RD_base | 0x00C0 | GICR_SYNCR |
This interface is accessible as follows:
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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