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CPTR_EL2, Architectural Feature Trap Register (EL2)

The CPTR_EL2 characteristics are:

Purpose

Controls trapping to EL2 of accesses to: CPACR, CPACR_EL1, trace, Activity Monitor, SVE, Advanced SIMD and floating-point functionality.

Configuration

AArch64 System register CPTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HCPTR[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

CPTR_EL2 is a 64-bit register.

Field descriptions

The CPTR_EL2 bit assignments are:

When FEAT_VHE is implemented and HCR_EL2.E2H == 1:

6362616059585756555453525150494847464544434241403938373635343332
RES0
TCPACTAMRES0TTARES0FPENRES0ZENRES0
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

TCPAC, bit [31]

When HCR_EL2.TGE is 0, traps EL1 accesses to CPACR_EL1 reported using ESR_ELx.ECEC syndrome value 0x18, and accesses to CPACR reported using ESR_ELx.ECEC syndrome value 0x03, to EL2 when EL2 is enabled in the current Security state.

TCPACMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when EL2 is enabled in the current Security state.

When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

TAM, bit [30]

When FEAT_AMUv1 is implemented:

Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, as follows:

TAMMeaning
0b0

Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.

0b1

Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bit [29]

Reserved, RES0.

TTA, bit [28]

Traps System register accesses to all implemented trace registers to EL2 when EL2 is enabled in the current Security state, from both Execution states, as follows:

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1 or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when EL2 is enabled in the current Security state, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA.

When HCR_EL2.TGE is 1, any attempt at EL0 or EL2 to execute a System register access to an implemented trace register is trapped to EL2 when EL2 is enabled in the current Security state.

Note

The ETMv4 architecture does not permit EL0 to access the trace registers. If the PE trace unit implements FEAT_ETMv4, EL0 access to the trace registers are UNDEFINED, and any resulting exception is higher priority than this trap exception that would be generated because the value of CPTR_EL2.TTA is 1.

EL2 does not provide traps on trace register accesses through the optional Memory-mapped interface.

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

Bits [27:22]

Reserved, RES0.

FPEN, bits [21:20]

Traps executionEL0, at EL2, EL1, and EL0 of instructions that directly access the SVE, Advanced SIMD and floating-point registers to EL2 when EL2 is enabled in the current Security state, from both Execution states.HCR_EL2.TGE is 0, EL1 accesses to the SVE, Advanced SIMD and floating-point registers to EL2 when EL2 is enabled in the current Security state, from both Execution states.

The exception is reported using ESR_ELx.EC value 0x07.

Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL2.ZEN has precedence over the value of CPTR_EL2.FPEN.

FPENMeaning
0b00

This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules.rules, unless they are trapped byCPTR_EL2.ZEN.

0b01

When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.

When HCR_EL2.TGE is 1, this control causes instructions at EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, butunless doesthey notare causetrapped any instruction at EL2 to be trapped.byCPTR_EL2.ZEN, but does not cause any instruction at EL2 to be trapped.

0b10

This control causes any instructions at EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules.rules, unless they are trapped byCPTR_EL2.ZEN.

0b11

This control does not cause any instructions to be trapped.

Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.

Note

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

Bits [19:18]

Reserved, RES0.

ZEN, bits [17:16]

When FEAT_SVE is implemented:

Traps execution at EL2, EL1, and EL0 of SVE instructions, andor instructions that directly access SVE System registers to EL2 when EL2 is enabled in the current Security state. ZCR_EL1 and ZCR_EL2 System registers to EL2 when EL2 is enabled in the current Security state.

The exception is reported using ESR_ELx.EC value 0x19.

Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL2.ZEN has precedence over the value of CPTR_EL2.FPEN.

ZENMeaning
0b00

This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

0b01

When HCR_EL2.TGE is 0, this control does not cause any instruction to be trapped.

When HCR_EL2.TGE is 1, this control causes these instructions executed at EL0 to be trapped, but does not cause any instruction at EL2 to be trapped.

0b10

This control causes execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

0b11

This control does not cause any instruction to be trapped.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [15:0]

Reserved, RES0.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
RES0
TCPACTAMRES0TTARES0RES1RES0TFPRES1TZRES1
313029282726252423222120191817161514131211109876543210

This format applies in all Armv8.0 implementations.

Bits [63:32]

Reserved, RES0.

TCPAC, bit [31]

Traps EL1 accesses to CPACR_EL1, reported using ESR_ELx.ECEC syndrome value 0x18 and accesses to CPACR, reported using ESR_ELx.ECEC syndrome value 0x03, to EL2 when EL2 is enabled in the current Security state.

TCPACMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2 when EL2 is enabled in the current Security state.

When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

TAM, bit [30]

When FEAT_AMUv1 is implemented:

Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor registers to EL2, as follows:

TAMMeaning
0b0

Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.

0b1

Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, when EL2 is enabled in the current Security state.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES0.

Bits [29:21]

Reserved, RES0.

TTA, bit [20]

Traps System register accesses to all implemented trace registers to EL2 when EL2 is enabled in the current Security state, from both Execution states as follows:

TTAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1, or EL2, to execute a System register access to an implemented trace register is trapped to EL2 when EL2 is enabled in the current Security state, unless it is trapped by CPACR.TRCDIS or CPACR_EL1.TTA.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

Bits [19:14]

Reserved, RES0.

Bits [13:12]

Reserved, RES1.

Bit [11]

Reserved, RES0.

TFP, bit [10]

Traps accesses to SVE, Advanced SIMD and floating-point functionality to EL2 when EL2 is enabled in the current Security state, from both Execution states, as follows:

Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL2.TZ has precedence over the value of CPTR_EL2.TFP.

TFPMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

Any attempt at EL0, EL1 or EL2, to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point execution is trapped to EL2 when EL2 is enabled in the current Security state, subject to the exception prioritization rules.rules, unless it is trapped byCPTR_EL2.TZ.

Note

FPEXC32_EL2 is not accessible from EL0 using AArch64.

FPSID, MVFR0, MVFR1, and FPEXC are not accessible from EL0 using AArch32.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.

Bit [9]

Reserved, RES1.

TZ, bit [8]

When FEAT_SVE is implemented:

Traps execution at EL2, EL1, or EL0 of SVE instructions and instructions that directly access SVE System registers to EL2 when EL2 is enabled in the current Security state. ZCR_EL2 and ZCR_EL1 System registers to EL2 when EL2 is enabled in the current Security state.

The exception is reported using ESR_ELx.EC value 0x19.

Trapping behavior is affected by precedence as follows: A trap taken as a result of CPTR_EL2.TZ has precedence over the value of CPTR_EL2.TFP.

TZMeaning
0b0

This control does not cause any instruction to be trapped.

0b1

This control causes these instructions to be trapped, subject to the exception prioritization rules.

On a Warm reset, thisThis field resets to an architecturally UNKNOWN value.


Otherwise:

Reserved, RES1.

Bits [7:0]

Reserved, RES1.

Accessing the CPTR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, CPTR_EL2

op0op1CRnCRmop2
0b110b1000b00010b00010b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return CPTR_EL2; elsif PSTATE.EL == EL3 then return CPTR_EL2;

MSR CPTR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00010b00010b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else CPTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then CPTR_EL2 = X[t];

MRS <Xt>, CPACR_EL1

op0op1CRnCRmop2
0b110b0000b00010b00000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TCPAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.CPACR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x100]; else return CPACR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then return CPTR_EL2; else return CPACR_EL1; elsif PSTATE.EL == EL3 then return CPACR_EL1;

MSR CPACR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00010b00000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TCPAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.CPACR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x100] = X[t]; else CPACR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then CPTR_EL2 = X[t]; else CPACR_EL1 = X[t]; elsif PSTATE.EL == EL3 then CPACR_EL1 = X[t];




3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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