TLBI ASIDE1OS, TLB Invalidate by ASID, EL1, Outer Shareable

The TLBI ASIDE1OS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.

Configuration

This instruction is present only when FEAT_TLBIOS is implemented. Otherwise, direct accesses to TLBI ASIDE1OS are UNDEFINED.

Attributes

TLBI ASIDE1OS is a 64-bit System instruction.

Field descriptions

The TLBI ASIDE1OS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDRES0
RES0
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this System instruction.

If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.

Bits [47:0]

Reserved, RES0.

Executing the TLBI ASIDE1OS instruction

Accesses to this instruction use the following encodings:

TLBI ASIDE1OS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00010b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBOS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIASIDE1OS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_ASIDE1OS(X[t]); elsif PSTATE.EL == EL2 then TLBI_ASIDE1OS(X[t]); elsif PSTATE.EL == EL3 then TLBI_ASIDE1OS(X[t]);




01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a

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