The GICV_HPPIR characteristics are:
Provides the INTID of the highest priority pending Group 0 virtual interrupt in the List registers.
This register corresponds to the physical CPU interface register GICC_HPPIR.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_HPPIR is a 32-bit register.
The GICV_HPPIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | INTID |
Reserved, RES0.
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
Reads of the GICC_HPPIR that do not return a valid INTID return a spurious INTID, 1022 or 1023. See 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
Highest priority pending interrupt Group | GICV_HPPIR read | GICV_CTLR.AckCtl | Returned INTID |
---|---|---|---|
1 | Non-secure | x | ID of Group 1 interrupt |
1 | Secure | 0 | 1022 |
1 | Secure | 1 | ID of Group 1 interrupt |
0 | Non-secure | x | 1023 |
0 | Secure | x | ID of Group 0 interrupt |
No pending interrupts | x | x | 1023 |
If the CPU interface supports only a single Security state, the entries that apply to Secure reads describe the behavior.
This register is used only when System register access is not enabled. When System register access is enabled:
This register is used for Group 0 interrupts only. GICV_AHPPIR provides equivalent functionality for Group 1 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x0018 | GICV_HPPIR |
This interface is accessible as follows:
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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