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TLBI VALE1OS, TLBI VALE1OSNXS, TLB Invalidate by VA, Last level, EL1, Outer Shareable

The TLBI VALE1OS, TLBI VALE1OSNXS characteristics are:

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.

Note

When a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

This instruction is present only when FEAT_TLBIOS is implemented. Otherwise, direct accesses to TLBI VALE1OS, TLBI VALE1OSNXS are UNDEFINED.

Attributes

TLBI VALE1OS, TLBI VALE1OSNXS is a 64-bit System instruction.

Field descriptions

The TLBI VALE1OS, TLBI VALE1OSNXS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDTTLVA[55:12]
VA[55:12]
313029282726252423222120191817161514131211109876543210

ASID, bits [63:48]

ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.

Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.

If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.

TTL, bits [47:44]

When FEAT_TTL is implemented:

Translation Table Level. Indicates the level of the page table walk that holds the leaf entry for the address being invalidated.

TTLMeaning
0b00xx

No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0.

0b01xx

The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : IfReserved. Treat as if TTL<3:2> is FEAT_LPA2 is implemented, level 0. Otherwise, treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

0b10xx

The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : IfReserved. Treat as if TTL<3:2> is FEAT_LPA2 is implemented, level 1. Otherwise, treat as if TTL<3:2> is 0b00.

0b10 : Level 2.

0b11 : Level 3.

0b11xx

The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as:

0b00 : Reserved. Treat as if TTL<3:2> is 0b00.

0b01 : Level 1.

0b10 : Level 2.

0b11 : Level 3.

If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB.


Otherwise:

Reserved, RES0.

VA[55:12], bits [43:0]

Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the ASID value (if appropriate) and VA will be affected by this System instruction.

If the TLB maintenance instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then the software must treat bits[55:32] as RES0.

The treatment of the low-order bits of this field depends on the translation granule size, as follows:

Executing the TLBI VALE1OS instruction

Accesses to this instruction use the following encodings:

TLBI VALE1OS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00010b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBOS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIVALE1OS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_VALE1OS(X[t]); elsif PSTATE.EL == EL2 then TLBI_VALE1OS(X[t]); elsif PSTATE.EL == EL3 then TLBI_VALE1OS(X[t]);

Executing the TLBI VALE1OS, TLBI VALE1OSNXS instruction

Accesses to this instruction use the following encodings:

TLBI VALE1OS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10000b00010b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBOS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIVALE1OS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else if IsFeatureImplemented(FEAT_XS) && HCRX_EL2.FnXS == '1' then TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Last, TLBI_AllAttr, X[t]); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_AllAttr, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Last, TLBI_AllAttr, X[t]); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_AllAttr, X[t]);

TLBI VALE1OSNXS{, <Xt>}

op0op1CRnCRmop2
0b010b0000b10010b00010b101

if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TTLBOS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HCRX_EL2.FGTnXS == '0' && HFGITR_EL2.TLBIVALE1OS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL2 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]); elsif PSTATE.EL == EL3 then if HCR_EL2.<E2H,TGE> == '11' then TLBI_VA(SecurityStateAtEL(EL2), Regime_EL20, VMID_NONE, Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]); else TLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_Outer, TLBILevel_Last, TLBI_ExcludeXS, X[t]);




3001/0907/2020 15:0657; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a

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