The HFGITR_EL2 characteristics are:
Provides controls for traps of execution of System instructions.
This register is present only when FEAT_FGT is implemented. Otherwise, direct accesses to HFGITR_EL2 are UNDEFINED.
HFGITR_EL2 is a 64-bit register.
The HFGITR_EL2 bit assignments are:
Reserved, RES0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCVAC | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of SVC at EL1 using AArch64 to EL2.
SVC_EL1 | Meaning |
---|---|
0b0 |
Execution of SVC is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of SVC at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 when EL1 is using AArch64 to EL2.
SVC_EL0 | Meaning |
---|---|
0b0 |
Execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception:
|
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of ERET* instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:
ERET | Meaning |
---|---|
0b0 |
Execution of the ERET* instructions is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the ERET* instructions is trapped to EL2 and reported with EC syndrome value 0x1A, unless the instruction generates a higher priority exception. If EL2 is implemented and enabled in the current Security state and HCR_EL2.API == 0, execution at EL1 using AArch64 of ERETAA or ERETAB instructions is reported with EC syndrome value 0x1A with its associated ISS field, as the fine-grained trap has higher priority than the HCR_EL2.API == 0. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.
CPPRCTX | Meaning |
---|---|
0b0 |
Execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception: |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.
DVPRCTX | Meaning |
---|---|
0b0 |
Execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception: |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.
CFPRCTX | Meaning |
---|---|
0b0 |
Execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception: |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VAALE1 at EL1 using AArch64 to EL2.
TLBIVAALE1 | Meaning |
---|---|
0b0 |
Execution of TLBI VAALE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VALE1 at EL1 using AArch64 to EL2.
TLBIVALE1 | Meaning |
---|---|
0b0 |
Execution of TLBI VALE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VAAE1 at EL1 using AArch64 to EL2.
TLBIVAAE1 | Meaning |
---|---|
0b0 |
Execution of TLBI VAAE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI ASIDE1 at EL1 using AArch64 to EL2.
TLBIASIDE1 | Meaning |
---|---|
0b0 |
Execution of TLBI ASIDE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VAE1 at EL1 using AArch64 to EL2.
TLBIVAE1 | Meaning |
---|---|
0b0 |
Execution of TLBI VAE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VMALLE1 at EL1 using AArch64 to EL2.
TLBIVMALLE1 | Meaning |
---|---|
0b0 |
Execution of TLBI VMALLE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI RVAALE1 at EL1 using AArch64 to EL2.
TLBIRVAALE1 | Meaning |
---|---|
0b0 |
Execution of TLBI RVAALE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVALE1 at EL1 using AArch64 to EL2.
TLBIRVALE1 | Meaning |
---|---|
0b0 |
Execution of TLBI RVALE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAAE1 at EL1 using AArch64 to EL2.
TLBIRVAAE1 | Meaning |
---|---|
0b0 |
Execution of TLBI RVAAE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAE1 at EL1 using AArch64 to EL2.
TLBIRVAE1 | Meaning |
---|---|
0b0 |
Execution of TLBI RVAE1 is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAALE1IS at EL1 using AArch64 to EL2.
TLBIRVAALE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAALE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVALE1IS at EL1 using AArch64 to EL2.
TLBIRVALE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI RVALE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAAE1IS at EL1 using AArch64 to EL2.
TLBIRVAAE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAAE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAE1IS at EL1 using AArch64 to EL2.
TLBIRVAE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VAALE1IS at EL1 using AArch64 to EL2.
TLBIVAALE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI VAALE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VALE1IS at EL1 using AArch64 to EL2.
TLBIVALE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI VALE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VAAE1IS at EL1 using AArch64 to EL2.
TLBIVAAE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI VAAE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI ASIDE1IS at EL1 using AArch64 to EL2.
TLBIASIDE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI ASIDE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VAE1IS at EL1 using AArch64 to EL2.
TLBIVAE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI VAE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI VMALLE1IS at EL1 using AArch64 to EL2.
TLBIVMALLE1IS | Meaning |
---|---|
0b0 |
Execution of TLBI VMALLE1IS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of TLBI RVAALE1OS at EL1 using AArch64 to EL2.
TLBIRVAALE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAALE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVALE1OS at EL1 using AArch64 to EL2.
TLBIRVALE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI RVALE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAAE1OS at EL1 using AArch64 to EL2.
TLBIRVAAE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAAE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI RVAE1OS at EL1 using AArch64 to EL2.
TLBIRVAE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI RVAE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VAALE1OS at EL1 using AArch64 to EL2.
TLBIVAALE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI VAALE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VALE1OS at EL1 using AArch64 to EL2.
TLBIVALE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI VALE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VAAE1OS at EL1 using AArch64 to EL2.
TLBIVAAE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI VAAE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI ASIDE1OS at EL1 using AArch64 to EL2.
TLBIASIDE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI ASIDE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VAE1OS at EL1 using AArch64 to EL2.
TLBIVAE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI VAE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of TLBI VMALLE1OS at EL1 using AArch64 to EL2.
TLBIVMALLE1OS | Meaning |
---|---|
0b0 |
Execution of TLBI VMALLE1OS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of AT S1E1WP at EL1 using AArch64 to EL2.
ATS1E1WP | Meaning |
---|---|
0b0 |
Execution of AT S1E1WP is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1WP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of AT S1E1RP at EL1 using AArch64 to EL2.
ATS1E1RP | Meaning |
---|---|
0b0 |
Execution of AT S1E1RP is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1RP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of AT S1E0W at EL1 using AArch64 to EL2.
ATS1E0W | Meaning |
---|---|
0b0 |
Execution of AT S1E0W is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E0W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of AT S1E0R at EL1 using AArch64 to EL2.
ATS1E0R | Meaning |
---|---|
0b0 |
Execution of AT S1E0R is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E0R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of AT S1E1W at EL1 using AArch64 to EL2.
ATS1E1W | Meaning |
---|---|
0b0 |
Execution of AT S1E1W is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of AT S1E1R at EL1 using AArch64 to EL2.
ATS1E1R | Meaning |
---|---|
0b0 |
Execution of AT S1E1R is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:
DCZVA | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCIVAC | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCVADP | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Reserved, RES0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCVAP | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of DC CVAU at EL1 and EL0 using AArch64 to EL2.
DCCVAU | Meaning |
---|---|
0b0 |
Execution of DC CVAU is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of DC CVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCISW | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:
DCCSW | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:
DCISW | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:
DCIVAC | Meaning |
---|---|
0b0 |
Execution of the System instructions listed above is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of IC IVAU at EL1 and EL0 using AArch64 to EL2.
ICIVAU | Meaning |
---|---|
0b0 |
Execution of IC IVAU is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of IC IALLU at EL1 using AArch64 to EL2.
ICIALLU | Meaning |
---|---|
0b0 |
Execution of IC IALLU is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IALLU at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Trap execution of IC IALLUIS at EL1 using AArch64 to EL2.
ICIALLUIS | Meaning |
---|---|
0b0 |
Execution of IC IALLUIS is not affected by this bit. |
0b1 |
If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IALLUIS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. |
In a system where the PE resets into EL2, this field resets to 0.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1C8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return HFGITR_EL2; elsif PSTATE.EL == EL3 then return HFGITR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1C8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGITR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HFGITR_EL2 = X[t];
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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