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The GICD_ICENABLER<n>E characteristics are:
Disables forwarding of the corresponding SPI in the extended SPI range to the CPU interfaces.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ICENABLER<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ICENABLER<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
GICD_ICENABLER<n>E is a 32-bit register.
The GICD_ICENABLER<n>E bit assignments are:
For the extended SPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:
Clear_enable_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. |
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 0. |
On a Warm reset, thisThis field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
The corresponding GICD_ICENABLER<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ICENABLER<n>E is (0x1400 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
When affinity routing is not enabled for the Security state of an interrupt in GICD_ICENABLER<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x1400 + (4 * n) | GICD_ICENABLER<n>E |
This interface is accessible as follows:
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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