The TLBI ALLE1 characteristics are:
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL1&0 translation regime.
If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL1&0 translation regime.
The invalidation applies to entries with any VMID.
The invalidation only applies to the PE that executes this System instruction.
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
There are no configuration notes.
TLBI ALLE1 is a 64-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
The instruction is UNDEFINED.
The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b100 | 0b1000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TLBI_ALLE1(); elsif PSTATE.EL == EL3 then TLBI_ALLE1();
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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