RMR_EL1, Reset Management Register (EL1)

The RMR_EL1 characteristics are:

Purpose

When this register is implemented:

Configuration

AArch64 System register RMR_EL1 bits [31:0] are architecturally mapped to AArch32 System register RMR[31:0] when the highest implemented Exception level is EL1.

This register is present only when the highest implemented Exception level is EL1. Otherwise, direct accesses to RMR_EL1 are UNDEFINED.

When EL1 is the highest implemented Exception level:

Attributes

RMR_EL1 is a 64-bit register.

Field descriptions

The RMR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0
RES0RRAA64
313029282726252423222120191817161514131211109876543210

Bits [63:2]

Reserved, RES0.

RR, bit [1]

Reset Request. Setting this bit to 1 requests a Warm reset.

On a Warm reset, this field resets to 0.

AA64, bit [0]

When EL1 is capable of using AArch32:

When EL1 can use AArch32, determines which Execution state the PE boots into after a Warm reset:

AA64Meaning
0b0

AArch32.

0b1

AArch64.

On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.

If EL1 can only use AArch64 state, this bit is RAO/WI.

When implemented as a RW field, this field resets to 1 on a Cold reset.


Otherwise:

Reserved, RAO/WI.

Accessing the RMR_EL1

Accesses to this register use the following encodings:

MRS <Xt>, RMR_EL1

op0op1CRnCRmop2
0b110b0000b11000b00000b010

if PSTATE.EL == EL1 && IsHighestEL(EL1) then return RMR_EL1; else UNDEFINED;

MSR RMR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b11000b00000b010

if PSTATE.EL == EL1 && IsHighestEL(EL1) then RMR_EL1 = X[t]; else UNDEFINED;




30/09/2020 15:06; ccead0cb9f089f9ceec50268e82aec9e71047211

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