The AMPIDR0 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Peripheral identification scheme'.
The power domain of AMPIDR0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMPIDR0 is a 32-bit register.
The AMPIDR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_0 |
Reserved, RES0.
Part number, least significant byte.
The value of this field is IMPLEMENTATION DEFINED.
Component | Offset | Instance |
---|---|---|
AMU | 0xFE0 | AMPIDR0 |
Accesses on this interface are RO.
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.