The DBGDTRRX_EL0 characteristics are:
Transfers data from an external debugger to the PE. For example, it is used by a debugger transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communications Channel.
AArch64 System register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0] .
AArch64 System register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to External register DBGDTRRX_EL0[31:0] .
DBGDTRRX_EL0 is a 64-bit register.
The DBGDTRRX_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | |||||||||||||||||||||||||||||||
Update DTRRX | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Update DTRRX.
Reads of this register:
If RXfull is set to 1, return the last value written to DTRRX.
If RXfull is set to 0, return an UNKNOWN value.
After the read, RXfull is cleared to 0.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b0000 | 0b0101 | 0b000 |
if Halted() then return DBGDTRRX_EL0; elsif PSTATE.EL == EL0 then if MDSCR_EL1.TDCC == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && MDCR_EL2.TDCC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDCC == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return DBGDTRRX_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && MDCR_EL2.TDCC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDCC == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return DBGDTRRX_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MDCR_EL3.TDCC == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return DBGDTRRX_EL0; elsif PSTATE.EL == EL3 then return DBGDTRRX_EL0;
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
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