The GICD_ICPENDR<n>E characteristics are:
Removes the pending state to the corresponding SPI in the extended SPI range.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ICPENDR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ICPENDR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
GICD_ICPENDR<n>E is a 32-bit register.
The GICD_ICPENDR<n>E bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Clear_pending_bit<x>, bit [x], for x = 0 to 31 |
For the extended PPIs, removes the pending state to interrupt number x. Reads and writes have the following behavior:
Clear_pending_bit<x> | Meaning |
---|---|
0b0 |
If read, indicates that the corresponding interrupt is not pending. If written, has no effect. |
0b1 |
If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:
|
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_ICPENDR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x1800 + (4 * n) | GICD_ICPENDR<n>E |
This interface is accessible as follows:
01/07/2020 15:57; 80324f0b9997bede489cc15ad1565345720bcd2a
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