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The ID_AA64DFR0_EL1 characteristics are:
Provides top level information about the debug system in AArch64 state.
For general information about the interpretation of the ID registers, see Principles of the ID scheme for fields in ID registers.
The external register EDDFR gives information from this register.
ID_AA64DFR0_EL1 is a 64-bit register.
The ID_AA64DFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RES0 | MTPMU | RES0 | TraceFilt | DoubleLock | PMSVer | ||||||||||||||||||||||||||
CTX_CMPs | RES0 | WRPs | RES0 | BRPs | PMUVer | TraceVer | DebugVer | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Multi-threaded PMU extension. Defined values are:
MTPMU | Meaning |
---|---|
0b0000 | FEAT_MTPMU not implemented. If FEAT_PMUv3 |
0b0001 | FEAT_MTPMU |
0b1111 | FEAT_MTPMU not implemented. If FEAT_PMUv3 |
All other values are reserved.
FEAT_MTPMU implements the functionality identified by the value 0b0001.
FromIn Armv8.6,an inArmv8.6-compliant an implementation that includes FEAT_PMUv3PMUv3, the value 0b0000 is not permitted.
In an implementation that does not include FEAT_PMUv3PMUv3, the value 0b0001 is not permitted.
Reserved, RES0.
Armv8.4 Self-hosted Trace Extension version. Defined values are:
TraceFilt | Meaning |
---|---|
0b0000 | Armv8.4 Self-hosted Trace Extension not implemented. |
0b0001 | Armv8.4 Self-hosted Trace Extension implemented. |
All other values are reserved.
FEAT_TRF implements the functionality identified by the value 0b0001.
From Armv8.4, if an Embedded Trace Macrocell Architecture PE Trace Unit is implemented, the value 0b0000 is not permitted.
OS Double Lock implemented. Defined values are:
DoubleLock | Meaning |
---|---|
0b0000 | OS Double Lock implemented. OSDLR_EL1 is RW. |
0b1111 | OS Double Lock not implemented. OSDLR_EL1 is RAZ/WI. |
All other values are reserved.
FEAT_DoubleLock implements the functionality identified by the value 0b0000.
In Armv8.0, the only permitted value is 0b0000.
If FEAT_Debugv8p2 is implemented and FEAT_DoPD is not implemented, the permitted values are 0b0000 and 0b1111.
If FEAT_DoPD is implemented, the only permitted value is 0b1111.
Statistical Profiling Extension version. Defined values are:
PMSVer | Meaning |
---|---|
0b0000 | Statistical Profiling Extension not implemented. |
0b0001 | Statistical Profiling Extension implemented. |
0b0010 | As 0b0001, and adds:
|
0b0011 | As 0b0010, and adds:
|
All other values are reserved.
FEAT_SPE implements the functionality identified by the value 0b0001.
FEAT_SPEv1p1 implements the functionality identified by the value 0b0010.
FEAT_SPEv1p2 implements the functionality identified by the value 0b0011.
From Armv8.5, if FEAT_SPE is implemented, the value 0b0001 is not permitted.
In Armv8.5, if FEAT_SPE is implemented, the value 0b0001 is not permitted.
From Armv8.7, if FEAT_SPE is implemented, the value 0b0010 is not permitted.
Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.
Reserved, RES0.
Number of watchpoints, minus 1. The value of 0b0000 is reserved.
Reserved, RES0.
Number of breakpoints, minus 1. The value of 0b0000 is reserved.
Performance Monitors Extension version.
This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version'
Defined values are:
PMUVer | Meaning |
---|---|
0b0000 | Performance Monitors Extension not implemented. |
0b0001 | Performance Monitors Extension, PMUv3 implemented. |
0b0100 | PMUv3 for Armv8.1. As 0b0001, and also includes support for:
|
0b0101 | PMUv3 for Armv8.4. As 0b0100, and also includes support for the PMMIR_EL1 register. |
0b0110 | PMUv3 for Armv8.5. As 0b0101, and also includes support for: |
0b0111 | PMUv3 for Armv8.7. As 0b0110, and also includes support for: |
0b1111 | IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations. |
All other values are reserved.
FEAT_PMUv3 implements the functionality identified by the value 0b0001.
FEAT_PMUv3p1 implements the functionality identified by the value 0b0100.
FEAT_PMUv3p4 implements the functionality identified by the value 0b0101.
FEAT_PMUv3p5 implements the functionality identified by the value 0b0110.
FEAT_PMUv3p7From implementsArmv8.1, theif functionalityFEAT_PMUv3 identifiedis byimplemented, the value 0b01110b0001.is not permitted.
InFrom Armv8.1Armv8.4, if FEAT_PMUv3 is implemented, the value 0b00010b0100 is not permitted.
InFrom Armv8.4Armv8.5, if FEAT_PMUv3 is implemented, the value 0b01000b0101 is not permitted.
In Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted.
From Armv8.7, if FEAT_PMUv3 is implemented, the value 0b0110 is not permitted.
Trace support. Indicates whether System register interface to a PE trace unit is implemented. Defined values are:
TraceVer | Meaning |
---|---|
0b0000 | PE trace unit System registers not implemented. |
0b0001 | PE trace unit System registers implemented. |
All other values are reserved.
See the ETM Architecture Specification for more information.
A value of 0b0000 only indicates that no System register interface to a PE trace unit is implemented. A PE trace unit might nevertheless be implemented without a System register interface.
Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:
DebugVer | Meaning |
---|---|
0b0110 | Armv8 debug architecture. |
0b0111 | Armv8 debug architecture with Virtualization Host Extensions. |
0b1000 | Armv8.2 debug architecture. |
0b1001 | Armv8.4 debug architecture. |
All other values are reserved.
FEAT_Debugv8p2 adds the functionality identified by the value 0b1000.
FEAT_Debugv8p4 adds the functionality identified by the value 0b1001.
In Armv8.1, the value 0b0110 is not permitted.
In Armv8.2, the value 0b0111 is not permitted.
From Armv8.4, the value 0b1000 is not permitted.
Accesses to this register use the following encodings:
if PSTATE.EL == EL0 then
if IsFeatureImplemented("FEAT_IDST") then
if EL2Enabled() && HCR_EL2.TGE == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
AArch64.SystemAccessTrap(EL1, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.TID3 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return ID_AA64DFR0_EL1;
elsif PSTATE.EL == EL2 then
return ID_AA64DFR0_EL1;
elsif PSTATE.EL == EL3 then
return ID_AA64DFR0_EL1;
Accesses to this register use the following encodings:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64DFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64DFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64DFR0_EL1;
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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