The GICD_ISPENDR<n>E characteristics are:
Adds the pending state to the corresponding SPI in the extended SPI range.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ISPENDR<n>E are RES0.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1, the number of implemented GICD_ISPENDR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
GICD_ISPENDR<n>E is a 32-bit register.
The GICD_ISPENDR<n>E bit assignments are:
For the extended SPIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:
Set_pending_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that the corresponding interrupt is not pending. If written, has no effect. |
0b1 | If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:
|
On a Warm reset, this field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_ISPENDR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Offset | Instance |
---|---|---|
GIC Distributor | 0x1600 + (4 * n) | GICD_ISPENDR<n>E |
This interface is accessible as follows:
30/09/2020 15:07; ccead0cb9f089f9ceec50268e82aec9e71047211
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.