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The SPSR characteristics are:
Holds the saved process state for the current mode.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to SPSR are UNDEFINED.
SPSR is a 32-bit register.
The SPSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | Q | IT[1:0] | J | SSBS | PAN | DIT | IL | GE | IT[7:2] | E | A | I | F | T | M[4:0] |
Negative Condition flag. Set to the value of PSTATE.N on taking an exception to the current mode, and copied to PSTATE.N on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Zero Condition flag. Set to the value of PSTATE.Z on taking an exception to the current mode, and copied to PSTATE.Z on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Carry Condition flag. Set to the value of PSTATE.C on taking an exception to the current mode, and copied to PSTATE.C on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Overflow Condition flag. Set to the value of PSTATE.V on taking an exception to the current mode, and copied to PSTATE.V on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Overflow or saturation flag. Set to the value of PSTATE.Q on taking an exception to the current mode, and copied to PSTATE.Q on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
If-Then.IT Setblock tostate thebits valuefor of PSTATE.IT[1:0] on taking an exception to the currentT32 mode,IT and(If-Then) copiedinstruction. toSee PSTATE.ITIT[17:02] onfor executingexplanation anof exceptionthis return operation in the current mode.field.
On executing an exception return operation in the current mode SPSR.IT must contain a value that is valid for the instruction being returned to.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
RES0.
In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. Armv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.
Speculative Store Bypass Safe. This bit is set to the value of PSTATE.SSBS on taking an exception to the current mode, and copied to PSTATE.SSBS on executing an exception return operation in the current mode.
Armv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.
Speculative Store Bypass. Set to the value of PSTATE.SSBS on taking an exception to the current mode, and copied to PSTATE.SSBS on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Privileged Access Never. SetThis bit is set to the value of PSTATE.PAN on taking an exception to the current mode, and copied to PSTATE.PAN on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Data Independent Timing. SetThis bit is set to the value of PSTATE.DIT on taking an exception to the current mode, and copied to PSTATE.DIT on executing an exception return operation in the current mode.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Reserved, RES0.
Illegal Execution state.state Setbit. toShows the value of PSTATE.IL onimmediately takingbefore an exception to the current mode, and copied to PSTATE.IL on executing an exception returnwas operation in the current mode.taken.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Greater than or Equal flags.flags, Setfor toparallel theaddition value of PSTATE.GE on taking an exception to the current mode, and copied to PSTATE.GE on executing an exception return operation in the current mode.subtraction.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
If-Then.IT Setblock tostate thebits valuefor of PSTATE.IT[7:2] on taking an exception to the currentT32 mode,IT and(If-Then) copiedinstruction. toThis PSTATE.IT[7:2]field onmust executingbe aninterpreted exception return operation in thetwo current mode.parts.
The IT field is 0b00000000 when no IT block is active.
SPSR.IT must contain a value that is valid for the instruction being returned to.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Endianness.Endianness Setstate tobit. theControls value of PSTATE.E on taking an exception to the currentload mode, and copiedstore toendianness PSTATE.Efor ondata executing an exception return operation in the current mode.accesses:
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Instruction fetches ignore this bit.
If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.
If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.
Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.
When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.
If the implementation does not support big-endian operation, SPSR.E is RES0. If the implementation does not support little-endian operation, SPSR.E is RES1. On executing an exception return operation in the current mode, if the implementation does not support big-endian operation at the Exception level being returned to, SPSR.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, SPSR.E is RES1.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SError interrupt mask.mask Set to the value of PSTATE.A on taking an exception to the current mode, and copied to PSTATE.A on executing an exception return operation in the current mode.bit.
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On a Warm reset, this field resets to an architecturally UNKNOWN value.
IRQ interruptmask mask. Set to the value of PSTATE.I on taking an exception to the current mode, and copied to PSTATE.I on executing an exception return operation in the current mode.bit.
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On a Warm reset, this field resets to an architecturally UNKNOWN value.
FIQ interruptmask mask. Set to the value of PSTATE.F on taking an exception to the current mode, and copied to PSTATE.F on executing an exception return operation in the current mode.bit.
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On a Warm reset, this field resets to an architecturally UNKNOWN value.
T32 Instruction set state.state Setbit. toDetermines the valueAArch32 ofinstruction PSTATE.Tset onstate takingthat an exception to the current mode, and copied to PSTATE.T on executing an exception returnwas operationtaken in the current mode.from.
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On a Warm reset, this field resets to an architecturally UNKNOWN value.
Mode. Set to the value of PSTATE.M[4:0] on taking an exception to the current mode, andthat copied to PSTATE.M[4:0] on executing an exception returnwas operationtaken in the current mode.from.
M[4:0] | Meaning |
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0b10000 | User. |
0b10001 | FIQ. |
0b10010 | IRQ. |
0b10011 | Supervisor. |
0b10110 | Monitor. |
0b10111 | Abort. |
0b11010 | Hyp. |
0b11011 | Undefined. |
0b11111 | System. |
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Other values are reserved. If SPSR.M[4:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in the current mode is an illegal return event, as described in 'Illegal return events from AArch32 state'.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SPSR can be read using the MRS instruction and written using the MSR (register) or MSR (immediate) instructions.
3001/0907/2020 15:0757; ccead0cb9f089f9ceec50268e82aec9e7104721180324f0b9997bede489cc15ad1565345720bcd2a
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