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FCVTZS (vector, integer)

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision

Scalar half precision
(Armv8.2)

Scalar half precision
(Armv8.2)

313029282726252423222120191817161514131211109876543210
0101111011111001101110RnRd
Uo2o1

FCVTZS <Hd>, <Hn>

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Scalar single-precision and double-precision

313029282726252423222120191817161514131211109876543210
010111101sz100001101110RnRd
Uo2o1

FCVTZS <V><d>, <V><n>

integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector half precision
(Armv8.2)

Vector half precision
(Armv8.2)

313029282726252423222120191817161514131211109876543210
0Q00111011111001101110RnRd
Uo2o1

FCVTZS <Vd>.<T>, <Vn>.<T>

if !HaveFP16Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Vector single-precision and double-precision

313029282726252423222120191817161514131211109876543210
0Q0011101sz100001101110RnRd
Uo2o1

FCVTZS <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; FPRounding rounding = FPDecodeRounding(o1:o2); boolean unsigned = (U == '1');

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is a width specifier, encoded in sz:

sz<V>
0S
1D
<V> Is a width specifier, encoded in sz:
sz<V>
0S
1D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

For the half-precision variant: is an arrangement specifier, encoded in Q:

Q<T>
04H
18H
<T> For the half-precision variant: is an arrangement specifier, encoded in Q:
Q<T>
04H
18H

For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:

szQ<T>
002S
014S
10RESERVED
112D
For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:
szQ<T>
002S
014S
10RESERVED
112D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) element; for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding); V[d] = result;

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(esize) element; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPToFixed(element, 0, unsigned, fpcr, rounding); V[d] = result;


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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