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PMULL, PMULL2

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

For information about multiplying polynomials see Polynomial arithmetic over {0, 1}.

The PMULL instruction extracts each source vector from the lower half of each source register, while the PMULL2 instruction extracts each source vector from the upper half of each source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001110size1Rm111000RnRd

PMULL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '01' || size == '10' then UNDEFINED; if size == '11' && !HaveBit128PMULLExt() then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize;

Assembler Symbols

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q2
0[absent]
1[present]
2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:
Q2
0[absent]
1[present]
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in size:

size<Ta>
008H
01RESERVED
10RESERVED
111Q
The '1Q' arrangement is only allocated in an implementation that includes the Cryptographic Extension, and is otherwise RESERVED.
<Ta> Is an arrangement specifier, encoded in size:
size<Ta>
008H
01RESERVED
10RESERVED
111Q
The '1Q' arrangement is only allocated in an implementation that includes the Cryptographic Extension, and is otherwise RESERVED.
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in size:Q:

sizeQ<Tb>
0008B
00116B
01xRESERVED
10xRESERVED
1101D
1112D
<Tb> Is an arrangement specifier, encoded in size:Q:
sizeQ<Tb>
0008B
00116B
01xRESERVED
10xRESERVED
1101D
1112D
<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(datasize) operand2 = Vpart[m, part]; bits(2*datasize) result; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; Elem[result, e, 2*esize] = PolynomialMult(element1, element2); V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

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