DECB, DECD, DECH, DECW (scalar)

Decrement scalar by multiple of predicate constraint element count

.

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the scalar destination.

The named predicate constraint limits the number of active elements in a single predicate to:

* A fixed number (VL1 to VL256)

* The largest power of two (POW2)

* The largest multiple of three or four (MUL3 or MUL4)

* All available, implicitly a multiple of two (ALL).

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

It has encodings from 4 classes: Byte , Doubleword , Halfword and Word

Byte

313029282726252423222120191817161514131211109876543210
000001000011imm4111001patternRdn
size<1>size<0>D

DECB <Xdn>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() then UNDEFINED; integer esize = 8; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Doubleword

313029282726252423222120191817161514131211109876543210
000001001111imm4111001patternRdn
size<1>size<0>D

DECD <Xdn>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() then UNDEFINED; integer esize = 64; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Halfword

313029282726252423222120191817161514131211109876543210
000001000111imm4111001patternRdn
size<1>size<0>D

DECH <Xdn>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() then UNDEFINED; integer esize = 16; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Word

313029282726252423222120191817161514131211109876543210
000001001011imm4111001patternRdn
size<1>size<0>D

DECW <Xdn>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() then UNDEFINED; integer esize = 32; integer dn = UInt(Rdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Assembler Symbols

<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<pattern>

Is the optional pattern specifier, defaulting to ALL, encoded in pattern:

pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL
<imm>

Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); integer count = DecodePredCount(pat, esize); bits(64) operand1 = X[dn]; X[dn] = operand1 - (count * imm);


Internal version only: isa v32.12, AdvSIMD v29.04, pseudocode v2020-09_xml, sve v2020-09_rc3 ; Build timestamp: 2020-11-18T17:23

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