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ST1B (scalar plus immediate)

.

Contiguous store of bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.

Contiguous store bytes from vector (immediate index).

Contiguous store of bytes from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.

313029282726252423222120191817161514131211109876543210
111001000size0imm4111PgRnZt
msz<1>msz<0>

ST1B { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 8 << UInt(size); integer msize = 8; integer offset = SInt(imm4);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D
<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; bits(VL) src = Z[t]; constant integer mbytes = msize DIV 8; if n == 31 then if LastActiveElement(mask, esize) >= 0 || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); if HaveMTEExt() then SetTagCheckedInstruction(FALSE); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; addr = base + offset * elements * mbytes; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>; addr = addr + mbytes;

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; bits(VL) src; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(n != 31); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; src = Z[t]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer eoff = (offset * elements) + e; bits(64) addr = base + eoff * mbytes; Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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