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PRFH (scalar plus scalar)

Contiguous prefetch halfwords (scalar index)).

Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 2 and added to the base address. After each element prefetch the index value is incremented, but the index register is not updated.

The predicate may be used to suppress prefetches from unwanted addresses.

.

Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 2 and added to the base address. After each element prefetch the index value is incremented, but the index register is not updated.

The predicate may be used to suppress prefetches from unwanted addresses.

313029282726252423222120191817161514131211109876543210
10000100100Rm110PgRn0prfop
msz<1>msz<0>

PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]

if !HaveSVE() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer esize = 16; integer g = UInt(Pg); integer n = UInt(Rn); integer m = UInt(Rm); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 1;

Assembler Symbols

<prfop>

Is the prefetch operation specifier, encoded in prfop:

prfop<prfop>
0000PLDL1KEEP
0001PLDL1STRM
0010PLDL2KEEP
0011PLDL2STRM
0100PLDL3KEEP
0101PLDL3STRM
x11x#uimm4
1000PSTL1KEEP
1001PSTL1STRM
1010PSTL2KEEP
1011PSTL2STRM
1100PSTL3KEEP
1101PSTL3STRM
<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop<prfop>
0000PLDL1KEEP
0001PLDL1STRM
0010PLDL2KEEP
0011PLDL2STRM
0100PLDL3KEEP
0101PLDL3STRM
x11x#uimm4
1000PSTL1KEEP
1001PSTL1STRM
1010PSTL2KEEP
1011PSTL2STRM
1100PSTL3KEEP
1101PSTL3STRM
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(64) base; bits(64) offset = X[m]; bits(64) addr; if n == 31 then base = SP[]; else base = X[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then addr = base + (UInt(offset) << scale); Hint_Prefetch(addr, pref_hint, level, stream); offset = offset + 1;


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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