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INS (element)

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.

Insert vector element from another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (element).

313029282726252423222120191817161514131211109876543210
01101110000imm50imm41RnRd

INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; integer dst_index = UInt(imm5<4:size+1>); integer src_index = UInt(imm4<3:size>); integer idxdsize = if imm4<3> == '1' then 128 else 64; // imm4<size-1:0> is IGNORED integer esize = 8 << size;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts> Is an element size specifier, encoded in imm5:
imm5<Ts>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<Ts>

Is an element size specifier, encoded in imm5:

imm5<Ts>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<index1> Is the destination element index encoded in imm5:
imm5<index1>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>
<index1>

Is the destination element index encoded in imm5:

imm5<index1>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index2> Is the source element index encoded in imm5:imm4:
imm5<index2>
x0000RESERVED
xxxx1imm4<3:0>
xxx10imm4<3:1>
xx100imm4<3:2>
x1000imm4<3>
Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.
<index2>

Is the source element index encoded in imm5:imm4:

imm5<index2>
x0000RESERVED
xxxx1imm4<3:0>
xxx10imm4<3:1>
xx100imm4<3:2>
x1000imm4<3>
Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.

Operation

CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n]; bits(128) result; result = V[d]; Elem[result, dst_index, esize] = Elem[operand, src_index, esize]; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

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