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Widening multiply unsigned integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
Unsigned multiply returning high half (predicated).
Widening multiply unsigned integer values in active elements of the first source vector by corresponding elements of the second source vector and destructively place the high half of the result in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | Pg | Zm | Zdn | |||||||||||
H | U |
if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Zdn); integer m = UInt(Zm); boolean unsigned = TRUE;
<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
size:
| ||||||||||
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<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) result;
for e = 0 to elements-1
integer element1 = Int(Elem[operand1, e, esize], unsigned);
integer element2 = Int(Elem[operand2, e, esize], unsigned);
if ElemP[mask, e, esize] == '1' then
integer product = (element1 * element2) >> esize;
Elem[result, e, esize] = product<esize-1:0>;
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn] = result;
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = Z[dn]; bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m] else Zeros(); bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, e, esize], unsigned); integer element2 = Int(Elem[operand2, e, esize], unsigned); if ElemP[mask, e, esize] == '1' then integer product = (element1 * element2) >> esize; Elem[result, e, esize] = product<esize-1:0>; else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
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