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SQRDMLAH (by element)

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_RDM)

Scalar
(Armv8.1)

313029282726252423222120191817161514131211109876543210
01111111sizeLMRm1101H0RnRd
S

SQRDMLAH <V><d>, <V><n>, <Vm>.<Ts>[<index>]

if !HaveQRDMLAHExt() then UNDEFINED; integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean rounding = TRUE; boolean sub_op = (S == '1');

Vector
(FEAT_RDM)

Vector
(Armv8.1)

313029282726252423222120191817161514131211109876543210
0Q101111sizeLMRm1101H0RnRd
S

SQRDMLAH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]

if !HaveQRDMLAHExt() then UNDEFINED; integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean rounding = TRUE; boolean sub_op = (S == '1');

Assembler Symbols

<V> Is a width specifier, encoded in size:
size<V>
00RESERVED
01H
10S
11RESERVED
<V>

Is a width specifier, encoded in size:

size<V>
00RESERVED
01H
10S
11RESERVED
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
<T>

Is an arrangement specifier, encoded in size:Q:

sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> Is the name of the second SIMD&FP source register, encoded in size:M:Rm:
size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Vm>

Is the name of the second SIMD&FP source register, encoded in size:M:Rm:

size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Ts> Is an element size specifier, encoded in size:
size<Ts>
00RESERVED
01H
10S
11RESERVED
<Ts>

Is an element size specifier, encoded in size:

size<Ts>
00RESERVED
01H
10S
11RESERVED
<index> Is the element index, encoded in size:L:H:M:
size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED
<index>

Is the element index, encoded in size:L:H:M:

size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; integer rounding_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer element3; integer product; boolean sat; element2 = SInt(Elem[operand2, index, esize]); for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element3 = SInt(Elem[operand3, e, esize]); if sub_op then accum = ((element3 << esize) - 2 * (element1 * element2) + rounding_const); else accum = ((element3 << esize) + 2 * (element1 * element2) + rounding_const); (Elem[result, e, esize], sat) = SignedSatQ(accum >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

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