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DUPM

.

Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. This instruction is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.

Broadcast logical bitmask immediate to vector (unpredicated).

Unconditionally broadcast the logical bitmask immediate into each element of the destination vector. This instruction is unpredicated. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits.

This instruction is used by the alias MOV (bitmask immediate).

313029282726252423222120191817161514131211109876543210
00000101110000imm13Zd

DUPM <Zd>.<T>, #<const>

if !HaveSVE() then UNDEFINED; integer esize = 64; integer d = UInt(Zd); bits(esize) imm; (imm, -) = DecodeBitMasks(imm13<12>, imm13<5:0>, imm13<11:6>, TRUE);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in imm13<12>:imm13<5:0>:
imm13<12>imm13<5:0><T>
00xxxxxS
010xxxxH
0110xxxB
01110xxB
011110xB
0111110RESERVED
0111111RESERVED
1xxxxxxD
<T>

Is the size specifier, encoded in imm13<12>:imm13<5:0>:

imm13<12>imm13<5:0><T>
00xxxxxS
010xxxxH
0110xxxB
01110xxB
011110xB
0111110RESERVED
0111111RESERVED
1xxxxxxD
<const>

Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.

Alias Conditions

AliasIs preferred when
MOV (bitmask immediate)SVEMoveMaskPreferred(imm13)

Operation

CheckSVEEnabled(); bits(VL) result = Replicate(imm); Z[d] = result;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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