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UQSUB

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
01111110size1Rm001011RnRd
U

UQSUB <V><d>, <V><n>, <V><m>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean unsigned = (U == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q101110size1Rm001011RnRd
U

UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size:Q == '110' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean unsigned = (U == '1');

Assembler Symbols

<V> Is a width specifier, encoded in size:
size<V>
00B
01H
10S
11D
<V>

Is a width specifier, encoded in size:

size<V>
00B
01H
10S
11D
<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<m>

Is the number of the second SIMD&FP source register, encoded in the "Rm" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
0008B
00116B
0104H
0118H
1002S
1014S
110RESERVED
1112D
<T>

Is an arrangement specifier, encoded in size:Q:

sizeQ<T>
0008B
00116B
0104H
0118H
1002S
1014S
110RESERVED
1112D
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; integer diff; boolean sat; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); diff = element1 - element2; (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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