(old) htmldiff from-(new)

URSHR

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
011111110!= 0000immb001001RnRd
Uimmho1o0

URSHR <V><d>, <V><n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; integer esize = 8 << 3; integer datasize = esize; integer elements = 1; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q1011110!= 0000immb001001RnRd
Uimmho1o0

URSHR <Vd>.<T>, <Vn>.<T>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; integer esize = 8 << HighestSetBit(immh); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');

Assembler Symbols

<V>

Is a width specifier, encoded in immh:

immh<V>
0xxxRESERVED
1xxxD
<V> Is a width specifier, encoded in immh:
immh<V>
0xxxRESERVED
1xxxD
<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in immh:Q:

immhQ<T>
0000xSEE Advanced SIMD modified immediate
000108B
0001116B
001x04H
001x18H
01xx02S
01xx14S
1xxx0RESERVED
1xxx12D
<T> Is an arrangement specifier, encoded in immh:Q:
immhQ<T>
0000xSEE Advanced SIMD modified immediate
000108B
0001116B
001x04H
001x18H
01xx02S
01xx14S
1xxx0RESERVED
1xxx12D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in immh:immb:

immh<shift>
0xxxRESERVED
1xxx(128-UInt(immh:immb))
<shift> For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in immh:immb:
immh<shift>
0xxxRESERVED
1xxx(128-UInt(immh:immb))

For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded in immh:immb:

immh<shift>
0000SEE Advanced SIMD modified immediate
0001(16-UInt(immh:immb))
001x(32-UInt(immh:immb))
01xx(64-UInt(immh:immb))
1xxx(128-UInt(immh:immb))
For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded in immh:immb:
immh<shift>
0000SEE Advanced SIMD modified immediate
0001(16-UInt(immh:immb))
001x(32-UInt(immh:immb))
01xx(64-UInt(immh:immb))
1xxx(128-UInt(immh:immb))

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) operand2; bits(datasize) result; integer round_const = if round then (1 << (shift - 1)) else 0; integer element; operand2 = if accumulate then V[d] else Zeros(); for e = 0 to elements-1 element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift; Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>; V[d] = result;


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)