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UADDLP

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q101110size100000001010RnRd
Uop

UADDLP <Vd>.<Ta>, <Vn>.<Tb>

integer d = UInt(Rd); integer n = UInt(Rn); if size == '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV (2*esize); boolean acc = (op == '1'); boolean unsigned = (U == '1');

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta> Is an arrangement specifier, encoded in size:Q:
sizeQ<Ta>
0004H
0018H
0102S
0114S
1001D
1012D
11xRESERVED
<Ta>

Is an arrangement specifier, encoded in size:Q:

sizeQ<Ta>
0004H
0018H
0102S
0114S
1001D
1012D
11xRESERVED
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Tb> Is an arrangement specifier, encoded in size:Q:
sizeQ<Tb>
0008B
00116B
0104H
0118H
1002S
1014S
11xRESERVED
<Tb>

Is an arrangement specifier, encoded in size:Q:

sizeQ<Tb>
0008B
00116B
0104H
0118H
1002S
1014S
11xRESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(2*esize) sum; integer op1; integer op2; if acc then result = V[d]; for e = 0 to elements-1 op1 = Int(Elem[operand, 2*e+0, esize], unsigned); op2 = Int(Elem[operand, 2*e+1, esize], unsigned); sum = (op1 + op2)<2*esize-1:0>; if acc then Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum; else Elem[result, e, 2*esize] = sum; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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