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MOV (scalar)

Move vector element to scalar. This instruction duplicates the specified vector element in the SIMD&FP source register into a scalar, and writes the result to the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Move vector element to scalar. This instruction duplicates the specified vector element in the SIMD&FP source register into a scalar, and writes the result to the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This is an alias of DUP (element). This means:

313029282726252423222120191817161514131211109876543210
01011110000imm5000001RnRd

MOV <V><d>, <Vn>.<T>[<index>]

is equivalent to

DUP <V><d>, <Vn>.<T>[<index>]

and is always the preferred disassembly.

Assembler Symbols

<V>

Is the destination width specifier, encoded in imm5:

imm5<V>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<V> Is the destination width specifier, encoded in imm5:
imm5<V>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T>

Is the element width specifier, encoded in imm5:

imm5<T>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<T> Is the element width specifier, encoded in imm5:
imm5<T>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<index>

Is the element index encoded in imm5:

imm5<index>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>
<index> Is the element index encoded in imm5:
imm5<index>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>

Operation

The description of DUP (element) gives the operational pseudocode for this instruction.

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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