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UQDECD (vector)

.

Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The results are saturated to the 64-bit unsigned integer range.

The named predicate constraint limits the number of active elements in a single predicate to:

* A fixed number (VL1 to VL256)

* The largest power of two (POW2)

* The largest multiple of three or four (MUL3 or MUL4)

* All available, implicitly a multiple of two (ALL).

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

Unsigned saturating decrement vector by multiple of 64-bit predicate constraint element count.

Determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements. The results are saturated to the 64-bit unsigned integer range.

The named predicate constraint limits the number of active elements in a single predicate to:

* A fixed number (VL1 to VL256)

* The largest power of two (POW2)

* The largest multiple of three or four (MUL3 or MUL4)

* All available, implicitly a multiple of two (ALL).

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

313029282726252423222120191817161514131211109876543210
000001001110imm4110011patternZdn
size<1>size<0>DU

UQDECD <Zdn>.D{, <pattern>{, MUL #<imm>}}

if !HaveSVE() then UNDEFINED; integer esize = 64; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1; boolean unsigned = TRUE;

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<pattern> Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern<pattern>
00000POW2
00001VL1
00010VL2
00011VL3
00100VL4
00101VL5
00110VL6
00111VL7
01000VL8
01001VL16
01010VL32
01011VL64
01100VL128
01101VL256
0111x#uimm5
101x1#uimm5
10110#uimm5
1x0x1#uimm5
1x010#uimm5
1xx00#uimm5
11101MUL4
11110MUL3
11111ALL
<pattern>

Is the optional pattern specifier, defaulting to ALL, encoded in pattern:

pattern<pattern>
00000POW2
00001VL1
00010VL2
00011VL3
00100VL4
00101VL5
00110VL6
00111VL7
01000VL8
01001VL16
01010VL32
01011VL64
01100VL128
01101VL256
0111x#uimm5
101x1#uimm5
10110#uimm5
1x0x1#uimm5
1x010#uimm5
1xx00#uimm5
11101MUL4
11110MUL3
11111ALL
<imm>

Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; integer count = DecodePredCount(pat, esize); bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, e, esize], unsigned); (Elem[result, e, esize], -) = SatQ(element1 - (count * imm), esize, unsigned); Z[dn] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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