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MUL (by element)

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Multiply (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001111sizeLMRm1000H0RnRd

MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]

integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
<T>

Is an arrangement specifier, encoded in size:Q:

sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> Is the name of the second SIMD&FP source register, encoded in size:M:Rm:
size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Vm>

Is the name of the second SIMD&FP source register, encoded in size:M:Rm:

size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Ts> Is an element size specifier, encoded in size:
size<Ts>
00RESERVED
01H
10S
11RESERVED
<Ts>

Is an element size specifier, encoded in size:

size<Ts>
00RESERVED
01H
10S
11RESERVED
<index> Is the element index, encoded in size:L:H:M:
size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED
<index>

Is the element index, encoded in size:L:H:M:

size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; integer element1; integer element2; bits(esize) product; element2 = UInt(Elem[operand2, index, esize]); for e = 0 to elements-1 element1 = UInt(Elem[operand1, e, esize]); product = (element1 * element2)<esize-1:0>; Elem[result, e, esize] = product; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

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