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FMINNM (immediate)

Floating-point minimum number with immediate (predicated)).

Determine the minimum number value of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate may take the value +0.0 or +1.0 only. If the element value is NaN then the result is the immediate. Inactive elements in the destination vector register remain unmodified.

.

Determine the minimum number value of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate may take the value +0.0 or +1.0 only. If the element value is NaN then the result is the immediate. Inactive elements in the destination vector register remain unmodified.

313029282726252423222120191817161514131211109876543210
01100101size011101100Pg0000i1Zdn

FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>

if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Zdn); bits(esize) imm = if i1 == '0' then Zeros() else FPOne('0');

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size<T>
00RESERVED
01H
10S
11D
<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<const>

Is the floating-point immediate value, encoded in i1:

i1<const>
0#0.0
1#1.0
<const> Is the floating-point immediate value, encoded in i1:
i1<const>
0#0.0
1#1.0

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = FPMinNum(element1, imm, FPCR); else Elem[result, e, esize] = element1; Z[dn] = result;

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = FPMinNum(element1, imm, FPCR[]); else Elem[result, e, esize] = element1; Z[dn] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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