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Load SIMD&FP Register (unscaled offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Load SIMD&FP Register (unscaled offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
size | 1 | 1 | 1 | 1 | 0 | 0 | x | 1 | 0 | imm9 | 0 | 0 | Rn | Rt | |||||||||||||||||
opc |
boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);
<Bt> | Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Dt> | Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Ht> | Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Qt> | Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<St> | Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<simm> | Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field. |
integer n = UInt(Rn); integer t = UInt(Rt); AccType acctype = AccType_VEC; MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; integer datasize = 8 << scale; boolean tag_checked = memop != MemOp_PREFETCH && (wback || n != 31);
if HaveMTE2ExtHaveMTEExt() then
SetTagCheckedInstruction(tag_checked);
CheckFPAdvSIMDEnabled64();
bits(64) address;
bits(datasize) data;
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
if ! postindex then
address = address + offset;
case memop of
when MemOp_STORE
data = V[t];
Mem[address, datasize DIV 8, acctype] = data;
when MemOp_LOAD
data = Mem[address, datasize DIV 8, acctype];
V[t] = data;
if wback then
if postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X[n] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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