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SYSL

System instruction with result. For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.

System instruction with result. For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.

313029282726252423222120191817161514131211109876543210
1101010100101op1CRnCRmop2Rt
L

SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>

AArch64.CheckSystemAccess('01', op1, CRn, CRm, op2, Rt, L); integer t = UInt(Rt); integer sys_op0 = 1; integer sys_op1 = UInt(op1); integer sys_op2 = UInt(op2); integer sys_crn = UInt(CRn); integer sys_crm = UInt(CRm); boolean has_result = (L == '1');

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field.

<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cn>

Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.

<Cm>

Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

Operation

if has_result then // No architecturally defined instructions here. X[t] = AArch64.SysInstrWithResult(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); else AArch64.SysInstr(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]);


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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