UZP1, UZP2 (vectors)

Concatenate even or odd elements from two vectors

.

Concatenate adjacent even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated.

It has encodings from 2 classes: Even and Odd

Even

313029282726252423222120191817161514131211109876543210
00000101size1Zm011010ZnZd
H

UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer part = 0;

Odd

313029282726252423222120191817161514131211109876543210
00000101size1Zm011011ZnZd
H

UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer part = 1;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; bits(VL*2) zipped = operand2:operand1; for e = 0 to elements-1 Elem[result, e, esize] = Elem[zipped, 2*e+part, esize]; Z[d] = result;


Internal version only: isa v32.12, AdvSIMD v29.04, pseudocode v2020-09_xml, sve v2020-09_rc3 ; Build timestamp: 2020-11-18T17:23

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