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Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements.
The named predicate constraint limits the number of active elements in a single predicate to:
* A fixed number (VL1 to VL256)
* The largest power of two (POW2)
* The largest multiple of three or four (MUL3 or MUL4)
* All available, implicitly a multiple of two (ALL).
Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
Decrement vector by multiple of predicate constraint element count.
Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements.
The named predicate constraint limits the number of active elements in a single predicate to:
* A fixed number (VL1 to VL256)
* The largest power of two (POW2)
* The largest multiple of three or four (MUL3 or MUL4)
* All available, implicitly a multiple of two (ALL).
Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.
It has encodings from 3 classes: Doubleword , Halfword and Word
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn | |||||||||||
size<1> | size<0> | D |
if !HaveSVE() then UNDEFINED; integer esize = 64; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn | |||||||||||
size<1> | size<0> | D |
if !HaveSVE() then UNDEFINED; integer esize = 16; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn | |||||||||||
size<1> | size<0> | D |
if !HaveSVE() then UNDEFINED; integer esize = 32; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;
<Zdn> | Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
<imm> | Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; integer count = DecodePredCount(pat, esize); bits(VL) operand1 = Z[dn]; bits(VL) result; for e = 0 to elements-1 Elem[result, e, esize] = Elem[operand1, e, esize] - (count * imm); Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
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