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BIC (vector, immediate)

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q10111100000abcxxx101defghRd
opcmode

16-bit (cmode == 10x1)

BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}

32-bit (cmode == 0xx1)

BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}

integer rd = UInt(Rd); integer datasize = if Q == '1' then 128 else 64; bits(datasize) imm; bits(64) imm64; ImmediateOp operation; case cmode:op of when '0xx00' operation = ImmediateOp_MOVI; when '0xx01' operation = ImmediateOp_MVNI; when '0xx10' operation = ImmediateOp_ORR; when '0xx11' operation = ImmediateOp_BIC; when '10x00' operation = ImmediateOp_MOVI; when '10x01' operation = ImmediateOp_MVNI; when '10x10' operation = ImmediateOp_ORR; when '10x11' operation = ImmediateOp_BIC; when '110x0' operation = ImmediateOp_MOVI; when '110x1' operation = ImmediateOp_MVNI; when '1110x' operation = ImmediateOp_MOVI; when '11110' operation = ImmediateOp_MOVI; when '11111' // FMOV Dn,#imm is in main FP instruction set if Q == '0' then UNDEFINED; operation = ImmediateOp_MOVI; imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h); imm = Replicate(imm64, datasize DIV 64);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP register, encoded in the "Rd" field.

<T> For the 16-bit variant: is an arrangement specifier, encoded in Q:
Q<T>
04H
18H
<T>

For the 16-bit variant: is an arrangement specifier, encoded in Q:

Q<T>
04H
18H
For the 32-bit variant: is an arrangement specifier, encoded in Q:
Q<T>
02S
14S

For the 32-bit variant: is an arrangement specifier, encoded in Q:

Q<T>
02S
14S
<imm8>

Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".

<amount> For the 16-bit variant: is the shift amount encoded in cmode<1>:
cmode<1><amount>
00
18
defaulting to 0 if LSL is omitted.
<amount>

For the 16-bit variant: is the shift amount encoded in cmode<1>:

cmode<1><amount>
00
18
defaulting to 0 if LSL is omitted.
For the 32-bit variant: is the shift amount encoded in cmode<2:1>:
cmode<2:1><amount>
000
018
1016
1124
defaulting to 0 if LSL is omitted.

For the 32-bit variant: is the shift amount encoded in cmode<2:1>:

cmode<2:1><amount>
000
018
1016
1124
defaulting to 0 if LSL is omitted.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand; bits(datasize) result; case operation of when ImmediateOp_MOVI result = imm; when ImmediateOp_MVNI result = NOT(imm); when ImmediateOp_ORR operand = V[rd]; result = operand OR imm; when ImmediateOp_BIC operand = V[rd]; result = operand AND NOT(imm); V[rd] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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