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FACLT

.

Compare active absolute values of floating-point elements in the first source vector being less than corresponding absolute values of elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

Floating-point absolute compare less than.

Compare active absolute values of floating-point elements in the first source vector being less than corresponding absolute values of elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.

This is a pseudo-instruction of FAC<cc>. This means:

313029282726252423222120191817161514131211109876543210
01100101size0Zm111PgZn1Pd

FACLT <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>

is equivalent to

FACGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D
<T>

Is the size specifier, encoded in size:

size<T>
00RESERVED
01H
10S
11D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

Operation

The description of FAC<cc> gives the operational pseudocode for this instruction.


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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