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UADDV

Unsigned add reduction to scalarscalar.

Unsigned add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first zero-extended to 64 bits. Inactive elements in the source vector are treated as zero.

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Unsigned add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first zero-extended to 64 bits. Inactive elements in the source vector are treated as zero.

313029282726252423222120191817161514131211109876543210
00000100size000001001PgZnVd
U

UADDV <Dd>, <Pg>, <Zn>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Vd);

Assembler Symbols

<Dd>

Is the 64-bit name of the destination SIMD&FP register, encoded in the "Vd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D
<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; integer sum = 0; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer element = UInt(Elem[operand, e, esize]); sum = sum + element; V[d] = sum<63:0>;


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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