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Gather load of unsigned halfwords to active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
Gather load unsigned halfwords to vector (immediate index).
Gather load of unsigned halfwords to active elements of a vector register from memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
It has encodings from 2 classes: 32-bit element and 64-bit element
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt | ||||||||||||||
msz<1> | msz<0> | U | ff |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer g = UInt(Pg); integer esize = 32; integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm5);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt | ||||||||||||||
msz<1> | msz<0> | U | ff |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer g = UInt(Pg); integer esize = 64; integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm5);
<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the base scalable vector register, encoded in the "Zn" field. |
<imm> | Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) base = Z[n];
bits(64) addr;
bits(PL) mask = P[g];
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
if HaveMTEExt() then SetTagCheckedInstruction(TRUE);
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
addr = ZeroExtend(Elem[base, e, esize], 64) + offset * mbytes;
data = Mem[addr, mbytes, AccType_NORMAL];
Elem[result, e, esize] = Extend(data, esize, unsigned);
else
Elem[result, e, esize] = Zeros();
Z[t] = result;
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) base; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if AnyActiveElement(mask, esize) then base = Z[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then bits(64) addr = ZeroExtend(Elem[base, e, esize], 64) + offset * mbytes; data = Mem[addr, mbytes, AccType_NORMAL]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(); Z[t] = result;
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
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