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PRFW (vector plus immediate)

Gather prefetch words (vector plus immediate)).

Gather prefetch of words from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive addresses are not prefetched from memory.

The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).

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Gather prefetch of words from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 4 in the range 0 to 124. Inactive addresses are not prefetched from memory.

The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).

It has encodings from 2 classes: 32-bit element and 64-bit element

32-bit element

313029282726252423222120191817161514131211109876543210
10000101000imm5111PgZn0prfop
msz<1>msz<0>

PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer esize = 32; integer g = UInt(Pg); integer n = UInt(Zn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 2; integer offset = UInt(imm5);

64-bit element

313029282726252423222120191817161514131211109876543210
11000101000imm5111PgZn0prfop
msz<1>msz<0>

PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}]

if !HaveSVE() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 2; integer offset = UInt(imm5);

Assembler Symbols

<prfop>

Is the prefetch operation specifier, encoded in prfop:

prfop<prfop>
0000PLDL1KEEP
0001PLDL1STRM
0010PLDL2KEEP
0011PLDL2STRM
0100PLDL3KEEP
0101PLDL3STRM
x11x#uimm4
1000PSTL1KEEP
1001PSTL1STRM
1010PSTL2KEEP
1011PSTL2STRM
1100PSTL3KEEP
1101PSTL3STRM
<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop<prfop>
0000PLDL1KEEP
0001PLDL1STRM
0010PLDL2KEEP
0011PLDL2STRM
0100PLDL3KEEP
0101PLDL3STRM
x11x#uimm4
1000PSTL1KEEP
1001PSTL1STRM
1010PSTL2KEEP
1011PSTL2STRM
1100PSTL3KEEP
1101PSTL3STRM
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<imm>

Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) base; bits(64) addr; base = Z[n]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then addr = ZeroExtend(Elem[base, e, esize], 64) + (offset << scale); Hint_Prefetch(addr, pref_hint, level, stream);


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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