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Bitwise NOT writes the bitwise inverse of a register value to the destination register.
This is an alias of ORN (shifted register). This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 1 | 0 | 1 | 0 | 1 | 0 | shift | 1 | Rm | imm6 | 1 | 1 | 1 | 1 | 1 | Rd | ||||||||||||||
opc | N | Rn |
MVN <Wd>, <Wm>{, <shift> #<amount>}
is equivalent to
ORN <Wd>, WZR, <Wm>{, <shift> #<amount>}
and is always the preferred disassembly.
MVN <Xd>, <Xm>{, <shift> #<amount>}
is equivalent to
ORN <Xd>, XZR, <Xm>{, <shift> #<amount>}
and is always the preferred disassembly.
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wm> | Is the 32-bit name of the general-purpose source register, encoded in the "Rm" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xm> | Is the 64-bit name of the general-purpose source register, encoded in the "Rm" field. |
<amount> | For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field. |
For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field, |
The description of ORN (shifted register) gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0
; Build timestamp: 2020-11-18T172020-07-03T12:2342
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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