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INSR (scalar)

Insert general-purpose register in shifted vectorvector.

Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

.

Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size100100001110RmZdn

INSR <Zdn>.<T>, <R><m>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer dn = UInt(Zdn); integer m = UInt(Rm);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D
<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D
<R>

Is a width specifier, encoded in size:

size<R>
01W
x0W
11X
<R> Is a width specifier, encoded in size:
size<R>
01W
x0W
11X
<m>

Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

Operation

CheckSVEEnabled(); bits(VL) dest = Z[dn]; bits(esize) src = X[m]; Z[dn] = dest<VL-esize-1:0> : src;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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