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Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | |||||||||||||
U | immh |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '000x' || (immh == '001x' && !HaveFP16Ext()) then UNDEFINED;
integer esize = if immh == '1xxx' then 64 else if immh == '01xx' then 32 else 16;
integer datasize = esize;
integer elements = 1;
integer fracbits = (esize * 2) - UInt(immh:immb);
boolean unsigned = (U == '1');
FPRounding rounding = FPRoundingMode(FPCR[]);(FPCR);
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | |||||||||||||
U | immh |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '0000' then SEE(asimdimm);
if immh == '000x' || (immh == '001x' && !HaveFP16Ext()) then UNDEFINED;
if immh<3>:Q == '10' then UNDEFINED;
integer esize = if immh == '1xxx' then 64 else if immh == '01xx' then 32 else 16;
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
integer fracbits = (esize * 2) - UInt(immh:immb);
boolean unsigned = (U == '1');
FPRounding rounding = FPRoundingMode(FPCR[]);(FPCR);
<V> | Is a width specifier,
encoded in
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<d> | Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> | Is an arrangement specifier,
encoded in
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<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<fbits> | For the scalar variant: is the number of fractional bits, in the range 1 to the operand width,
encoded in
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For the vector variant: is the number of fractional bits, in the range 1 to the element width,
encoded in
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CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
bits(esize) element;
for e = 0 to elements-1
element = Elem[operand, e, esize];
Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, FPCR, rounding);
V[d] = result;
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(esize) element; FPCRType fpcr = FPCR[]; boolean merge = elements == 1 && IsMerging(fpcr); bits(128) result = if merge then V[d] else Zeros(); for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, fpcr, rounding); V[d] = result;
Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0
; Build timestamp: 2020-11-18T172020-07-03T12:2342
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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