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Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Unsigned Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
The UMLSL instruction extracts vector elements from the lower half of the first source register, while the UMLSL2 instruction extracts vector elements from the upper half of the first source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 0 | 1 | 1 | 0 | H | 0 | Rn | Rd | ||||||||||||
U | o2 |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean unsigned = (U == '1'); boolean sub_op = (o2 == '1');
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Ta> |
Is an arrangement specifier,
encoded in
size:
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<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Tb> |
Is an arrangement specifier,
encoded in
size:Q:
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<Vm> |
Is the name of the second SIMD&FP source register,
encoded in
size:M:Rm:
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<Ts> |
Is an element size specifier,
encoded in
size:
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<index> |
Is the element index,
encoded in
size:L:H:M:
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CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part]; bits(idxdsize) operand2 = V[m]; bits(2*datasize) operand3 = V[d]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; element2 = Int(Elem[operand2, index, esize], unsigned); for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); product = (element1 * element2)<2*esize-1:0>; if sub_op then Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] - product; else Elem[result, e, 2*esize] = Elem[operand3, e, 2*esize] + product; V[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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