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Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
Contiguous store words from vector (immediate index).
Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | size | 0 | imm4 | 1 | 1 | 1 | Pg | Rn | Zt | ||||||||||||||
msz<1> | msz<0> |
if !HaveSVE() then UNDEFINED; if size != '1x' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 8 << UInt(size); integer msize = 32; integer offset = SInt(imm4);
<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<T> |
Is the size specifier,
encoded in
size<0>:
| ||||||
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<imm> | Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(64) base;
bits(64) addr;
bits(PL) mask = P[g];
bits(VL) src = Z[t];
constant integer mbytes = msize DIV 8;
if n == 31 then
if LastActiveElement(mask, esize) >= 0 ||
ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
CheckSPAlignment();
if HaveMTEExt() then SetTagCheckedInstruction(FALSE);
base = SP[];
else
if HaveMTEExt() then SetTagCheckedInstruction(TRUE);
base = X[n];
addr = base + offset * elements * mbytes;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>;
addr = addr + mbytes;
CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g]; bits(VL) src; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(n != 31); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n]; src = Z[t]; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer eoff = (offset * elements) + e; bits(64) addr = base + eoff * mbytes; Mem[addr, mbytes, AccType_NORMAL] = Elem[src, e, esize]<msize-1:0>;
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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