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ADDP (scalar)

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
01011110size110001101110RnRd

ADDP <V><d>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if size != '11' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = esize * 2; integer elements = 2; ReduceOp op = ReduceOp_ADD;

Assembler Symbols

<V> Is the destination width specifier, encoded in size:
size<V>
0xRESERVED
10RESERVED
11D
<V>

Is the destination width specifier, encoded in size:

size<V>
0xRESERVED
10RESERVED
11D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T> Is the source arrangement specifier, encoded in size:
size<T>
0xRESERVED
10RESERVED
112D
<T>

Is the source arrangement specifier, encoded in size:

size<T>
0xRESERVED
10RESERVED
112D

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; V[d] = Reduce(op, operand, esize);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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