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UZP1, UZP2 (predicates)

.

Concatenate adjacent even or odd-numbered elements from the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

Concatenate even or odd elements from two predicates.

Concatenate adjacent even or odd-numbered elements from the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

It has encodings from 2 classes: Even and Odd

Even

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100100Pn0Pd
H

UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 0;

Odd

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100110Pn0Pd
H

UZP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 1;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D
<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D
<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) operand1 = P[n]; bits(PL) operand2 = P[m]; bits(PL) result; bits(PL*2) zipped = operand2:operand1; for e = 0 to elements-1 Elem[result, e, esize DIV 8] = Elem[zipped, 2*e+part, esize DIV 8]; P[d] = result;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

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