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Floating-point maximum number recursive reduction to scalarscalar.
Floating-point maximum number horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the default NaN.
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Floating-point maximum number horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the default NaN.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Pg | Zn | Vd |
if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Vd);
<V> | Is a width specifier,
encoded in
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<d> | Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field. |
<T> | Is the size specifier,
encoded in
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CheckSVEEnabled(); bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(esize) identity = FPDefaultNaN(); V[d] = ReducePredicated(ReduceOp_FMAXNUM, operand, mask, identity);
Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0
; Build timestamp: 2020-11-18T172020-07-03T12:2342
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