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USHLL, USHLL2

The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

The USHLL instruction extracts vector elements from the lower half of the source register, while the USHLL2 instruction extracts vector elements from the upper half of the source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias UXTL, UXTL2.

313029282726252423222120191817161514131211109876543210
0Q1011110!= 0000immb101001RnRd
Uimmh

USHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3> == '1' then UNDEFINED; integer esize = 8 << HighestSetBit(immh); integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; integer shift = UInt(immh:immb) - esize; boolean unsigned = (U == '1');

Assembler Symbols

2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:
Q2
0[absent]
1[present]
2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q2
0[absent]
1[present]
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta> Is an arrangement specifier, encoded in immh:
immh<Ta>
0000SEE Advanced SIMD modified immediate
00018H
001x4S
01xx2D
1xxxRESERVED
<Ta>

Is an arrangement specifier, encoded in immh:

immh<Ta>
0000SEE Advanced SIMD modified immediate
00018H
001x4S
01xx2D
1xxxRESERVED
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Tb> Is an arrangement specifier, encoded in immh:Q:
immhQ<Tb>
0000xSEE Advanced SIMD modified immediate
000108B
0001116B
001x04H
001x18H
01xx02S
01xx14S
1xxxxRESERVED
<Tb>

Is an arrangement specifier, encoded in immh:Q:

immhQ<Tb>
0000xSEE Advanced SIMD modified immediate
000108B
0001116B
001x04H
001x18H
01xx02S
01xx14S
1xxxxRESERVED
<shift> Is the left shift amount, in the range 0 to the source element width in bits minus 1, encoded in immh:immb:
immh<shift>
0000SEE Advanced SIMD modified immediate
0001(UInt(immh:immb)-8)
001x(UInt(immh:immb)-16)
01xx(UInt(immh:immb)-32)
1xxxRESERVED
<shift>

Is the left shift amount, in the range 0 to the source element width in bits minus 1, encoded in immh:immb:

immh<shift>
0000SEE Advanced SIMD modified immediate
0001(UInt(immh:immb)-8)
001x(UInt(immh:immb)-16)
01xx(UInt(immh:immb)-32)
1xxxRESERVED

Alias Conditions

AliasIs preferred when
UXTL, UXTL2immb == '000' && BitCount(immh) == 1

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = Vpart[n, part]; bits(datasize*2) result; integer element; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], unsigned) << shift; Elem[result, e, 2*esize] = element<2*esize-1:0>; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3 ; Build timestamp: 2020-12-16T142020-11-18T17:1723

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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