DUP (indexed)

Broadcast indexed element to vector (unpredicated)

.

Unconditionally broadcast the indexed source vector element into each element of the destination vector. This instruction is unpredicated.

The immediate element index is in the range of 0 to 63 (bytes), 31 (halfwords), 15 (words), 7 (doublewords) or 3 (quadwords). Selecting an element beyond the accessible vector length causes the destination vector to be set to zero.

This instruction is used by the alias MOV (SIMD&FP scalar, unpredicated).

313029282726252423222120191817161514131211109876543210
00000101imm21tsz001000ZnZd

DUP <Zd>.<T>, <Zn>.<T>[<imm>]

if !HaveSVE() then UNDEFINED; bits(7) imm = imm2:tsz; case tsz of when '00000' UNDEFINED; when '10000' esize = 128; index = UInt(imm<6:5>); when 'x1000' esize = 64; index = UInt(imm<6:4>); when 'xx100' esize = 32; index = UInt(imm<6:3>); when 'xxx10' esize = 16; index = UInt(imm<6:2>); when 'xxxx1' esize = 8; index = UInt(imm<6:1>); integer n = UInt(Zn); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tsz:

tsz <T>
00000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
10000 Q
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm>

Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

Alias Conditions

AliasIs preferred when
MOV (SIMD&FP scalar, unpredicated)BitCount(imm2:tsz) == 1
MOV (SIMD&FP scalar, unpredicated)BitCount(imm2:tsz) > 1

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) result; bits(esize) element; if index >= elements then element = Zeros(); else element = Elem[operand1, index, esize]; result = Replicate(element); Z[d] = result;


Internal version only: isa v32.12, AdvSIMD v29.04, pseudocode v2020-09_xml, sve v2020-09_rc3 ; Build timestamp: 2020-11-18T17:23

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