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Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
Bitwise invert predicate.
Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
This is an alias of EOR, EORS (predicates). This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | 0 | 1 | Pg | 1 | Pn | 0 | Pd | ||||||||||||
S |
<Pd> | Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
<Pg> | Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
<Pn> | Is the name of the first source scalable predicate register, encoded in the "Pn" field. |
The description of EOR, EORS (predicates) gives the operational pseudocode for this instruction.
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
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