SQDECP (scalar)

Signed saturating decrement scalar by count of true predicate elements

.

Counts the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the source general-purpose register's signed integer range. A 32-bit saturated result is then sign-extended to 64 bits.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit

313029282726252423222120191817161514131211109876543210
00100101size1010101000100PmRdn
DUsf

SQDECP <Xdn>, <Pm>.<T>, <Wdn>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = FALSE; integer ssize = 32;

64-bit

313029282726252423222120191817161514131211109876543210
00100101size1010101000110PmRdn
DUsf

SQDECP <Xdn>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = FALSE; integer ssize = 64;

Assembler Symbols

<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Pm>

Is the name of the source scalable predicate register, encoded in the "Pm" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Wdn>

Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(ssize) operand1 = X[dn]; bits(PL) operand2 = P[m]; bits(ssize) result; integer count = 0; for e = 0 to elements-1 if ElemP[operand2, e, esize] == '1' then count = count + 1; integer element = Int(operand1, unsigned); (result, -) = SatQ(element - count, ssize, unsigned); X[dn] = Extend(result, 64, unsigned);


Internal version only: isa v32.12, AdvSIMD v29.04, pseudocode v2020-09_xml, sve v2020-09_rc3 ; Build timestamp: 2020-11-18T17:23

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