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UQDECP (scalar)

Unsigned saturating decrement scalar by count of true predicate elementselements.

Counts the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.

.

Counts the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit

313029282726252423222120191817161514131211109876543210
00100101size1010111000100PmRdn
DUsf

UQDECP <Wdn>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = TRUE; integer ssize = 32;

64-bit

313029282726252423222120191817161514131211109876543210
00100101size1010111000110PmRdn
DUsf

UQDECP <Xdn>, <Pm>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer m = UInt(Pm); integer dn = UInt(Rdn); boolean unsigned = TRUE; integer ssize = 64;

Assembler Symbols

<Wdn>

Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Pm>

Is the name of the source scalable predicate register, encoded in the "Pm" field.

<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D
<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(ssize) operand1 = X[dn]; bits(PL) operand2 = P[m]; bits(ssize) result; integer count = 0; for e = 0 to elements-1 if ElemP[operand2, e, esize] == '1' then count = count + 1; integer element = Int(operand1, unsigned); (result, -) = SatQ(element - count, ssize, unsigned); X[dn] = Extend(result, 64, unsigned);


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc3v2020-06_rel0 ; Build timestamp: 2020-11-18T172020-07-03T12:2342

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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