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If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector). This instruction multiplies the vector elements of the first source SIMD&FP register with the corresponding vector elements of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.
Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector). This instruction multiplies the vector elements of the first source SIMD&FP register with the corresponding vector elements of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.
If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | size | 0 | Rm | 1 | 0 | 0 | 0 | 1 | 1 | Rn | Rd | |||||||||||||
S |
if !HaveQRDMLAHExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' || size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean rounding = TRUE; boolean sub_op = (S == '1');
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | size | 0 | Rm | 1 | 0 | 0 | 0 | 1 | 1 | Rn | Rd | |||||||||||||
S |
if !HaveQRDMLAHExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' || size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean rounding = TRUE; boolean sub_op = (S == '1');
<V> |
Is a width specifier,
encoded in
size:
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<d> | Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<m> | Is the number of the second SIMD&FP source register, encoded in the "Rm" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; integer rounding_const = if rounding then 1 << (esize - 1) else 0; integer element1; integer element2; integer element3; integer product; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); element3 = SInt(Elem[operand3, e, esize]); if sub_op then accum = ((element3 << esize) - 2 * (element1 * element2) + rounding_const); else accum = ((element3 << esize) + 2 * (element1 * element2) + rounding_const); (Elem[result, e, esize], sat) = SignedSatQ(accum >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc3
; Build timestamp: 2020-12-16T142020-11-18T17:1723
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