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Floating-point Square Root (scalar). This instruction calculates the square root of the value in the SIMD&FP source register and writes the result to the SIMD&FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rd | |||||||||
opc |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer esize;
case ftype of
when '00' esize = 32;
when '01' esize = 64;
when '10' UNDEFINED;
when '11'
if HaveFP16Ext() then
esize = 16;
else
UNDEFINED;FPUnaryOp fpop;
case opc of
when '00' fpop = FPUnaryOp_MOV;
when '01' fpop = FPUnaryOp_ABS;
when '10' fpop = FPUnaryOp_NEG;
when '11' fpop = FPUnaryOp_SQRT;
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Dn> | Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> | Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPEnabled64();
FPCRType fpcr = FPCR[];
boolean merge =fpcr = FPCR[];
boolean merge = fpop != FPUnaryOp_MOV && IsMerging(fpcr);
bits(128) result = if merge then V[d] else Zeros();
bits(esize) operand = V[n];
case fpop of
when FPUnaryOp_MOV Elem[result, 0, esize] = operand;
when FPUnaryOp_ABS Elem[result, 0, esize] = FPAbs(operand);
when FPUnaryOp_NEG Elem[result, 0, esize] = FPNeg(operand);
when FPUnaryOp_SQRT[n];
Elem[result, 0, esize] = FPSqrt(operand, fpcr);
V[d] = result;
Internal version only: isa v32.21, AdvSIMD v29.05, pseudocode v2021-06_xml, sve v2021-06_rc2b
; Build timestamp: 2021-06-28T172021-06-28T16:0241
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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