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Load Exclusive Pair of Registers derives an address from a base register value, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers. For information on single-copy atomicity and alignment requirements, see Requirements for single-copy atomicity and Alignment of data accesses. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | sz | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | (1) | 0 | Rt2 | Rn | Rt | ||||||||||||
L | Rs | o0 |
integer n = UInt(Rn);
integer t = UInt(Rt);
integer t2 = UInt(Rt2);
integer elsize = 32 <<(Rt2); // ignored by load/store single register
integer s = UInt(sz);
integer datasize = elsize * 2;
boolean tag_checked = n != 31;
boolean rt_unknown = FALSE;
if t == t2 then(Rs); // ignored by all loads and store-release
AccType acctype = if o0 == '1' then AccType_ORDEREDATOMIC else AccType_ATOMIC;
boolean pair = TRUE;
MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE;
integer elsize = 32 << UInt(sz);
integer regsize = if elsize == 64 then 64 else 32;
integer datasize = if pair then elsize * 2 else elsize;
boolean tag_checked = n != 31;
boolean rt_unknown = FALSE;
boolean rn_unknown = FALSE;
if memop == MemOp_LOAD && pair && t == t2 then
Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if memop == MemOp_STORE then
if s == t || (pair && s == t2) then
Constraint c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // store UNKNOWN value
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
if s == n && n != 31 then
Constraint c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN
whenrn_unknown = TRUE; // address is UNKNOWN
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDXP.
<Wt1> | Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
<Wt2> | Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
<Xt1> | Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
<Xt2> | Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;
if HaveMTE2Ext() then
SetTagCheckedInstruction(tag_checked);
if n == 31 then
CheckSPAlignment();
address = SP[];
elsif rn_unknown then
address = bits(64) UNKNOWN;
else
address = X[n];
// Tell the Exclusives monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusives monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.case memop of
when
AArch64.SetExclusiveMonitorsMemOp_STORE(address, dbytes);
if rt_unknown then
// ConstrainedUNPREDICTABLE case data = bits(datasize) UNKNOWN;
elsif pair then
bits(datasize DIV 2) el1 =
X[t] = bits(datasize) UNKNOWN; // In this case t = t2
elsif elsize == 32 then
// 32-bit load exclusive pair (atomic)
data =[t];
bits(datasize DIV 2) el2 = X[t2];
data = if BigEndian(acctype) then el1 : el2 else el2 : el1;
else
data = X[t];
bit status = '1';
// Check whether the Exclusives monitors are set to include the
// physical memory locations corresponding to virtual address
// range [address, address+dbytes-1].
if AArch64.ExclusiveMonitorsPass(address, dbytes) then
// This atomic write will be rejected if it does not refer
// to the same physical locations after address translation.
Mem[address, dbytes,[address, dbytes, acctype] = data;
status = AccType_ATOMICExclusiveMonitorsStatus];
if(); BigEndianX([s] =AccType_ATOMICZeroExtend) then(status, 32);
when
MemOp_LOAD
// Tell the Exclusives monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusives monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.
AArch64.SetExclusiveMonitors(address, dbytes);
if pair then
if rt_unknown then
// ConstrainedUNPREDICTABLE case
X[t] = data<datasize-1:elsize>;[t] = bits(datasize) UNKNOWN; // In this case t = t2
elsif elsize == 32 then
// 32-bit load exclusive pair (atomic)
data =
Mem[address, dbytes, acctype];
if BigEndian(acctype) then
X[t2] = data<elsize-1:0>;
else[t] = data<datasize-1:elsize>;
X[t] = data<elsize-1:0>;[t2] = data<elsize-1:0>;
else
X[t2] = data<datasize-1:elsize>;
else // elsize == 64
// 64-bit load exclusive pair (not atomic),
// but must be 128-bit aligned
if address !=[t] = data<elsize-1:0>; X[t2] = data<datasize-1:elsize>;
else // elsize == 64
// 64-bit load exclusive pair (not atomic),
// but must be 128-bit aligned
if address != Align(address, dbytes) then(address, dbytes) then
iswrite = FALSE;
secondstage = FALSE;
AArch64.Abort(address, AlignmentFault((acctype, iswrite, secondstage));AccType_ATOMICX, FALSE, FALSE));[t] =
Mem[address + 0, 8, acctype];
X[t] =[t2] = Mem[address, 8,[address + 8, 8, acctype];
else
data = AccType_ATOMICMem];[address, dbytes, acctype];
X[t2] =[t] = MemZeroExtend[address+8, 8, AccType_ATOMIC];(data, regsize);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v32.21, AdvSIMD v29.05, pseudocode v2021-06_xml, sve v2021-06_rc2b
; Build timestamp: 2021-06-28T172021-06-28T16:0241
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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