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Return predicate of succesfully loaded elements
Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.
Read the first-fault register (FFR) and place active elements in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Optionally sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | Pg | 0 | Pd | ||||||
S |
if !HaveSVE() then UNDEFINED; integer g = UInt(Pg); integer d = UInt(Pd); boolean setflags = FALSE;
if !HaveSVE() then UNDEFINED;
integer g = UInt(Pg);
integer d = UInt(Pd);
boolean setflags = TRUE;
<Pd> | Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
<Pg> | Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
CheckSVEEnabled(); bits(PL) mask = P[g]; bits(PL) ffr = FFR[]; bits(PL) result = ffr AND mask; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, 8); P[d] = result;
Internal version only: isa v32.21v32.15, AdvSIMD v29.05, pseudocode v2021-06_xmlv2021-03, sve v2021-06_rc2bv2021-03_rc2
; Build timestamp: 2021-06-28T162021-03-30T21:4122
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