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Load Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, loads two 32-bit words or two 64-bit doublewords from memory, and writes them to two registers.
For information about memory accesses, see Load/Store addressing modes. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
x | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
opc | L |
boolean wback = FALSE; boolean postindex = FALSE;
For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDNP.
<Wt1> | Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
<Wt2> | Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
<Xt1> | Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
<Xt2> | Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); AccType acctype = AccType_STREAM; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; if opc<0> == '1' then UNDEFINED; integer scale = 2 + UInt(opc<1>); integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale); boolean tag_checked = wback || n != 31; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();
bits(64) address;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;
if HaveMTE2Ext() then
SetTagCheckedInstruction(tag_checked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
if ! postindex then
address = address + offset;
case memop of
when MemOp_STORE
if rt_unknown && t == n then
data1 = bits(datasize) UNKNOWN;
else
data1 = X[t];
if rt_unknown && t2 == n then
data2 = bits(datasize) UNKNOWN;
else
data2 = X[t2];
Mem[address + 0 , dbytes, acctype] = data1;
Mem[address + dbytes, dbytes, acctype] = data2;
when MemOp_LOAD
ifdata1 = HaveLSE2Ext() then
bits(2*datasize) full_data;
boolean ispair = TRUE;
full_data = Mem[address, 2 * dbytes, AccType_NORMAL, ispair];
if BigEndian(acctype) then
data2 = full_data<(datasize-1) : 0>;
data1 = full_data<(2*datasize-1) : datasize>;
else
data1 = full_data<(datasize-1) : 0>;
data2 = full_data<(2*datasize-1) : datasize>;
else
data1 = Mem[address + 0 , dbytes, acctype];
data2 = Mem[address + dbytes, dbytes, acctype];
if rt_unknown then
data1 = bits(datasize) UNKNOWN;
data2 = bits(datasize) UNKNOWN;
X[t] = data1;
X[t2] = data2;
if wback then
if postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X[n] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v32.15v32.13, AdvSIMD v29.05, pseudocode v2021-03v2020-12, sve v2021-03_rc2v2020-12
; Build timestamp: 2021-03-30T212021-03-05T20:2214
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This document is Non-Confidential.
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