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Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier.
A DSB instruction with the nXS qualifier is complete when the subset of these memory accesses with the XS attribute set to 0 are complete. It does not require that memory accesses with the XS attribute set to 1 are complete.
This instruction is used by the aliases PSSBB, and SSBB.
It has encodings from 2 classes: Memory barrier and Memory nXS barrier
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |||
opc |
boolean nXS = FALSE;
case CRm of
when '0000' alias =case CRm<3:2> of
when '00' domain = DSBAlias_SSBB;
when '0100' alias = DSBAlias_PSSBB;
otherwise alias = DSBAlias_DSB;
case CRm<3:2> of
when '00' domain = MBReqDomain_OuterShareable;
when '01' domain = MBReqDomain_Nonshareable;
when '10' domain = MBReqDomain_InnerShareable;
when '11' domain = MBReqDomain_FullSystem;
case CRm<1:0> of
when '00' types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
when '01' types = MBReqTypes_Reads;
when '10' types = MBReqTypes_Writes;
when '11' types = MBReqTypes_All;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | imm2 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
if !HaveFeatXS() then UNDEFINED;
MBReqTypes types = MBReqTypes_All;
boolean nXS = TRUE;boolean nXS = TRUE;
case imm2 of
when '00' domain =
DSBAlias alias = DSBAlias_DSB;
case imm2 of
when '00' domain = MBReqDomain_OuterShareable;
when '01' domain = MBReqDomain_Nonshareable;
when '10' domain = MBReqDomain_InnerShareable;
when '11' domain = MBReqDomain_FullSystem;
<option> | For the memory barrier variant: specifies the limitation on the barrier operation. Values are:
All other encodings of CRm, other than the values 0b0000 and 0b0100, that are not listed above are reserved, and can be encoded using the #<imm> syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see Data Memory Barrier (DMB) or see Data Synchronization Barrier (DSB). The value 0b0000 is used to encode SSBB and the value 0b0100 is used to encode PSSBB. |
For the memory nXS barrier variant: specifies the limitation on the barrier operation. Values are:
|
Alias | Is preferred when |
---|---|
PSSBB | CRm == '0100' |
SSBB | CRm == '0000' |
case alias of
whenif !nXS && DSBAlias_SSBBSpeculativeStoreBypassBarrierToVA();
when DSBAlias_PSSBBSpeculativeStoreBypassBarrierToPA();
when DSBAlias_DSB
if !nXS && HaveFeatXS() && HaveFeatHCX() then
nXS = PSTATE.EL IN {EL0, EL1} && IsHCRXEL2Enabled() && HCRX_EL2.FnXS == '1';
DataSynchronizationBarrier(domain, types, nXS);
otherwise
Unreachable();(domain, types, nXS);
Internal version only: isa v32.21v32.15, AdvSIMD v29.05, pseudocode v2021-06_xmlv2021-03, sve v2021-06_rc2bv2021-03_rc2
; Build timestamp: 2021-06-28T162021-03-30T21:4122
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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