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LDAPR

Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

This difference in memory ordering is not described in the pseudocode.

For information about memory accesses, see Load/Store addressing modes.

Integer
(FEAT_LRCPC)

313029282726252423222120191817161514131211109876543210
1x111000101(1)(1)(1)(1)(1)110000RnRt
sizeRs

32-bit (size == 10)

LDAPR <Wt>, [<Xn|SP> {,#0}]

64-bit (size == 11)

LDAPR <Xt>, [<Xn|SP> {,#0}]

integer n = UInt(Rn); integer t = UInt(Rt); integer elsize = 8 <<integer s = UInt(size); integer regsize = if elsize == 64 then 64 else 32; boolean tag_checked = n != 31;(Rs); // ignored by all loads and store-releaseAccType acctype = AccType_ORDERED; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize; boolean tag_checked = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v32.21, AdvSIMD v29.05, pseudocode v2021-06_xml, sve v2021-06_rc2b ; Build timestamp: 2021-06-28T172021-06-28T16:0241

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