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MOV (SIMD&FP scalar, unpredicated)

Move indexed element or SIMD&FP scalar to vector (unpredicated)

Unconditionally broadcast the SIMD&FP scalar into each element of the destination vector. This instruction is unpredicated.

This is an alias of DUP (indexed). This means:

313029282726252423222120191817161514131211109876543210
00000101imm21tsz001000ZnZd

MOV <Zd>.<T>, <Zn><V><n>.<T>[<imm>]

is equivalent to

DUP <Zd>.<T>, <Zn>.<T>[0]<imm>]

and is the preferred disassembly when BitCount(imm2:tsz) >== 1.

MOV <Zd>.<T>, <V><Zn>.<T>[<imm>]<n>

is equivalent to

DUP <Zd>.<T>, <Zn>.<T>[0]<imm>]

and is the preferred disassembly when BitCount(imm2:tsz) ==> 1.

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tsz:

tsz<T>
00000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
10000Q
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm>

Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

<V>

Is a width specifier, encoded in tsz:

tsz<V>
00000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
10000Q
<n>

Is the number [0-31] of the source SIMD&FP register, encoded in the "Zn" field.

Operation

The description of DUP (indexed) gives the operational pseudocode for this instruction.


Internal version only: isa v32.21v32.15, AdvSIMD v29.05, pseudocode v2021-06_xmlv2021-03, sve v2021-06_rc2bv2021-03_rc2 ; Build timestamp: 2021-06-28T162021-03-30T21:4122

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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