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UMINV

Unsigned minimum reduction to scalar

Unsigned minimum horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as the maximum unsigned integer for the element size.

313029282726252423222120191817161514131211109876543210
00000100size001011001PgZnVd
U
313029282726252423222120191817161514131211109876543210
00000100size001011001PgZnVd
U

UMINV <V><d>, <Pg>, <Zn>.<T>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Vd); boolean unsigned = TRUE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size<V>
00B
01H
10S
11D
<d>

Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<T>

Is the size specifier, encoded in size:

size<T>
00B
01H
10S
11D

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n] else Zeros(); integer minimum = if unsigned then (2^esize - 1) else (2^(esize-1) - 1); for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer element = Int(Elem[operand, e, esize], unsigned); minimum = Min(minimum, element); V[d] = minimum<esize-1:0>;


Internal version only: isa v32.15v32.13, AdvSIMD v29.05, pseudocode v2021-03v2020-12, sve v2021-03_rc2v2020-12 ; Build timestamp: 2021-03-30T212021-03-05T20:2214

Copyright © 2010-20212010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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