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Single-copy Atomic 64-byte Load derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers, Xt to X(t+7). The data that is loaded is atomic and is required to be 64-byte aligned.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rn | Rt |
if !HaveFeatLS64() then UNDEFINED; if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; integer n = UInt(Rn); integer t = UInt(Rt); boolean tag_checked = n != 31;
<Xt> | Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
CheckLDST64BEnabled();
bits(512) data;
bits(64) address;
bits(64) value;
acctype = AccType_ATOMICLS64;
if HaveMTE2Ext() then
SetTagCheckedInstruction(tag_checked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
data = MemLoad64B(address, acctype);
for i = 0 to 7
value = data<63+64*i:64*i>;
value = data<63+64*i : 64*i>;
if BigEndian(acctype) then value = BigEndianReverse(value);
X[t+i] = value;
Internal version only: isa v32.21, AdvSIMD v29.05, pseudocode v2021-06_xml, sve v2021-06_rc2b
; Build timestamp: 2021-06-28T172021-06-28T16:0241
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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