The ATS1HW characteristics are:
Performs stage 1 address translation as defined for PL2 and the Non-secure state, with permissions as if writing to the given virtual address.
This instruction is present only when AArch32 is supported at EL0. Otherwise, direct accesses to ATS1HW are UNDEFINED.
ATS1HW is a 32-bit System instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Input address for translation |
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. The resulting address is the PA that is the output address of the translation.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
Accesses to this instruction use the following encodings in the System instruction encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0111 | 0b1000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else ATS1HW(R[t]); elsif PSTATE.EL == EL2 then ATS1HW(R[t]); elsif PSTATE.EL == EL3 then ATS1HW(R[t]);
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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