The TRCTRACEIDR characteristics are:
Sets the trace ID for instruction trace.
External register TRCTRACEIDR bits [31:0] are architecturally mapped to AArch64 System register TRCTRACEIDR[31:0].
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCTRACEIDR are RES0.
TRCTRACEIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | TRACEID |
Reserved, RES0.
Trace ID field. Sets the trace ID value for instruction trace. The width of the field is indicated by the value of TRCIDR5.TRACEIDSIZE. Unimplemented bits are RES0.
If an implementation supports AMBA ATB, then:
See the AMBA ATB Protocol Specification for information about which ATID values are reserved.
The reset behaviour of this field is:
Must be programmed if implemented.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Component | Offset | Instance |
---|---|---|
ETE | 0x040 | TRCTRACEIDR |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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