(old) | htmldiff from- | (new) |
The CNTHCTL_EL2 characteristics are:
Controls the generation of an event stream from the physical counter, and access from EL1 to the physical counter and the EL1 physical timer.
AArch64 System register CNTHCTL_EL2 bits [31:0] are architecturally mapped to AArch32 System register CNTHCTL[31:0].
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
CNTHCTL_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | CNTPMASK | CNTVMASK | EVNTIS | EL1NVVCT | EL1NVPCT | EL1TVCT | EL1TVT | ECV | EL1PTEN | EL1PCTEN | EL0PTEN | EL0VTEN | EVNTI | EVNTDIR | EVNTEN | EL0VCTEN | EL0PCTEN |
Reserved, RES0.
CNTPMASK | Meaning |
---|---|
0b0 | This control has no affect on CNTP_CTL_EL0.IMASK. |
0b1 | CNTP_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. |
This bit is RES0 in Non-secure and Secure state.
The reset behaviour of this field is:
Reserved, RES0.
CNTVMASK | Meaning |
---|---|
0b0 | This control has no affect on CNTV_CTL_EL0.IMASK. |
0b1 | CNTV_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. |
This bit is RES0 in Non-secure and Secure state.
The reset behaviour of this field is:
Reserved, RES0.
Controls the scale of the generation of the event stream.
EVNTIS | Meaning |
---|---|
0b0 | The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[15:0]. |
0b1 | The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[23:8]. |
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL1 accesses to the specified EL1 virtual timer registers using the EL02 descriptors to EL2, when EL2 is enabled for the current Security state.
EL1NVVCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If ((HCR_EL2.E2H==1 && HCR_EL2.TGE==1) || HCR_EL2.NV2==0 || HCR_EL2.NV1==1 || HCR_EL2.NV==0), this control does not cause any instructions to be trapped. If ((HCR_EL2.E2H==0 || HCR_EL2.TGE==0) && HCR_EL2.NV2==1 && HCR_EL2.NV1==0 && HCR_EL2.NV==1), then EL1 accesses to CNTV_CTL_EL02 and CNTV_CVAL_EL02 are trapped to EL2. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL1 accesses to the specified EL1 physical timer registers using the EL02 descriptors to EL2, when EL2 is enabled for the current Security state.
EL1NVPCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If ((HCR_EL2.E2H==1 && HCR_EL2.TGE==1) || HCR_EL2.NV2==0 || HCR_EL2.NV1==1 || HCR_EL2.NV==0), this control does not cause any instructions to be trapped. If (HCR_EL2.E2H==0 || HCR_EL2.TGE==0) && HCR_EL2.NV2==1 && HCR_EL2.NV1==0 && HCR_EL2.NV==1, then EL1 accesses to CNTP_CTL_EL02 and CNTP_CVAL_EL02, are trapped to EL2. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL0 and EL1 accesses to the EL1 virtual counter registers to EL2, when EL2 is enabled for the current Security state.
EL1TVCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If HCR_EL2.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped. If HCR_EL2.E2H is 0 or HCR_EL2.TGE is 0, then:
|
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL0 and EL1 accesses to the EL1 virtual timer registers to EL2, when EL2 is enabled for the current Security state.
EL1TVT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If HCR_EL2.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped. If HCR_EL2.E2H is 0 or HCR_EL2.TGE is 0, then:
|
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Enables the Enhanced Counter Virtualization functionality registers.
ECV | Meaning |
---|---|
0b0 | Enhanced Counter Virtualization functionality is disabled. |
0b1 | When HCR_EL2.{E2H, TGE} == {1, 1} or SCR_EL3.{NS, EEL2} == {0, 0}, then Enhanced Counter Virtualization functionality is disabled. When SCR_EL3.NS or SCR_EL3.EEL2 are 1, and HCR_EL2.E2H or HCR_EL2.TGE are 0, then Enhanced Counter Virtualziation functionality is enabled when EL2 is enabled for the current Security state. This means that:
|
The reset behaviour of this field is:
Reserved, RES0.
When HCR_EL2.TGE is 0, traps EL0 and EL1 accesses to the E1 physical timer registers to EL2 when EL2 is enabled in the current Security state.
EL1PTEN | Meaning |
---|---|
0b0 | From AArch64 state: EL0 and EL1 accesses to the CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PTEN. From AArch32 state: EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN. |
0b1 | This control does not cause any instructions to be trapped. |
When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.
The reset behaviour of this field is:
When HCR_EL2.TGE is 0, traps EL0 and EL1 accesses to the EL1 physical counter register to EL2 when EL2 is enabled in the current Security state, as follows:
EL1PCTEN | Meaning |
---|---|
0b0 | From AArch64 state: EL0 and EL1 accesses to the CNTPCT_EL0 are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PCTEN. From AArch32 state: EL0 and EL1 accesses to the CNTPCT are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN. |
0b1 | This control does not cause any instructions to be trapped. |
When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.
The reset behaviour of this field is:
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.
When HCR_EL2.TGE is 1, traps EL0 accesses to the physical timer registers to EL2.
EL0PTEN | Meaning |
---|---|
0b0 | EL0 using AArch64: EL0 accesses to the CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 registers are trapped to EL2. EL0 using AArch32: EL0 accesses to the CNTP_CTL, CNTP_CVAL and CNTP_TVAL registers are trapped to EL2. |
0b1 | This control does not cause any instructions to be trapped. |
The reset behaviour of this field is:
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.
When HCR_EL2.TGE is 1, traps EL0 accesses to the virtual timer registers to EL2.
EL0VTEN | Meaning |
---|---|
0b0 | EL0 using AArch64: EL0 accesses to the CNTV_CTL_EL0, CNTV_CVAL_EL0, and CNTV_TVAL_EL0 registers are trapped to EL2. EL0 using AArch32: EL0 accesses to the CNTV_CTL, CNTV_CVAL, and CNTV_TVAL registers are trapped to EL2. |
0b1 | This control does not cause any instructions to be trapped. |
The reset behaviour of this field is:
Selects which bit of the counter register CNTPCT_EL0 is the trigger for the event stream generated from that counter, when that stream is enabled.
If FEAT_ECV is implemented, and CNTHCTL_EL2.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of the counter register CNTPCT_EL0.
Otherwise, this field selects a trigger bit in the range 0 to 15 of the counter register.
The reset behaviour of this field is:
Controls which transition of the counter register CNTPCT_EL0 trigger bit, defined by EVNTI, generates an event when the event stream is enabled.
EVNTDIR | Meaning |
---|---|
0b0 | A 0 to 1 transition of the trigger bit triggers an event. |
0b1 | A 1 to 0 transition of the trigger bit triggers an event. |
The reset behaviour of this field is:
Enables the generation of an event stream from the counter register CNTPCT_EL0.
EVNTEN | Meaning |
---|---|
0b0 | Disables the event stream. |
0b1 | Enables the event stream. |
The reset behaviour of this field is:
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.
When HCR_EL2.TGE is 1, traps EL0 accesses to the frequency register and virtual counter register to EL2.
EL0VCTEN | Meaning |
---|---|
0b0 | EL0 using AArch64: EL0 accesses to the CNTVCT_EL0 are trapped to EL2. EL0 using AArch64: EL0 accesses to the CNTFRQ_EL0 register are trapped to EL2, if CNTHCTL_EL2.EL0PCTEN is also 0. EL0 using AArch32: EL0 accesses to the CNTVCT are trapped to EL2. EL0 using AArch32: EL0 accesses to the CNTFRQ register are trapped to EL2, if CNTHCTL.EL0PCTEN is also 0. |
0b1 | This control does not cause any instructions to be trapped. |
The reset behaviour of this field is:
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.
When HCR_EL2.TGE is 1, traps EL0 accesses to the frequency register and physical counter register to EL2.
EL0PCTEN | Meaning |
---|---|
0b0 | EL0 using AArch64: EL0 accesses to the CNTPCT_EL0 are trapped to EL2. EL0 using AArch64: EL0 accesses to the CNTFRQ_EL0 register are trapped to EL2, if CNTHCTL_EL2.EL0VCTEN is also 0. EL0 using AArch32: EL0 accesses to the CNTPCT are trapped to EL2. EL0 using AArch32: EL0 accesses to the CNTFRQ and register are trapped to EL2, if CNTHCTL_EL2.EL0VCTEN is also 0. |
0b1 | This control does not cause any instructions to be trapped. |
The reset behaviour of this field is:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | CNTPMASK | CNTVMASK | EVNTIS | EL1NVVCT | EL1NVPCT | EL1TVCT | EL1TVT | ECV | RES0 | EVNTI | EVNTDIR | EVNTEN | EL1PCEN | EL1PCTEN |
This format applies in all Armv8.0 implementations, and it also contains a description of the behavior when EL3 is implemented and EL2 is not implemented.
Reserved, RES0.
CNTPMASK | Meaning |
---|---|
0b0 | This control has no affect on CNTP_CTL_EL0.IMASK. |
0b1 | CNTP_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. |
This bit is RES0 in Non-secure and Secure state.
The reset behaviour of this field is:
Reserved, RES0.
CNTVMASK | Meaning |
---|---|
0b0 | This control has no affect on CNTV_CTL_EL0.IMASK. |
0b1 | CNTV_CTL_EL0.IMASK behaves as if set to 1 for all purposes other than a direct read of the field. |
This bit is RES0 in Non-secure and Secure state.
The reset behaviour of this field is:
Reserved, RES0.
Controls the scale of the generation of the event stream.
EVNTIS | Meaning |
---|---|
0b0 | The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[15:0]. |
0b1 | The CNTHCTL_EL2.EVNTI field applies to CNTPCT_EL0[23:8]. |
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL1 accesses to the specified EL1 virtual timer registers using the EL02 descriptors to EL2, when EL2 is enabled for the current Security state.
EL1NVVCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If ((HCR_EL2.E2H==1 && HCR_EL2.TGE==1) || HCR_EL2.NV2==0 || HCR_EL2.NV1==1 || HCR_EL2.NV==0), this control does not cause any instructions to be trapped. If ((HCR_EL2.E2H==0 || HCR_EL2.TGE==0) && HCR_EL2.NV2==1 && HCR_EL2.NV1==0 && HCR_EL2.NV==1), then EL1 accesses to CNTV_CTL_EL02 and CNTV_CVAL_EL02 are trapped to EL2. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL1 accesses to the specified EL1 physical timer registers using the EL02 descriptors to EL2, when EL2 is enabled for the current Security state.
EL1NVPCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If ((HCR_EL2.E2H==1 && HCR_EL2.TGE==1) || HCR_EL2.NV2==0 || HCR_EL2.NV1==1 || HCR_EL2.NV==0), this control does not cause any instructions to be trapped. If (HCR_EL2.E2H==0 || HCR_EL2.TGE==0) && HCR_EL2.NV2==1 && HCR_EL2.NV1==0 && HCR_EL2.NV==1, then EL1 accesses to CNTP_CTL_EL02 and CNTP_CVAL_EL02, are trapped to EL2. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL0 and EL1 accesses to the EL1 virtual counter registers to EL2, when EL2 is enabled for the current Security state.
EL1TVCT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If HCR_EL2.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped. If HCR_EL2.E2H is 0 or HCR_EL2.TGE is 0, then: In AArch64 state, traps EL0 and EL1 accesses to CNTVCT_EL0 to EL2, unless they are trapped by CNTKCTL_EL1.EL0VCTEN. In AArch32 state, traps EL0 and EL1 accesses to CNTVCT to EL2, unless they are trapped by CNTKCTL_EL1.EL0VCTEN or CNTKCTL.PL0VCTEN. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Traps EL0 and EL1 accesses to the EL1 virtual timer registers to EL2, when EL2 is enabled for the current Security state.
EL1TVT | Meaning |
---|---|
0b0 | This control does not cause any instructions to be trapped. |
0b1 | If HCR_EL2.{E2H, TGE} is {1, 1}, this control does not cause any instructions to be trapped. If HCR_EL2.E2H is 0 or HCR_EL2.TGE is 0, then:
|
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 0 other than for the purpose of a direct read.
This control applies regardless of the value of the CNTHCTL_EL2.ECV bit.
The reset behaviour of this field is:
Reserved, RES0.
Enables the Enhanced Counter Virtualization functionality registers.
ECV | Meaning |
---|---|
0b0 | Enhanced Counter Virtualization functionality is disabled. |
0b1 | When HCR_EL2.{E2H, TGE} == {1, 1} or SCR_EL3.{NS, EEL2} == {0, 0}, then Enhanced Counter Virtualization functionality is disabled. When SCR_EL3.NS or SCR_EL3.EEL2 are 1, and HCR_EL2.E2H or HCR_EL2.TGE are 0, then Enhanced Counter Virtualziation functionality is enabled when EL2 is enabled for the current Security state. This means that:
|
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Selects which bit of the counter register CNTPCT_EL0 is the trigger for the event stream generated from that counter, when that stream is enabled.
If FEAT_ECV is implemented, and CNTHCTL_EL2.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of the counter register CNTPCT_EL0.
Otherwise, this field selects a trigger bit in the range 0 to 15 of the counter register.
The reset behaviour of this field is:
Controls which transition of the counter register CNTPCT_EL0 trigger bit, defined by EVNTI, generates an event when the event stream is enabled.
EVNTDIR | Meaning |
---|---|
0b0 | A 0 to 1 transition of the trigger bit triggers an event. |
0b1 | A 1 to 0 transition of the trigger bit triggers an event. |
The reset behaviour of this field is:
Enables the generation of an event stream from the counter register CNTPCT_EL0.
EVNTEN | Meaning |
---|---|
0b0 | Disables the event stream. |
0b1 | Enables the event stream. |
The reset behaviour of this field is:
Traps EL0 and EL1 accesses to the EL1 physical timer registers to EL2 when EL2 is enabled in the current Security state, as follows:
EL1PCEN | Meaning |
---|---|
0b0 | From AArch64 state: EL0 and EL1 accesses to the CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PTEN. From AArch32 state: EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN. |
0b1 | This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
Traps EL0 and EL1 accesses to the EL1 physical counter register to EL2 when EL2 is enabled in the current Security state, as follows:
EL1PCTEN | Meaning |
---|---|
0b0 | From AArch64 state: EL0 and EL1 accesses to the CNTPCT_EL0 are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PCTEN. From AArch32 state: EL0 and EL1 accesses to the CNTPCT are trapped to EL2 when EL2 is enabled in the current Security state, unless they are trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN. |
0b1 | This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHCTL_EL2 or CNTKCTL_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return CNTHCTL_EL2; elsif PSTATE.EL == EL3 then return CNTHCTL_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then CNTHCTL_EL2 = X[t]; elsif PSTATE.EL == EL3 then CNTHCTL_EL2 = X[t];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return CNTKCTL_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return CNTHCTL_EL2; else return CNTKCTL_EL1; elsif PSTATE.EL == EL3 then return CNTKCTL_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then CNTKCTL_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then CNTHCTL_EL2 = X[t]; else CNTKCTL_EL1 = X[t]; elsif PSTATE.EL == EL3 then CNTKCTL_EL1 = X[t];
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |