The AMPIDR0 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Peripheral identification scheme'.
The power domain of AMPIDR0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMPIDR0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_0 |
Reserved, RES0.
Part number, least significant byte.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xFE0 | AMPIDR0 |
Accesses on this interface are RO.
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.