PMPIDR2, Performance Monitors Peripheral Identification Register 2

The PMPIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information, see 'About the Peripheral identification scheme'.

Configuration

Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

PMPIDR2 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0REVISIONJEDECDES_1

Bits [31:8]

Reserved, RES0.

REVISION, bits [7:4]

Part major revision. Parts can also use this field to extend Part number to 16-bits.

JEDEC, bit [3]

RAO. Indicates a JEP106 identity code is used.

DES_1, bits [2:0]

Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.

Accessing PMPIDR2

PMPIDR2 can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xFE8PMPIDR2

This interface is accessible as follows:


30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.