ERR<n>CTLR, Error Record Control Register, n = 0 - 65534

The ERR<n>CTLR characteristics are:

Purpose

The error control register contains enable bits for the node that writes to this record:

For each bit, if the node does not support the feature, then the bit is RES0. The definition of each record is IMPLEMENTATION DEFINED.

Configuration

This register is present only when error record <n> is implemented and error record <n> is the first error record owned by a node. Otherwise, direct accesses to ERR<n>CTLR are RES0.

ERR<n>FR describes the features implemented by the node.

Attributes

ERR<n>CTLR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
RES0CIRES0WDUIBit[10]WCFIBit[8]WUEWFIWUIBit[4]Bit[3]Bit[2]IMPLEMENTATION DEFINEDED

IMPLEMENTATION DEFINED, bits [63:32]

Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.

Bits [31:14]

Reserved, RES0.

CI, bit [13]
When ERR<n>FR.CI == 0b10:

Critical error interrupt enable. When enabled, the critical error interrupt is generated for a critical error condition.

CIMeaning
0b0

Critical error interrupt not generated for critical errors. Critical errors are treated as Uncontained errors.

0b1

Critical error interrupt generated for critical errors.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

Bit [12]

Reserved, RES0.

WDUI, bit [11]
When ERR<n>FR.DUI == 0b11:

Error recovery interrupt for Deferred errors on writes enable.

When enabled, the error recovery interrupt is generated for errors recorded as Deferred error on writes.

WDUIMeaning
0b0

Error recovery interrupt not generated for Deferred errors on writes.

0b1

Error recovery interrupt generated for Deferred errors on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

DUI, bit [10]
When ERR<n>FR.DUI == 0b10:

Error recovery interrupt for Deferred errors enable.

When ERR<n>FR.DUI == 0b10, this control applies to errors arising from both reads and writes.

When enabled, the error recovery interrupt is generated for all errors recorded as Deferred error.

DUIMeaning
0b0

Error recovery interrupt not generated for Deferred errors.

0b1

Error recovery interrupt generated for Deferred errors.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


When ERR<n>FR.DUI == 0b11:

Error recovery interrupt for Deferred errors on reads enable.

When ERR<n>FR.DUI == 0b11, this field is named RDUI.

When enabled, the error recovery interrupt is generated for errors recorded as Deferred error on reads.

RDUIMeaning
0b0

Error recovery interrupt not generated for Deferred errors on reads.

0b1

Error recovery interrupt generated for Deferred errors on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

WCFI, bit [9]
When ERR<n>FR.CFI == 0b11:

Fault handling interrupt for Corrected errors on writes enable.

When enabled:

WCFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors on writes.

0b1

Fault handling interrupt generated for Corrected errors on writes.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

CFI, bit [8]
When ERR<n>FR.CFI == 0b10:

Fault handling interrupt for Corrected errors enable.

When ERR<n>FR.CFI == 0b10, this control applies to errors arising from both reads and writes.

When enabled:

CFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors.

0b1

Fault handling interrupt generated for Corrected errors.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


When ERR<n>FR.CFI == 0b11:

Fault handling interrupt for Corrected errors on reads enable.

When ERR<n>FR.CFI == 0b11, this field is named RCFI.

When enabled:

RCFIMeaning
0b0

Fault handling interrupt not generated for Corrected errors on reads.

0b1

Fault handling interrupt generated for Corrected errors on reads.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

WUE, bit [7]
When ERR<n>FR.UE == 0b11:

In-band error response on writes enable.

When enabled, responses to writes that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External Abort).

It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester.

WUEMeaning
0b0

In-band error response for uncorrected errors on writes disabled.

0b1

In-band error response for uncorrected errors on writes enabled.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

WFI, bit [6]
When ERR<n>FR.FI == 0b11:

Fault handling interrupt on writes enable.

When enabled:

WFIMeaning
0b0

Fault handling interrupt on writes disabled.

0b1

Fault handling interrupt on writes enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

WUI, bit [5]
When ERR<n>FR.UI == 0b11:

Uncorrected error recovery interrupt on writes enable.

When enabled, the error recovery interrupt is generated for errors recorded as Uncorrected error on writes.

WUIMeaning
0b0

Error recovery interrupt on writes disabled.

0b1

Error recovery interrupt on writes enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

UE, bit [4]
When ERR<n>FR.UE == 0b10:

In-band error response enable.

When ERR<n>FR.UE == 0b10, this control applies to errors arising from both reads and writes.

When enabled, responses to transactions that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External Abort).

It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester.

UEMeaning
0b0

In-band error response for uncorrected errors disabled.

0b1

In-band error response for uncorrected errors enabled.

The reset behaviour of this field is:


When ERR<n>FR.UE == 0b11:

In-band error response on reads enable.

When ERR<n>FR.UE == 0b11, this field is named RUE.

When enabled, responses to reads that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External Abort).

It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester.

RUEMeaning
0b0

In-band error response for uncorrected errors on reads disabled.

0b1

In-band error response for uncorrected errors on reads enabled.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

FI, bit [3]
When ERR<n>FR.FI == 0b10:

Fault handling interrupt enable.

When ERR<n>FR.FI == 0b10, this control applies to errors arising from both reads and writes.

When enabled:

FIMeaning
0b0

Fault handling interrupt disabled.

0b1

Fault handling interrupt enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


When ERR<n>FR.FI == 0b11:

Fault handling interrupt on reads enable.

When ERR<n>FR.FI == 0b11, this field is named RFI.

When enabled:

RFIMeaning
0b0

Fault handling interrupt on reads disabled.

0b1

Fault handling interrupt on reads enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

UI, bit [2]
When ERR<n>FR.UI == 0b10:

Uncorrected error recovery interrupt enable.

When ERR<n>FR.UI == 0b10, this control applies to errors arising from both reads and writes.

When enabled, the error recovery interrupt is generated for all errors recorded as Uncorrected error.

UIMeaning
0b0

Error recovery interrupt disabled.

0b1

Error recovery interrupt enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


When ERR<n>FR.UI == 0b11:

Uncorrected error recovery interrupt on reads enable.

When ERR<n>FR.UI == 0b11, this field is named RUI.

When enabled, the error recovery interrupt is generated for errors recorded as Uncorrected error on reads.

RUIMeaning
0b0

Error recovery interrupt on reads disabled.

0b1

Error recovery interrupt on reads enabled.

The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

IMPLEMENTATION DEFINED, bit [1]

Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software.

ED, bit [0]
When ERR<n>FR.ED == 0b10:

Error reporting and logging enable. When disabled, the node behaves as if error detection and correction are disabled, and no errors are recorded or signaled by the node. Arm recommends that, when disabled, correct error detection and correction codes are written for writes, unless disabled by an IMPLEMENTATION DEFINED control for error injection.

EDMeaning
0b0

Error reporting disabled.

0b1

Error reporting enabled.

It is IMPLEMENTATION DEFINED whether the node fully disables error detection and correction when reporting is disabled. That is, even with error reporting disabled, the node might continue to silently correct errors. Uncorrected errors might result in corrupt data being silently propagated by the node.

Note

If this node requires initialization after Cold reset to prevent signaling false errors, then Arm recommends this field is set to 0 on Cold reset, meaning errors are not reported from Cold reset. This allows boot software to initialize a node without signaling errors. Software can enable error reporting after the node is initialized. Otherwise, the Cold reset value is IMPLEMENTATION DEFINED. If the Cold reset value is 1, the reset values of other controls in this register are also IMPLEMENTATION DEFINED and should not be UNKNOWN.

The reset behaviour of this field is:


Otherwise:

Reserved, RES0.

Accessing ERR<n>CTLR

ERR<n>CTLR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x008 + (64 * n)ERR<n>CTLR

Accesses on this interface are RW.


30/06/2021 09:40; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.