The TRCSEQSTR characteristics are:
Use this to set, or read, the Sequencer state.
External register TRCSEQSTR bits [31:0] are architecturally mapped to AArch64 System register TRCSEQSTR[31:0].
This register is present only when FEAT_ETE is implemented and TRCIDR5.NUMSEQSTATE != 0b000. Otherwise, direct accesses to TRCSEQSTR are RES0.
TRCSEQSTR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | STATE |
Reserved, RES0.
Set or returns the state of the Sequencer.
STATE | Meaning |
---|---|
0b00 |
State 0. |
0b01 |
State 1. |
0b10 |
State 2. |
0b11 |
State 3. |
The reset behaviour of this field is:
Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.SEQUENCER != 0b0000.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
Component | Offset | Instance |
---|---|---|
ETE | 0x11C | TRCSEQSTR |
This interface is accessible as follows:
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.