GPCCR_EL3, Granule Protection Check Control Register (EL3)

The GPCCR_EL3 characteristics are:

Purpose

The control register for Granule Protection Checks.

Configuration

This register is present only when FEAT_RME is implemented. Otherwise, direct accesses to GPCCR_EL3 are UNDEFINED.

Attributes

GPCCR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0L0GPTSZRES0GPCPGPCPGSSHORGNIRGNRES0PPS

Bits [63:24]

Reserved, RES0.

L0GPTSZ, bits [23:20]

Level 0 GPT entry size.

This field advertises the number of least-significant address bits protected by each entry in the level 0 GPT.

L0GPTSZMeaning
0b0000

30-bits. Each entry covers 1GB of address space.

0b0100

34-bits. Each entry covers 16GB of address space.

0b0110

36-bits. Each entry covers 64GB of address space.

0b1001

39-bits. Each entry covers 512GB of address space.

All other values are reserved.

Access to this field is RO.

Bits [19:18]

Reserved, RES0.

GPCP, bit [17]

Granule Protection Check Priority.

This control governs behavior of granule protection checks on fetches of stage 2 Table descriptors.

GPCPMeaning
0b0

GPC faults are all reported with a priority that is consistent with the GPC being performed on any access to physical address space.

0b1

A GPC fault for the fetch of a Table descriptor for a stage 2 translation table walk might not be generated or reported.

All other GPC faults are reported with a priority consistent with the GPC being performed on all accesses to physical address spaces.

The value of this field is permitted to be cached in a TLB.

The reset behaviour of this field is:

GPC, bit [16]

Granule Protection Check Enable.

GPCMeaning
0b0

Granule protection checks are disabled. Accesses are not prevented by this mechanism.

0b1

All accesses to physical address spaces are subject to granule protection checks, except for fetches of GPT information and accesses governed by the GPCCR_EL3.GPCP control.

If any stage of translation is enabled, the value of this field is permitted to be cached in a TLB.

The reset behaviour of this field is:

PGS, bits [15:14]

Physical Granule size.

PGSMeaning
0b00

4KB.

0b01

64KB.

0b10

16KB.

All other values are reserved.

The value of this field is permitted to be cached in a TLB.

Granule sizes not supported for stage 1 and not supported for stage 2, as defined in ID_AA64MMFR0_EL1, are reserved. For example, if ID_AA64MMFR0_EL1.TGran16 == 0b0000 and ID_AA64MMFR0_EL1.TGran16_2 == 0b0001, then the PGS encoding 0b10 is reserved.

The reset behaviour of this field is:

SH, bits [13:12]

GPT fetch Shareability attribute

SHMeaning
0b00

Non-shareable.

0b10

Outer Shareable.

0b11

Inner Shareable.

All other values are reserved.

Fetches of GPT information are made with the Shareability attribute that is configured in this field.

If both ORGN and IRGN are configured with Non-cacheable attributes, it is invalid to configure this field to any value other than 0b10.

The reset behaviour of this field is:

ORGN, bits [11:10]

GPT fetch Outer cacheability attribute.

ORGNMeaning
0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable.

0b11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable.

Fetches of GPT information are made with the Outer cacheability attributes configured in this field.

The reset behaviour of this field is:

IRGN, bits [9:8]

GPT fetch Inner cacheability attribute.

IRGNMeaning
0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable.

0b11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable.

Fetches of GPT information are made with the Inner cacheability attributes configured in this field.

The reset behaviour of this field is:

Bits [7:3]

Reserved, RES0.

PPS, bits [2:0]

Protected Physical Address Size.

The size of the memory region protected by GPTBR_EL3, in terms of the number of least-significant address bits.

PPSMeaning
0b000

32 bits, 4GB protected address space.

0b001

36 bits, 64GB protected address space.

0b010

40 bits, 1TB protected address space.

0b011

42 bits, 4TB protected address space.

0b100

44 bits, 16TB protected address space.

0b101

48 bits, 256TB protected address space.

0b110

52 bits, 4PB protected address space.

All other values are reserved.

Configuration of this field to a value exceeding the implemented physical address size is invalid.

The value of this field is permitted to be cached in a TLB.

The reset behaviour of this field is:

Accessing GPCCR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, GPCCR_EL3

op0op1CRnCRmop2
0b110b1100b00100b00010b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return GPCCR_EL3;

MSR GPCCR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00100b00010b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then GPCCR_EL3 = X[t];


30/06/2021 15:21; 2a17f7750cfd1ab239f20f6cf29877ba8041794f

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