ERR<n>FR, Error Record Feature Register, n = 0 - 65534

The ERR<n>FR characteristics are:

Purpose

Defines whether <n> is the first record owned by a node:

If <n> is the first record owned by the node, defines which of the common architecturally-defined features are implemented by the node and, of the implemented features, which are software programmable.

Configuration

This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>FR are RES0.

Attributes

ERR<n>FR is a 64-bit register.

Field descriptions

When error record <n> is not the first error record owned by the node:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0ED

Bits [63:2]

Reserved, RES0.

ED, bits [1:0]

Error reporting and logging. Indicates error record <n> is not the first error record owned the node.

EDMeaning
0b00

Error record <n> is not the first error record owned by the node.

This field reads as 0b00.

When error record <n> is the first error record owned by the node:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINEDCEDEUEOUERUEUUCIMPLEMENTATION DEFINED
FRXRES0TSCIINJCEODUIRPCECCFIUEFIUIIMPLEMENTATION DEFINEDED

IMPLEMENTATION DEFINED, bits [63:55]
When ERR<n>FR.FRX != 1:

Reserved for identifying IMPLEMENTATION DEFINED controls.


Otherwise:

Reserved, RES0.

CE, bits [54:53]
When ERR<n>FR.FRX == 1:

Corrected Error recording. Describes the types of Corrected errors the node can record, if any.

CEMeaning
0b00

Does not record Corrected errors.

0b01

Records only transient or persistent Corrected errors. That is, Corrected errors recorded by setting ERR<n>STATUS.CE to either 0b01 or 0b11.

0b10

Records only non-specific Corrected errors. That is, Corrected errors recorded by setting ERR<n>STATUS.CE to 0b10.

0b11

Records all types of Corrected error.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

DE, bit [52]
When ERR<n>FR.FRX == 1:

Deferred Error recording. Describes whether the node supports recording Deferred errors.

DEMeaning
0b0

Does not record Deferred errors.

0b1

Records Deferred errors.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

UEO, bit [51]
When ERR<n>FR.FRX == 1:

Latent or Restartable Error recording. Describes whether the node supports recording Latent or Restartable errors.

UEOMeaning
0b0

Does not record Latent or Restartable errors.

0b1

Records Latent or Restartable errors.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

UER, bit [50]
When ERR<n>FR.FRX == 1:

Signaled or Recoverable Error recording. Describes whether the node supports recording Signaled or Recoverable errors.

UERMeaning
0b0

Does not record Signaled or Recoverable errors.

0b1

Records Signaled or Recoverable errors.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

UEU, bit [49]
When ERR<n>FR.FRX == 1:

Unrecoverable Error recording. Describes whether the node supports recording Unrecoverable errors.

UEUMeaning
0b0

Does not record Unrecoverable errors.

0b1

Records Unrecoverable errors.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

UC, bit [48]
When ERR<n>FR.FRX == 1:

Uncontainable Error recording. Describes whether the node supports recording Uncontainable errors.

UCMeaning
0b0

Does not record Uncontainable errors.

0b1

Records Uncontainable errors.


Otherwise:

Reserved for identifying IMPLEMENTATION DEFINED controls.

IMPLEMENTATION DEFINED, bits [47:32]

Reserved for identifying IMPLEMENTATION DEFINED controls.

FRX, bit [31]
When RAS System Architecture v1.1 is implemented:

Feature Register extension. Defines whether ERR<n>FR[63:48] are architecturally defined.

FRXMeaning
0b0

ERR<n>FR[63:48] are IMPLEMENTATION DEFINED.

0b1

ERR<n>FR[63:48] are defined by the architecture.


Otherwise:

Reserved, RES0.

Bits [30:26]

Reserved, RES0.

TS, bits [25:24]

Timestamp Extension. Indicates whether, for each error record <m> owned by this node, ERR<m>MISC3 is used as the timestamp register, and, if it is, the timebase used by the timestamp.

TSMeaning
0b00

Does not support a timestamp register.

0b01

Implements a timestamp register in ERR<n>MISC3 for each error record <m> owned by the node. The timestamp uses the same timebase as the system Generic Timer.

Note

For an error record that has an affinity to a PE, this is the same timer that is visible through CNTPCT_EL0 at the highest Exception level on that PE.

0b10

Implements a timestamp register in ERR<m>MISC3 for each error record <m> owned by the node. The timestamp uses an IMPLEMENTATION DEFINED timebase.

All other values are reserved.

CI, bits [23:22]

Critical error interrupt. Indicates whether the critical error interrupt and associated controls are implemented by the node.

CIMeaning
0b00

Does not support the critical error interrupt. ERR<n>CTLR.CI is RES0.

0b01

Critical error interrupt is supported and always enabled. ERR<n>CTLR.CI is RES0.

0b10

Critical error interrupt is supported and controllable using ERR<n>CTLR.CI.

All other values are reserved.

INJ, bits [21:20]

Fault Injection Extension. Indicates whether the Common Fault Injection Model Extension is implemented by the node.

INJMeaning
0b00

Does not support the Common Fault Injection Model Extension.

0b01

Supports the Common Fault Injection Model Extension. See ERR<n>PFGF for more information.

All other values are reserved.

CEO, bits [19:18]
When ERR<n>FR.CEC != 0b000:

Corrected Error overwrite. Indicates the behavior of the node when a second or subsequent Corrected error is recorded and a first Corrected error has previously been recorded by an error record <m> owned by the node.

CEOMeaning
0b00

Keeps the previous error syndrome.

0b01

If ERR<m>STATUS.OF is 1 before the Corrected error is counted, then the error record keeps the previous syndrome. Otherwise the previous syndrome is overwritten.

All other values are reserved.

The second or subsequent Corrected error is counted by the Corrected error counter, regardless of the value of this field. If counting the error causes unsigned overflow of the counter, then ERR<m>STATUS.OF is set to 1.

This means that, if no other error is subsequently recorded that overwrites the syndrome:


Otherwise:

Reserved, RES0.

DUI, bits [17:16]
When ERR<n>FR.UI != 0b00:

Error recovery interrupt for deferred errors control. Indicates whether the enabling and disabling of error recovery interrupts on deferred errors is supported by the node.

DUIMeaning
0b00

Does not support the enabling and disabling of error recovery interrupts on deferred errors. ERR<n>CTLR.DUI is RES0.

0b10

Enabling and disabling of error recovery interrupts on deferred errors is supported and controllable using ERR<n>CTLR.DUI.

0b11

Enabling and disabling of error recovery interrupts on deferred errors is supported, and controllable using ERR<n>CTLR.WDUI for writes and ERR<n>CTLR.RDUI for reads.

All other values are reserved.


Otherwise:

Reserved, RES0.

RP, bit [15]
When ERR<n>FR.CEC != 0b000:

Repeat counter. Indicates whether the node implements a second Corrected error counter in ERR<m>MISC0 for each error record <m> owned by the node that can record countable errors.

RPMeaning
0b0

Implements a single Corrected error counter in ERR<m>MISC0 for each error record <m> owned by the node that can record countable errors.

0b1

Implements a first (repeat) counter and a second (other) counter in ERR<m>MISC0 for each error record <m> owned by the node that can record countable errors. The repeat counter is the same size as the primary error counter.


Otherwise:

Reserved, RES0.

CEC, bits [14:12]

Corrected Error Counter. Indicates whether the node implements the standard Corrected error counter mechanisms in ERR<m>MISC0 for each error record <m> owned by the node that can record countable errors.

CECMeaning
0b000

Does not implement the standard Corrected error counter model.

0b010

Implements an 8-bit Corrected error counter in ERR<m>MISC0[39:32] for each error record <m> owned by the node that can record countable errors.

0b100

Implements a 16-bit Corrected error counter in ERR<m>MISC0[47:32] for each error record <m> owned by the node that can record countable errors.

All other values are reserved.

Note

Implementations might include other error counter models, or might include the standard model and not indicate this in ERR<n>FR.

CFI, bits [11:10]
When ERR<n>FR.FI != 0b00:

Fault handling interrupt for corrected errors control. Indicates whether the enabling and disabling of fault handling interrupts on corrected errors is supported by the node.

CFIMeaning
0b00

Does not support the enabling and disabling of fault handling interrupts on corrected errors. ERR<n>CTLR.CFI is RES0.

0b10

Enabling and disabling of fault handling interrupts on corrected errors is supported and controllable using ERR<n>CTLR.CFI.

0b11

Enabling and disabling of fault handling interrupts on corrected errors is supported, and controllable using ERR<n>CTLR.WCFI for writes and ERR<n>CTLR.RCFI for reads.

All other values are reserved.


Otherwise:

Reserved, RES0.

UE, bits [9:8]

In-band error reponse (External Abort). Indicates whether the in-band error response and associated controls are implemented by the node.

UEMeaning
0b00

Does not support the in-band error response. ERR<n>CTLR.UE is RES0.

0b01

In-band error response is supported and always enabled. ERR<n>CTLR.UE is RES0.

0b10

In-band error response is supported and controllable using ERR<n>CTLR.UE.

0b11

In-band error response is supported, and controllable using ERR<n>CTLR.WUE for writes and ERR<n>CTLR.RUE for reads.

It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester.

FI, bits [7:6]

Fault handling interrupt. Indicates whether the fault handling interrupt and associated controls are implemented by the node.

FIMeaning
0b00

Does not support the fault handling interrupt. ERR<n>CTLR.FI is RES0.

0b01

Fault handling interrupt is supported and always enabled. ERR<n>CTLR.FI is RES0.

0b10

Fault handling interrupt is supported and controllable using ERR<n>CTLR.FI.

0b11

Fault handling interrupt is supported, and controllable using ERR<n>CTLR.WFI for writes and ERR<n>CTLR.RFI for reads.

UI, bits [5:4]

Error recovery interrupt for uncorrected errors. Indicates whether the error handling interrupt and associated controls are implemented by the node.

UIMeaning
0b00

Does not support the error handling interrupt. ERR<n>CTLR.UI is RES0.

0b01

Error handling interrupt is supported and always enabled. ERR<n>CTLR.UI is RES0.

0b10

Error handling interrupt is supported and controllable using ERR<n>CTLR.UI.

0b11

Error handling interrupt is supported, and controllable using ERR<n>CTLR.WUI for writes and ERR<n>CTLR.RUI for reads.

IMPLEMENTATION DEFINED, bits [3:2]

IMPLEMENTATION DEFINED.

ED, bits [1:0]

Error reporting and logging. Indicates error record <n> is the first record owned the node, and whether the node implements the controls for enabling and disabling error reporting and logging.

EDMeaning
0b01

Error reporting and logging always enabled. ERR<n>CTLR.ED is RES0.

0b10

Error reporting and logging is controllable using ERR<n>CTLR.ED.

All other values are reserved.

Accessing ERR<n>FR

ERR<n>FR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0x000 + (64 * n)ERR<n>FR

Accesses on this interface are RO.


30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f

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