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The DC ISW characteristics are:
Invalidate data cache by set/way.
When FEAT_MTE2 is implemented, this instruction might invalidate Allocation Tags from caches. When it invalidates Allocation Tags from caches, it also cleans them.
AArch64 System instruction DC ISW performs the same function as AArch32 System instruction DCISW.
DC ISW is a 64-bit System instruction.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
SetWay | Level | RES0 |
Reserved, RES0.
Contains two fields:
Bits[L-1:4] are RES0.
A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).
ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.
Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.
Reserved, RES0.
If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b0111 | 0b0110 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.TSW == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCISW == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elseelsif EL2Enabled() && HCR_EL2.SWIO == '1' then
AArch64.DCDC_CISW(X[t],]);
elsif CacheType_Data,EL2Enabled() CacheOp_Invalidate&& HCR_EL2.<DC,VM> CacheOpScope_SetWay);!= '00' then
DC_CISW(X[t]);
else
DC_ISW(X[t]);
elsif PSTATE.EL == EL2 then
AArch64.DCDC_ISW(X[t], CacheType_Data, CacheOp_Invalidate, CacheOpScope_SetWay);]);
elsif PSTATE.EL == EL3 then
AArch64.DCDC_ISW(X[t], CacheType_Data, CacheOp_Invalidate, CacheOpScope_SetWay);]);
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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