The MSMON_OFLOW_MSI_ADDR_L characteristics are:
MSMON_OFLOW_MSI_ADDR_L is a 32-bit read/write register for the low part of the MPAM monitor MSI address.
The power domain of MSMON_OFLOW_MSI_ADDR_L is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAMv1p1 is implemented and MPAMF_MSMON_IDR.HAS_OFLW_MSI == 1. Otherwise, direct accesses to MSMON_OFLOW_MSI_ADDR_L are RES0.
MSMON_OFLOW_MSI_ADDR_L, MSMON_OFLOW_MSI_ADDR_H, MSMON_OFLOW_MSI_ATTR, MSMON_OFLOW_MSI_DATA, and MSMON_OFLOW_MSI_MPAM must all be implemented to support MSI writes for monitor overflow interrupts.
The power and reset domain of each MSC component is specific to that component.
MSMON_OFLOW_MSI_ADDR_L is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_ADDR_L | Bits[1:0] |
MSI write address bits[31:2].
Reads as 0b00.
Access to this field is RO.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.
MSMON_OFLOW_MSI_ADDR_L_s, MSMON_OFLOW_MSI_ADDR_L_ns, MSMON_OFLOW_MSI_ADDR_L_rt, and MSMON_OFLOW_MSI_ADDR_L_rl must be separate registers.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x08E0 | MSMON_OFLOW_MSI_ADDR_L_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x08E0 | MSMON_OFLOW_MSI_ADDR_L_ns |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x08E0 | MSMON_OFLOW_MSI_ADDR_L_rt |
When FEAT_RME is implemented access on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x08E0 | MSMON_OFLOW_MSI_ADDR_L_rl |
When FEAT_RME is implemented access on this interface are RW.
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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