The CNTP_TVAL characteristics are:
Holds the timer value for the EL1 physical timer.
The power domain of CNTP_TVAL is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTP_TVAL is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TimerValue |
The TimerValue view of the EL1 physical timer.
On a read of this register:
On a write of this register, CompareValue is set to (CNTPCT + TimerValue), where TimerValue is treated as a signed 32-bit integer.
When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:
When CNTP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count, so the TimerValue view appears to continue to count down.
The reset behaviour of this field is:
CNTP_TVAL can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.
'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:
For an implemented CNTBaseN frame:
For an implemented CNTEL0BaseN frame:
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTBaseN | 0x028 | CNTP_TVAL |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTEL0BaseN | 0x028 | CNTP_TVAL |
Accesses on this interface are RW.
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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