The AMDEVAFF0 characteristics are:
Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the AMU component relates to.
The power domain of AMDEVAFF0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMDEVAFF0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPIDR_EL1lo |
MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented Exception level.
Component | Offset | Instance |
---|---|---|
AMU | 0xFA8 | AMDEVAFF0 |
Accesses on this interface are RO.
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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