The TRCCIDR1 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCCIDR1 are RES0.
TRCCIDR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CLASS | PRMBL_1 |
Reserved, RES0.
Component class.
CLASS | Meaning |
---|---|
0b1001 |
CoreSight peripheral. |
Other values are defined by the CoreSight Architecture.
This field reads as 0x9.
Component identification preamble, segment 1.
Reads as 0b0000.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFF4 | TRCCIDR1 |
This interface is accessible as follows:
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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