The ID_AA64PFR0_EL1 characteristics are:
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
The external register EDPFR gives information from this register.
ID_AA64PFR0_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CSV3 | CSV2 | RME | DIT | AMU | MPAM | SEL2 | SVE | ||||||||||||||||||||||||
RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 |
Speculative use of faulting data. Defined values are:
CSV3 | Meaning |
---|---|
0b0000 |
This PE does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the load in the speculative sequence. |
0b0001 |
Data loaded under speculation with a permission or domain fault cannot be used to form an address or generate condition codes or SVE predicate values to be used by instructions newer than the load in the speculative sequence. |
All other values are reserved.
FEAT_CSV3 implements the functionality identified by the value 0b0001.
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.5, the only permitted value is 0b0001.
If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented.
Speculative use of out of context branch targets. Defined values are:
CSV2 | Meaning |
---|---|
0b0000 |
This PE does not disclose whether branch targets trained in one hardware-described context can exploitatively control speculative execution in a different hardware-described context. |
0b0001 |
Branch targets trained in one hardware-described context can exploitatively control speculative execution in a different hardware-described context only in a hard-to-determine way. Contexts do not include the SCXTNUM_ELx register contexts. Support for the SCXTNUM_ELx registers is defined in ID_AA64PFR1_EL1.CSV2_frac. |
0b0010 |
Branch targets trained in one hardware-described context can exploitatively control speculative execution in a different hardware-described context only in a hard-to-determine way. The SCXTNUM_ELx registers are supported and the contexts include the SCXTNUM_ELx register contexts. |
All other values are reserved.
FEAT_CSV2 implements the functionality identified by the value 0b0001.
FEAT_CSV2_2 implements the functionality identified by the value 0b0010.
In Armv8.0, the permitted values are 0b0000, 0b0001, and 0b0010.
From Armv8.5, the permitted values are 0b0001 and 0b0010.
Realm Management Extension (RME). Defined values are:
RME | Meaning |
---|---|
0b0000 |
Realm Management Extension not implemented. |
0b0001 |
RMEv1 is implemented. |
All other values are reserved.
FEAT_RME implements the functionality identified by the value 0b0001.
Data Independent Timing. Defined values are:
DIT | Meaning |
---|---|
0b0000 |
AArch64 does not guarantee constant execution time of any instructions. |
0b0001 |
AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions. |
All other values are reserved.
FEAT_DIT implements the functionality identified by the value 0b0001.
From Armv8.4, the only permitted value is 0b0001.
Indicates support for Activity Monitors Extension. Defined values are:
AMU | Meaning |
---|---|
0b0000 |
Activity Monitors Extension is not implemented. |
0b0001 |
FEAT_AMUv1 is implemented. |
0b0010 |
FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. |
All other values are reserved.
FEAT_AMUv1 implements the functionality identified by the value 0b0001.
FEAT_AMUv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0, the only permitted value is 0b0000.
In Armv8.4, the permitted values are 0b0000 and 0b0001.
From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010.
Indicates support for MPAM Extension. Defined values are:
MPAM | Meaning |
---|---|
0b0000 | If ID_AA64PFR1_EL1.MPAM_frac == 0b0000, MPAM Extension is not implemented. If ID_AA64PFR1_EL1.MPAM_frac == 0b0001, MPAM Extension version 0.1 is implemented. |
0b0001 | If ID_AA64PFR1_EL1.MPAM_frac == 0b0000, MPAM Extension version 1.0 is implemented. If ID_AA64PFR1_EL1.MPAM_frac == 0b0001, MPAM Extension version 1.1 is implemented. |
All other values are reserved.
Secure EL2. Defined values are:
SEL2 | Meaning |
---|---|
0b0000 |
Secure EL2 is not implemented. |
0b0001 |
Secure EL2 is implemented. |
All other values are reserved.
FEAT_SEL2 implements the functionality identified by the value 0b0001.
Scalable Vector Extension. Defined values are:
SVE | Meaning |
---|---|
0b0000 |
SVE architectural state and programmers' model are not implemented. |
0b0001 |
SVE architectural state and programmers' model are implemented. |
All other values are reserved.
If implemented, refer to ID_AA64ZFR0_EL1 for information about which SVE instructions are available.
RAS Extension version. Defined values are:
RAS | Meaning |
---|---|
0b0000 |
No RAS Extension. |
0b0001 |
RAS Extension implemented. |
0b0010 | FEAT_RASv1p1 implemented and, if EL3 is implemented, FEAT_DoubleFault implemented. As 0b0001, and adds support for:
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions. |
All other values are reserved.
FEAT_RAS implements the functionality identified by the value 0b0001.
FEAT_RASv1p1 and FEAT_DoubleFault implement the functionality identified by the value 0b0010.
In Armv8.0 and Armv8.1, the permitted values are 0b0000 and 0b0001.
In Armv8.2, the only permitted value is 0b0001.
From Armv8.4, if FEAT_DoubleFault is implemented, the only permitted value is 0b0010.
From Armv8.4, when FEAT_DoubleFault is not implemented, and ERRIDR_EL1 is 0, the permitted values are IMPLEMENTATION DEFINED 0b0001 or 0b0010.
When the value of this field is 0b0001, ID_AA64PFR1_EL1.RAS_frac indicates whether FEAT_RASv1p1 is implemented.
System register GIC CPU interface. Defined values are:
GIC | Meaning |
---|---|
0b0000 |
GIC CPU interface system registers not implemented. |
0b0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
0b0011 |
System register interface to version 4.1 of the GIC CPU interface is supported. |
All other values are reserved.
Advanced SIMD. Defined values are:
AdvSIMD | Meaning |
---|---|
0b0000 | Advanced SIMD is implemented, including support for the following SISD and SIMD operations:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Advanced SIMD is not implemented. |
All other values are reserved.
This field must have the same value as the FP field.
The permitted values are:
Floating-point. Defined values are:
FP | Meaning |
---|---|
0b0000 | Floating-point is implemented, and includes support for:
|
0b0001 |
As for 0b0000, and also includes support for half-precision floating-point arithmetic. |
0b1111 |
Floating-point is not implemented. |
All other values are reserved.
This field must have the same value as the AdvSIMD field.
The permitted values are:
EL3 Exception level handling. Defined values are:
EL3 | Meaning |
---|---|
0b0000 |
EL3 is not implemented. |
0b0001 |
EL3 can be executed in AArch64 state only. |
0b0010 |
EL3 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL2 Exception level handling. Defined values are:
EL2 | Meaning |
---|---|
0b0000 |
EL2 is not implemented. |
0b0001 |
EL2 can be executed in AArch64 state only. |
0b0010 |
EL2 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL1 Exception level handling. Defined values are:
EL1 | Meaning |
---|---|
0b0001 |
EL1 can be executed in AArch64 state only. |
0b0010 |
EL1 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL0 Exception level handling. Defined values are:
EL0 | Meaning |
---|---|
0b0001 |
EL0 can be executed in AArch64 state only. |
0b0010 |
EL0 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0100 | 0b000 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64PFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64PFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64PFR0_EL1;
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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