TRCCIDR1, Component Identification Register 1

The TRCCIDR1 characteristics are:

Purpose

Provides discovery information about the component.

For additional information, see the CoreSight Architecture Specification.

Configuration

This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCCIDR1 are RES0.

Attributes

TRCCIDR1 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0CLASSPRMBL_1

Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class.

CLASSMeaning
0b1001

CoreSight peripheral.

Other values are defined by the CoreSight Architecture.

This field reads as 0x9.

PRMBL_1, bits [3:0]

Component identification preamble, segment 1.

Reads as 0b0000.

Access to this field is RO.

Accessing TRCCIDR1

External debugger accesses to this register are unaffected by the OS Lock.

TRCCIDR1 can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0xFF4TRCCIDR1

This interface is accessible as follows:


30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

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