The DBGDTRRX_EL0 characteristics are:
Transfers data from an external debugger to the PE. For example, it is used by a debugger transferring commands and data to a debug target. See DBGDTR_EL0 for additional architectural mappings. It is a component of the Debug Communications Channel.
External register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch64 System register DBGDTRRX_EL0[31:0].
External register DBGDTRRX_EL0 bits [31:0] are architecturally mapped to AArch32 System register DBGDTRRXint[31:0].
DBGDTRRX_EL0 is in the Core power domain.
DBGDTRRX_EL0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Update DTRRX |
Update DTRRX.
Writes to this register:
If RXfull is set to 1, set DTRRX to UNKNOWN.
If RXfull is set to 0, update the value in DTRRX.
After the write, RXfull is set to 1.
Reads of this register:
If RXfull is set to 1, return the last value written to DTRRX.
If RXfull is set to 0, return an UNKNOWN value.
After the read, RXfull remains unchanged.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register'.
The reset behaviour of this field is:
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
Component | Offset | Instance |
---|---|---|
Debug | 0x080 | DBGDTRRX_EL0 |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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