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The ADFSR characteristics are:
Provides additional IMPLEMENTATION DEFINED fault status information for Data Abort exceptions taken to EL1 modes, and EL3 modes when EL3 is implemented and is using AArch32.
AArch32 System register ADFSR bits [31:0] are architecturally mapped to AArch64 System register AFSR0_EL1[31:0].
This register is present only when AArch32 is supported at EL0.any Exception level. Otherwise, direct accesses to ADFSR are UNDEFINED.
ADFSR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0101 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then return ADFSR_NS; else return ADFSR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then return ADFSR_NS; else return ADFSR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then return ADFSR_S; else return ADFSR_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0101 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T5 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T5 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then ADFSR_NS = R[t]; else ADFSR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then ADFSR_NS = R[t]; else ADFSR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then ADFSR_S = R[t]; else ADFSR_NS = R[t];
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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