System Register XML
for Armv9
(2021-06)
30 June 2021
1. Introduction
This is the 2021-06 release
of the System Registers XML for Armv9 A-profile architecture.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com. Give:
- The title, "System Register XML for Armv9".
- The version, "2021-06".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
2. Contents
3. Release notes
Armv9 change history
-
This release of the Armv9 architecture XML introduces FEAT_SME, Scalable Matrix Extension.
-
The BRBINFINJ_EL1.TYPE and BRBINF<n>_EL1.TYPE field descriptions are updated to have two separate values for
conditional and unconditional direct branches, and the function BRBEBranch() has been updated accordingly.
-
Field descriptions for PMBIDR_EL1.P and TRBIDR_EL1.P updated to include conditions on Realms and FEAT_RME.
-
Fields RLH, RLK, and RLU to control Realm filtering are added to the External and AArch64 PMCCFILTR registers, and RLU is added to the
AArch32 PMCCFILTR and AArch32 PMEVTYPER<n> registers.
-
EDSCR.NSE description is updated to define Security and Realm state behavior when FEAT_RME is implemented.
-
EDECCR.RTR3 and RTE3 are removed. EDECCR.SE3 and SR3 are updated to include Exception catch entry control.
-
GPTBR.BADDR and TLBI_RPAOS and TLBI_RPALOS SIZE and Address descriptions are changed to clarify ambiguities.
-
CFP RCTX, CPP RCTX, and DVP RCTX system instructions updated to indicate when the instruction is treated as a NOP.
-
TRCDEVARCH.VERSION value 0b0010 is added.
-
GPCCR_EL3.PGS updated to indicate behavior of TLBI if configured to a reserved value.
-
Where FEAT_RME is implemented, EDSCR.INTdis values extended to cover Realm or Root debug.
-
ID_AA64PFR1_EL1.SME field added.
-
SMPRI_EL1 and SMPRIMAP_EL2 register traps at EL3 corrected.
-
ID_AA64SMFR0_EL1.SMEver field added.
Armv9 known issues
-
HFGITR_EL2.SVC_ELx and HCR_EL2.TSC field descriptions will be clarified to indicate the exception
uses the Trap exception type, and the value of the encoding.
-
The BRBINFINJ_EL1.EL field value 0b11 will be added to indicate EL3.
-
The description of GPCCR_EL3.GPCP field value will be clarified.
Armv8.7 change history
-
The ITD and CP15BEN field descriptions in SCTLR_EL1, SCTLR_EL2, HSCTLR and SCTLR are corrected to indicate that
the controls must be implemented in either all or none of the registers.
-
Accessibility pseudocode has been updated in the following registers:
FPEXC, FPSCR, FPSID, MVFR0, MVFR1, MVFR2.
-
Mentions of Armv7 have been removed from the following registers:
-
The following registers have been updated to remove a redundant line from the description of the TargetList field
that ignores the RS field.
- AArch64: ICC_ASGI1R_EL1, ICC_SGI0R_EL1, ICC_SGI1R_EL1
- AArch32: ICC_ASGI1R, ICC_SGI0R, ICC_SGI1R
-
Correction to conditions when SCR_EL3.API traps accesses to instructions.
-
In the The ESR_ELx registers, the Rt, Rt2 and Rn field descriptions are updated to clarify the possible values when the field does not contain the AArch64 view of the register.
- ERR<n>PFGF.MV description clarifies the IMPLEMENTATION DEFINED behaviors controlled by this field value.
-
GIT_TYPER.INV field added.
-
Accessibility pseudocode for PMCEIDx_EL0 and PMCEIDx registers updated to trap to EL2 due to
HDFGRTR_EL2.PMCIDn_EL0.
-
The refactoring of the DC and IC System instructions moves the alternate access due to HCR_EL2.FB for
the IC instructions and the alternate access due to HCR_EL2.{DC, VM} for the DC instructions out of the
accessibility pseudocode and into the shared pseudocode. The architecture is not changed.
-
Pseudocode functions for AArch32 and AArch64 DC and IC System instructions are added and called from the System
instruction accessibility pseudocode.
-
GIC registers are now conditional on GIC feature implementation.
-
Clarification of GICD_ICFGRnE, GICR_ICFGR0 and GICR_ICFGRnE.IntConfig field values.
-
Relaxation of SPEv1p2, makes implementation of last branch target address OPTIONAL.
-
The architecture deprecates any use of MDRAR_EL1 and DBGDRAR. The Valid field descriptions in these registers
are updated to indicate that Arm recommends this field is set to zero.
-
The value text description of EDSCR.RW is clarified for the case where the PE is executing at EL1 or above and EL0
using AArch32 is supported.
-
The TTBRx_ELy.BADDR fields description of generating an Address size fault is updated to refer to the Effective
value of TCR_ELy.{I}PS.
-
The condition for the SCTLR.EnRCTX field is corrected from FEAT_CSV2 to FEAT_SPECRES.
-
The HCR_EL2.{AMO, IMO, FMO} field descriptions are ambiguous and hence clarified as to when interrupts are taken.
-
The definitions of the FPEXC.EN and FPEXC32_EL2.EN fields are updated to clarify that the Effective value of
HCR_EL2.RW should be used to determine the behavior.
-
The P<n> field description in the AArch64, AArch32 and External AMCNTENCLRx and AMCTENSETx registers is
updated to cover the case where N is 16.
-
CNTHCTL_EL2.EVNTEN and CNTKCTL_EL1.EVNTEN are corrected to reset to an architecturally UNKNOWN value in all cases.
-
The EL2 conditions for the behavior of values 0b110x and 0b10xx in the EDSCR.RW field are corrected.
-
The ID_AA64MMFR0_EL1.TGranx_2 field descriptions are updated to clarify they do not use the usual ID scheme.
-
The PMSIDR_EL1.MaxSize field description is updated to clarify that the values 0b0100 and 0b0101 are not
permitted.
-
Tables showing register value/Group priority split mapping have been removed, and text is updated to avoid
repeating information in the following fields:
- ICC_BPR1_EL1.BinaryPoint
- ICC_BPR1.BinaryPoint
-
The permitted values that identify FEAT_EVT in ID_MMFR4_EL1.EVT and ID_MMFR4.EVT descriptions
have been clarified to indicate the dependency on support for AArch32.
-
The 'Configuration' in the ID_AA64ISAR2_EL1 description incorrectly specified that this register is present from
Armv8.7. This is corrected to indicate that this register was previously unnamed and reserved, RES0.
-
Renamed the Pseudocode condition functions HaveAnyAArch32() to HaveAArch32() and HaveAnyAArch64()
to HaveAArch64() and updated the function comments to clarify their meaning. Removed the function
HighestELUsingAArch32() and changed usage to !HaveAArch64().
-
The SCR_EL3.ATA, HCR_EL2.ATA and SCTLR_ELx.ATA fields have been clarified to indicate that they are no longer permitted to be cached in a TLB.
-
CTICONTROL.GLBEN is updated to relax the effect on ongoing triggers to be de-asserted when GLBEN is changed from 1
to 0.
-
Corrected ID_ISAR4.SMC and ID_ISAR4_EL1.SMC descriptions to indicate the role of EL3.
-
The FPCR.{FZ, AH, FIZ} fields are updated to correctly reflect the behavior of FEAT_AFP.
-
The MPAMIDR_EL1.HAS_TIDR field description is updated to recommend that MPAM2.TIDR is implemented.
-
The reserved type for the HWU* fields is corrected from RES0 to RAZ/WI in the following System registers: TCR_EL1,
TCR_EL2, TCR_EL3, VTCR_EL2, TTBCR2, VTCR. TTBCR.T2E is similarly corrected.
-
ID_AA64ISAR2_EL1.WFxT value 0b0010 is defined to indicate that the register number is recorded in bits [9:5] of
the ISS of ESR_ELx for trapped WFxT instructions.
-
The accessibility pseudocode for write to the Secure instance of TTBR1 at EL3 is updated to include checks for
CP15SDISABLE2 signal.
-
The VMID and ASID fields in the CFP RCTX, CPP RCTX, and DVP RCTX System instructions are updated to indicate that
software in implementations that support 16 bits of VMID and ASID must write the upper 8 bits to 0 when the
affected context only uses 8 bits.
-
The external view of PMMIR is updated to add BUS_WIDTH and BUS_SLOTS fields.
-
The following RAZ fields in External AMU registers are relaxed to RES0, to align with a previous relaxation to
RES0 in the architecturally mapped AArch64 and AArch32 views of the registers:
AMEVTYPER0<n>, bits [31:25], AMEVTYPER1<n>, bits [31:25], AMCR, bits [9:0].
-
References to writability are removed from the following External AMU registers, as they are accessed through the
read-only memory-mapped interface:
AMCNTENCLR0, AMCNTENCLR1, AMCNTENSET0, AMCNTENSET1, AMEVCNTR0<n>, AMEVCNTR1<n>, AMEVTYPER0<n>,
AMEVTYPER1<n>.
-
The Purpose of the following System instructions is updated to clarify the PE executing the instruction:
- AArch64: IC IALLU, IC IALLUIS.
- AArch32: IC IALLU, ICI ALLUIS.
-
The CSV3 field descriptions in the following registers have been updated to allow for the possibility of transient
reordering within the speculation sequences:
- AArch64: ID_AA64PFR0_EL1, ID_PFR2_EL1
- AArch32: ID_PFR2
-
PMBIDR_EL1.P description of the Owning Exception level is clarified.
-
The value and description of MPAM2_EL2.SDEFLT is updated to include PMG.
Armv8.7 known issues
-
The accessibility pseudocode will be updated to represent the generic timer registers accesses more
accurately.
-
Pseudocode functions for AArch32 and AArch64 AT System Instructions will be added and called from the System Instruction accessibility pseudocode
-
Recommendations for ERR<n>STATUS will be clarified.
-
ICC_CTLR_EL3.RM description will be clarified.
-
In GICF_ISPENDR<n> and GICD_ICPENDR<n>, the meaning of field array value 1 will be clarified.
Potential upcoming changes
We are looking in improvements to the information that is provided in the XML. In some cases these changes may
impact users. Here is a list of areas where we may make change in a future release:
-
When bits of two registers are architecturally mapped, it is captured in XML via (mapped_from_startbit,
mapped_from_endbit) and (mapped_to_startbit, mapped_to_endbit) tags. This does not allow for succinctly describing
a non-contiguous mapping. We are looking into refining the presentation in a future release.
-
We are looking at separating accessors (instructions/external accesses) from registers. This is likely to impact
"Index by Encoding", "External registers by offset" and may introduce separate pages for instructions/accessors
vs. the registers. This may impact the schema and the presentation of the content.
-
Some changes to register names may be introduced and there may be changes to the number of registers or names. The
instructions accessing registers would be unchanged preserving the architecture intent.
-
Register accesses that always look like simple reads or writes might be extended to have some ASL expressions.
Where register accesses cause additional side effects, ASL functions that describe these effects would be added.
Currently these details are only expressed in text.
-
We are considering the obsoletion of some DTD elements based on usage and analysis.
-
The instruction encoding tables currently present values as binary values, with the prefix "0b". We are
considering whether these values are better represented in a syntax compatible with pseudocode.
-
The reset information in the 'Configuration' section of some register descriptions have incorrect information, and
must not be relied upon. Please refer to the field descriptions for the correct reset information. The information
in the 'Configuration' section will be removed in a future release.
4. Documentation
General
A description within the XML contains the following sections:
- Purpose
-
A short description of the purpose of the register in the
Armv8 Architecture.
- Configuration
-
How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here.
- Attributes
-
The size of the register.
- Field descriptions
-
The register diagram and a description of the behavior of each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Accessing ...
-
The address or offset of the register in the memory map, and
the accessibility.
System registers
A System register description also contains an "Accessing ..." section, that includes:
-
The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
-
Pseudocode that describes the execution of all instructions
used to access the register, including information about
traps and enables that apply upon that access.
-
For some System registers, additional text is provided which
gives extra information regarding the access to the
register.
-
The accessibility pseudocode for a register assumes that
that register is implemented and that all features which
affects its accesses are implemented. In most cases, the
behavior upon access to a register is determined in part or
in whole by the Exception level at which it is accessed.