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The CTIPIDR2 characteristics are:
Provides information to identify a CTI component.
For more information, see 'About the Peripheral identification scheme'.
CTIPIDR2 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR2 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
Part major revision. Parts can also use this field to extend Part number to 16-bits.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
RAO. Indicates a JEP106 identity code is used.
Reads as 0b1.
Access to this field is RO.
Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
CTI | 0xFE8 | CTIPIDR2 |
Accesses on this interface are RO.
30/06/2021 1509:2139; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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