The TLBI RPAOS characteristics are:
Invalidates cached copies of GPT entries from TLBs. Details:
The invalidation applies to TLB entries containing GPT information relating to a physical address.
The invalidation affects all TLBs in the Outer Shareable domain.
Invalidates TLB entries containing GPT information from all levels of the GPT walk that relates to the supplied physical address.
Invalidations are range-based, invalidating TLB entries starting from the address in BaseADDR, within the range as specified by SIZE.
The full set of TLB maintenance instructions that invalidate cached GPT entries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.
These instructions have the same ordering, observability, and completion behavior as all other TLBI instructions.
This instruction is present only when FEAT_RME is implemented. Otherwise, direct accesses to TLBI RPAOS are UNDEFINED.
TLBI RPAOS is a 64-bit System instruction.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SIZE | RES0 | Address | ||||||||||||||||||||||||||||
Address |
Reserved, RES0.
Size of the range for invalidation.
If SIZE is a reserved value, no TLB entries are required to be invalidated.
SIZE | Meaning |
---|---|
0b0000 |
4KB. |
0b0001 |
16KB. |
0b0010 |
64KB. |
0b0011 |
2MB. |
0b0100 |
32MB. |
0b0101 |
512MB. |
0b0110 |
1GB. |
0b0111 |
16GB. |
0b1000 |
64GB. |
0b1001 |
512GB. |
All other values are reserved.
Reserved, RES0.
The starting address for the range of the maintenance instruction.
This field is decoded with reference to the value of GPCCR_EL3.PGS to give BaseADDR as follows:
GPCCR_EL3.PGS | BaseADDR |
---|---|
0b00 (4KB) | BaseADDR[51:12] = Xt[39:0] |
0b10 (16KB) | BaseADDR[51:14] = Xt[39:2] |
0b01 (64KB) | BaseADDR[51:16] = Xt[39:4] |
If BaseADDR is not aligned with the size specified in SIZE, no TLB entries are required to be invalidated.
Other bits of BaseADDR are taken as zero.
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b110 | 0b1000 | 0b0100 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then AArch64.TLBI_RPA(TLBILevel_Any, X[t], Shareability_OSH);
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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