(old) | htmldiff from- | (new) |
The DCCISW characteristics are:
Clean and Invalidate data or unified cache line by set/way.
AArch32 System instruction DCCISW performs the same function as AArch64 System instruction DC CISW.
This instruction is present only when AArch32 is supported at EL0.any Exception level. Otherwise, direct accesses to DCCISW are UNDEFINED.
DCCISW is a 32-bit System instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SetWay | Level | RES0 |
Contains two fields:
Bits[L-1:4] are RES0.
A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).
ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.
Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.
Reserved, RES0.
If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:
Accesses to this instruction use the following encodings in the System instruction encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b1110 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TSW == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TSW == '1' then
AArch32.TakeHypTrapException(0x03);
else
AArch32.DCDCCISW(R[t], CacheOp_CleanInvalidate, CacheOpScope_SetWay);]);
elsif PSTATE.EL == EL2 then
AArch32.DCDCCISW(R[t], CacheOp_CleanInvalidate, CacheOpScope_SetWay);]);
elsif PSTATE.EL == EL3 then
AArch32.DCDCCISW(R[t], CacheOp_CleanInvalidate, CacheOpScope_SetWay);]);
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |