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The IC IALLU characteristics are:
Invalidate all instruction caches of the PE executing the instruction to the Point of Unification.
AArch64 System instruction IC IALLU performs the same function as AArch32 System instruction ICIALLU.
IC IALLU is a 64-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
The instruction is UNDEFINED.
The instruction behaves as if the Rt field is set to 0b11111.
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b0111 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.TPU == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.TOCU == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ICIALLU == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.FB == '1' then
AArch64.IC(CacheOpScope_ALLUIS);IC_IALLUIS();
else
AArch64.IC(CacheOpScope_ALLU);IC_IALLU();
elsif PSTATE.EL == EL2 then
AArch64.IC(CacheOpScope_ALLU);IC_IALLU();
elsif PSTATE.EL == EL3 then
AArch64.IC(CacheOpScope_ALLU);IC_IALLU();
30/06/2021 1509:2139; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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