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The MPAMSM_EL1 characteristics are:
Holds information to generate MPAM labels for memory requests issued by SME, SVE, and SIMD&FP load and store instructions when the PE is in Streaming SVE mode. For those requests, the MPAM labels in this register have precedence over the labels in MPAM0_EL1, MPAM1_EL1, MPAM2_EL2, and MPAM3_EL3.
It is IMPLEMENTATION DEFINED whether the MPAM labels in this register are used for memory requests due to hardware page table walks and page table updates performed as a result of SME, SVE, and SIMD&FP load/store instructions, and SVE prefetch instructions, when the PE is in Streaming SVE mode.
For memory requests issued from EL0, the MPAM PARTID in this register is virtual and mapped into a physical PARTID when all of the following are true:
For memory requests issued from EL1, the MPAM PARTID in this register is virtual and mapped into a physical PARTID when all of the following are true:
This register is present only when FEAT_MPAM is implemented and FEAT_SME is implemented. Otherwise, direct accesses to MPAMSM_EL1 are UNDEFINED.
MPAMSM_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PMG_D | RES0 | |||||||||||||||||||||||||||||
PARTID_D | RES0 |
Reserved, RES0.
Performance monitoring group property for PARTID_D.
The reset behaviour of this field is:
Reserved, RES0.
Partition ID for data accesses due to the execution of SME, SVE, and SIMD&FP load and store instructions performed when the PE is in Streaming SVE mode, at any Exception level.
The reset behaviour of this field is:
Reserved, RES0.
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1010 | 0b0101 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.EnMPAMSM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else return MPAMSM_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return MPAMSM_EL1; elsif PSTATE.EL == EL3 then return MPAMSM_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1010 | 0b0101 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.EnMPAMSM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else MPAMSM_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MPAMSM_EL1 = X[t]; elsif PSTATE.EL == EL3 then MPAMSM_EL1 = X[t];
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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