The GICR_ICPENDR0 characteristics are:
Removes the pending state from the corresponding SGI or PPI.
A copy of this register is provided for each Redistributor.
GICR_ICPENDR0 is a 32-bit register.
Removes the pending state from interrupt number x. Reads and writes have the following behavior:
Clear_pending_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that the corresponding interrupt is not pending. If written, has no effect. |
0b1 | If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:
|
The reset behaviour of this field is:
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ICPENDR<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ICENABLER<n>.
When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0280 | GICR_ICPENDR0 |
This interface is accessible as follows:
30/06/2021 15:21; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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