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The DCCIMVAC characteristics are:
Clean and Invalidate data or unified cache line by virtual address to PoC.
AArch32 System instruction DCCIMVAC performs the same function as AArch64 System instruction DC CIVAC.
This instruction is present only when AArch32 is supported at EL0.any Exception level. Otherwise, direct accesses to DCCIMVAC are UNDEFINED.
DCCIMVAC is a 32-bit System instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use |
Virtual address to use. No alignment restrictions apply to this VA.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'AArch32 data cache maintenance instructions (DC*)'.
Accesses to this instruction use the following encodings in the System instruction encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b1110 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPCP == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TPC == '1' then
AArch32.TakeHypTrapException(0x03);
else
AArch32.DCDCCIMVAC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC);]);
elsif PSTATE.EL == EL2 then
AArch32.DCDCCIMVAC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC);]);
elsif PSTATE.EL == EL3 then
AArch32.DCDCCIMVAC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC);]);
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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