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The FPEXC32_EL2 characteristics are:
Allows access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.
AArch64 System register FPEXC32_EL2 bits [31:0] are architecturally mapped to AArch32 System register FPEXC[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to FPEXC32_EL2 are UNDEFINED.
If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.
Implemented only if the implementation includes the Advanced SIMD and floating-point functionality.
FPEXC32_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
EX | EN | DEX | FP2V | VV | TFV | RES0 | VECITR | IDF | RES0 | IXF | UFF | OFF | DZF | IOF |
Reserved, RES0.
Exception bit. From Armv8, this bit is RAZ/WI.
The reset behaviour of this field is:
Enables access to the Advanced SIMD and floating-point functionality from all Exception levels, except that setting this field to 0 does not disable the following:
EN | Meaning |
---|---|
0b0 | Accesses to the FPSCR, and any of the SIMD and floating-point registers Q0-Q15, including their views as D0-D31 registers or S0-S31 registers, are UNDEFINED at all Exception levels. |
0b1 | This control permits access to the Advanced SIMD and floating-point functionality at all Exception levels. |
Execution of Advanced SIMD and floating-point instructions in AArch32 state can be disabled or trapped by the following controls:
See the descriptions of the controls for more information.
When executing at EL0 using AArch32:
The reset behaviour of this field is:
Defined synchronous exception on floating-point execution.
This field identifies whether a synchronous exception generated by the attempted execution of an instruction was generated by an unallocated encoding. The instruction must be in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr() returning TRUE. This field also indicates whether the FPEXC32_EL2.TFV field is valid.
The meaning of this bit is:
DEX | Meaning |
---|---|
0b0 | The exception was generated by the attempted execution of an unallocated instruction in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr(). If FPEXC32_EL2.TFV is RW then it is invalid and UNKNOWN. If FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} are RW then they are invalid and UNKNOWN. |
0b1 | The exception was generated during the execution of an allocated encoding. FPEXC32_EL2.TFV is valid and indicates the cause of the exception. |
On an exception that sets this bit to 1 the exception-handling routine must clear this bit to 0.
On an implementation that both does not support trapping of floating-point exceptions and implements the AArch32 FPSCR.{Stride, Len} fields as RAZ, this bit is RES0.
The reset behaviour of this field is:
FPINST2 instruction valid bit. From Armv8, this bit is RES0.
The reset behaviour of this field is:
VECITR valid bit. From Armv8, this bit is RES0.
The reset behaviour of this field is:
Trapped Fault Valid bit. Valid only when the value of FPEXC.DEX is 1. When valid, it indicates the cause of the exception and therefore whether the FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} bits are valid.
TFV | Meaning |
---|---|
0b0 | The exception was caused by the execution of a floating-point VABS, VADD, VDIV, VFMA, VFMS, VFNMA, VFNMS, VMLA, VMLS, VMOV, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VSQRT, or VSUB instruction when one or both of FPSCR.{Stride, Len} was non-zero. If the FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} bits are RW then they are invalid and UNKNOWN. |
0b1 | FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} indicate the presence of trapped floating-point exceptions that had occurred at the time of the exception. Bits are set for all trapped exceptions that had occurred at the time of the exception. |
This bit returns a status value and ignores writes.
When the value of FPEXC.DEX is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
On an implementation that supports the trapping of floating-point exceptions and implements FPSCR.{Stride, Len} as RAZ, this bit is RAO/WI.
The reset behaviour of this field is:
Reserved, RES0.
Vector iteration count. From Armv8, this field is RES1.
The reset behaviour of this field is:
Input Denormal trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Input Denormal exception occurred while FPSCR.IDE was 1:
IDF | Meaning |
---|---|
0b0 | Input Denormal exception has not occurred. |
0b1 | Input Denormal exception has occurred. |
Input Denormal exceptions can occur only when FPSCR.FZ is 1.
A half-precision floating-point value that is flushed to zero because the value of FPSCR.FZ16 is 1 does not generate an Input Denormal exception.
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC32_EL2.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Reserved, RES0.
Inexact trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Inexact exception occurred while FPSCR.IXE was 1:
IXF | Meaning |
---|---|
0b0 | Inexact exception has not occurred. |
0b1 | Inexact exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Underflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Underflow exception occurred while FPSCR.UFE was 1:
UFF | Meaning |
---|---|
0b0 | Underflow exception has not occurred. |
0b1 | Underflow exception has occurred. |
Underflow trapped exceptions can occur:
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC32_EL2.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Overflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Overflow exception occurred while FPSCR.OFE was 1:
OFF | Meaning |
---|---|
0b0 | Overflow exception has not occurred. |
0b1 | Overflow exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Divide by Zero trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether a Divide by Zero exception occurred while FPSCR.DZE was 1:
DZF | Meaning |
---|---|
0b0 | Divide by Zero exception has not occurred. |
0b1 | Divide by Zero exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Invalid Operation trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Invalid Operation exception occurred while FPSCR.IOE was 1:
IOF | Meaning |
---|---|
0b0 | Invalid Operation exception has not occurred. |
0b1 | Invalid Operation exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0101 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else return FPEXC32_EL2; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else return FPEXC32_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0101 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HCR_EL2.E2H == '1' && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPEXC32_EL2 = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPEXC32_EL2 = X[t];
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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