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PMBIDR_EL1, Profiling Buffer ID Register

The PMBIDR_EL1 characteristics are:

Purpose

Provides information to software as to whether the buffer can be programmed at the current Exception level.

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMBIDR_EL1 are UNDEFINED.

Attributes

PMBIDR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0FPAlign

Bits [63:6]

Reserved, RES0.

F, bit [5]

Flag updates. Defines whether the address translation performed by the Profiling Buffer manages the Access Flag and dirty state. Defined values are:

FMeaning
0b0

Hardware management of the Access Flag and dirty state for accesses made by the Statistical Profiling Extension is always disabled for all translation stages.

0b1

Hardware management for the Access Flag and dirty state for accesses made by the Statistical Profiling Extension is controlled in the same way as explicit memory accesses in the owning translation regime.

If hardware management of the Access Flag is disabled for a stage of translation, an access to Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.

If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor might generate a Permission fault, depending on the values of the access permission bits in the descriptor.

P, bit [4]

Programming not allowed. WhenThe read at EL3, this field reads as zero. Otherwise, indicates that the Profiling Buffer is owned by a higher Exception level or anotherthe other Security state. Defined values are:

PMeaning
0b0

ProgrammingProfiling Buffer is allowed.owned by the current or a lower Exception level in the current Security state.

0b1

ProgrammingProfiling notBuffer allowed.is owned by a higher Exception level or the other Security state.

The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSPB, and MDCR_EL3.NSPBE, and MDCR_EL2.E2PB:

Align, bits [3:0]

Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then the PE must pad every record up to a multiple of this size. Defined values are:

AlignMeaning
0b0000

Byte

0b0001

Halfword.

0b0010

Word.

0b0011

Doubleword.

0b0100

16 Bytes.

0b0101

32 Bytes.

0b0110

64 Bytes.

0b0111

128 Bytes.

0b1000

256 Bytes.

0b1001

512 Bytes.

0b1010

1KB.

0b1011

2KB.

For more information, see 'Restrictions on the current write pointer'.

Accessing PMBIDR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMBIDR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10100b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMBIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return PMBIDR_EL1; elsif PSTATE.EL == EL2 then return PMBIDR_EL1; elsif PSTATE.EL == EL3 then return PMBIDR_EL1;


30/06/2021 1509:2240; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

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