The PAR_EL1 characteristics are:
Returns the output address (OA) from an Address translation instruction that executed successfully, or fault information if the instruction did not execute successfully.
AArch64 System register PAR_EL1 bits [63:0] are architecturally mapped to AArch32 System register PAR[63:0].
PAR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATTR | RES0 | PA[51:48] | PA[47:12] | ||||||||||||||||||||||||||||
PA[47:12] | NSE | IMPLEMENTATION DEFINED | NS | SH | RES0 | F |
This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
On a successful conversion, the PAR_EL1 can return a value that indicates the resulting attributes, rather than the values that appear in the translation table descriptors. More precisely:
Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR_EL1, MAIR_EL2, and MAIR_EL3.
The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.
The attributes presented are consistent with the stages of translation applied in the address translation instruction. If the instruction performed a stage 1 translation only, the attributes are from the stage 1 translation. If the instruction performed a stage 1 and stage 2 translation, the attributes are from the combined stage 1 and stage 2 translation.
The reset behaviour of this field is:
Reserved, RES0.
Extension to PA[47:12]. For more information, see PA[47:12].
The reset behaviour of this field is:
Reserved, RES0.
Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[47:12].
When FEAT_LPA is implemented and 52-bit addresses are in use, PA[51:48] forms the upper part of the address value. Otherwise, when 52-bit addresses are not in use, PA[51:48] is RES0.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
The reset behaviour of this field is:
Reports the NSE attribute for a translation table entry from the EL3 translation regime.
For a description of the values derived by evaluating NS and NSE together, see PAR_EL1.NS.
For a result from a Secure, Non-secure, or Realm translation regime, this bit is UNKNOWN.
Reserved, RES1.
IMPLEMENTATION DEFINED.
The reset behaviour of this field is:
Non-secure. The NS attribute for a translation table entry from a Secure translation regime, a Realm translation regime, and the EL3 translation regime.
For a result from an EL3 translation regime, NS and NSE are evaluated together to report the physical address space:
NSE | NS | Meaning |
---|---|---|
0b0 | 0b0 | Secure. |
0b0 | 0b1 | Non-secure. |
0b1 | 0b0 | Root. |
0b1 | 0b1 | Realm. |
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit reflects the Security state of the intermediate physical address space of the translation for the instructions:
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
For a result from an S1E1 or S1E0 operation on the Realm EL1&0 translation regime, this bit is UNKNOWN.
The reset behaviour of this field is:
Non-secure. The NS attribute for a translation table entry from a Secure translation regime.
For a result from a Secure translation regime, when SCR_EL3.EEL2 is 1, this bit reflects the Security state of the intermediate physical address space of the translation for the instructions:
Otherwise, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.
For a result from a Non-secure translation regime, this bit is UNKNOWN.
The reset behaviour of this field is:
Shareability attribute, for the returned output address.
SH | Meaning |
---|---|
0b00 |
Non-shareable. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
The value 0b01 is reserved.
This field returns the value 0b10 for:
The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.
The reset behaviour of this field is:
Reserved, RES0.
Indicates whether the instruction performed a successful address translation.
F | Meaning |
---|---|
0b0 |
Address translation completed successfully. |
The reset behaviour of this field is:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | RES0 | ||||||||||||||||||||||||||||
RES0 | RES1 | RES0 | S | PTW | RES0 | FST | F |
This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.
IMPLEMENTATION DEFINED.
The reset behaviour of this field is:
IMPLEMENTATION DEFINED.
The reset behaviour of this field is:
IMPLEMENTATION DEFINED.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Indicates the translation stage at which the translation aborted:
S | Meaning |
---|---|
0b0 |
Translation aborted because of a fault in the stage 1 translation. |
0b1 |
Translation aborted because of a fault in the stage 2 translation. |
The reset behaviour of this field is:
If this bit is set to 1, it indicates the translation aborted because of a stage 2 fault during a stage 1 translation table walk.
The reset behaviour of this field is:
Reserved, RES0.
Fault status code, as shown in the Data Abort ESR encoding.
FST | Meaning | Applies when |
---|---|---|
0b000000 |
Address size fault, level 0 of translation or translation table base register. | |
0b000001 |
Address size fault, level 1. | |
0b000010 |
Address size fault, level 2. | |
0b000011 |
Address size fault, level 3. | |
0b000100 |
Translation fault, level 0. | |
0b000101 |
Translation fault, level 1. | |
0b000110 |
Translation fault, level 2. | |
0b000111 |
Translation fault, level 3. | |
0b001001 |
Access flag fault, level 1. | |
0b001010 |
Access flag fault, level 2. | |
0b001011 |
Access flag fault, level 3. | |
0b001000 |
Access flag fault, level 0. | When FEAT_LPA2 is implemented |
0b001100 |
Permission fault, level 0. | When FEAT_LPA2 is implemented |
0b001101 |
Permission fault, level 1. | |
0b001110 |
Permission fault, level 2. | |
0b001111 |
Permission fault, level 3. | |
0b010011 |
Synchronous External abort on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented |
0b010100 |
Synchronous External abort on translation table walk or hardware update of translation table, level 0. | |
0b010101 |
Synchronous External abort on translation table walk or hardware update of translation table, level 1. | |
0b010110 |
Synchronous External abort on translation table walk or hardware update of translation table, level 2. | |
0b010111 |
Synchronous External abort on translation table walk or hardware update of translation table, level 3. | |
0b011011 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented and FEAT_RAS is not implemented |
0b011100 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 0. | When FEAT_RAS is not implemented |
0b011101 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 1. | When FEAT_RAS is not implemented |
0b011110 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 2. | When FEAT_RAS is not implemented |
0b011111 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level 3. | When FEAT_RAS is not implemented |
0b100011 |
Granule Protection Fault on translation table walk or hardware update of translation table, level -1. | When FEAT_RME is implemented and FEAT_LPA2 is implemented |
0b100100 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 0. | When FEAT_RME is implemented |
0b100101 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 1. | When FEAT_RME is implemented |
0b100110 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 2. | When FEAT_RME is implemented |
0b100111 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 3. | When FEAT_RME is implemented |
0b101000 |
Granule Protection Fault, not on translation table walk or hardware update of translation table. | When FEAT_RME is implemented |
0b101001 |
Address size fault, level -1. | When FEAT_LPA2 is implemented |
0b101011 |
Translation fault, level -1. | When FEAT_LPA2 is implemented |
0b110000 |
TLB conflict abort. | |
0b110001 |
Unsupported atomic hardware update fault. | When FEAT_HAFDBS is implemented |
0b111101 |
Section Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format. | When EL1 is capable of using AArch32 |
0b111110 |
Page Domain fault, from an AArch32 stage 1 EL1&0 translation regime using Short-descriptor translation table format. | When EL1 is capable of using AArch32 |
The reset behaviour of this field is:
Indicates whether the instruction performed a successful address translation.
F | Meaning |
---|---|
0b1 |
Address translation aborted. |
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0111 | 0b0100 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.PAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return PAR_EL1; elsif PSTATE.EL == EL2 then return PAR_EL1; elsif PSTATE.EL == EL3 then return PAR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0111 | 0b0100 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.PAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else PAR_EL1 = X[t]; elsif PSTATE.EL == EL2 then PAR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PAR_EL1 = X[t];
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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