AMCR, Activity Monitors Control Register

The AMCR characteristics are:

Purpose

Global control register for the activity monitors implementation. AMCR is applicable to both the architected and the auxiliary counter groups.

Configuration

External register AMCR bits [31:0] are architecturally mapped to AArch64 System register AMCR_EL0[31:0].

External register AMCR bits [31:0] are architecturally mapped to AArch32 System register AMCR[31:0].

The power domain of AMCR is IMPLEMENTATION DEFINED.

This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCR are RES0.

Attributes

AMCR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0HDBGRAZ/WI

Bits [31:11]

Reserved, RES0.

HDBG, bit [10]

This bit controls whether activity monitor counting is halted when the PE is halted in Debug state.

HDBGMeaning
0b0

Activity monitors do not halt counting when the PE is halted in Debug state.

0b1

Activity monitors halt counting when the PE is halted in Debug state.

The reset behaviour of this field is:

Bits [9:0]

Reserved, RAZ/WI.

Accessing AMCR

AMCR can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xE04AMCR

Accesses on this interface are RO.


30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.