The ATS12NSOUR characteristics are:
Performs stage 1 and 2 address translations as defined for PL0 and the Non-secure state, with permissions as if reading from the given virtual address.
This instruction is present only when AArch32 is supported at EL0. Otherwise, direct accesses to ATS12NSOUR are UNDEFINED.
ATS12NSOUR is a 32-bit System instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Input address for translation |
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. The resulting address is the PA that is the output address of the stage 2 translation.
Accesses to this instruction use the following encodings in the System instruction encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then ATS12NSOUR(R[t]); elsif PSTATE.EL == EL3 then ATS12NSOUR(R[t]);
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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