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The EDSCR characteristics are:
Main control register for the debug implementation.
External register EDSCR bits [30:29] are architecturally mapped to AArch64 System register MDCCSR_EL0[30:29].
EDSCR is in the Core power domain.
EDSCR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TFO | RXfull | TXfull | ITO | RXO | TXU | PipeAdv | ITE | INTdis | TDA | MA | SC2 | NS | RES0 | SDD | NSE | HDE | RW | EL | A | ERR | STATUS |
Trace Filter Override. Overrides the Trace Filter controls allowing the external debugger to trace any visible Exception level.
TFO | Meaning |
---|---|
0b0 | Trace Filter controls are not affected. |
0b1 | Trace Filter controls in TRFCR_EL1 and |
When OSLSR_EL1.OSLK == 1, this bit can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
This bit is ignored by the PE when ExternalSecureNoninvasiveDebugEnabled() == FALSE and the Effective value of MDCR_EL3.STE == 1.
The reset behaviour of this field is:
Reserved, RES0.
DTRRX full.
The reset behaviour of this field is:
Access to this field is RO.
DTRTX full.
The reset behaviour of this field is:
Access to this field is RO.
ITR overrun.
If the PE is in Non-debug state, this bit is UNKNOWN. ITO is set to 0 on entry to Debug state.
Access to this field is RO.
DTRRX overrun.
The reset behaviour of this field is:
Access to this field is RO.
DTRTX underrun.
The reset behaviour of this field is:
Access to this field is RO.
Pipeline advance. Set to 1 every time the PE pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
Access to this field is RO.
ITR empty.
If the PE is in Non-debug state, this bit is UNKNOWN. It is always valid in Debug state.
Access to this field is RO.
Interrupt disable. Disables taking interrupts in Non-debug state.
INTdis | Meaning |
---|---|
0b00 | This |
0b01 | If ExternalInvasiveDebugEnabled() is If ExternalSecureInvasiveDebugEnabled() is If ExternalRootInvasiveDebugEnabled() is TRUE, then all interrupts taken to Root state are masked. If ExternalRealmInvasiveDebugEnabled() is TRUE, then all interrupts taken to Realm state are masked. |
When OSLSR_EL1.OSLK == 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
This field has no effect when ExternalInvasiveDebugEnabled() == FALSE.
When FEAT_Debugv8p4 is implemented, bit[23] of the register is RES0.
All interrupts includes virtual and SError interrupts.
When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
When FEAT_RME is implemented, bit[23] of this register is RES0.
The reset behaviour of this field is:
Interrupt disable. Disables taking interrupts in Non-debug state.
INTdis | Meaning |
---|---|
0b00 | Masking of interrupts is controlled by PSTATE and interrupt routing controls. |
0b01 | If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts taken to Non-secure state are masked. If ExternalSecureInvasiveDebugEnabled() is TRUE, then all interrupts taken to Secure state are masked. |
All interrupts includes virtual and SError interrupts.
When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
When FEAT_Debugv8p4 is implemented, bit[23] of this register is RES0.
The reset behaviour of this field is:
Interrupt disable. Disables taking interrupts in Non-debug state.
INTdis | Meaning |
---|---|
0b00 | Masking of interrupts is controlled by PSTATE and interrupt routing controls. |
0b01 | If ExternalInvasiveDebugEnabled() is |
0b10 | If ExternalInvasiveDebugEnabled() is If ExternalSecureInvasiveDebugEnabled() is |
0b11 | If ExternalInvasiveDebugEnabled() is If ExternalSecureInvasiveDebugEnabled() is |
When OSLSR_EL1.OSLK == 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
This field has no effect when ExternalInvasiveDebugEnabled() == FALSE.
All interrupts includes virtual and SError interrupts.
When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the MDSCR_EL1 and DBGDSCRext System registers.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
Support for the values 0b01 and 0b10 is IMPLEMENTATION DEFINED. If these values are not supported, they are reserved. If programmed with a reserved value, the PE behaves as if INTdis has been programmed with a defined value, other than for a direct read of EDSCR, and the value returned by a read of EDSCR.INTdis is UNKNOWN.
The reset behaviour of this field is:
Traps accesses to the following debug System registers:
The possible values of this field are:
TDA | Meaning |
---|---|
0b0 | Accesses to debug System registers do not generate a Software Access Debug event. |
0b1 | Accesses to debug System registers generate a Software Access Debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed. |
The reset behaviour of this field is:
Memory access mode. Controls the use of memory-access mode for accessing ITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.
Possible values of this field are:
MA | Meaning |
---|---|
0b0 | Normal access mode. |
0b1 | Memory access mode. |
The reset behaviour of this field is:
Sample CONTEXTIDR_EL2. Controls whether the PC Sample-based Profiling Extension samples CONTEXTIDR_EL2 or VTTBR_EL2.VMID.
SC2 | Meaning |
---|---|
0b0 | Sample VTTBR_EL2.VMID. |
0b1 | Sample CONTEXTIDR_EL2. |
The reset behaviour of this field is:
Reserved, RES0.
Non-secure status. Together with the NSE field, gives the current Security state:
NSE | NS | Meaning |
---|---|---|
0b0 | 0b0 | Secure. |
0b0 | 0b1 | Non-secure. |
0b1 | 0b0 | Root. |
0b1 | 0b1 | Realm. |
In Non-debug state, this bit is UNKNOWN.
Access to this field is RO.
Non-secure status. When in Debug state, gives the current Security state:
NS | Meaning |
---|---|
0b0 | Secure state. |
0b1 | Non-secure state. |
In Non-debug state, this bit is UNKNOWN.
Access to this field is RO.
Reserved, RES0.
Secure debug disabled.
Reports the inverse of ExternalRootInvasiveDebugEnabled().
Access to this field is RO.
Secure debug disabled.
On entry to Debug state:
In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.
In Non-debug state:
If EL3 is not implemented and the implementation is Non-secure, this bit is RES1.
Access to this field is RO.
Together with the NS field, this field gives the current Security state.
For a description of the values derived by evaluating NS and NSE together, see EDSCR.NS.
In Non-debug state, this bit is UNKNOWN.
Access to this field is RO.
Reserved, RES0.
Halting debug enable. The possible values of this field are:
HDE | Meaning |
---|---|
0b0 | Halting disabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
0b1 | Halting enabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
The reset behaviour of this field is:
Exception level Execution state status. In Debug state, each bit gives the current Execution state of each Exception level.
RW | Meaning | Applies when |
---|---|---|
0b1111 | Any
| |
0b1110 | The PE is in Debug state | When AArch32 is supported at EL0 |
0b110x | The PE is in Debug state. EL0 and EL1 are using AArch32. EL2 is | When AArch32 is supported at EL0 |
0b10xx | The PE is in Debug state. EL0 | When AArch32 is supported at EL0 |
0b0xxx | The PE is in Debug state. All Exception levels are using AArch32. | When AArch32 is supported at EL0 |
In Non-debug state, this field is RAO.
Access to this field is RO.
Exception level. In Debug state, this gives the current Exception level of the PE.
In Non-debug state, this field is RAZ.
Access to this field is RO.
SError interrupt pending. In Debug state, indicates whether an SError interrupt is pending:
A | Meaning |
---|---|
0b0 | No SError interrupt pending. |
0b1 | SError interrupt pending. |
A debugger can read EDSCR to check whether an SError interrupt is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.
UNKNOWN in Non-debug state.
Access to this field is RO.
Cumulative error flag. This bit is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
The reset behaviour of this field is:
Access to this field is RO.
Debug status flags.
STATUS | Meaning |
---|---|
0b000001 | PE is restarting, exiting Debug state. |
0b000010 | PE is in Non-debug state. |
0b000111 | Breakpoint. |
0b010011 | External debug request. |
0b011011 | Halting step, normal. |
0b011111 | Halting step, exclusive. |
0b100011 | OS Unlock Catch. |
0b100111 | Reset Catch. |
0b101011 | Watchpoint. |
0b101111 | HLT instruction. |
0b110011 | Software access to debug register. |
0b110111 | Exception Catch. |
0b111011 | Halting step, no syndrome. |
All other values of STATUS are reserved.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0x088 | EDSCR |
This interface is accessible as follows:
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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