The GICD_ISPENDR<n> characteristics are:
Adds the pending state to the corresponding interrupt.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
The number of implemented GICD_ISPENDR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_ISPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ISPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
GICD_ISPENDR<n> is a 32-bit register.
For SPIs and PPIs, adds the pending state to interrupt number 32n + x. Reads and writes have the following behavior:
Set_pending_bit<x> | Meaning |
---|---|
0b0 | If read, indicates that the corresponding interrupt is not pending on any PE. If written, has no effect. |
0b1 | If read, indicates that the corresponding interrupt is pending, or active and pending:
If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:
|
The reset behaviour of this field is:
Set-pending bits for SGIs are read-only and ignore writes. The Set-pending bits for SGIs are provided as GICD_SPENDSGIR<n>.
When affinity routing is enabled for the Security state of an interrupt:
Bits corresponding to unimplemented interrupts are RAZ/WI.
If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x0200 + (4 * n) | GICD_ISPENDR<n> |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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