The AMEVTYPER1<n> characteristics are:
Provides information on the events that an auxiliary activity monitor event counter AMEVCNTR1<n> counts.
External register AMEVTYPER1<n> bits [31:0] are architecturally mapped to AArch64 System register AMEVTYPER1<n>_EL0[31:0].
External register AMEVTYPER1<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER1<n>[31:0].
The power domain of AMEVTYPER1<n> is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER1<n> are RES0.
AMEVTYPER1<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAZ | RES0 | evtCount |
Reserved, RAZ.
Reserved, RES0.
Event to count. The event number of the event that is counted by the auxiliary activity monitor event counter AMEVCNTR1<n>.
It is IMPLEMENTATION DEFINED what values are supported by each counter.
If software writes a value to this field which is not supported by the corresponding counter AMEVCNTR1<n>, then:
The event counted by AMEVCNTR1<n> might be fixed at implementation. In this case, the field is read-only and writes are UNDEFINED.
If the corresponding counter AMEVCNTR1<n> is enabled, writes to this register have UNPREDICTABLE results.
The reset behaviour of this field is:
If <n> is greater than or equal to the number of auxiliary activity monitor event counters, reads of AMEVTYPER1<n> are RAZ/WI. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
AMCGCR.CG1NC identifies the number of auxiliary activity monitor event counters.
Component | Offset | Instance |
---|---|---|
AMU | 0x480 + (4 * n) | AMEVTYPER1<n> |
Accesses on this interface are RO.
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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