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The SMCR_EL3 characteristics are:
This register controls aspects of Streaming SVE that are visible at all Exception levels.
This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SMCR_EL3 are UNDEFINED.
This register has no effect if the PE is not in Streaming SVE mode.
SMCR_EL3 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RAZ/WI | LEN |
Reserved, RES0.
Reserved, RAZ/WI.
Effective Streaming SVE Vector Length (SVL).
Constrains the effective Streaming SVE vector register length for all Exception levels to (LEN+1)*128 bits when the PE is in Streaming SVE mode.
For all purposes other than returning the result of a direct read of SMCR_EL3, this field selects the effective vector length as follows:
If the requested length is smaller than the minimum implemented Streaming SVE vector length, then the minimum implemented Streaming SVE vector length is used.
If the requested length is not implemented, then the requested length rounded down to the nearest implemented Streaming SVE vector length is used.
Otherwise, the requested length is used.
An indirect read of SMCR_EL3.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0010 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else return SMCR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0010 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else SMCR_EL3 = X[t];
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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