The HDFGWTR_EL2 characteristics are:
Provides controls for traps of MSR and MCR writes of debug, trace, PMU, and Statistical Profiling System registers.
This register is present only when FEAT_FGT is implemented. Otherwise, direct accesses to HDFGWTR_EL2 are UNDEFINED.
HDFGWTR_EL2 is a 64-bit register.
Reserved, RES0.
Trap MSR writes of PMSNEVFR_EL1 at EL1 using AArch64 to EL2.
nPMSNEVFR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSNEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMSNEVFR_EL1 are not trapped by this mechanism. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
nBRBDATA | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
nBRBCTL | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMUSERENR_EL0 at EL1 using AArch64 to EL2.
PMUSERENR_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMUSERENR_EL0 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMUSERENR_EL0 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRBTRG_EL1 at EL1 using AArch64 to EL2.
TRBTRG_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBTRG_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBTRG_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRBSR_EL1 at EL1 using AArch64 to EL2.
TRBSR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBSR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRBPTR_EL1 at EL1 using AArch64 to EL2.
TRBPTR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBPTR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRBMAR_EL1 at EL1 using AArch64 to EL2.
TRBMAR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBMAR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBMAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRBLIMITR_EL1 at EL1 using AArch64 to EL2.
TRBLIMITR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBLIMITR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRBBASER_EL1 at EL1 using AArch64 to EL2.
TRBBASER_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRBBASER_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRBBASER_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRFCR_EL1 at EL1 using AArch64 to EL2.
TRFCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of TRFCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRCVICTLR at EL1 using AArch64 to EL2.
TRCVICTLR | Meaning |
---|---|
0b0 |
MSR writes of TRCVICTLR are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCVICTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCSSCSR<n> at EL1 using AArch64 to EL2.
TRCSSCSRn | Meaning |
---|---|
0b0 |
MSR writes of TRCSSCSR<n> are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCSSCSR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If Single-shot Comparator n is not implementented, a write of TRCSSCSR<n> is UNDEFINED.
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRCSEQSTR at EL1 using AArch64 to EL2.
TRCSEQSTR | Meaning |
---|---|
0b0 |
MSR writes of TRCSEQSTR are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCSEQSTR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRCPRGCTLR at EL1 using AArch64 to EL2.
TRCPRGCTLR | Meaning |
---|---|
0b0 |
MSR writes of TRCPRGCTLR are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCPRGCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCOSLAR at EL1 using AArch64 to EL2.
TRCOSLAR | Meaning |
---|---|
0b0 |
MSR writes of TRCOSLAR are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCOSLAR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRCIMSPEC<n> at EL1 using AArch64 to EL2.
TRCIMSPECn | Meaning |
---|---|
0b0 |
MSR writes of TRCIMSPEC<n> are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCIMSPEC<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
TRCIMSPEC<1-7> are optional. If TRCIMSPEC<n> is not implemented, a write of TRCIMSPEC<n> is UNDEFINED.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of TRCCNTVR<n> at EL1 using AArch64 to EL2.
TRCCNTVRn | Meaning |
---|---|
0b0 |
MSR writes of TRCCNTVR<n> are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCCNTVR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If Counter n is not implemented, a write of TRCCNTVR<n> is UNDEFINED.
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRCCLAIM | Meaning |
---|---|
0b0 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of TRCAUXCTLR at EL1 using AArch64 to EL2.
TRCAUXCTLR | Meaning |
---|---|
0b0 |
MSR writes of TRCAUXCTLR are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of TRCAUXCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
TRC | Meaning |
---|---|
0b0 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
A write of an unimplemented register is UNDEFINED.
TRCEXTINSELR<n> and TRCRSR are only implemented if FEAT_ETE is implemented.
TRCEXTINSELR is only implemented if FEAT_ETE is not implemented and FEAT_ETMv4 is implemented.
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSLATFR_EL1 at EL1 using AArch64 to EL2.
PMSLATFR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSLATFR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSLATFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSIRR_EL1 at EL1 using AArch64 to EL2.
PMSIRR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSIRR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSIRR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMSICR_EL1 at EL1 using AArch64 to EL2.
PMSICR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSICR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSICR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSFCR_EL1 at EL1 using AArch64 to EL2.
PMSFCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSFCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSEVFR_EL1 at EL1 using AArch64 to EL2.
PMSEVFR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSEVFR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSCR_EL1 at EL1 using AArch64 to EL2.
PMSCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMSCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMBSR_EL1 at EL1 using AArch64 to EL2.
PMBSR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMBSR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMBPTR_EL1 at EL1 using AArch64 to EL2.
PMBPTR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMBPTR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.
PMBLIMITR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of PMBLIMITR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCR_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMCR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCR at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception: |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMSWINC_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMSWINC_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSWINC at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMSELR_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMSELR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMSELR at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
PMOVS | Meaning |
---|---|
0b0 |
The operations listed above are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
PMINTEN | Meaning |
---|---|
0b0 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
PMCNTEN | Meaning |
---|---|
0b0 |
The operations listed above are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCNTR_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MCR and MCRR writes of PMCCNTR at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 to EL2.
PMCCFILTR_EL0 | Meaning |
---|---|
0b0 |
MSR writes of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MCR writes of PMCCFILTR at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
PMCCFILTR_EL0 can also be accessed in AArch64 state using PMXEVTYPER_EL0 when PMSELR_EL0.SEL == 31, and PMCCFILTR can also be accessed in AArch32 state using PMXEVTYPER when PMSELR.SEL == 31.
Setting this field to 1 has no effect on accesses to PMXEVTYPER_EL0 and PMXEVTYPER, regardless of the value of PMSELR_EL0.SEL or PMSELR.SEL.
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
PMEVTYPERn_EL0 | Meaning |
---|---|
0b0 |
The operations listed above are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
Regardless of the value of this field, for each value n:
See also HDFGWTR_EL2.PMCCFILTR_EL0.
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes and MCR writes of multiple System registers.
Enables a trap to EL2 the following operations:
PMEVCNTRn_EL0 | Meaning |
---|---|
0b0 |
The operations listed above are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the write generates a higher priority exception:
|
Regardless of the value of this field, for each value n:
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of OSDLR_EL1 at EL1 using AArch64 to EL2.
OSDLR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of OSDLR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of OSDLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of OSECCR_EL1 at EL1 using AArch64 to EL2.
OSECCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of OSECCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of OSECCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of OSLAR_EL1 at EL1 using AArch64 to EL2.
OSLAR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of OSLAR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of OSLAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Trap MSR writes of DBGPRCR_EL1 at EL1 using AArch64 to EL2.
DBGPRCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of DBGPRCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of DBGPRCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
DBGCLAIM | Meaning |
---|---|
0b0 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Trap MSR writes of MDSCR_EL1 at EL1 using AArch64 to EL2.
MDSCR_EL1 | Meaning |
---|---|
0b0 |
MSR writes of MDSCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of MDSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
The reset behaviour of this field is:
Trap MSR writes of DBGWVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWVRn_EL1 | Meaning |
---|---|
0b0 |
MSR writes of DBGWVR<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of DBGWVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If watchpoint n is not implemented, a write of DBGWVR<n>_EL1 is UNDEFINED.
The reset behaviour of this field is:
Trap MSR writes of DBGWCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGWCRn_EL1 | Meaning |
---|---|
0b0 |
MSR writes of DBGWCR<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of DBGWCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If watchpoint n is not implemented, a write of DBGWCR<n>_EL1 is UNDEFINED.
The reset behaviour of this field is:
Trap MSR writes of DBGBVR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBVRn_EL1 | Meaning |
---|---|
0b0 |
MSR writes of DBGBVR<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of DBGBVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If breakpoint n is not implemented, a write of DBGBVR<n>_EL1 is UNDEFINED.
The reset behaviour of this field is:
Trap MSR writes of DBGBCR<n>_EL1 at EL1 using AArch64 to EL2.
DBGBCRn_EL1 | Meaning |
---|---|
0b0 |
MSR writes of DBGBCR<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MSR writes of DBGBCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
If breakpoint n is not implemented, a write of DBGBCR<n>_EL1 is UNDEFINED.
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1D8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return HDFGWTR_EL2; elsif PSTATE.EL == EL3 then return HDFGWTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1D8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HDFGWTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HDFGWTR_EL2 = X[t];
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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