The HFGRTR_EL2 characteristics are:
Provides controls for traps of MRS and MRC reads of System registers.
This register is present only when FEAT_FGT is implemented. Otherwise, direct accesses to HFGRTR_EL2 are UNDEFINED.
HFGRTR_EL2 is a 64-bit register.
Reserved, RES0.
Trap MRS reads of ACCDATA_EL1 at EL1 using AArch64 to EL2.
nACCDATA_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ACCDATA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
0b1 |
MRS reads of ACCDATA_EL1 are not trapped by this mechanism. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXADDR_EL1 at EL1 using AArch64 to EL2.
ERXADDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXADDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXADDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 to EL2.
ERXPFGCDN_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGCDN_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 to EL2.
ERXPFGCTL_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGCTL_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXPFGF_EL1 at EL1 using AArch64 to EL2.
ERXPFGF_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXPFGF_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGF_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXMISC<n>_EL1 at EL1 using AArch64 to EL2.
ERXMISCn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXMISC<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXMISC<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 to EL2.
ERXSTATUS_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXSTATUS_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXCTLR_EL1 at EL1 using AArch64 to EL2.
ERXCTLR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXCTLR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXCTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERXFR_EL1 at EL1 using AArch64 to EL2.
ERXFR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERXFR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERRSELR_EL1 at EL1 using AArch64 to EL2.
ERRSELR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERRSELR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERRSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ERRIDR_EL1 at EL1 using AArch64 to EL2.
ERRIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ERRIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERRIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 to EL2.
ICC_IGRPENn_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ICC_IGRPEN<n>_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of VBAR_EL1 at EL1 using AArch64 to EL2.
VBAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of VBAR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of VBAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of TTBR1_EL1 at EL1 using AArch64 to EL2.
TTBR1_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TTBR1_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TTBR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of TTBR0_EL1 at EL1 using AArch64 to EL2.
TTBR0_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TTBR0_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TTBR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 when EL1 is using AArch64 to EL2.
TPIDR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: |
The reset behaviour of this field is:
Trap MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 when EL1 is using AArch64 to EL2.
TPIDRRO_EL0 | Meaning |
---|---|
0b0 |
MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 are not trapped by this mechanism. |
0b1 | If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:
|
The reset behaviour of this field is:
Trap MRS reads of TPIDR_EL1 at EL1 using AArch64 to EL2.
TPIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TPIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of TCR_EL1 at EL1 using AArch64 to EL2.
TCR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of TCR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 to EL2.
SCXTNUM_EL0 | Meaning |
---|---|
0b0 |
MRS reads of SCXTNUM_EL0 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of SCXTNUM_EL1 at EL1 using AArch64 to EL2.
SCXTNUM_EL1 | Meaning |
---|---|
0b0 |
MRS reads of SCXTNUM_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SCXTNUM_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of SCTLR_EL1 at EL1 using AArch64 to EL2.
SCTLR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of SCTLR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SCTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of REVIDR_EL1 at EL1 using AArch64 to EL2.
REVIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of REVIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of REVIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of PAR_EL1 at EL1 using AArch64 to EL2.
PAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of PAR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of MPIDR_EL1 at EL1 using AArch64 to EL2.
MPIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MPIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of MIDR_EL1 at EL1 using AArch64 to EL2.
MIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of MAIR_EL1 at EL1 using AArch64 to EL2.
MAIR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of MAIR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of LORSA_EL1 at EL1 using AArch64 to EL2.
LORSA_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORSA_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORSA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of LORN_EL1 at EL1 using AArch64 to EL2.
LORN_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORN_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of LORID_EL1 at EL1 using AArch64 to EL2.
LORID_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORID_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORID_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of LOREA_EL1 at EL1 using AArch64 to EL2.
LOREA_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LOREA_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LOREA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of LORC_EL1 at EL1 using AArch64 to EL2.
LORC_EL1 | Meaning |
---|---|
0b0 |
MRS reads of LORC_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORC_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of ISR_EL1 at EL1 using AArch64 to EL2.
ISR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ISR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ISR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of FAR_EL1 at EL1 using AArch64 to EL2.
FAR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of FAR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of FAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of ESR_EL1 at EL1 using AArch64 to EL2.
ESR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of ESR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ESR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 to EL2.
DCZID_EL0 | Meaning |
---|---|
0b0 |
MRS reads of DCZID_EL0 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 to EL2.
CTR_EL0 | Meaning |
---|---|
0b0 |
MRS reads of CTR_EL0 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CSSELR_EL1 at EL1 using AArch64 to EL2.
CSSELR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CSSELR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CSSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CPACR_EL1 at EL1 using AArch64 to EL2.
CPACR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CPACR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CPACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 to EL2.
CONTEXTIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CONTEXTIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CLIDR_EL1 at EL1 using AArch64 to EL2.
CLIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CLIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CLIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of CCSIDR_EL1 at EL1 using AArch64 to EL2.
CCSIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of CCSIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CCSIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APIBKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APIAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APGAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APDBKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
APDAKey | Meaning |
---|---|
0b0 |
MRS reads of the System registers listed above are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Reserved, RES0.
Trap MRS reads of AMAIR_EL1 at EL1 using AArch64 to EL2.
AMAIR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AMAIR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AMAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of AIDR_EL1 at EL1 using AArch64 to EL2.
AIDR_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AIDR_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of AFSR1_EL1 at EL1 using AArch64 to EL2.
AFSR1_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AFSR1_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AFSR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Trap MRS reads of AFSR0_EL1 at EL1 using AArch64 to EL2.
AFSR0_EL1 | Meaning |
---|---|
0b0 |
MRS reads of AFSR0_EL1 are not trapped by this mechanism. |
0b1 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AFSR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. |
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x1B8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return HFGRTR_EL2; elsif PSTATE.EL == EL3 then return HFGRTR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0001 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1B8] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGRTR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HFGRTR_EL2 = X[t];
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.