(old) htmldiff from-(new)

AMCNTENSET0, Activity Monitors Count Enable Set Register 0

The AMCNTENSET0 characteristics are:

Purpose

Enable control bits for the architected activity monitors event counters, AMEVCNTR0<n>.

Configuration

External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0].

External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET0[31:0].

The power domain of AMCNTENSET0 is IMPLEMENTATION DEFINED.

This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET0 are RES0.

Attributes

AMCNTENSET0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0RAZ/WIP3P2P1P0
313029282726252423222120191817161514131211109876543210
RES0P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [31:16]

Reserved, RES0.

BitsP<n>, bit [n], for n = 15:4] to 0

Possible values of each bit are:

P<n>Meaning
0b0

When read, means that AMEVCNTR0<n> is disabled. When written, has no effect.

0b1

When read, means that AMEVCNTR0<n> is enabled. When written, enables AMEVCNTR0<n>.

The reset behaviour of this field is:

Reserved,Activity RAZ/WI.monitor event counter enable bit forAMEVCNTR0<n>.

ThisBits field[15:N] isare reserved for additional architected activity monitor event countersRAZ/WI, whichwhere ArmN mightis define in a future version of the Activityvalue Monitors architecture.inAMCGCR.CG0NC.

P<n>, bit [n], for n = 3 to 0

Activity monitor event counter enable bit for AMEVCNTR0<n>.

Note

AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.

Possible values of each bit are:

P<n>Meaning
0b0

When read, means that AMEVCNTR0<n> is disabled.

0b1

When read, means that AMEVCNTR0<n> is enabled.

The reset behaviour of this field is:

Accessing AMCNTENSET0

AMCNTENSET0 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xC00AMCNTENSET0

Accesses on this interface are RO.


30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)