TPIDR_EL0, EL0 Read/Write Software Thread ID Register

The TPIDR_EL0 characteristics are:

Purpose

Provides a location where software executing at EL0 can store thread identifying information, for OS management purposes.

The PE makes no use of this register.

Configuration

AArch64 System register TPIDR_EL0 bits [31:0] are architecturally mapped to AArch32 System register TPIDRURW[31:0].

Attributes

TPIDR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Thread ID
Thread ID

Bits [63:0]

Thread ID. Thread identifying information stored by software running at this Exception level.

The reset behaviour of this field is:

Accessing TPIDR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TPIDR_EL0

op0op1CRnCRmop2
0b110b0110b11010b00000b010

if PSTATE.EL == EL0 then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return TPIDR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return TPIDR_EL0; elsif PSTATE.EL == EL2 then return TPIDR_EL0; elsif PSTATE.EL == EL3 then return TPIDR_EL0;

MSR TPIDR_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b11010b00000b010

if PSTATE.EL == EL0 then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TPIDR_EL0 = X[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TPIDR_EL0 = X[t]; elsif PSTATE.EL == EL2 then TPIDR_EL0 = X[t]; elsif PSTATE.EL == EL3 then TPIDR_EL0 = X[t];


30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f

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