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The ID_PFR2_EL1 characteristics are:
Gives information about the AArch32 programmers' model.
Must be interpreted with ID_PFR0_EL1 and ID_PFR1_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register ID_PFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_PFR2[31:0].
ID_PFR2_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RAS_frac | SSBS | CSV3 |
Reserved, RES0.
RAS Extension fractional field. Defined values are:
RAS_frac | Meaning |
---|---|
0b0000 | If ID_PFR0_EL1.RAS == 0b0001, RAS Extension implemented. |
0b0001 | If ID_PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. |
All other values are reserved.
This field is valid only if ID_PFR0_EL1.RAS == 0b0001.
Speculative Store Bypassing controls in AArch64 state. Defined values are:
SSBS | Meaning |
---|---|
0b0000 | AArch32 provides no mechanism to control the use of Speculative Store Bypassing. |
0b0001 | AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. |
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.5, the only permitted value is 0b0001.
All other values are reserved.
Speculative use of faulting data. Defined values are:
CSV3 | Meaning |
---|---|
0b0000 | This PE does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by other instructions |
0b0001 | Data loaded under speculation with a permission or domain fault cannot be used to form an address or generate condition codes or SVE predicate values to be used by other instructions |
All other values are reserved.
FEAT_CSV3 implements the functionality identified by the value 0b0001.
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.5, the only permitted value is 0b0001.
If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UNKNOWN | |||||||||||||||||||||||||||||||
UNKNOWN |
Reserved, UNKNOWN.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_PFR2_EL1; elsif PSTATE.EL == EL2 then return ID_PFR2_EL1; elsif PSTATE.EL == EL3 then return ID_PFR2_EL1;
30/06/2021 1509:2239; 2a17f7750cfd1ab239f20f6cf29877ba8041794f4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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