The ID_MMFR5 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_MMFR5 bits [31:0] are architecturally mapped to AArch64 System register ID_MMFR5_EL1[31:0].
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_MMFR5 are UNDEFINED.
ID_MMFR5 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | nTLBPA | ETS |
Reserved, RES0.
Indicates support for intermediate caching of translation table walks. Defined values are:
nTLBPA | Meaning |
---|---|
0b0000 | The intermediate caching of translation table walks might include non-coherent caches of previous valid translation table entries since the last completed relevant TLBI applicable to the PE where either:
|
0b0001 | The intermediate caching of translation table walks does not include non-coherent caches of previous valid translation table entries since the last completed TLBI applicable to the PE where either:
|
All other values are reserved.
FEAT_nTLBPA implements the functionality identified by the value 0b0001.
From Armv8.0, the permitted values are 0b0000 and 0b0001.
Indicates support for Enhanced Translation Synchronization. Defined values are:
ETS | Meaning |
---|---|
0b0000 |
Enhanced Translation Synchronization is not supported. |
0b0001 |
Enhanced Translation Synchronization is supported. |
All other values are reserved.
FEAT_ETS implements the functionality identified by the value 0b0001.
From Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.7, the only permitted value is 0b0001.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0011 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!IsZero(ID_MMFR5) || boolean IMPLEMENTATION_DEFINED "ID_MMFR5 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && (!IsZero(ID_MMFR5) || boolean IMPLEMENTATION_DEFINED "ID_MMFR5 trapped by HCR.TID3") && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_MMFR5; elsif PSTATE.EL == EL2 then return ID_MMFR5; elsif PSTATE.EL == EL3 then return ID_MMFR5;
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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