The PMSIDR_EL1 characteristics are:
Describes the Statistical Profiling implementation to software
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSIDR_EL1 are UNDEFINED.
PMSIDR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | Format | CountSize | MaxSize | Interval | RES0 | FnE | ERnd | LDS | ArchInst | FL | FT | FE |
Reserved, RES0.
Defines the format of the sample records. Defined values are:
Format | Meaning |
---|---|
0b0000 |
Format 0. |
All other values are reserved.
Reserved, RAZ.
Defines the size of the counters. Defined values are:
CountSize | Meaning |
---|---|
0b0010 |
12-bit saturating counters. |
All other values are reserved.
Reserved values might be defined in a future version of the architecture.
Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size. Defined values are:
MaxSize | Meaning |
---|---|
0b0100 |
16 bytes |
0b0101 |
32 bytes |
0b0110 |
64 bytes |
0b0111 |
128 bytes |
0b1000 |
256 bytes |
0b1001 |
512 bytes |
0b1010 |
1024 bytes |
0b1011 |
2KB |
All other values are reserved.
Reserved values might be defined in a future version of the architecture.
Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N. Defined values are:
Interval | Meaning |
---|---|
0b0000 |
256 |
0b0010 |
512 |
0b0011 |
768 |
0b0100 |
1,024 |
0b0101 |
1,536 |
0b0110 |
2,048 |
0b0111 |
3,072 |
0b1000 |
4,096 |
All other values are reserved.
Reserved values might be defined in a future version of the architecture.
Reserved, RES0.
Filtering by events, inverted. Defined values are:
FnE | Meaning |
---|---|
0b0 |
PMSNEVFR_EL1 is not implemented and PMSFCR_EL1.FnE is RES0. |
0b1 |
PMSNEVFR_EL1 and PMSFCR_EL1.FnE are implemented. |
The value 1 indicates support for the FEAT_SPEv1p2 feature.
Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND. Defined values are:
ERnd | Meaning |
---|---|
0b0 |
The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires. |
0b1 |
The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires. |
Data source indicator for sampled load instructions. Defined values are:
LDS | Meaning |
---|---|
0b0 |
Loaded data source not implemented. |
0b1 |
Loaded data source implemented. |
Architectural instruction profiling. Defined values are:
ArchInst | Meaning |
---|---|
0b0 |
Micro-op sampling implemented. |
0b1 |
Architecture instruction sampling implemented. |
Filtering by latency. This bit is RAO.
Filtering by operation type. This bit is RAO.
Filtering by events. This bit is RAO.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMSIDR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMSIDR_EL1; elsif PSTATE.EL == EL3 then return PMSIDR_EL1;
30/06/2021 09:40; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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