The HDCR characteristics are:
Controls the trapping to Hyp mode of Non-secure accesses, at EL1 or lower, to functions provided by the debug and trace architectures and the Performance Monitors Extension.
AArch32 System register HDCR bits [31:0] are architecturally mapped to AArch64 System register MDCR_EL2[31:0].
This register is present only when AArch32 is supported at EL0. Otherwise, direct accesses to HDCR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3, and other than for a direct read of the register, the PE behaves as if HDCR.HPMN == PMCR.N.
HDCR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | HPMFZO | MTPME | TDCC | HLP | RES0 | HCCD | RES0 | TTRF | RES0 | HPMD | RES0 | TDRA | TDOSA | TDA | TDE | HPME | TPM | TPMCR | HPMN |
Reserved, RES0.
Hyp Performance Monitors Freeze-on-overflow. Stop event counters on overflow.
HPMFZO | Meaning |
---|---|
0b0 |
Do not freeze on overflow. |
0b1 |
Event counters do not count when PMOVSR[(PMCR.N-1):HDCR.HPMN] is nonzero. |
If HDCR.HPMN is less than PMCR.N, this field affects the operation of event counters in the range [HDCR.HPMN .. (PMCR.N-1)].
If HDCR.HPMN is equal to PMCR.N, this field has no effect.
This field does not affect the operation of event counters in the range [0 .. (HDCR.HPMN-1)] and PMCCNTR.
The operation of this field ignores the values of PMOVSR[(HDCR.HPMN-1):0].
The operation of this field applies even when EL2 is disabled in the current Security state.
The reset behaviour of this field is:
Reserved, RES0.
Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>.MT bits.
MTPME | Meaning |
---|---|
0b0 |
FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is zero. |
0b1 |
PMEVTYPER<n>.MT bits not affected by this bit. |
If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this bit is 0b0.
The reset behaviour of this field is:
Reserved, RES0.
Trap DCC. Traps use of the Debug Comms Channel at EL1 and EL0 to EL2.
TDCC | Meaning |
---|---|
0b0 |
This control does not cause any register accesses to be trapped. |
0b1 | If EL2 is implemented and enabled in the current Security state, accesses to the DCC registers at EL1 and EL0 generate a Hyp Trap exception, unless the access also generates a higher priority exception. Traps on the DCC data transfer registers are ignored when the PE is in Debug state. |
The DCC registers trapped by this control are:
The traps are reported with EC syndrome value:
When the PE is in Debug state, HDCR.TDCC does not trap any accesses to:
The reset behaviour of this field is:
Reserved, RES0.
Hypervisor Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
HLP | Meaning |
---|---|
0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>[31:0]. |
0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>[63:0]. |
If the highest implemented Exception level is using AArch32, it is IMPLEMENTATION DEFINED whether this bit is read/write or RAZ/WI.
If HDCR.HPMN is less than PMCR.N, this bit affects the operation of event counters in the range [HDCR.HPMN..(PMCR.N-1)]. Otherwise this bit has no effect on the operation of the event counters.
The effect of HDCR.HPMN on the operation of this bit always applies if EL2 is implemented, at all Exception levels including EL2 and EL3, and regardless of whether EL2 is enabled in the current Security state.
For more information see the description of the HDCR.HPMN field.
PMEVCNTR<n>[63:32] cannot be accessed directly in AArch32 state.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Hypervisor Cycle Counter Disable. Prohibits PMCCNTR from counting at EL2.
HCCD | Meaning |
---|---|
0b0 |
Cycle counting by PMCCNTR is not affected by this mechanism. |
0b1 |
Cycle counting by PMCCNTR is prohibited at EL2. |
This field does not affect the CPU_CYCLES event or any other event that counts cycles.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Traps use of the Trace Filter Control registers at EL1 to EL2.
TTRF | Meaning |
---|---|
0b0 |
Accesses to TRFCR at EL1 are not affected by this control bit. |
0b1 |
Accesses to TRFCR at EL1 generate a Hyp Trap exception. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Guest Performance Monitors Disable. Controls event counting by some event counters at EL2.
HPMD | Meaning |
---|---|
0b0 |
Event counting and PMCCNTR are not affected by this mechanism. |
0b1 |
Event counting by some event counters is prohibited in Hyp mode. If PMCR.DP is 1, PMCCNTR is disabled in Hyp mode. Otherwise, PMCCNTR is not affected by this mechanism. |
This field applies only to:
The other event counters are not affected. When PMCR.DP is 0, PMCCNTR is not affected.
The reset behaviour of this field is:
Guest Performance Monitors Disable. Controls event counting by some event counters at EL2.
HPMD | Meaning |
---|---|
0b0 |
Event counting and PMCCNTR are not affected by this mechanism. |
0b1 |
If ExternalSecureNoninvasiveDebugEnabled() is FALSE, event counting by some event counters is prohibited in Hyp mode, and if PMCR.DP is 1, PMCCNTR is disabled in Hyp mode. |
If ExternalSecureNoninvasiveDebugEnabled() is TRUE, the event counters and PMCCNTR are not affected by this field.
Otherwise, this field applies only to:
The other event counters are not affected. When PMCR.DP is 0, PMCCNTR is not affected.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Trap Debug ROM Address register access. Traps Non-secure EL0 and EL1 System register accesses to the Debug ROM registers to Hyp mode.
TDRA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL0 and EL1 System register accesses to the DBGDRAR or DBGDSAR are trapped to Hyp mode, unless it is trapped by DBGDSCRext.UDCCdis. |
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
Trap debug OS-related register access. Traps Non-secure EL1 System register accesses to the powerdown debug registers to Hyp mode.
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL1 System register accesses to the powerdown debug registers are trapped to Hyp mode. |
The registers for which accesses are trapped are as follows:
These registers are not accessible at EL0.
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
Trap debug OS-related register access. Traps Non-secure EL1 System register accesses to the powerdown debug registers to Hyp mode.
TDOSA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL1 System register accesses to the powerdown debug registers are trapped to Hyp mode. |
The registers for which accesses are trapped are as follows:
It is IMPLEMENTATION DEFINED whether accesses to DBGOSDLR are trapped.
These registers are not accessible at EL0.
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
Trap debug access. Traps Non-secure EL0 and EL1 System register accesses to those debug System registers in the (coproc==0b1110) encoding space that are not trapped by either of the following:
TDA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL0 or EL1 System register accesses to the debug registers, other than the registers trapped by HDCR.TDRA and HDCR.TDOSA, are trapped to Hyp mode, unless it is trapped by DBGDSCRext.UDCCdis. |
Traps of AArch32 accesses to DBGDTRRXint and DBGDTRTXint are ignored in Debug state.
If HCR.TGE or HDCR.TDE is 1, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behaviour of this field is:
Trap Debug exceptions. Controls routing of Debug exceptions, and defines the debug target Exception level, ELD.
TDE | Meaning |
---|---|
0b0 |
The debug target Exception level is EL1. |
0b1 | If EL2 is enabled for the current Effective value of SCR.NS, the debug target Exception level is EL2, otherwise the debug target Exception level is EL1. The HDCR.{TDRA, TDOSA, TDA} fields are treated as being 1 for all purposes other than returning the result of a direct read of the register. |
For more information, see 'Routing debug exceptions'.
When HCR.TGE == 1, the PE behaves as if the value of this field is 1 for all purposes other than returning the value of a direct read of the register.
The reset behaviour of this field is:
[HDCR.HPMN..(N-1)] event counters enable.
HPME | Meaning |
---|---|
0b0 |
Event counters in the range [HDCR.HPMN..(PMCR.N-1)] are disabled. |
0b1 |
Event counters in the range [HDCR.HPMN..(PMCR.N-1)] are enabled by PMCNTENSET. |
If HDCR.HPMN is less than PMCR.N, the event counters in the range [HDCR.HPMN..(PMCR.N-1)], are enabled and disabled by this bit. Otherwise this bit has no effect on the operation of the event counters.
The effect of HDCR.HPMN on the operation of this bit applies regardless of whether EL2 is enabled in the current Security state.
For more information see the description of the HPMN field.
The reset behaviour of this field is:
Reserved, RES0.
Trap Performance Monitors accesses. Traps Non-secure EL0 and EL1 accesses to all Performance Monitors registers to Hyp mode.
TPM | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL0 and EL1 accesses to all Performance Monitors registers are trapped to Hyp mode. |
EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.
The reset behaviour of this field is:
Reserved, RES0.
Trap PMCR accesses. Traps Non-secure EL0 and EL1 accesses to the PMCR to Hyp mode.
TPMCR | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL0 and EL1 accesses to the PMCR are trapped to Hyp mode, unless it is trapped by PMUSERENR.EN. |
EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.
The reset behaviour of this field is:
Reserved, RES0.
Defines the number of event counters that are accessible from Non-secure EL1 modes, and from Non-secure EL0 modes if unprivileged access is enabled.
If HPMN is less than PMCR.N, HPMN divides the event counters into two ranges, [0..(HPMN-1)] and [HPMN..(PMCR.N-1)].
For an event counter in the range [0..(HPMN-1)]:
If HPMN is equal to PMCR.N, this applies to all event counters.
If HPMN is less than PMCR.N, for an event counter in the range [HPMN..(PMCR.N-1)]:
If this field is set to 0, or to a value larger than PMCR.N, then the following CONSTRAINED UNPREDICTABLE behaviors apply:
The reset behaviour of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return HDCR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else return HDCR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else HDCR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else HDCR = R[t];
30/06/2021 15:21; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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