The TRCSSPCICR<n> characteristics are:
Returns the status of the corresponding Single-shot Comparator Control.
External register TRCSSPCICR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCSSPCICR<n>[31:0].
This register is present only when FEAT_ETE is implemented, TRCIDR4.NUMSSCC > n, TRCIDR4.NUMPC > 0b0000 and TRCSSCSR<n>.PC == 1. Otherwise, direct accesses to TRCSSPCICR<n> are RES0.
TRCSSPCICR<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PC[7] | PC[6] | PC[5] | PC[4] | PC[3] | PC[2] | PC[1] | PC[0] |
Reserved, RES0.
Selects one or more PE Comparator Inputs for Single-shot control.
PC[<m>] | Meaning |
---|---|
0b0 |
The single PE Comparator Input <m>, is not selected as for Single-shot control. |
0b1 |
The single PE Comparator Input <m>, is selected as for Single-shot control. |
This bit is RES0 if m >= TRCIDR4.NUMPC.
The reset behaviour of this field is:
Must be programmed if implemented and any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
Component | Offset | Instance |
---|---|---|
ETE | 0x2C0 + (4 * n) | TRCSSPCICR<n> |
This interface is accessible as follows:
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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