The GICD_IROUTER<n> characteristics are:
When affinity routing is enabled, provides routing information for the SPI with INTID n.
These registers are available in all configurations of the GIC. If the GIC implementation supports two Security states, these registers are Common.
The maximum value of n is given by (32*(GICD_TYPER.ITLinesNumber+1) - 1). GICD_IROUTER<n> registers where n=0 to 31 are reserved.
GICD_IROUTER<n> is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Aff3 | ||||||||||||||||||||||||||||||
Interrupt_Routing_Mode | RES0 | Aff2 | Aff1 | Aff0 |
Reserved, RES0.
Affinity level 3.
The reset behaviour of this field is:
Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy:
Interrupt_Routing_Mode | Meaning |
---|---|
0b0 |
Interrupts routed to the PE specified by a.b.c.d. In this routing, a, b, c, and d are the values of fields Aff3, Aff2, Aff1, and Aff0 respectively. |
0b1 |
Interrupts routed to any PE defined as a participating node. |
If GICD_IROUTER<n>.IRM == 0 and the affinity path does not correspond to an implemented PE, then if the corresponding interrupt becomes pending behavior is CONSTRAINED UNPREDICTABLE:
The interrupt is not forwarded to any PE, direct reads return the written value
The affinity path is treated as an UNKNOWN implemented PE, direct reads return the UNKNOWN implemented PE
The affinity path is treated as an UNKNOWN implemented PE, direct reads return the written value
In implementations that do not require 1 of N distribution of SPIs, this bit might be RAZ/WI.
When this bit is set to 1, GICD_IROUTER<n>.{Aff3, Aff2, Aff1, Aff0} are UNKNOWN.
An implementation might choose to make the Aff<n> fields RO when this field is 1.
The reset behaviour of this field is:
Reserved, RES0.
Affinity level 2.
The reset behaviour of this field is:
Affinity level 1.
The reset behaviour of this field is:
Affinity level 0.
The reset behaviour of this field is:
For an SPI with INTID m:
These registers are used only when affinity routing is enabled. When affinity routing is not enabled:
When affinity routing becomes enabled for a Security state (for example, following a reset or following a write to GICD_CTLR) the value of all writeable fields in this register is UNKNOWN for that Security state. When the group of an interrupt changes so the ARE setting for the interrupt changes to 1, the value of this register is UNKNOWN for that interrupt.
If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any GICD_IROUTER<n> registers that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.
For each interrupt, a GIC implementation might support fewer than 256 values for an affinity level. In this case, some bits of the corresponding affinity level field might be RO. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x6000 + (8 * n) | GICD_IROUTER<n> |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.