PMCIDR2, Performance Monitors Component Identification Register 2

The PMCIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information, see 'About the Component Identification scheme'.

Configuration

Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

PMCIDR2 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0PRMBL_2

Bits [31:8]

Reserved, RES0.

PRMBL_2, bits [7:0]

Preamble.

Reads as 0x05.

Access to this field is RO.

Accessing PMCIDR2

PMCIDR2 can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xFF8PMCIDR2

This interface is accessible as follows:


30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

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