AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)

The AFSR0_EL2 characteristics are:

Purpose

Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL2.

Configuration

AArch64 System register AFSR0_EL2 bits [31:0] are architecturally mapped to AArch32 System register HADFSR[31:0].

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

AFSR0_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

The reset behaviour of this field is:

Accessing AFSR0_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AFSR0_EL2 or AFSR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AFSR0_EL2

op0op1CRnCRmop2
0b110b1000b01010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return AFSR0_EL2; elsif PSTATE.EL == EL3 then return AFSR0_EL2;

MSR AFSR0_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b01010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then AFSR0_EL2 = X[t]; elsif PSTATE.EL == EL3 then AFSR0_EL2 = X[t];

MRS <Xt>, AFSR0_EL1

op0op1CRnCRmop2
0b110b0000b01010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.AFSR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x128]; else return AFSR0_EL1; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return AFSR0_EL2; else return AFSR0_EL1; elsif PSTATE.EL == EL3 then return AFSR0_EL1;

MSR AFSR0_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b01010b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.AFSR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x128] = X[t]; else AFSR0_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then AFSR0_EL2 = X[t]; else AFSR0_EL1 = X[t]; elsif PSTATE.EL == EL3 then AFSR0_EL1 = X[t];


30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.