The EDECR characteristics are:
Controls Halting debug events.
If FEAT_DoPD is implemented, this register is in the Core power domain.
If FEAT_DoPD is not implemented, this register is in the Debug power domain.
EDECR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SS | RCE | OSUCE |
Reserved, RES0.
Halting step enable. Possible values of this field are:
SS | Meaning |
---|---|
0b0 |
Halting step debug event disabled. |
0b1 |
Halting step debug event enabled. |
If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state'.
The reset behaviour of this field is:
Reset Catch Enable.
RCE | Meaning |
---|---|
0b0 |
Reset Catch debug event disabled. |
0b1 |
Reset Catch debug event enabled. |
The reset behaviour of this field is:
Reserved, RES0.
OS Unlock Catch Enable.
OSUCE | Meaning |
---|---|
0b0 |
OS Unlock Catch debug event disabled. |
0b1 |
OS Unlock Catch debug event enabled. |
The reset behaviour of this field is:
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
Debug | 0x024 | EDECR |
This interface is accessible as follows:
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
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