The PMCFGR characteristics are:
Contains PMU-specific configuration data.
PMCFGR is in the Core power domain.
PMCFGR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCG | RES0 | FZO | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N |
This feature is not supported, so this field is RAZ.
Reserved, RES0.
Freeze-on-overflow supported. Defined values are:
FZO | Meaning |
---|---|
0b0 |
Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0. |
0b1 |
Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW. |
FEAT_PMUv3p7 implements the functionality added by the value 0b1.
From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
This feature is not supported, so this bit is RAZ.
This feature is not supported, so this bit is RAZ.
Export supported. Value is IMPLEMENTATION DEFINED.
EX | Meaning |
---|---|
0b0 |
PMCR_EL0.X is RES0. |
0b1 |
PMCR_EL0.X is read/write. |
Access to this field is RO.
Cycle counter has prescale.
This is RES1 if AArch32 is supported at any Exception level, and RAZ otherwise.
CCD | Meaning |
---|---|
0b0 |
PMCR_EL0.D is RES0. |
0b1 |
PMCR_EL0.D is read/write. |
Dedicated cycle counter (counter 31) supported. This bit is RAO.
Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.
From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.
Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31.
N | Meaning |
---|---|
0x00 |
Only PMCCNTR_EL0 implemented. |
0x01 |
PMCCNTR_EL0 plus one event counter implemented. |
and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented.
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0xE00 | PMCFGR |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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