The GICR_ICFGR<n>E characteristics are:
Determines whether the corresponding PPI in the extended PPI range is edge-triggered or level-sensitive.
This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICR_ICFGR<n>E are RES0.
A copy of this register is provided for each Redistributor.
GICR_ICFGR<n>E is a 32-bit register.
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit [2x]) is RES0.
Possible values of Int_config[1] (bit [2x+1]) are:
Int_config<x> | Meaning |
---|---|
0b0 |
The corresponding interrupt is level-sensitive. |
0b1 |
The corresponding interrupt is edge-triggered. |
The reset behaviour of this field is:
For each supported extended PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
When affinity routing is not enabled for the Security state of an interrupt in GICR_ICFGR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0C00 + (4 * n) | GICR_ICFGR<n>E |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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