The PMMIR characteristics are:
Describes Performance Monitors parameters specific to the implementation.
PMMIR is in the Core power domain.
This register is present only when FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.
PMMIR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SLOTS |
Reserved, RES0.
Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is implemented, this field must not be zero.
If the Core power domain is off or in a low-power state, access on this interface returns an Error.
Component | Offset | Instance |
---|---|---|
PMU | 0xE40 | PMMIR |
This interface is accessible as follows:
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.