The CNTEL0ACR characteristics are:
An implementation of CNTEL0ACR in the frame at CNTBaseN controls whether the CNTPCT, CNTVCT, CNTFRQ, EL1 Physical Timer, and Virtual Timer registers are visible in the frame at CNTEL0BaseN.
The power domain of CNTEL0ACR is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTEL0ACR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | EL0PTEN | EL0VTEN | RES0 | EL0VCTEN | EL0PCTEN |
Reserved, RES0.
Second view read/write access control for the EL1 Physical Timer registers. This bit controls whether the CNTP_CVAL, CNTP_TVAL, and CNTP_CTL registers in the current CNTBaseN frame are also accessible in the corresponding CNTEL0BaseN frame. The possible values of this bit are:
EL0PTEN | Meaning |
---|---|
0b0 |
No access. Registers are RES0 in the second view. |
0b1 |
Access permitted. If the registers are accessible in the current frame then they are accessible in the second view. |
The reset behaviour of this field is:
Second view read/write access control for the Virtual Timer registers. This bit controls whether the CNTV_CVAL, CNTV_TVAL, and CNTV_CTL registers in the current CNTBaseN frame are also accessible in the corresponding CNTEL0BaseN frame. The possible values of this bit are:
EL0VTEN | Meaning |
---|---|
0b0 |
No access. Registers are RES0 in the second view. |
0b1 |
Access permitted. If the registers are accessible in the current frame then they are accessible in the second view. |
The definition of this bit means that, if the Virtual Timer registers are not implemented in the current CNTBaseN frame, then the Virtual Timer register addresses are RES0 in the corresponding CNTEL0BaseN frame, regardless of the value of this bit.
The reset behaviour of this field is:
Reserved, RES0.
Second view read access control for CNTVCT and CNTFRQ. The possible values of this bit are:
EL0VCTEN | Meaning |
---|---|
0b0 | CNTVCT is not visible in the second view. If EL0PCTEN is set to 0, CNTFRQ is not visible in the second view. |
0b1 |
Access permitted. If CNTVCT and CNTFRQ are visible in the current frame then they are visible in the second view. |
The reset behaviour of this field is:
Second view read access control for CNTPCT and CNTFRQ. The possible values of this bit are:
EL0PCTEN | Meaning |
---|---|
0b0 | CNTPCT is not visible in the second view. If EL0VCTEN is set to 0, CNTFRQ is not visible in the second view. |
0b1 |
Access permitted. If CNTPCT and CNTFRQ are visible in the current frame then they are visible in the second view. |
The reset behaviour of this field is:
CNTEL0ACR can be implemented in any implemented CNTBaseN frame.
'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:
If CNTEL0ACR is not implemented in an implemented CNTBaseN frame:
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTBaseN | 0x014 | CNTEL0ACR |
Accesses on this interface are RW.
30/06/2021 15:22; 2a17f7750cfd1ab239f20f6cf29877ba8041794f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.