The MPAMCFG_CMAX characteristics are:
The MPAMCFG_CMAX is a 32-bit read/write register that controls the maximum fraction of the cache capacity that the PARTID selected by MPAMCFG_PART_SEL is permitted to allocate.
If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
The power domain of MPAMCFG_CMAX is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented and MPAMF_IDR.HAS_CCAP_PART == 1. Otherwise, direct accesses to MPAMCFG_CMAX are RES0.
The power and reset domain of each MSC component is specific to that component.
MPAMCFG_CMAX is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CMAX |
Reserved, RES0.
Maximum cache capacity usage in fixed-point fraction format by the partition selected by MPAMCFG_PART_SEL. The fraction represents the portion of the total cache capacity that the PARTID is permitted to allocate.
The implemented width of the fixed-point fraction is given in MPAMF_CCAP_IDR.CMAX_WD. Unimplemented bits within the field are RAZ/WI. The implemented bits of the CMAX field are always the most significant bits of the field.
The fixed-point fraction CMAX is less than 1. The implied binary point is between bits 15 and 16. This representation has as the largest fraction of the cache that can be represented in an implementation with w implemented bits is 1.0 minus one half to the power w.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.
MPAMCFG_CMAX_s, MPAMCFG_CMAX_ns, MPAMCFG_CMAX_rt, and MPAMCFG_CMAX_rl must be separate registers.
When RIS is implemented, loads and stores to MPAMCFG_CMAX access the cache maximum capacity partitioning configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When RIS is not implemented, loads and stores to MPAMCFG_CMAX access the cache maximum capacity partitioning configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When PARTID narrowing is implemented, loads and stores to MPAMCFG_CMAX access the cache maximum capacity partitioning configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.
When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CMAX access the cache maximum capacity partitioning configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0108 | MPAMCFG_CMAX_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0108 | MPAMCFG_CMAX_ns |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x0108 | MPAMCFG_CMAX_rt |
When FEAT_RME is implemented access on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x0108 | MPAMCFG_CMAX_rl |
When FEAT_RME is implemented access on this interface are RW.
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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