The SCTLR_EL3 characteristics are:
Provides top level control of the system, including its memory system, at EL3.
This register is present only when EL3 is implemented. Otherwise, direct accesses to SCTLR_EL3 are UNDEFINED.
SCTLR_EL3 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | TME | RES0 | TMT | RES0 | DSSBS | ATA | RES0 | TCF | RES0 | ITFSB | BT | RES0 | |||||||||||||||||||
EnIA | EnIB | RES1 | EnDA | RES0 | EE | RES0 | RES1 | EIS | IESB | RES0 | WXN | RES1 | RES0 | RES1 | RES0 | EnDB | I | EOS | RES0 | nAA | RES1 | SA | C | A | M |
Reserved, RES0.
Enables the Transactional Memory Extension at EL3.
TME | Meaning |
---|---|
0b0 |
Any attempt to execute a TSTART instruction at EL3 is trapped, unless HCR_EL2.TME or SCR_EL3.TME causes TSTART instructions to be UNDEFINED at EL3. |
0b1 |
This control does not cause any TSTART instruction to be trapped. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Forces a trivial implementation of the Transactional Memory Extension at EL3.
TMT | Meaning |
---|---|
0b0 |
This control does not cause any TSTART instruction to fail. |
0b1 |
When the TSTART instruction is executed at EL3, the transaction fails with a TRIVIAL failure cause. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Default PSTATE.SSBS value on Exception Entry.
DSSBS | Meaning |
---|---|
0b0 |
PSTATE.SSBS is set to 0 on an exception to EL3. |
0b1 |
PSTATE.SSBS is set to 1 on an exception to EL3. |
The reset behaviour of this field is:
Reserved, RES0.
Allocation Tag Access in EL3. Controls EL3 access to Allocation Tags.
ATA | Meaning |
---|---|
0b0 |
Access to Allocation Tags is prevented. |
0b1 |
This control does not prevent access to Allocation Tags. |
This bit is permitted to be cached in a TLB.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Tag Check Fault in EL3. Controls the effect of Tag Check Faults due to Loads and Stores in EL3.
If FEAT_MTE3 is not implemented, the value 0b11 is reserved.
TCF | Meaning | Applies when |
---|---|---|
0b00 |
Tag Check Faults have no effect on the PE. | |
0b01 |
Tag Check Faults cause a synchronous exception. | |
0b10 |
Tag Check Faults are asynchronously accumulated. | |
0b11 |
Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes. | When FEAT_MTE3 is implemented |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
When synchronous exceptions are not being generated by Tag Check Faults, this field controls whether on exception entry into EL3, all Tag Check Faults due to instructions executed before exception entry, that are reported asynchronously, are synchronized into TFSRE0_EL1 and TFSR_ELx registers.
ITFSB | Meaning |
---|---|
0b0 |
Tag Check Faults are not synchronized on entry to EL3. |
0b1 |
Tag Check Faults are synchronized on entry to EL3. |
The reset behaviour of this field is:
Reserved, RES0.
PAC Branch Type compatibility at EL3.
BT | Meaning |
---|---|
0b0 |
When the PE is executing at EL3, PACIASP and PACIBSP are compatible with PSTATE.BTYPE == 0b11. |
0b1 |
When the PE is executing at EL3, PACIASP and PACIBSP are not compatible with PSTATE.BTYPE == 0b11. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Controls enabling of pointer authentication (using the APIAKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnIA | Meaning |
---|---|
0b0 |
Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is not enabled. |
0b1 |
Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is enabled. |
For more information, see 'System register control of pointer authentication'.
This field controls the behavior of the AddPACIA and AuthIA pseudocode functions. Specifically, when the field is 1, AddPACIA returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
The reset behaviour of this field is:
Reserved, RES0.
Controls enabling of pointer authentication (using the APIBKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnIB | Meaning |
---|---|
0b0 |
Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is not enabled. |
0b1 |
Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is enabled. |
For more information, see 'System register control of pointer authentication'.
This field controls the behavior of the AddPACIB and AuthIB pseudocode functions. Specifically, when the field is 1, AddPACIB returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES1.
Controls enabling of pointer authentication (using the APDAKey_EL1 key) of instruction addresses in the EL3 translation regime.
EnDA | Meaning |
---|---|
0b0 |
Pointer authentication (using the APDAKey_EL1 key) of data addresses is not enabled. |
0b1 |
Pointer authentication (using the APDAKey_EL1 key) of data addresses is enabled. |
For more information, see 'System register control of pointer authentication'.
This field controls the behavior of the AddPACDA and AuthDA pseudocode functions. Specifically, when the field is 1, AddPACDA returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime.
EE | Meaning |
---|---|
0b0 |
Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are little-endian. |
0b1 |
Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are big-endian. |
If an implementation does not provide Big-endian support at Exception levels higher than EL0, this bit is RES0.
If an implementation does not provide Little-endian support at Exception levels higher than EL0, this bit is RES1.
The EE bit is permitted to be cached in a TLB.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES1.
Exception Entry is Context Synchronizing.
EIS | Meaning |
---|---|
0b0 |
The taking of an exception to EL3 is not a context synchronizing event. |
0b1 |
The taking of an exception to EL3 is a context synchronizing event. |
If SCTLR_EL3.EIS is set to 0b0:
The following are not affected by the value of SCTLR_EL3.EIS:
The reset behaviour of this field is:
Reserved, RES1.
Implicit Error Synchronization event enable.
IESB | Meaning |
---|---|
0b0 |
Disabled. |
0b1 | An implicit error synchronization event is added:
|
When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field and, if implemented, SCR_EL3.NMEA. If the Effective value of the field is 1, then an implicit error synchronization event is added after each DCPSx instruction taken to EL3 and before each DRPS instruction executed at EL3, in addition to the other cases where it is added.
When FEAT_DoubleFault is implemented, the PE is in Non-debug state, and the Effective value of SCR_EL3.NMEA is 1, this field is ignored and its Effective value is 1.
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES0.
Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:
WXN | Meaning |
---|---|
0b0 |
This control has no effect on memory access permissions. |
0b1 |
Any region that is writable in the EL3 translation regime is forced to XN for accesses from software executing at EL3. |
This bit applies only when SCTLR_EL3.M bit is set.
The WXN bit is permitted to be cached in a TLB.
The reset behaviour of this field is:
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Controls enabling of pointer authentication (using the APDBKey_EL1 key) of instruction addresses in the EL3 translation regime.
EnDB | Meaning |
---|---|
0b0 |
Pointer authentication (using the APDBKey_EL1 key) of data addresses is not enabled. |
0b1 |
Pointer authentication (using the APDBKey_EL1 key) of data addresses is enabled. |
For more information, see 'System register control of pointer authentication'.
This field controls the behavior of the AddPACDB and AuthDB pseudocode functions. Specifically, when the field is 1, AddPACDB returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
The reset behaviour of this field is:
Reserved, RES0.
Instruction access Cacheability control, for accesses at EL3:
I | Meaning |
---|---|
0b0 | All instruction access to Normal memory from EL3 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. |
0b1 | This control has no effect on the Cacheability of instruction access to Normal memory from EL3. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. |
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
The reset behaviour of this field is:
Exception Exit is Context Synchronizing.
EOS | Meaning |
---|---|
0b0 |
An exception return from EL3 is not a context synchronizing event |
0b1 |
An exception return from EL3 is a context synchronizing event |
If SCTLR_EL3.EOS is set to 0b0:
The following are not affected by the value of SCTLR_EL3.EOS:
The reset behaviour of this field is:
Reserved, RES1.
Reserved, RES0.
Non-aligned access. This bit controls generation of Alignment faults at EL3 under certain conditions.
nAA | Meaning |
---|---|
0b0 |
LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH, LDLAR, LDLARH, STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH generate an Alignment fault if all bytes being accessed are not within a single 16-byte quantity, aligned to 16 bytes for accesses. |
0b1 |
This control bit does not cause LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH, LDLAR, LDLARH, STLLR, STLLRH, STLR, STLRH, STLUR, or STLURH to generate an Alignment fault if all bytes being accessed are not within a single 16-byte quantity, aligned to 16 bytes. |
The reset behaviour of this field is:
Reserved, RES0.
Reserved, RES1.
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking'.
The reset behaviour of this field is:
Cacheability control, for data accesses.
C | Meaning |
---|---|
0b0 |
All data access to Normal memory from EL3, and all Normal memory accesses to the EL3 translation tables, are Non-cacheable for all levels of data and unified cache. |
0b1 | This control has no effect on the Cacheability of:
|
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
The reset behaviour of this field is:
Alignment check enable. This is the enable bit for Alignment fault checking at EL3.
A | Meaning |
---|---|
0b0 | Alignment fault checking disabled when executing at EL3. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed. |
0b1 | Alignment fault checking enabled when executing at EL3. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. |
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
The reset behaviour of this field is:
MMU enable for EL3 stage 1 address translation. Possible values of this bit are:
M | Meaning |
---|---|
0b0 | EL3 stage 1 address translation disabled. See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory. |
0b1 |
EL3 stage 1 address translation enabled. |
The reset behaviour of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then return SCTLR_EL3;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b110 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then SCTLR_EL3 = X[t];
30/06/2021 09:39; 4f5dd962f4e34e1ac282f76da4d6e7fc4cab087e
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